IMS-MTP for Consumer Goods Industry MTP PROGRAM: SUSTAINABLE MANUFACTURING
OTP and MTP Non-Volatile Memory IP for Standard … · May 6, 2015 1 OTP and MTP Non-Volatile...
Transcript of OTP and MTP Non-Volatile Memory IP for Standard … · May 6, 2015 1 OTP and MTP Non-Volatile...
May 6, 2015 1
OTP and MTP Non-Volatile Memory IP for Standard Logic CMOS Technologies
May 6, 2015
NSCore, Inc.
Kenji Noda Executive VP & CTO
May 6, 2015 2
Embedded Logic OTP/MTP NVM Technology
Benefits to LSI Design: Reduced Cost
Reliability Improved Security Level
on CMOS Process Platforms
-Program Code -Security Code -Analog Trimming -SRAM Repair -Gamma Correction
Non-Volatile Memory IP
Applications:
May 6, 2015 3
Program, Read and Erase Mechanism
May 6, 2015 4
Drain
Programming Mechanism
Source Electrons
Hot electron
Ec
Electrons
Impact Ionization
Si3N4
SiO2
Common sidewall spacer structure
When nMOSFET turns ON, hot-electrons are generated and trapped in side-wall spacer.
LDD implant is masked to accelerate impact ionization.
5-7V
5-7V
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In Read Operation
Source Drain
Trapped electron
Ec
Trapped electron bends the conduction band to form a barrier. Channel current is reduced. Conduction band
without electron trapping
Electrons
“Source” and “Drain” are reversed from Program Operation
0.5-1V
1.8-3.3V
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Erase Mechanism for MTP
Drain Source
Hot-Hole Injection and Recombination
0V 5-7V
- 5-7V
When Gate is negatively biased, hot-holes are injected into the spacer and recombine with the trapped electrons.
Band-to-Band Tunneling current generates hot-carriers.
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-
Gate
Source Drain
-
Our OTP Cell Tr. SONOS NVM Cell Tr.
Gate
Source Drain
Si3N4
SiO2
Similarity with SONOS Memory
Program mechanism in Our OTP is similar to SONOS memory, which has strong track record as embedded Flash memories. Both memories uses electron trapping in Si3N4 layer. Our OTP does not need any extra process, while SONOS requires special gate structure.
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Excellent Retention Characteristics
The cell current was drastically reduced and has been stable even after baking for 100 hours at 200°C, which is equivalent to over 30 years at 125°C.
ID[A
]
0.18mm process
program
Baking
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Program Operation
Driver & Pre-Amplifier
WL0 On
L H
Ex. High
High Off
Low WL1
Bit Bit
Gate Voltage
Dra
in C
urr
en
t
Hot-Carrier Effect
Program current flows in one transistor in a cell and generate hot-carriers.
OTP bit cell
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Read Operation
Ion0 << Ion1
Amplifying Latch Driver &
Pre-Amplifier
WL0
H H L
Low
High
Low WL1
Bit Bit
Ion1 Ion0
Hot Carrier Trapped Tr.
Both bit-lines are pre-charged and current flows through selected cell transistors. Sense amplifier senses current difference and latches.
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Erase Operation for MTP
Driver & Pre-Amplifier
SWL0
L L
Ex. High
Negative
Negative SWL1
Bit Bit
Data at all word-lines can be erased at the same time.
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OTP Technology PermSRAMTM
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Cell array (64b x 4)
“Pro
gra
m T
ime
Co
un
ter“
su
pp
ort
s m
ult
i-ti
me
pro
gram
min
g.
(185um x 120um)
256b OTP/64b 4-Time-Programmable -Single-Word Architecture -Process Generation: 0.13mm Process -IO: 64b (configurable from 1b to 256b) -Metal Usage: 3 Layers (no limitation on routing over the macro)
64b Data Latch
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16Kb One-Time-Programmable
CELL ARRAY
YSW
DIO
TEST
XDEC
VW
LGEN
(329um x 144um)
-SRAM-Like Architecture -Process Generation: 65nm Process -IO: 64b -Metal Usage: 3 Layers (no limitation on routing over the macro)
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OTP Availability in Foundry Processes TSMC 0.18mm TSMC 0.13mm TSMC 0.11mm TSMC 90nm TSMC 65nm IBM 0.18mm TowerJazz 0.18mm UMC 0.11mmAE UMC 0.11mmE SMIC 0.13mm GF 0.13mm Silterra 0.18mm Silterra 0.13mm Silterra 0.11mm LFoundry 0.15mm LFoundry 0.11mm
IP9000 Full Qual., Volume Production IP9000 Full Qual., Volume Production Silicon Verified Silicon Verified IP9000 Full Qual., Volume Production Ready-for-IBM, Volume Production Full Qualification Silicon Verified Silicon Verified Silicon Verified Silicon Verified Silicon Verified In Silicon Verification In Silicon Verification In Silicon Verification In Silicon Verification
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2T-MTP Technology TwinBitTM
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Targeted Market Segment of Our MTP
Write/Erase Cycle
Me
mo
ry C
apac
ity
1 time OTP
1K-10K times MTP
Company- A, B, C
NSCore
100bit-10Kbit
100Kbit-10Mbit
Company-D
1T-MTP PolarBitTM
2T-MTP TwinBitTM
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Program/Erase Characteristics
1st Program 1st Erase
Program & Erase 1K Times Program & Erase 10K Times
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1T-MTP Technology PolarBitTM
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sample5 32-47 LDDなし store条件 VD=5.5V,VG=1.8V,Tw=10ms
0.00E+00
1.00E-05
2.00E-05
3.00E-05
4.00E-05
5.00E-05
6.00E-05
7.00E-05
8.00E-05
9.00E-05
1.00E-04
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VG[V]
ID[A
]
ini
ini
ini
ini
ini
ini
ini
ini
ini
ini
ini
ini
ini
ini
ini
ini
reverce
reverce
reverce
reverce
reverce
reverce
reverce
reverce
reverce
reverce
reverce
reverce
reverce
reverce
reverce
reverce
normal
normal
normal
normal
normal
normal
normal
normal
normal
normal
normal
normal
normal
S D
S D
S D
Polarity of Vg-Id Characteristics
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Technology Comparison
Embedded Flash
Conventional CMOS MTP
Bit Area Endurance Add. Mask Add. Process Read Cycle Max. Operation Temp. Retention (10years@) Program Voltage Read Program Erase
NSCore’s MTP “PolarBit”
1 10K-100K cycle 0/+1 Mask None 30-50MHz 125-150ºC 85-150ºC 5.5V Byte Block Block
2 1K-10K cycle +10 Mask Stacked Poly 30-50MHz 125-150ºC 85-150ºC 10V Byte Block Block
20-100 100K cycle None None 30MHz 125ºC 85-125ºC 20V Byte Byte Byte
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Summary
We have developed and qualified unique OTP and MTP non-volatile technologies using hot-carrier trapping mechanism.
The electron trapped in Si4N3 layer in the MOSFET spacer is very stable even at high temperature.
We have demonstrated 10K cycle endurance and over 20 years retention at 150C for 2T-MTP.
1T-MTP has a potential to replace existing embedded Flash memory IPs.