ORNL/SNS

Spallation Neutron SourceLow-Level RF Control System

Kay-Uwe Kasemir, Mark Champion

April 2005

EPICS Meeting 2005, SLAC

ORNL/SNS2

SNS Linac LLRF

• LLRF produces the Milliwatt-level “RF drive”: Pulsed @ 60Hz, 1.3ms

• 96 cavities of various types,15 warm (RFQ, MEBT, DTL, CCL), rest superconducting (SCL);some cavities at 402.5, some at 805 MHz.

• RF Reference, forward, reflected and cavity data is down-converted to50 MHz, then sampled at 40 MHz,resulting in data streams of I, Q, -I, -Q, … (re. & im. of complex data)

• At 40 MHz, a fully digital control system (FPGA & CPU) computes output data stream which gets up-converted to 402.5 resp. 805 MHz.

RF Reference Line, Timing System

LLRF Klystron[mW] [MW] Cavit

y

Fwd Ref

ORNL/SNS3

LLRF Hardware

• VXI Crate with– MVME2100 CPU– SNS Utility board

Time of day, events, etc.via SNS real-time data link

– SNS Timing board TTL timing pulses

– “High Power Protection Module” Monitors power levels,

arc detectors, …for fast shutdown

– “Field Control Module” 40MHz FPGA-based control loop

• SC Linac uses IOCs with 2xHPM, 2xFCM.Total of about 55 IOCs.

• We use VXI as if it was VME– No need for VXI “slot-based” addressing– 8-bit VME instead of 16-bit VXI interrupt vectors.– VME CPU on extender board cheaper than VXI slot-zero controller.

ORNL/SNS4

HPM - High Power Protection Module

• Fast RF Shutdown• Monitors 8 RF channels,

-50…+10 dBm (10nW…10mW),for the duration of the RF gate.– Per-channel threshold and time limit.

Trips when RF above threshold longer than time limit.• Monitors 14 arc detector inputs.• Computed/software interlocks.• Everything can be enabled/disabled,

except one hardware input for “Vacuum OK” signal.• 2 history buffers capture 2ms of data (2s resolution).

User selectable for any RF channel, arc detector,or misc. other internals of the HPM.

• Trip information is sent to the FCM via redundant VXI backplane lines. FCM then cuts the RF drive.

ORNL/SNS5

FCM Ancestor: SNS “Generation 1 & 2” LLRF

• LBNL MEBT LLRF Control Box(Larry Doolittle, http://recycle.lbl.gov/~ldoolitt/llrf )

– “nanoEngine”check-card computer,runs Linux & EPICS R3.14.

– Xilinx Spartan FPGAXC2S150for 40MHz control loop.

– Mini-Circuits components.

– OK, but at its limit:6kB of history buffer,no floating-point CPU.

ORNL/SNS6

FCM - “Generation 3”

• VXI Carrier Board

• Analog Front End

– Replaces Mini-Circuits.

• Digital Front End

– From SNS BPMs

– Xilinx Virtex II XC2V1500 (2xI/O, 4xlogic cells over gen. 1,2)

• RF Output

– AFE & RFOspecific to 805vs. 402.5 MHz

• Firmware (VHDL)translated fromGen. 1/2 LLRF(Verilog),then extended.

ORNL/SNS7

FCM Firmware vs. CPU Software

• FCM Firmware

– 40 Mhz PI controller.

– History Buffers: 5 x 512 x 16 bit x {I, Q}with configurable zoom & pan.

– Feed-Forward Buffer: 4096 x 8bit x {I,Q},200ns or 400ns granularity.

• CPU Software

– ‘Arm’ waveform updates synchronously with SNS event link.

– Decode raw buffer data intoI, Q, Phase, Amplitude waveforms.

– Resonance Error Calculation.

– Adaptive Feed-Forward.

– Automation.

ORNL/SNS8

Example SNS LLRF Screen for one cavity

Calls up Auto-Run sequencer page

Calls up FCM “expert” pages including Adaptive FeedForward controls

Cavity amplitude & phase controls

ORNL/SNS9

The Auto-Run Sequence simplifiesturn on of an RF station

• Ramp RF drive level open-loop in frequency-tracking mode until desired cavity gradient is reached.

• Warmup the cavity in frequency-tracking mode until acceptable resonance error is reached.

• Close the feedback loop after setting loop phase.

• Monitor the status of the HPRF system throughout the sequence.

ORNL/SNS10

Adaptive FeedForward Beam Compensation

Fig. 1 Beam loading in DTL6 with ~40 us, 20 mA beam induced error of 2.7% and 2 deg in amplitude and phase.

Fig. 2 Beam loading eliminated by means of Adaptive FeedForward.

ORNL/SNS11

SNS LLRF Status

• Installation of IOCs completed,maybe 80% of the cavities connected.

• Working on improved

– Interlocks

– Closed loop for superconducting section

– Adaptive feed forward

– Firmware:Larry Doolittle wrote new firmware in Verilog which synthesizes for Generation 1, 2 & 3 hardware.Debug this ‘portable’ firmware and use it,or stay with proven ‘FCM-only’ firmware?