Optimizations for Faster Execution of Esterel Programs
description
Transcript of Optimizations for Faster Execution of Esterel Programs
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Optimizations for Faster Execution of Esterel Programs
Dumitru Potop Robert de Simone IRISA Rennes INRIA Sophia Antipolis
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Outline
1. The Esterel language
• The problem of efficient code generation
2. The GRC intermediate representation
• Intuitive description
• Software code generation
• Code analysis and optimizations
3. Practical results. Conclusion. Future work
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The Esterel language
Esterelspecification
SWtranslation
HW (RTL)generation
• Formal semantics (FSMs, circuits)
• Formal verification
• Simulation• SW implementation
• HW prototype (FPGA)• Synthesis input
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The Esterel language
• Reactive, clock-driven execution
module ABRO:input A,B,R;output O; » loop [ await A || await B ]; emit O; halt every R end module
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The Esterel language
• Reactive, clock-driven execution
module ABRO:input A,B,R;output O;
loop [ await A || await B ]; emit O; halt every R end module
execution instant inputs outputs
0 any -
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The Esterel language
• Reactive, clock-driven execution
module ABRO:input A,B,R;output O;
loop [ await A || await B ]; emit O; halt every R end module
execution instant inputs outputs
0 any -
1 AB O
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The Esterel language
• Reactive, clock-driven execution
module ABRO:input A,B,R;output O;
loop [ await A || await B ]; emit O; halt every R end module
execution instant inputs outputs
0 any -
1 AB O
2 R -
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The Esterel language
• Synchrony– Causality cycles present S else emit S end– Constructive semantics (SOS rules)
·signal S,T in emit S; present T then present S else emit T end else emit O end; end
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The Esterel language
signal S,T in ·emit S; present T then present S else emit T end else emit O end; end
• Synchrony– Causality cycles present S else emit S end– Constructive semantics (SOS rules)
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The Esterel language
signal S,T in emit S; ·present T then present S else emit T end else emit O end; end
• Synchrony– Causality cycles present S else emit S end– Constructive semantics (SOS rules)
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The Esterel language
signal S,T in emit S; ·present T then present S else emit T end else emit O end; end
causality cycle
• Synchrony– Causality cycles present S else emit S end– Constructive semantics (SOS rules)
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The Esterel language
signal S,T in emit S; ·present T then present S else emit T end else emit O end; end
causality cycle
break the cycle
• Synchrony– Causality cycles present S else emit S end– Constructive semantics (SOS rules)
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First compilation scheme (1980’s)
• FSM-based translation – Exhaustive semantic expansion– Explosion in size, expensive analysis– Fast code (execute only active code)
loop [ await A || await B ]; emit O; halt every R
1
2 3
4
0
A/ B/
AB/O
A/OB/O
R/ R/
R/
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• Circuit-based translation – Encode primitives into gates– Small circuit size (quasi-linear)– Slow software code (acyclic circuit evaluation)
loop [ await A || await B ]; emit O; halt every R start
R
A
B
O
Second compilation scheme (1990’s)
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• “Simulation” code – Follows the naïve semantics (control-flow) – Accept less programs (acyclic circuits)– Code: small and very fast (statically scheduled)– Edwards, Closse/Weil
loop [ await A || await B ]; emit O; halt every R
if(START){A_active=1;B_active=1;START=0}else { if(R){A_active=1;B_active=1;} else if(A_active|B_active) { if(A_active) if(A) A_active=0; if(B_active) if(B) B_active=0; if(!(A_active|B_active)) O=1; } }
Third compilation scheme (2000’s)
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• My goal: Formal intermediate model– Preserve high-level information from Esterel
(Static analysis, optimization techniques)– Relation with constructive semantics
(soundness of analysis and optimization)– Relation with the circuit translation
(soundness of execution, unique notion of acyclicity)
Third compilation scheme (2000’s)
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#
||
01
2
boot:
await A
await B
haltsequenceloop-every
#
34
5
6
loop [ await A;emit B || await B ]; emit O; halt every R
[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
The GRC intermediate formatHierarchical state
(structure)
Control/Dataflow graph(behaviour)
activation new state
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#
||
0
1
2
boot:
await A
await B
haltsequenceloop-every
#
34
5
6
loop [ await A;emit B || await B ]; emit O; halt every R
The hierarchical state structure
• parallel/exclusive abstraction of the syntax tree• nodes represent the activity condition of various
subprogram fragments
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
loop [ await A;emit B || await B ]; emit O; halt every R
Flowgraph execution
[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Activated from the
hierarchical state
sequenceloop-every
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
• loop [ await A;emit B || await B ]; emit O; halt every R
•
R absent,A present
Flowgraph execution
[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Activated from the
hierarchical state
sequenceloop-every
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
•loop [ await A;emit B || await B ]; emit O; halt every R
R absent,A present
Flowgraph execution
•[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Activated from the
hierarchical state
sequenceloop-every
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
loop [ await A;emit B •|| await B ]; emit O; halt every R
R absent,A present
Flowgraph execution
•
[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Activated from the
hierarchical state
sequenceloop-every
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
loop [ •await A;emit B || await B ]; emit O; halt every R
R absent,A present
Flowgraph execution
•
[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Activated from the
hierarchical state
sequenceloop-every
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
loop [ await A;•emit B || await B ]; emit O; halt every R
R absent,A present
•[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Flowgraph executionActivated from the
hierarchical state
sequenceloop-every
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
loop [ await A;emit B• || await B ]; emit O; halt every R
R absent,A present
Flowgraph execution
[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Activated from the
hierarchical state
sequenceloop-every
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
loop [ await A;emit B || await B ]; •emit O; halt every R
R absent,A present
Flowgraph execution
•[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Activated from the
hierarchical state
sequenceloop-every
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
loop [ await A;emit B || await B ]; emit O; •halt every R
R absent,A present
Flowgraph execution
•[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Activated from the
hierarchical state
sequenceloop-every
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#
||
0
1
2
boot:
await A
await B
halt
#
34
5
6
loop [ await A;emit B || await B ]; emit O; halt every R
R absent,A present
Flowgraph execution
[2]
[3]
0[1]
enter 5
enter 4enter 3enter 2exit 1
2
enter 6exit 3term
Inactive[4]
R
exit 2
4A
exit 4 term[4]
pause[4]Inactive[5]
5B
exit 5 term[5]
pause[5]
[6]
emit Oemit B
3
3
3
pause
Activated from the
hierarchical state
sequenceloop-every
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Simulation code generation
• State encoding
• Static scheduling– Sequential code– Respects the causality (signal emission
statements before tests statements)
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Inactive[5]
Simulation code generation#
||
boot:
#
await A
await B
loop-every
0 1 2 3 4
0
1
0
1
halt
0
2
34
5
6
term
Inactive[4]
R
A
term[4]
pause[4]
B
term[5]
pause[5]
emit Oemit B
3
3
pause
S[1]
S[2]
S[3]
S[4]
S[4]=1
S[3]=1S[2]=0S[1]=1 3
S[2]=1 S[3]=0
S[4]=0
• State encoding
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Inactive[5]
Simulation code generation
term
Inactive[4]
R
A
term[4]
pause[4]
B
term[5]
pause[5]
emit Oemit B
3
3
pause
S[1]
S[2]
S[3]
S[4]
S[1..4]=1011
S[2]=1S[3]=0
S[4]=0
• Static schedulingbool aux=0;if(S[1]){ if(R){aux=1;} else { if(!S[2]){ if(S[3])if(A){S[3]=0;B=1;} if(S[4])if(B)S[4]=0; if(S[3]=0&S[4]=0){ O=1;S[2]=1; } }}} else {aux=1;}if(aux){S[1..4]=1011;}
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• Based on static analysis (semantic-preserving, fast, efficient)– Redundant state bit elimination– False signal/data dependency elimination– Node grouping– Dead code removal
Optimizations
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• Utility– Simplify the state access/update protocol– Simplify the state encoding
• Static analysis, example
trap T in sustain A|| await B;await C;exit Tend
||
sustain A
await B
#
await C
#
boot:
nt:
nt:Same status at all instants
Optimizations
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• Dependency removal
[2]
0[1]
enter 3enter 2exit 1
exit 3 S
exit 4
enter 4
exit 2 exit 0
[4]
2[3]
pause; present S then emit T end;pause;emit S;
#
#
0
1
2
3
4
boot:
emit S
emit T
GRC code optimizations
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[2]
0[1]
enter 3enter 2exit 1
exit 3 S
exit 4
enter 4
exit 2 exit 0
[4]
2[3]
pause; present S then emit T end;pause;emit S;
#
#
0
1
2
3
4
boot:
emit S
emit T
GRC code optimizations
• Dependency removal
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pause; present S then emit T end;pause;emit S;
GRC code optimizations
[2]
0[1]
enter 3enter 2exit 1
exit 3 S
exit 4
enter 4
exit 2 exit 0
[4]
2[3]
#
#
0
1
2
3
4
boot:
emit S
emit T
• Dependency removal
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Results Size (kbytes)
0
50
100
150
200
250
300
350
1 2 3 4 5 6 7 8
GRC2C
FTR&D
Synopsys
Test configuration: PIII/1GHz/128M/Linuxgcc-2.96 –O, 1Mcycle random or given
Relative execution
time(%grc2c)
0
50
100
150
200
250
300
350
400
450
500
1 2 3 4 5 6 7 8
GRC2C
FTR&D
Synopsys
• Optimizing compiler
• Examples:– Turbo channel bus– Berry’s wristwatch– Video generator– Shock absorber– Operating system model– Avionics fuel controller– Avionics cockpit– Man-machine interface
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• Intermediate model for Esterel programs
• Static analysis, optimizations at GRC level
• GRC-acyclic = circuit-acyclic
• Code generation scheme
• Good practical results
Conclusion
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Future work
• Digital circuit synthesis– State encoding + translation into gates– Good partial results
• Distributed implementation– Connection between Esterel and Signal at
source or GRC/HCDG level
Control registers Control clock hierarchy