Optimisation of signal phase split in vector modulator phase shifters

R.W. Bernstein C.F. Heide

Indexing t e r m : Phased w a y antennas, Phase sh$ modulation, QPSK, Serrodyne translators

Abstract: Choosing a phase split larger than 90" influences the output characteristics of a vector modulator operated as a continuous phase shifter. It is shown that for a vector modulator with a phase split larger than 90", less amplitude varia- tion is required to achieve a specified phase range as compared to a conventional design with a split of 90". Analytical expressions are given for phase and amplitude errors in the output signal resulting from errors in the phase split and amplitude of the signal vector components. By assuming simple models for errors in the signal components, the authors have performed calculations showing that a larger phase split reduces phase errors, although amplitude errors might be larger. In addition, the overall maximum power gain is reduced as the square sine of the phase split, leaving a trade-off.

1 Introduction A vector modulator is one way of designing an analogue phase shifter [l-181. In a vector modulator the phase shift is achieved by adding two signals taking into account their phase difference. This can be viewed as a vector addition [l, 21.

Vector modulators have several applications. These include serrodyne frequency translators [2-51, digital phase shift modulation [2] such as quadrature phase shift keying [6, 71, and phased array antennas [l-51, [8-131 where the vector modulator often is used in a digital fashion.

The conventional type of vector modulators adds two orthogonal vectors, i.e. signals with a phase difference a = 90". One may then choose the phase of the resulting signal to be anywhere on the interval [O", 90"] by con- trolling the amplitude of the signal components. The amplitude control is achieved either by single-gate tran- sistors [l], dual-gate transistors [l, 2, 81, p-i-n-diode attenuators [16], or any other kind of voltage controlled gain or attenuation circuit. Even though a phase of a = 90" is the most obvious choice, it is not necessarily the best. In this paper we discuss some advantages and disadvantages of choosing an obtuse split angle.

2 Analysis Fig. 1 shows a situation where the phase split a is between 90" and 180". We normalise the amplitude of the

0 IEE, 1994 Paper 99026 (E12), first received 20th May and in revised form 5th October 1993 R.W. Bernstein is with SINTEF-SI, PO Box 124, Blindern, N-0314 Oslo, Norway C.F. Heide is with Ostfold College, N-1757 Halden, Norway

IEE Prac.-Circuits Devices Syst., Vol. 141, No. 3, June I994

\ V.

Fig. 1 8 phaseangJe 8, rckrenceanglc U phasesplit 6 chosen phase range

Signal vector summation with signal phase split a z 90"

transistor maximum output signals VI,, and V,,, to 1. By requiring the amplitude of the output signal to be independent of the phase angle 8 the largest resulting vector that can be achieved is I V, I = V, = sin a. By these normalisations,

V, = sin (a - 8) (1)

(2) for the two transistor output signals as a function of the phase angle 8. In many applications a standard control function has to be applied to all the transistors in the phase shifter. As pointed out by Selin [8], process varia- tions result in differences in the response function of each transistor. Consequently, errors in the settability of the phase angle are introduced. Furthermore, the transistor insertion phase changes with control voltage, resulting in additional phase errors. Selin [8] demonstrates that a reduction in the overall phase error may be achieved by avoiding operation of the two amplifiers near their gain extremes, i.e. reducing the phase range 4. He also shows that the phase error is reduced by increasing the phase split a.

On basis of eqns. 1 and 2 one can calculate the maximum variation in the output signals of the tran- sistors as a function of the reference angle O1 for a total phase range of 4 = 45". From these calculations the maximum variation is encountered in the angle extremes, i.e. when 8, = 0" and when O1 = a - 4. The minimum signal variation is achieved with 8, = 22.5", 32.5" and 45" for phase splits of a = 90°, 110" and 135", respectively. This illustrates that a symmetric angle range minimises amplitude variations of the signal components. The cal- culations also indicate that a larger phase split a requires less amplitude variation in the signal components to

V, = sin 8

The authors are greatly indebted to Dr. Geir Uri Jensen at Norwegian Telecom Research, Kjeller, Norway, for valuable discussions.

207

obtain a specific phase range. This is clearer from Fig. 2. In this Figure, which is based on eqns. 1 and 2, we have plotted the maximum variation in the signal components

phase spllt a, deg

Fig. 2 Maximum transistor output signal variation as function of phase split a assuming symmetric phase range 4

as a function of the phase split a. We have assumed a symmetric phase range of 4 = 45" and 4 = 90". It is seen that one gains a lot by choosing a larger phase split. Also it is advantageous to use a smaller phase range 4. This agrees with the experiments reported by Selin [8] .

The reduced variations in the component amplitudes obtained by a larger phase split results in reduced control voltage variation. This reduces the insertion phase varia- tions of the transistors. In addition, the phase error caused by deviations in the absolute values of the control functions* of the transistors tend to cancel as the split is increased. This is discussed in more detail subsequently.

The condition for a symmetric phase range is easily found. Requiring such symmetry,

Vl(01) = V,(@l + 4) (3) To achieve this, the two control transistors are to be used in approximately the same bias range. Using eqns. 1, 2 and 3 obtains

a - 4 el =- 2 (4)

2.1 Phase error analysis We have stated some qualitative arguments showing that the phase error of a vector modulator may be reduced if the phase split a is increased. We now discuss quantifica- tions of this effect.

Assume that the lengths of the component vectors VI and V, deviate by an amount of AV, and AV, compared to the values expected from a standard control function. These deviations are normally due to process variations. This gives rise to a phase error in the output signal. It is easy to show that this error is

AV, sin (a - 0) - AV, sin 0 sin a A0, = (5)

AV, and AV, are in general unknown functions of the applied gate voltages and thereby of the phase angle 0. Often, however, these deviations may be estimated if the statistics of the fabrication process is known.

In Fig. 3 we have, as an example, plotted the phase error A@, as a function of the phase angle 0 relative to the

By control function we mean S,, as a function of the gate voltage.

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reference angle 0,. according to eqn. 5. It is assumed that the phase range of 90" is symmetrically placed when a z 90". In the plot AV, and AV, are set to 20% and

15- i

q a -5

0 22.5 45 67.5 90 relotive phase angle@-e,.deg

Fig. 3 Phase error AfJ, as result of deviations in input signal ampli- tudes as function of relative phase angle (0 - 0,) for symmetric phase range

given the same sign. The Figure shows that by increasing the phase split a a reduction in the phase error is achieved. It is relatively easy to show that the opposite is true when the component errors are of opposite sign. One also sees that the errors are larger in the angle extrema.

There may also be deviations in the phases of the com- ponent vectors, denoted Aa, and Aaz . These may be due to process variations as well as to changes in the inser- tion phase of the transistors upon bias voltage changes. These deviations result in a phase error

(6)

This relation is plotted in Fig. 4. In this Figure Aa, and Aa, are taken to vary proportionally with the signal

Aa, cot (a - 0) + Aa, cot 0 cot (a - 0) + cot 0

AOP =

1 2 r 1

10 n /

0 0 22 5 45 675 90

relative phase angle 8-8, ,deg

Fig. 4 Phase error Atlp as result of bias dependence of insertion phase of input signal, as function of the relative phase angle (0 - e,) for a sym- metric phase range. Insertion phase is taken to vary linearly with bias voltagefiom 0 to 10"

amplitudes V, and V, respectively, from 0" to 10". This is a very simple model of a typical behaviour of a FET at 4 GHz, according to Mondal et al. [l]. Because we have set the slope equal for Aa,(V,) and Aa,(V,), the plot of eqn. 6 in Fig. 4 does not include any process variations. Even so, the Figure illustrates two important facts. First, the phase errors caused by these bias-dependent phase

IEE Proc-Circuits Devices Syst., Vol. 141, No. 3, June 1994

variations in the signal components are reduced as the phase split is increased. Secondly, it is desirable to choose a symmetric phase range.

22 Amplitude error analysis Errors in the signal amplitudes also result in an ampli- tude error in the output signal. The error is easily found using the cosine relation:

(7) The amplitude error caused by the phase errors in the signal components Aa, and Aa, is found in the same way as eqn. 7, and is

AV, = AV, COS 0 + AV, COS (a - 0)

AVp = (Aa, - ha,) sin (a - 6) sin 0 (8) Aa, - Act, must be expressed in radians. One sees from these relations that both A K and AV, increase with increasing phase split.

As mentioned previously, a larger phase split a reduces the amplitude of the output signal. Given the normal- isation VI,, = V,,, = 1 together with the requirement that the amplitude of the output signal is the maximum that can be maintained for all phase angles, the ampli- tude of the output signal is sin a. This can easily be deduced by geometrical considerations. This gives, as an example, a signal level degradation of 1.25 dB and 3 dB with a = 125” and a = 135”, respectively, relative to its value with a = 90”.

3 Conclusion

We have discussed different categories of input and output signal errors and shown that by choosing a sym- metric phase range within a signal phase split larger than 90”, less variations in the control voltages are needed to achieve a specific phase shift. This reduces the phase error and give better reproducibility of the phase shifter. We have derived analytical expressions showing the dependence of errors in the output signal on the different kinds of deviations in the input signal components. These expressions show that the phase error in the output signal is reduced while the amplitude error in the output signal increases as the phase split increases, assuming a symmetric phase range. Also, the overall gain is reduced, leaving a trade-off that must be considered specifically for each application.

4 References

1 MONDAL, J.P., MILNES, A.G., OAKES, J.G., and WANG, S.-K.: ‘Phase shifts in single- and dual-gate GaAs MESFETs for 2-4 GHz

quadrature phase shifters’, I E E E Tram., 1984, MlT-32, pp. 1280- 1288

2 KUMAR, M., MENNA, R.J., and HUANG, H.-C.: ‘Broad-band active Dhase shifter usina dual aate MESFET, I E E E Trans., 1981, m - 2 9 , p p . 1098-1102- -

3 VAN DEN BOGAART, F.L.M., and PYNDIAH, R.: ‘A high- performance vector modulator integrated on GaAs for phased-array radar and ECM amlications’. Proceedings of conference on Mili- tary microwaves, 199b, pp. 387-392

4 FROST, R.D., FISHER, D.A., and PECK, D.E.: ‘A GaAs MMIC voltage-controlled phase shifter’, Microwaue J., 1991, 34, (8), pp. !2-04 I, ,-

5 ALI, F., MITCHELL, S., MOGRI, J., and PODELL, A.: ‘A single chip C-band GaAs monolithic five-bit phase shifter with on chip digital decoder’. IEEE MTT-S international symposium digest on Microwaves 1990, pp. 1235-1237

6 PYNDIAH, R., LEBLANC, R., and BALLAGE, J.P.: ‘GaAs MMIC direct linear vector modulators in digital radio links’, Microwave J. , 1990,33, (3), pp. 136-144

7 PYNDIAH, R., JEAN, P., LEBLANC, R., and MEUNIER, J.-C.: ‘GaAs monolithic direct linear (1-2.8) GHz Q.P.S.K. modulator’. Proceedings of 19th European conference on Microwaves, 1989, pp. 597-602

8 SELIN, J.R.: ‘Continuously variable L-band monolithic GaAs phase shifter’, Microwaue J., 1987, 30, (9), pp. 211-218

9 GAZIT, Y., and JOHNSON, H.C.: ‘A continuously variable Ku-band phase/amplitude control module’. IEEE M’IT-S interna- tional symposium digest on Microwaves, 1981, pp. 436-438

10 LEVY, D., NOBLET, A., and BENDER, Y.: ‘A 2-18 GHz contin- uously variable 0-360” phase shifter’. Proceedings of 17th European conference on Microwaves, 1987, pp. 125-130

11 LEVY, D., NOBLET, A., and BENDER, Y.: ‘A 2-18 GHz mono- litic phase shifter for electronic warfare phased array applications’. Proceedings of the 1988 symposium on GaAs integrated circuits, 1988, pp. 265-268

12 ALI, F., MITCHELL, S., MURPHY, A., ADAR, A., HO, P., and PODELL, A.: ‘Production results of X-band GaAs MMIC 5-bit phase shifters’. IEEE MlT-S international symposium digest on Microwaves, 1990, pp. 633-636

13 SUCKLING, C.W., RIGBY, P.N., BAMBRIDGE, T., PENGELLY, R.S., and BUTLIN, R.S.: ‘The performance of GaAs lumped-element phase shifters at S- and C-band‘. Proceedings of 13th European conference on Microwaues, 1983, pp. 374-379

14 BAMBRIDGE, T., LANE, A., and SUCKLING, C.W.: ‘Active and passive phase shifters employing GaAs MMICs’. IEE colloquium on Manipulating microwave signals, 1984, pp. 611-614

15 VORHAUS, J.L., PUCEL, R.A., and TAJIMA, Y.: ‘Monolithic dual-gate GaAs FET digital phase shifter’, I E E E Trans., 1982, m - 3 0 , pp. 982-992

16 DUNLEAVY, L.: ‘GaAs MMICs perform in phase shifters‘, Micro- waves & RF, 1984,23, (4), pp. 49-52

17 CHEN, Y.K., HWANG, Y.C., NASTER, R.J., RAGONESE, L.J., and WANG, R.F.: ‘A GaAs multi-band digitally controlled 0-360” phase shifter’. IEEE symposium technical digest on GaAs integrated circuits, 1985, pp. 125-128

18 HWANG, Y.C., CHEN, Y.K., NASTER, R.J., and TEMME, D.: ‘A microwave phase and gain controller with segmented dual-gate MESFETs in GaAs MMICs’. IEEE 1984 symposium digest on Microwaue and millimeter-wave monolithic circuits, 1984, pp. 1-5

19 POZAR, D.M.: ‘Microwave engineering’ (Addison-Wesley, Reading, MA, USA, 1990), ch. 8

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