Optimal Placement of Bank Selection Instructions in ...
Transcript of Optimal Placement of Bank Selection Instructions in ...
Partitioned Memory Architectures
Allow using a physical address space larger than the logicalone
Common in embedded systems
Bank selection instructions change which part of the physicaladdress space is mapped into a window in logical addressspace
Example Architecture: Z180
Z8018xFamily MPU User Manual
56
UM005003-0703
Figure 24. Physical Address Transition
MMU Block Diagram
The MMU block diagram is depicted in Figure 25. The MMU translates internal 16-bit logical addresses to external 20-bit physical addresses.
Figure 25. MMU Block Diagram
Logical Address Space
Physical Address Space
Common Area 1
Bank Area
Common Area 0
Common Base
Bank Base
FFFFH
0000H
FFFFFH
00000H
0
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+
+x y z
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MMU Common/Bank AreaRegister; CBAR (8) Memory
Management
8PA12—PA19
LA12—LA154
MMU Common Base Register; CBR (8)MMU Bank Base Register; BBR (8)
LA: Logical AddressPA: Physical Address
Internal Address/Data Bus
Unit
0Zilog Z180 manual
Placement of Bank Selection Instructions
Inserting bank selection instructions optimally is hard
Previous approaches are not optimal or do not havepolynomial runtime
Graph structure theory allows an efficient, optimal approach
C Code
int binomial_coefficient(int n, int k){ int i, delta, max, c; if(n < k) return(0); if(n == k) return(1); if(k < n - k) { delta = n - k; max = k; } else { delta = k; max = n - k; } c = delta + 1; for(i = 2; i <= max; i++) c = (c * (delta + i)) / i; return(c);}
Control Flow Graph
int binomial_coefficient(int n, int k){ int i, delta, max, c; if(n < k) return(0); if(n == k) return(1); if(k < n - k) { delta = n - k; max = k; } else { delta = k; max = n - k; } c = delta + 1; for(i = 2; i <= max; i++) c = (c * (delta + i)) / i; return(c);}
Tree Decomposition
Given a graph G with nodes Π a tree decomposition of G is a pair(T ,X ) of a tree T and a family X = {Xi | i node of T} ofsubsets of Π:⋃
i node of T Xi = Π,
∀{x , y} edge in Π: ∃i node of T : x , y ∈ Xi ,
∀x ∈ Π: {i node of T | x ∈ Xi} is connected in T .
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Tree Width
The width of a tree decomposition (T ,X ) ismax{|Xi | | i node of T} − 1.
The tree-width tw(G ) of a graph G is the minimum widthover all tree decompositions of G .
The tree-width of control-flow graphs is bounded1.
1M. Thorup, 1998
Nice Tree Decomposition
A tree decomposition (T ,X ) of a graph G is called nice, iff
T is oriented, with root t, Xt = ∅.Each node i of T is of one of the following types:
Leaf node, no childrenIntroduce node, one child j ,Xj ( Xi
Forget node, one child j ,Xj ) Xi
Join node, two children j1, j2,Xi = Xj1 = Xj2
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Notation
Let B be the set of memory banks in the architecture.
Let G = (Π,E ) be the control-flow graph of the program.
Let c : E ×B×B→ R be the cost function.
Let (T ,X ) be a nice tree decomposition of minimum width ofG with root t.
Placement of Bank Selection Instructions
For a fixed set of memory banks B, the problemof Optimal Placement of Bank SelectionInstructions with input program consisting of apartially colored control-flow graph G = (Π,E )and cost function c is the following: Find acompatible coloring f : Π→ B of G , such that∑
e∈Ec(e, f (e0), f (e1))
is minimal over all compatible colorings.
Accumulated cost function
s(i , f ) gives the minimum possible cost for the edges covered inthe subtree rooted at i , excluding the edges between nodes in inXi , when using f as the coloring for Xi .
Leaf: s(i , f ) := 0.
Introduce: s(i , f ) :=
{∞ if coloring incompatible
s(j , f |Xj) otherwise.
Forget: s(i , f ) :=
min
s(j , g) +∑
e∈(E∩(X 2j rX 2
i ))
c(e, g(e0), g(e1))
∣∣∣∣∣∣∣ g |Xi= f
.
Join: s(i , f ) := s(j1, f ) + s(j2, f ).
The optimal coloring in polynomial time
The nice tree-decomposition of minimum width can becalculated in linear time2.
s can be calculated in time O(|T |tw(G )2|B|tw(G)+1).
Extend the single remaining f at the root t to all nodes toobtain the optimal coloring.
2H. Bodlaender 1996
Example code
i f ( . . . )a c c e s s b ank a ;
e l s edo not acce s s banked memory ;
sw i t c h ( . . . ){ca se 0 :
do not acce s s banked memory ;b reak ;
ca s e 1 :a c c e s s b ank b ; b reak ;
ca s e 2 :do not acce s s banked memory ;b reak ;
.
.
.c a s e n−1:
a c c e s s b ank b ;b reak ;
d e f a u l t :do not acce s s banked memory ;b reak ;
}
a c c e s s b ank a ;