Design and characterisations of double-channel GaAs pHEMT Schottky diodes based on vertically-stacked MMICs for a receiver protection limiter

Norshakila Haris, Peter B K Kyabaggu and Ali A Rezazadeh

Microwave and Communication Systems Research Group, The University of Manchester, Sackville Street Building, M13 9PL Manchester, UK

E-mail: norshakila.haris@manchester.ac.uk

AbstractA microwave receiver protection limiter circuit has been designed, fabricated and tested using vertically-stacked GaAs MMIC technology. The limiter circuit with a dimension of 2.5 x 1.3 mm 2 is formed by using double-channel AlGaAs/InGaAs pseudomorphic HEMT (pHEMT) Schottky diodes integrated with a low loss V-shaped coplanar waveguide multilayer structure. The electrical parameter characteristics of the pHEMT Schottky diodes are presented including the C-V profile showing the presence of double-channel in the device layer structure. This unique feature can also be seen from the double-peak responses of electron density as a function of device layer width, which represent the high electron concentration at two different 2-DEG layers of the structures. Equivalent circuit model of pHEMT Schottky diodes is demonstrated showing good agreement with the measured results. At zero-bias condition, the devices show high performance in diode detectors applications with voltage sensitivities of more than 89 mV/µW at 10 GHz and at least 5.4 mV/µW at 35 GHz. The measurement results of the limiter circuit demonstrated the blocking of input power signal greater than 20 dBm input power at 3 GHz. To the best of our knowledge this is the first demonstration of the use of pHEMT Schottky diodes in microwave power limiter applications.

Keywords: diode limiter, equivalent circuits, multilayer MMICs, parameter extraction, pHEMTs Schottky diodes, zero bias detector._____________________________________________________________________________________________

1. Introduction

Typical reliable Microwave and RF receivers have sensitive low noise amplifiers (LNAs) at their input to detect and process weak incoming signals. Due to the sensitive nature of these LNAs, they can easily be damaged if exposed to unwanted high RF power. A diode limiter is normally a promising solution for most receiver protector applications. It acts as a buffer against high power signals while exhibiting low loss at small signal levels. (p-i-n)-type diodes are commonly used in the limiter circuits because they can handle high power signals [1], [2] and are commercially available. However, the fabrication of these devices is rather complicated and also their sizes are excessively bulky, which results in a costly design for consumer and commercial applications [3]–[5]. Another drawback is that they cannot be easily integrated in monolithic microwave integrated circuits (MMICs) technology due to its incompatibility with the

standard open foundry mode. To overcome these problems, MMICs Schottky diodes are being introduced in limiter design due to their efficient signal rectification at high frequencies and well-suited to be fabricated on a typical GaAs foundry process [6], [7].

One method in reducing the size of MMIC chips is to use the concept of multilayer three-dimensional (3-D) MMICs. Using this technology, active components can be integrated with vertically stacked passive components in-between layers of metals and dielectrics [8]–[10]. Schottky diode limiter can be realised using multilayer 3-D MMICs technology, producing miniaturised components and reducing the cost of the production. The design is based on the use of Schottky diodes incorporated within the design of a multilayer pHEMTs. pHEMT Schottky diodes have several advantages. First, they can be easily fabricated using existing MMICs wafers which contain pre-fabricated pHEMTs. Second, they

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have a lower forward voltage than Silicon p-n diode resulting in less power being consumed. Third, since the current consists of majority carriers they have fast switching characteristics so they can be used at higher frequencies.

Although several works on the use of pHEMT Schottky diodes in limiter design have been reported [11], [12], few studies were dedicated towards the DC and RF characterisations of these devices. Furthermore, the integration of active and passive components in multilayer 3-D MMICs can reduce the size of the chip by about 50% [13]. In this paper, we describe the design and characterisations of double-channel pHEMT Schottky diodes which are fabricated in a vertically stacked MMICs arrangement. Two of the devices are connected in shunt configuration to design the receiver protection limiter circuit, integrated with a 50 Ω low loss coplanar waveguide (CPW) transmission line, as shown in figure 1. The type of transmission line chosen is a V-shaped structure which can be easily designed and manufactured using multilayer technology. Conventional CPW transmission lines have losses especially around the edge of the conductor reducing the signals level. By using a V-shape transmission line, the current crowding effect of the conductor can be minimised, thus reducing the losses [14]. To the best of our knowledge this is the first demonstration of the use of pHEMT Schottky diodes in microwave power limiter applications.

Figure 1. Schematic diagram of the receiver protection limiter consisting of two pHEMT Schottky diodes connected in shunt configuration. The 50 Ω transmission lines used to connect both devices is a V-shaped coplanar waveguide multilayer structure.

2. pHEMT Schottky Diodes Design and Fabrication

As mentioned earlier, the Schottky diodes under consideration are based on pre-fabricated double-gate fingers pHEMT structures [15]. Two different gate widths of 120 µm and 200 µm are chosen which designated as pHSD120 and pHSD200, respectively. Both structures have similar gate length of 0.5 µm. The top view illustration of the pHEMT Schottky diode is demonstrated in figure 2. The design of the pHEMT Schottky

diode is made by connecting the source contact (S) to the drain contact (D) of the pHEMT using multilayer fabrication technology and this becomes the output port (Ohmic contact) while the gate contact (G) is the input port (Schottky contact). ‘x’ and ‘y’ in figure 2 represent the spacing between G-S and G-D contacts of the device and their values are 0.5 µm and 2.5 µm, respectively.

Figure 2. Top view layout of pHEMT Schottky diode where its drain contact is shorted to the source.

The multilayer fabrication of the pHEMT Schottky diodes and the receiver protection limiter is identical and comprises of five-mask levels, developed and fabricated at The University of Manchester, U.K. Three metal layers made of gold (Au) are sandwiched between two dielectric layers made of polyimide. Thicknesses of individual metal and polyimide layers are 0.8 µm and 2.5 µm, respectively. The relative dielectric constant of the polyimide is 3.7. The structures are grown on a 600 µm thick semi-insulating GaAs substrate with dielectric constant of 12.9. The ohmic and gate contact layers are deposited by thermal evaporation to form the double gate fingers structure as well as the CPW pads for the device, having characteristic impedance of 50 Ω.

Figure 3 illustrates the micrographs of the fabricated devices. The cross-sectional view of the double-channel pHEMT used in this fabrication is shown in figure 4. The substrate uses double heterojunctions where the undoped InGaAs channel layer is sandwiched between two n-AlGaAs supply layers. The structure provides a much broader transconductance versus input gate bias, resulting in better linearity characteristics making it suitable for high speed and high frequency devices.

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Figure 3. Micrographs of fabricated receiver protection limiter and pHEMT Schottky diode using a V-shape low loss CPW transmission line.

Figure 4. Epitaxial layer structure of GaAs pHEMT containing double-channel 2-DEG layers (not drawn to scale).

3. Results and Discussion

3.1. Forward Current-Voltage (I-V) Characteristics

The fabricated pHSD120 and pHSD200 are characterised at microwave frequencies using Cascade Microtech on-wafer probe station at room temperature. They are connected to a HP8510C (110 GHz) vector network analyser using 200 µm pitch probes and calibrated using a standard LRRM calibration substrate and de-embedded using open-short, and thru structures. Keysight ADS and IC-CAP software are used to simulate and to extract the DC/RF parameters.

The relationship between the current (I) flowing through a Schottky diode and the applied voltage across its terminal (V) can be defined from thermionic emission model (for V > 3kT/q) as follows [16]:

(1)

where A is the Schottky contact area, A* is the effective Richardson constant which is equal to 8.16 A/k2cm2for GaAs, T is the absolute temperature in Kelvin, q is the electronic charge, ϕBn is the effective barrier height from metal to

semiconductor, k is the Boltzmann constant and V is the voltage across the junction. At forward bias and when diode series resistance is considered, the diode equation (1) can be expressed as:

(2)

The first term of (2) represents the saturation current, Is

and it is used to calculate the Schottky barrier height of the device:

(3)

Taking natural logarithms of both sides of (1), the equation becomes:

(4)

According to (4), the ideality factor (n) can be obtained from the linear interpolation of ln(I) versus V plot and Is from the continuation of the curve with the vertical axis. Figure 5 shows the measured current versus voltage (I-V) and ln (I)-V characteristics of the devices. The plot of ln (I)-V shows two linear regions with different slopes, where the first one is at low biasing point of < 0.3V and the second one is at mid biasing point of 0.3 V < V < 0.65 V. The linear region at mid biasing point is due to the diffusion component of the current where an exponential relationship of the current and voltage can be observed. At large biasing point, the series resistance, Rs dominates the current from the linear part.

The diode series resistance can be extracted based on [17] by differentiating (2) with respect to I and re-arranging the terms:

(5)

Thus, the slope and the y-intercept of versus I

plot will give the value of Rs and , respectively as demonstrated in figure 6.

Figure 7 shows the diode resistances extracted from I-V characteristics from linear characteristic in figure 5 as a function of voltage. It is observed that the series resistance (Rs) value obtained from this plot agrees well with the Rs

value obtained from plot in figure 6, hence the accuracy of both techniques are confirmed. Table 1

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summarises all the extracted parameters obtained from the I-V measurement.

Figure 5. Measured linear and semi-log I-V characteristics of the two fabricated pHEMT Schottky diodes with contact areas of (120 x 0.5) µm 2and (200 x 0.5) µm2.

Figure 6. Extracted slopes, versus current for the two pHEMT Schottky diode structures.

Figure 7. Resistance of pHEMT Schottky diodes versus applied voltage, extracted from measured I-V characteristics. The inset shows the R-V plot from 0.6 V to 1 V.

Table 1. Summary of extracted parameters of pHEMT Schottky diodes from I-V measurement at room temperature.

Description pHSD120 pHSD200

Saturation current, Is (pA) 5.1 2.6Ideality factor, n 1.3 1.2Series parasitic resistance, Rs (Ω):

- From curve11.9 9.1

- From R-V curve 12.3 9.9

Barrier height, ϕBn (V) 0.7 0.6

3.2. Capacitance-Voltage (C-V) Profiling

The characterisation of pHEMT Schottky diodes is continued by applying C-V measurement technique to gain a better understanding of the device performances. The measurement is carried out by connecting the samples to Keysight E4980A Precision LCR meter using probe station at room temperature. It is measured in forward and reverse bias conditions with measurement frequency of 2 MHz. C-V measurements obtained from pHEMT Schottky diodes are shown in figure 8. The relationship between the capacitance of a Schottky junction and the applied voltage is given by:

(6)

where Vbi is the built-in voltage, V is the applied voltage across the depletion layer, ε is the dielectric permittivity of the semiconductor, and Nd is the doping concentration in the epitaxial layer. The built-in voltage (Vbi), electron concentration (Nd) and barrier height, ϕbn are determined from the slope and the intercept of the 1/C2 versus voltage based on the equation (6). Careful observation of figure 8indicates two identical slopes at two different bias voltages for each device. These slopes represent the two channels of the device layer structure as shown in figure 4.These findings have been further supported by the plot of Nd versus width, W in figure 9, where two strong peaks can be observed corresponding to the presence of double-channel 2-DEG at the AlGaAs/InGaAs interface. The relationship between Nd and space charge width, W is given by:

(7)

and,

(8)

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Figure 8. Measured C-V and 1/C2 as a function of voltage for the two pHEMT Schottky diodes.

Figure 9. Electron density profile extracted from C-V characteristics as a function of device layer width for the pHSD120 showing the presences of double channels.

Table 2 summaries the extracted parameters of pHEMT Schottky diodes from C-V measurements. It is found that both

channels exhibit similar 2-DEG concentration densities and their values are quiet high. The separation of these two channels corresponds to this 2-DEG layers which is about 10 nm.

3.3. pHEMT Schottky Diode Equivalent Circuit Model

An equivalent circuit is used to model the pHEMT Schottky diode as shown in figure 10. The model yields the physical insight of the device for a given set of operating conditions, to enable accurate design and circuit analysis. It is consisting of bias-dependent junction capacitance (Cj) and junction resistance (Rj) which formed the intrinsic parts of the device. The extrinsic elements comprise of series parasitic resistance (Rs), series parasitic inductance (Ls), anode pad-to-ground parasitic capacitance(Ca) and cathode pad-to-ground parasitics capacitance (Cc).

3.3.1. Parameter Extraction Procedure

The extraction of the above model parameters requires a methodical and straight forward procedure. It follows an analytical procedure based on S-parameters measurements in forward and reverse-biased conditions. The steps involved in the extraction procedure are discussed next.

Step 1: Extraction of Parasitic and Junction Capacitances

At reverse-bias condition (V < Vbi), Rj contribution is predominant over that Cj at low frequencies, resulting in a simplified equivalent circuit as shown in figure 11.

Ca, Cc and Cj can be extracted from the above equivalent circuit by considering low frequency operation where the capacitance effects are dominant. Hence, the equivalent circuit of figure 11 can then be represented in a π-network topology as shown in figure 12.

Table 2. Summary of extracted parameters of pHEMT Schottky diodes from C-V measurements at room temperature.

Channel Description pHSD120 pHSD200

1 Electron density (cm-3) 1.12 x 1020

Built-in potential, Vbi (V) - 0.3 - 0.4

2 Electron density (cm-3) 1.38 x 1020

Built-in potential, Vbi (V) 0.4 0.4

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Figure 10. Equivalent circuit model of the pHEMT Schottky diode.

Figure 11. Simplified equivalent circuit model of pHEMT Schottky diode in reverse-bias (V < Vbi) condition.

Figure 12. Low frequency pHEMT Schottky diode equivalent circuit.

The measured S-parameters of the chosen bias point are transformed into Y-parameters and their expressions are given as follows:

(9)

(10)

(11)

The parasitics capacitances (Ca and Cc) can be obtained by rearranging (9) to (11):

(12)

(13)

(14)

Figure 13 and figure 14 show the plots of junction and parasitic capacitances versus frequency at pinch-off condition.

Both plots indicate that the simplified equivalent circuit based on this assumption is only valid at low frequency range between 2 GHz to 7 GHz where flat capacitance values can be observed.

Step 2: Extraction of Total Resistance

At forward-bias condition (V > Vbi), the depletion layer of the pHEMT Schottky diode extends into the semi-insulating substrate which made Cj becomes almost zero so it can be neglected. Figure 15shows the reduced equivalent circuit at this condition.

Similar to capacitances extraction, the total resistance, RT

which consists of Rs and Rj can be extracted based on figure 15 at low frequency range. At this frequency range Ca, Cc and Ls have little effect on the pHEMT Schottky diode. It is purely resistance so it can be represented as (15). With this, the RT

can be extracted using (16) and Rj can be obtained from DC measurement at the chosen bias point.

(15)

(16)

Step 3: Extraction of Series Parasitic Inductance

The extraction of Ls can be based on the same bias condition as in figure 15 but at high frequency range. At this frequency range, the impedance elements of the simplified model become (17). Thus, Ls can be extracted by (18).

(17)

(18)

Table 3 summarises all the extracted parameters for both pHEMT Schottky diodes. It can be seen that the smaller Schottky contact area, the smaller the Cc, Cj(0), and Ls. At low frequency, Ca is bias-independent therefore there is no change with the Schottky contact area.

3.3.2. Comparison between modelled and measured results

The accuracy of the pHEMT Schottky diode equivalent circuit model is validated by comparing the modelled and measured s-parameters data, shown in figure 16 and 17. Both pHSD120 and pHSD200 show a lower S11 than S21, indicating both devices reflect more but transmit less microwave energy over the whole frequency range. From 0 to 40 GHz, both measured

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and modelled data of pHSD120 show relatively good agreement with nearly 14% maximum error magnitude of S11. An approximately 6% error magnitude of S11 is observed for pHSD200 from 0 to 20 GHz. However, its performance degrades at higher frequencies due to the increasing parasitic effects.

Figure 13. Junction capacitances of pHEMT Schottky diodes at zero bias voltage.

Figure 14. Parasitic capacitances of pHEMT Schottky diodes at zero biasing voltage.

Figure 15. Simplified equivalent circuit model of pHEMT Schottky diode in forward-bias (V > Vbi) condition.

3.3.3. Zero-bias pHEMT Schottky diodes

Schottky diodes can be used for detecting the presence of any signal due to their low turn on voltage and high frequency capability. The need for DC bias at low levels is eliminated by the development of Schottky diodes. A key performance criterion for a Schottky diode detector is the voltage sensitivity, γ, generally expressed in mV/µW. It is the product of the current sensitivity, β, and the junction resistance (the inverse of the derivative of current with respect to voltage). When considering the effect of a diode capacitance, diode resistance, and load resistance, the voltage sensitivity for the zero bias diode becomes [18]:

(19)

The first term of the above equation represents the effect of diode capacitance and resistance (γ) and the second term of the equation represents the load resistance, RL. It is assumed that typical load resistance is 100 kΩ. All the RF parameters are extracted from Table 3.

In zero bias diode detectors, most of the incident powers are absorbed by losses in the matching network. By assuming the zero bias diode to be worked under a 50 Ω system, the reflection losses effect is considered and the equation becomes [18]:

(20)

where ZD is the diode’s parasitics and is a function of frequency.

Voltage sensitivity comparison between our devices with those currently available zero bias diodes in the market are shown in Table 4. The calculations of voltage sensitivity of these devices are based on (20). At 10 GHz, pHSD200 produces the highest voltage sensitivity of 107 mV/µW followed by pHSD120 with 89 mV/µW. At 35 GHz, the same patterns can be observed which indicate that both devices are capable of giving excellent performances as zero bias detectors. Figure 18 illustrates the voltage sensitivity of our devices. At 1 GHz, pHSD200 demonstrates 40% higher voltage sensitivity than pHSD120. This is due to the higher I s

value of pHSD120 compared to pHSD200. As the frequency increases, the voltage sensitivity of both devices decreases which agrees well with (19) and (20), with 10% difference.

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Table 3. Extracted parameter values for pHEMT Schottky diodes at zero bias condition.

Description pHSD120 pHSD200

Anode pad-to-ground parasitics capacitance, Ca(fF) 22.6 22.6Cathode pad-to-ground parasitic capacitance, Cc (fF) 45.2 67.8Zero-bias junction capacitance, Cj (0) (fF) 302.8 445.9Series parasitic inductance, Ls (pH) 121.7 153.8Series parasitic resistance, Rs (Ω) 5.3 4.4Zero-bias Junction Resistance, Rj(0) (MΩ) 3.5 3.4

Figure 16. Reflection and transmission coefficients of pHEMT diode with (120 x 0.5) µm2 Schottky contact area.

Figure 17. Reflection and transmission coefficients of pHEMT diode with (200 x 0.5) µm2 Schottky contact area.

Figure 18. Comparison of two zero bias Schottky diodes, considering reflection losses’ effects.

Table 4. Comparison of voltage sensitivity of zero bias diode detectors

DescriptionVoltage Sensitivity (mV/µW)

At 10 GHz At 35 GHz

pHSD120(This work) 89 5.4pHSD200 (This work) 107 6HSMS-2850[19] 6.5 -HSCH-3486[19] 7.5 -PDB GB322[20] 6.5

(at 9.375 GHz)2.6

3.4. Receiver protection limiter based on pHEMT Schottky diodes

The application suitability of the pHEMT Schottky diodes in receiver protection limiter is tested by using pHSD200 structures as discussed in II. Good agreement between the simulated and the measured results of the fabricated limiter is observed in figure 19 and 20, indicating the validity of the design. At 3 GHz response, the measured return loss, S11 is better than 8.2 dB and the

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measured insertion loss, S21 is less than 1.94 dB. The insertion loss is high due to inductive and capacitive losses introduced by the 50 Ω V-shaped multilayer transmission lines. The measured data are raw data without de-embedding; hence the losses can be reduced by subtracting the contribution of these unwanted portions of the structure. ADS software has been used to provide an ideal loss-less condition of the device as a comparison with the fabricated one. In this simulated circuit, a pair of shunt pHEMT diodes is connected to an ideal loss-loss transmission lines. The ideal behaviour in figure 20 shown that when all the parasitics losses are eliminated, low insertion loss showing 0.6 dB at 3 GHz can be observed, showing promising design for microwave power limiter circuit application.

Figure 21 shows the measured power transfer curve of the fabricated receiver protection limiter at 3 GHz. The input power, Pin is swept from 7 dBm to 27 dBm. From 7 dBm to 20 dBm of the input power, the insertion loss of the device is low due to its maximum high impedance at low incident power. High incident power (which exceeds the threshold level) will transform the diode’s impedance into a much lower value, resulting in an impedance mismatch that reflects most of the input signal power back towards its source. From the measurement, it is observed that the limiting threshold of the device is 20 dBm at 3 GHz. It is the point where the device able to block the high power level signals from damaging power sensitive devices. It is also found that the attenuation is around 5 dB at 15 dBm input power and 10 dBm output power. Up to 27 dBm of input power measurement, the device has not shown any catastrophic failure. This behaviour is comparable to [6] which uses similar GaAs pHEMT diode pair configuration and process. The degradation of the performance of the fabricated device is estimated to start increase rapidly at input power levels of above 35 dBm and the catastrophic failure is likely to occur around 38 dBm. Similar behaviour of these effects can be found in [21] where a distributed GaAs MMICs limiter showing a damage point at the same input power level.

The vertically-stacked MMIC limiter based on this paper has the smallest chip size and better insertion loss compared to previously reported p-i-n diodes [22], [23], with high integration potential with other MMIC components based on the above-mentioned technology.

4. Conclusion

The electrical properties of pHEMT-based Schottky diodes have been successfully characterised using I-V, C-V and S-parameters measurements. The parameter extraction procedure is reliable and very useful for understanding the device physics and behaviour. A power limiter circuits in MMIC configuration using pHEMTs Schottky diodes has been reported for the first time offering zero bias high voltage

sensitivity detection of more than 89 mV/µW at 10 GHz and at least 5.4 mV/µW at 35 GHz. At 3 GHz the limiter circuit demonstrated a 20 dBm threshold power level with low signal losses at zero bias. They also offer a promising solution in designing multilayer 3-D MMIC diode limiter circuit with other MMIC components.

Figure 19. Return loss comparison of ideal, simulated and measured results of the receiver protection limiter circuit.

Figure 20. Insertion loss comparison of ideal, simulated and measured results of the receiver protection limiter circuit.

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Figure 21. Measured output power versus input power of the receiver protection limiter circuit at 3 GHz.

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