OPAL-RT and ANSYS - HIL simulation
-
Upload
opal-rt-technologies -
Category
Technology
-
view
324 -
download
13
description
Transcript of OPAL-RT and ANSYS - HIL simulation
![Page 1: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/1.jpg)
Finite Element Based, FPGA-Implemented Electric
Machine Model for Hardware-in-the-Loop (HIL)
Simulation
Leveraging Simulation for Hybrid and Electric Powertrain Design in the Automotive,
Transportation, and Aerospace Industries
![Page 2: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/2.jpg)
2
Presentation Agenda
1. HIL Simulation by OPAL-RT – Introduction & Context
2. E-drive simulation - Why FPGA?
3. PMSM solver on FPGA
4. Integration of Maxwell FEA models and eDRIVEsim
5. Conclusion
6. Q&A
Leveraging Simulation for Hybrid and Electric Powertrain Design in the Automotive,
Transportation, and Aerospace Industries
![Page 3: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/3.jpg)
3
OPAL-RT Introduction
We supply real-time digital simulators to industry, research labs and educational institutions for hardware-in-the-loop (HIL), rapid control prototyping and accelerated non-realtime (number crunching) applications
![Page 4: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/4.jpg)
4
OPAL-RT: Turnkey HIL Simulators
We program sophisticated solvers and interfaces for real-time applications
We design full range I/O signal processing peripherals (modular mapping boxes, FIU, break out boxes)
We develop/integrate application models and solutions for various industries (automotive, aerospace, military, power utilities)
Hardware, software and integration for
real-time simulation and testing
![Page 5: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/5.jpg)
5
The Challenge of Electric Motor Control Testing testing
Faster time to market with parallel development and accelerated test: a proven approach with HIL simulation
![Page 6: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/6.jpg)
6
The Challenge of Electric Motor Control Testing testing
Motor control engineers want :
To test the motor controller with non-ideal behavior.
To test the motor controller with different points of operation, such a saturated states
To insert fault conditions
To rapidly simulate different types of motors
High-fidelity and flexible motor simulation
![Page 7: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/7.jpg)
7
The Challenge of Electric Motor Control Testing testing
• increase test case coverage
• reduce costs
• accelerate time to market
By reducing testing time on real dynamometer
By detecting errors at earlier stages of the design
Faster improvement of complex control strategies
Managers want to:
Creation of a technical link between motor designer
and control engineer – HIL model IS the design
![Page 8: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/8.jpg)
8
RT-LAB for ECU Testing and Validation
Virtual Plant
Electronic Control Unit (ECU) Under Test
![Page 9: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/9.jpg)
Model-based Design (MBD) & Hardware-in-the-Loop (HIL)
Validate
Model
Off-line simulation
Virtual Prototype
HIL, RT simulation
3D visualization
Control Prototype
HIL, RT simulation,
Physical Components
Design
Implementation
Production Code
Physical Components
Lab Testing
with actual
controller
Integration & Test
In-system commiss-
ioning & calibration
Deployment
Production
Maintenance
9
This implementation is
performed by the
software team
This implementation is
performed by the
control team
This implementation
is performed by the
integration team
Models become the method to share
information with disparate
development teams
RPC HIL
![Page 10: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/10.jpg)
10
Why use FPGA?
Macintosh prototype, 1980
Hang on… First, what’s an FPGA???
Well, Before FPGAs, years ago…
![Page 11: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/11.jpg)
11
What is an FPGA?
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Programmableinterconnect
Connection block
FPGA
Now in one integrated cirduit
![Page 12: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/12.jpg)
12
What is an FPGA?
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Programmableinterconnect
Connection block
Yeah, I’ve heard of Integrated Circuits! What’s an FPGA!?!?
Cells interconnection – Field programmable Gate Array
![Page 13: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/13.jpg)
13
What is an FPGA?
Logiccell
LUT
A
B
C
X
XA B C0
1
00
0
00
0
00
0
00
11 1
11
11
1 111
1
1
1100
0
0
X = (C if A = 0, B if A=1)
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Programmableinterconnect
Connection block
Inside a Virtex 5 Logic Cell
![Page 14: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/14.jpg)
14
FPGA for Parallel Computing
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Mu
ltip
lier
Mu
ltip
lier
RA
M m
em
ory
blo
ck
RA
M m
em
ory
blo
ck
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Mu
ltip
lier
RA
M m
em
ory
blo
ck
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
Logiccell
I/O
I/O
I/O
I/O
I/O
I/O
•OPAL-RT Analog inputs
•RT-LAB Digital inputs
•RT-LAB CPU Model
•OPAL-RT Analog Outputs
•RT-LAB Digital Outputs
•RT-LAB CPU Model
![Page 15: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/15.jpg)
15
Constraints
Limited Ressources
Logic Cells
Memory
LUTs
Etc.
Might not be possible to route the design
Propagation delays
Fixed Point calculation
Image Sourcre: http://www.student.uni-kl.de/~alles/fpga/pics/fpga-layout.jpg
![Page 16: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/16.jpg)
16
FPGAs in Numbers…
Virtex II
Pro(XC2VP7)
Virtex 5(XC5VSX50T
)
ML506
Virtex 6(XC6VLX240
T)
ML605
Spartan
III(XC3S500)
Arrays
(Row x Col) 40x34 120x34 46x34 46x34
Slices
(Logic
Cells)4,928 7,200 37,680 4,656
Flip-Flops 9,856 28,800 301,440 9,312
LUTs 9,856 28,800 150,720 9,312
Multipliers44
(18x18)
48
(25x18)
768
(25x18)
20
(18x18)
Block RAM 792kb 4,752kb 14,976kb 360kb
Virtex 5
![Page 17: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/17.jpg)
17
• Typically 3.3 GHz clock
• Operations are executed sequentially
• Floating point engine is embedded inside the
chip
• Typically 200 MHz clock
• No instruction, everything “executes” at the
same time
• Logic blocks are connected together
• Floating point is more challenging
(requires a lot of resources)
• Routing & dealing with delays are challenging
Recap
FPGA CPU
![Page 18: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/18.jpg)
18
Ok! Why FPGA for HIL then?
Physically near I/O
Low latency
Parallel signal processing
Rapidly improving capacity
Advantages compared to CPU-based model processing:
![Page 19: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/19.jpg)
19
Why (not) FPGA ?
Are complex to use
Lack flexibility
Have low fidelity
For most engineers, FPGAs:
HIL turnkey solutionfixed vs. floating point
Generic approach to FPGA
Implementation of ANSYS Maxwell FEA motor models
OPAL-RT’s answer
![Page 20: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/20.jpg)
20
PMSM Solver on FPGA
OPAL-RT latest developments:
CPU equivalent Step Time :5-20us
Model total Latency:15-40us
Step Time :100-450ns
Model total Latency:Below 2.5us
High fidelity modeling + High speed I/Os
OPAL-RT PMSM FPGA Solver
![Page 21: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/21.jpg)
21
PMSM Solver on FPGA
Upgrade of motor solver to latest FEA software levels
Streamlining of integration steps
Improvement of solver accuracy
OPAL-RT latest developments:
Solver compatible with PMSM spatial harmonics and VarDQ approach
Solver configuration ready in a few clicks with online reconfiguration of I/O mapping
Model entirely computed in floating point
![Page 22: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/22.jpg)
22
PMSM Solver on FPGA
Export Netlist from ANSYS Maxwell Software
Import Netlist into RT-LAB environment
Ready-for-Realtime
Implementation:
Precalculation of multiple operating points
Use RT-LAB to build your realtime simulation
Integrate I/O and any other required application peripherals
![Page 23: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/23.jpg)
OPAL-RT Benchmark Simulation
Maxwell 16.0
![Page 24: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/24.jpg)
OS Linux cluster specifications:
• Total CPUs (cores): 48
• Total hosts (nodes): 4
Large Scale Distributed Solve Option (LS-DSO)
Prius motor project
17195 variations
Cores used 48
IPM Motor Simulations on LS-DSO
![Page 25: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/25.jpg)
Maxwell Setup
![Page 26: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/26.jpg)
Maxwell Setup
Alignment of the initial rotor position is done
Flux linkage is maximum when theta = 0 and Iamp =0
![Page 27: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/27.jpg)
Parametric sweep table of 17195 rows:
• Beta = 0:20:360
• Theta = 0:0.25:45
• Iamp = 0:50:200
Parametric table was run on (LS-DSO)
Results post-processed using Matlab
Final Table:
• Beta = 0:5:360
• Theta = 0:0.25:45
• Iamp = [0,2.5,5,8,11,18,25,37.50,50,75,100,125,150,175,20]
Note: Results were post-processed using spline interpolation in Matlab
IPM Motor Simulations on LS-DSO
![Page 28: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/28.jpg)
Results – Flux Linkage
Flux linkage of phase U when Beta = 0 deg and Iamp = 0A
0 10 20 30 40 50 60 70 80 90-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
Theta, deg
fu
, W
eber
Flux Linkage of Phase U
![Page 29: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/29.jpg)
Results – Instantaneous Torque
Instantaneous torque of phase U when Beta = 45 deg and Iamp = 200A
0 5 10 15 20 25 30 35 40 45280
290
300
310
320
330
340
350
Theta, deg
To
rqu
e, N
.m
Instantaneous Torque
![Page 30: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/30.jpg)
Results – Instantaneous Torque
Instantaneous torque of phase U when Beta = 45 deg and Iamp = 200A
0 5 10 15 20 25 30 35 40 45280
290
300
310
320
330
340
350
Theta, deg
To
rqu
e, N
.m
Instantaneous Torque
![Page 31: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/31.jpg)
Results – Incremental Inductance
Incremental inductance of phase U when Beta = 45 deg and Iamp = 200A
0 5 10 15 20 25 30 35 40 451.5
2
2.5
3
3.5
4
4.5
5
5.5x 10
-5
Theta, deg
Lu
u,
H
Incremental Inductance
Note: Maxwell also can compute the incremental inductance when Iamp = 0
![Page 32: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/32.jpg)
Results – Average Torque
Average torque of phase U when Beta = 45 deg and Iamp = 200A
Note: For motor mode operation, Beta ranges from 0 deg to 90 deg which adheres to the alignment criteria shown in the phasor diagram
0 50 100 150 200 250 300 350-400
-300
-200
-100
0
100
200
300
400
Beta, deg
Ave
rag
e T
orq
ue,
N.m
Average Torque
![Page 33: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/33.jpg)
Results – Instantaneous Torque
Instantaneous Torque
![Page 34: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/34.jpg)
Results – Instantaneous Flux Linkage
Instantaneous Flux Linkage
![Page 35: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/35.jpg)
Results – Instantaneous Flux Linkage
Instantaneous Flux Linkage
![Page 36: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/36.jpg)
Speed-up factor and cores utilizations:
IPM Motor Simulations on LS-DSO
Number
of cores
Simulation time
(hours)
Speed-up
factor
Cores
utilization %
1 368.3 1 100%
6 63.7 5.7 95%
12 32.9 11.2 94%
24 16.2 22.8 95%
36 10.9 33.4 94%
48 8.0 46.1 96%
60 6.4 57.6 96%
96 4.2 90.0 94%
![Page 37: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/37.jpg)
Simulation time in log scale:
IPM Motor Simulations on LS-DSO
0 10 20 30 40 50 60 70 80 90 10010
0
101
102
103
Number of cores
Tim
e, h
ours
![Page 38: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/38.jpg)
Speed-up factor:
IPM Motor Simulations on LS-DSO
This graph shows that the simulation time is reduced linearly
with the increase of number of cores
0 20 40 60 80 1000
20
40
60
80
100
Number of cores
Sp
eed-u
p f
acto
r
![Page 39: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/39.jpg)
Results for all variations extracted using LSDSO extractor with –mergecsv option
Extraction of Results on LS-DSO
All results of the
variations are
combined in a
single CSV file
![Page 40: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/40.jpg)
– Plant model exported from Maxwell, is integrated with I/O & any peripheral plant model
components in Simulink to be compiled for real-time.
– Xilinx System Generator is a FPGA Simulink blockset
• No need to know VHDL language
– User can customize the I/O for complex applications
RT-LAB I/Os are fully programmable with Xilinx System Generator
A typical XSG model in RT-LAB
![Page 41: OPAL-RT and ANSYS - HIL simulation](https://reader030.fdocuments.us/reader030/viewer/2022012307/558ec9b71a28ab293c8b45af/html5/thumbnails/41.jpg)
41
Conclusion
FPGA will soon be the reference for HIL testing
High-fidelity HIL model on FPGA is a reality
Large scale parametric analysis of (example) Prius Motor was done to prepare data for OPAL-RT software using ANSYS Maxwell software
Motor prototyping is ready
Enhanced control algorithm validation is now possible on HIL
Faster test means lower cost
Motor and controller designer can work closely together –The exported Maxwell model (Design) IS the HIL plant model