On Pre-bond TSV Test Time reduction and Yield Improvement of 3D StackedICs

by

Bei Zhang

A dissertation submitted to the Graduate Faculty ofAuburn University

in partial fulfillment of therequirements for the Degree of

Doctor of Philosophy

Auburn, AlabamaDecember 10, 2014

Keywords: 3D IC, pre-bond TSV probing, test sessions, through silicon via (TSV) defects,wafer-on-wafer stacking, compound yield, sector symmetry and cut, cost analysis

Copyright 2014 by Bei Zhang

Approved by

Vishwani D. Agrawal, Chair, James J. Danaher Professor of Electrical & Computer Eng.Adit Singh, James B. Davis Professor of Electrical and Computer Engineering

Victor P. Nelson, Professor of Electrical and Computer Engineering

Abstract

Three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional

IC (2D IC), including heterogeneous integration, reduced delay and power dissipation, com-

pact device dimension, etc. However, to commercialize 3D IC products, still, many challenges

exist. In this dissertation, we focus on conquering two of these challenges. The first challenge

is to reduce pre-bond faulty TSV diagnosis time. The second challenge is to improve the

compound yield and reduce cost of wafer-on-wafer stacked 3D ICs. Novel ideas are proposed

and are demonstrated to be good solutions for these two challenges.

Pre-bond TSV testing and defect identification is extremely important for yield assur-

ance of 3D stacked devices. In this dissertation, we proposed a three-step optimization

method named “SOS3” to greatly reduce pre-bond TSV test time without losing the ca-

pability of identifying certain number of faulty TSVs. The three steps of optimization are

as follows. First, an ILP (integer linear programming) model is proposed to generate near-

optimal set of test sessions for pre-bond TSV diagnosis. The sessions generated by our ILP

model identify defective TSVs in a TSV network with the same capability as that of other

available heuristic methods, but with consistently reduced test time. Second, an iterative

greedy procedure to sort the order of test sessions is proposed. Third, a fast TSV identifica-

tion algorithm is proposed to actually diagnoses the faulty TSVs based on given test sessions.

Extensive experiments are done for various TSV networks and the results show SOS3 as a

framework greatly speeds up the pre-bond TSV test. SOS3 provides useful known-good-die

information for 3D die-on-die, die-on-wafer, and wafer-on-wafer stacking.

Wafer-on-wafer stacking offers practical advantages over die-on-die and die-on-wafer

stacking in 3D IC fabrication, but it suffers from low compound yield. To improve the

yield, a novel manipulation scheme of wafer named n-sector symmetry and cut (SSCn) is

ii

also proposed in this dissertation. In this method, wafers with rotational symmetry are cut

into n identical sectors, where n is a suitably chosen integer. The sectors are then used to

replenish repositories. The SSCn method is combined with best-pair matching algorithm

for compound yield evaluation. Simulation of wafers with nine different defect distributions

shows that previously known plain rotation of wafers offers only a trivial benefits in yield. A

cut number four is optimal for most of the defect models. The SSC4 provides significantly

higher yield and the advantage becomes more obvious with increase of the repository size

and the number of stacked layers. Cost model of SSCn is analyzed and the cost-effectiveness

of SSC4 is established. Observations made are: 1) Cost benefits of SSC4 become larger

as the manufacturing overhead of SSC4 become smaller, 2) cost improvement of SSC4 over

conventional basic method increases as the number of stacked layers increases and 3) for

most defect models, SSC4 largely reduces the cost even when manufacturing overhead of

SSC4 is considered to be very large.

iii

Acknowledgments

There are many people to whom I want to say a thousand thanks. First, I would like

to thank my advisor Professor Vishwani D. Agrawal. When I got stucked in my research, he

is always there for guidance and more importantly, encouragement. No matter how simple

the question is, he always answers with extreme patience and points me to many useful

references. He always puts himself in the students’ position, and give them lots of care not

only in academic research but also in their ordinary lives.

I would also like to thank Dr. Adit Singh and Dr. Victor Nelson for serving as my

committee members. Dr Singh’s VLSI Testing course serves as the starting point of my PhD

research. From Dr. Nelson’s Computer-Aided Design Course, I learned how to use various

useful tools like DFTAdvisor, Fastscan, IC station, etc. I would like to thank Prof. Xiao

Qin for agreeing to be my external reader.

I would also like to thank my colleagues in my department, especially, Chao Han, Baohu

Li, Guangjie Huang, Yingsong Huang, Jiao Yu, Hua Mu, and Xing Wu, Tiantian Xie, etc.

It is them who make my life in Auburn more joyful.

Above all, I would like to thank my parents for their constant support. Without them,

I wouldn’t even have the chance to study in the US.

Finally, I must acknowledge that the research presented in this dissertation, is supported

in part by the National Science Foundation Grants CCF-1116213, IIP-0738088 and IIP-

1266036.

iv

Table of Contents

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Various 3D Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Fabrication of TSV-based 3D Stacked ICs . . . . . . . . . . . . . . . . . . . 3

1.2.1 TSV Fabrication Process, Characteristics, and Possible Defects . . . . 3

1.2.2 3D IC Stacking Orientations and Stacking scales . . . . . . . . . . . . 8

1.3 3D IC Testing Issues and Emerging Solutions . . . . . . . . . . . . . . . . . 10

1.3.1 2D Versus 3D Test Moments . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.2 Pre-bond TSV Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.3 Emerging Test Standard for 3D ICs . . . . . . . . . . . . . . . . . . . 15

1.4 Other Challenges of 3D Stacking Technology . . . . . . . . . . . . . . . . . . 18

1.5 Organization of Dissertaion . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2 Test Session Optimization for Pre-bond TSV Probing in 3D Stacked ICs . . . . 21

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2 ILP Model for Test Session Generation with Specified Identification Capability 23

2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3 An Optimal Probing Method of Pre-Bond TSV Fault Identification in 3D Stacked

ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

v

3.2 A Dynamically Optimized TSV Identification Algorithm . . . . . . . . . . . 34

3.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4 SOS3: Three-Step Optimization of Pre-Bond TSV Test for 3D Stacked ICs . . . 38

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2 Probabilistic Analysis of Number of Faulty TSVs Within a TSV Network . . 38

4.3 An Iterative Greedy Procedure for Test Session Scheduling . . . . . . . . . . 40

4.4 A Three-step Test Time Optimization Simulator . . . . . . . . . . . . . . . . 44

4.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5 A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction

of 3D Wafer-on-Wafer Stacked ICs . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.3 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.1 Defect Distributions on a Wafer . . . . . . . . . . . . . . . . . . . . . 55

5.3.2 Wafers with Rotational Symmetry . . . . . . . . . . . . . . . . . . . . 57

5.3.3 Running Repository Based Best-pair Matching Algorithm . . . . . . . 57

5.3.4 Matching Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.5 A Hybrid Wafer-on-Wafer Stacking Procedure . . . . . . . . . . . . . 59

5.4 Sector Symmetry and Cut for Yield Improvement . . . . . . . . . . . . . . . 59

5.4.1 Wafers Cut into Sectors . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.4.2 Sector Symmetry and Cut . . . . . . . . . . . . . . . . . . . . . . . . 61

5.4.3 Discussion on the Number of Cuts . . . . . . . . . . . . . . . . . . . . 62

5.4.4 Summing it up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

vi

5.5.2 Comparison of Various Stacking Procedures for Different Defect Dis-

tributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.5.3 Impact of Number of Stacked Layers on Compound Yield . . . . . . . 73

5.5.4 Impact of Production Size on Compound Yield . . . . . . . . . . . . 73

5.6 Cost Effectiveness of Sector Symmetry and Cut Method . . . . . . . . . . . 76

5.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

A Impact of Number of Cuts on Final Production Size of Good 3D ICs . . . . . . 93

vii

List of Figures

1.1 TSV Process Sequence showing etch, CVD oxide, PVD Ti/Cu, Cu electroplating

and CMP for 10x100 µm vias [19]. . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 RC circuit model of defect-free blind and open-sleeve TSVs. . . . . . . . . . . . 6

1.3 RC model of resistance defective TSV and capacitance defective TSVs. . . . . . 7

1.4 Illustration of different die stacking orientations. . . . . . . . . . . . . . . . . . . 8

1.5 Illustration of Die-on-Die stacking. . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.6 Illustration of Die-on-Wafer stacking. . . . . . . . . . . . . . . . . . . . . . . . . 9

1.7 Illustration of Wafer-on-Wafer stacking. . . . . . . . . . . . . . . . . . . . . . . 10

1.8 Illustration of test moments of 2D and 3D ICs. . . . . . . . . . . . . . . . . . . 11

1.9 Illustration of pre-bond TSV probing. . . . . . . . . . . . . . . . . . . . . . . . 14

1.10 Circuit model for pre-bond TSV probing. . . . . . . . . . . . . . . . . . . . . . 15

1.11 Conceptual illustration of IEEE P1838 standard architecture and wrapper for a

3-die stack with flip chip bumps on the bottom die [42]. . . . . . . . . . . . . . 16

1.12 Various test moments supported by P1838 standard. . . . . . . . . . . . . . . . 18

2.1 ILP model 1 for finding near-optimal test sessions with specified identification

capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

viii

2.2 Test time comparison between ILP model 1 and heuristic [40] for a 20-TSV network. 29

2.3 Test time comparison between ILP model 1 and heuristic [40] for resolution con-

straint r = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.4 Comparison of number of sessions between ILP model 1 and heuristic [40] for

resolution constraint r = 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1 A dynamically optimized TSV identification algorithm. . . . . . . . . . . . . . . 34

4.1 Pseudo-code for iterative test session sorting. . . . . . . . . . . . . . . . . . . . 43

4.2 Three-step test time optimization simulator. . . . . . . . . . . . . . . . . . . . . 45

5.1 Wafer-on-wafer stacking procedures. . . . . . . . . . . . . . . . . . . . . . . . . 54

5.2 Gray maps showing the yield level distribution on the wafer. . . . . . . . . . . . 56

5.3 Wafer maps showing rotational symmetry. . . . . . . . . . . . . . . . . . . . . . 57

5.4 A conventional wafer cut into four sectors. . . . . . . . . . . . . . . . . . . . . . 60

5.5 Cutting a rotationally symmetric wafer into identical subwafers. . . . . . . . . . 61

5.6 Illustration of die loss for cutting the wafer into 6 sectors. . . . . . . . . . . . . 62

5.7 Two different ways of placing dies on a rotationally symmetric wafer. . . . . . . 63

5.8 Calculation of DPW1 for sector placement method 1. . . . . . . . . . . . . . . 64

5.9 Calculation of DPW2 for sector placement method 2. . . . . . . . . . . . . . . 65

5.10 Calculation of DPW2 of 3-cuts for sector placement method 2. . . . . . . . . . 66

5.11 DPW1 and DPW2 versus number of cuts for placement methods 1 and 2. . . . 67

ix

5.12 Process flow of sector symmetry and cut method. . . . . . . . . . . . . . . . . . 68

5.13 Yield improvement by various stacking procedures for different defect distribution

patterns of Figure 5.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.14 Normalized yield for various stacking methods versus number of stacked layers

for different defect distribution patterns of Figure 5.2. . . . . . . . . . . . . . . 74

5.15 Yield reduction for various defect distributions (Figure 5.2) as production size

increases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

A.1 Exploring the impact of number n of cuts on final production size of good 3D

ICs produced by the sector symmetry and cut (SSCn) procedure. . . . . . . . . 94

x

List of Tables

2.1 Capacitor charging time of parallel TSV test [50]. . . . . . . . . . . . . . . . . . 22

3.1 Exhaustive and dynamically optimized (Figure 3.1) application of TSV test ses-sions constructed by ILP model 1. . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1 Probability of different number of failing TSVs φ within a 15-TSV network. . . 40

4.2 Expectation of number of tested sessions, defect clustering coefficient α = 1, datashows (sessions for SOS2, sessions for SOS3, reduction by SOS3). . . . . . . . . 47

4.3 Expectation of test time (µs), defect clustering coefficient α = 1, data shows (testtime for SOS2, test time for SOS3, reduction by SOS3). . . . . . . . . . . . . . 47

5.1 Geometrical parameters for dies per wafer (DPW) calculation. . . . . . . . . . . 63

5.2 Wafer manipulation methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.3 Cost improvement percentage for SSC4 over basic under various defect distribu-tions (Figure 5.2) and for number of staking layers (l) ranging from 2 to 6. . . . 80

xi

Chapter 1

Introduction

1.1 Various 3D Technologies

Currently, there are several 3D IC integration technologies. Examples are monolithic

3D, system in package (SIP), package on package (POP), and 3D stacked IC technology. By

allowing higher component density, these 3D techniques are mainly favored in applications

with small footprint requirement, such as mobile phones, digital cameras, etc.

In monolithic manufacturing, multiple device layer are grown on the same wafer. After

the first device layer and the corresponding interconnects are finished, a dielectric layer such

as SiO2 is deposited. The isolation layer is then polished to allow the growth of the second

device layer. This process is repeated so that multiple layers can grow in a serial manner.

Communications between different device layers are provided by vias etched through the

dielectric layer. Monolithic 3D IC provides high via density, and possibly smaller mask

count. The biggest obstacle to achieve monolithic 3D devices is that the thermal processing

of upper silicon layer can disturb the already processed devices and interconnects underneath.

The system in package (SIP) technique is also known as chip stack MCM (multi-chip

module). In this technique, multiple chips are stacked vertically and enclosed in a single

package. Communications between internal dies are provided by wire bonds. Communication

to the outside world can be either provided by wires or flip chip bumps. In package on package

technique (POP), multiple packaged chips are stacked vertically. The signal routing between

packaged chips is provided by a standard interface. Within each packaged chip, wire bond

is always used to connect the IO pad on the die to the package solder balls. Both SIP and

POP enable heterogeneous system integration which means that dies in the stack may have

different functions may even be fabricated by different vendors. Dies within the stack can

1

be optimized according to their own technologies [14, 31, 34]. Both SIP and POP also offer

benefit of smaller footprint. However, both techniques are based on wiring interconnects

which is power consuming and incurs large delay.

The current industry trend is in favor of 3D stacked IC technology. To achieve higher

levels of integration, multiple dies of active electronic component are stacked vertically in

a 3D IC. We call a die within a 3D stacked IC a layer. Connections between layers are

provided by through silicon vias (TSVs) [7, 19, 33, 46]. TSVs are short and reduce the

need for long interconnects as required on planar ICs, thus reducing the delay and power

consumption [14, 64, 65]. 3D stacked IC also offers heterogeneous integration and smaller

device footprint, which is desirable in hand-held devices. Though challenges remain, the 3D

stacked IC is a very hot topic in recent ten years. Several experimental chips and commercial

chips are emerging successively.

The earliest experimental 3D stacked chip is a 3D version of the Pentium 4 CPU pre-

sented by Intel in 2004 [8]. This chip contains two dies stacked face-to-face. By arranging

functional blocks manually in these two dies, the 3D version offers 15% performance im-

provement and also 15% less power consumption than the 2D version. In 2007, Intel again

introduced the Teraflops research chip [9]. This is an experimental 80-core design with

stacked memory. By implementing a TSV-based memory bus, the total bandwidth of the

chip reaches 1 TB per second while consuming much less power than traditional I/O ap-

proach. The first academic 3D stacked processor was presented in 2008 at the university of

Rochester [51]. After that, two more 3D-stacked-IC-based multi-core design were presented

in International Solid-State Circuits Conference in 2012 [30, 21]. These two chips utilize

Tezzazon’s FaStack technology and are fabricated by GlobalFoundry with 130 nm process.

The above mentioned chips are mostly experimental chips and thus not involved in volume

production. In July 23, 2013, Xilinx announced the world’s first commercial heterogeneous

stacked 3D IC, i.e. the Virtex-7 H80T FPGA [1]. Two weeks later, Samsung Electronics

announced the industry’s first 3D stacked NAND flash memory which offers much higher

2

Figure 1.1: TSV Process Sequence showing etch, CVD oxide, PVD Ti/Cu, Cu electroplatingand CMP for 10x100 µm vias [19].

device density than any existing NAND flash technology [2]. As researchers continue push-

ing the 3D stacking technology forward, more and more commercialized 3D products are

expected to emerge in the near future.

This dissertation focuses on 3D stacking technology. For the rest of this work, 3D

stacked IC and 3D stacking technology are called 3D IC or 3D technology for simplicity.

1.2 Fabrication of TSV-based 3D Stacked ICs

1.2.1 TSV Fabrication Process, Characteristics, and Possible Defects

TSVs act as the media to transport power supply and signals among stacks of a 3D

stacked IC. Because of its essential role in 3D IC, its fabrication is critical. Figure 1.1

illustrates the five fabrication steps of TSVs [19].

The first step of TSV fabrication is via drilling. In this step, vias are always etched

by DRIE (deep reactive ion etching) technique [27]. During etching, slightly tapered side

wall (typically desired to be in the range of 83 to 89 degrees [39]) is always preferred to

improve the step coverage of the following deposition of SiO2 insulation layer, the barrier

layer, and the seed layer. The second step is insulation layer deposition. In this step, either

SACVD (semi-atmosphere chemical vapor deposition) or low-temperature PECVD (plasma

enhanced chemical vapor deposition) is used [6]. The third step is barrier and seed layer

deposition which is always achieved through PVD (physical vapor deposition) process [6].

3

The fourth step is via filling. Periodic pulse reverse (PPR) current plating is demonstrated

to be the most popular and successful way in via filling [32].. Different materials can be used

for via filling, such as copper, tungsten, doped polysilicon [6]. The most popular material is

copper due to high conducting property and its compatibility to the conventional interconnect

processing [6]. For vias with large size, poly-silicon is preferred because deposition of poly-

silicon is much slower than copper which results in a denser deposition that can stand higher

stress. The final step of fabrication is CMP (chemical mechanical polishing [27]) which is

utilized to thin the wafer so as to expose the buried TSV tips for subsequent die stacking.

When to fabricate TSVs in the complete fabrication flow of a layer? Well, there can be

three different schemes.

1. “Via first before FEOL” which means TSVs are formed before the FEOL (front-end of

the line) [32][45]. The front-end-of-line is the first portion of IC fabrication where the

individual devices (transistors, capacitors, resistors, etc.) are patterned in the semi-

conductor. FEOL generally covers everything up to (but not including) the deposition

of metal interconnect layers. Because there will be further high-temperature (over

1000 degrees) CMOS fabrication process, the filling material should have the ability to

withstand high temperature. From this aspect of concern, the filling material is always

chosen as poly-silicon. Refilling poly-silicon requires narrow feature, so this process

requires the width of the via to be typically smaller than 5 µm. The wafer needs to

be finally thinned to about 150 µm, which means the etched down via needs to have

depth with at least 150 µm. This makes the high aspect ratio of the TSV (150:5 or

30:1), and thus brings more challenges in fabrication. The advantage of this scheme is

that no barrier and seed layer is needed, and the isolation layer can be easily achieved

by traditional oxidation process.

2. “Via first after BEOL” (also called ”Via last” in [32]) which means TSVs are formed

after the back-end of the line (BEOL) of IC fabrication. The back end of line (BEOL)

4

is the second portion of IC fabrication where the individual devices (transistors, ca-

pacitors, resistors, etc.) get interconnected with wiring on the wafer. In this scheme,

TSVs are formed after the completion of the CMOS chip but before wafer thinning.

Because the CMOS device is completed and the passivation layer is already formed,

no further high-thermal requirement process will be needed. We can fill the via with

copper which brings better electrical and thermal properties compared to poly-silicon.

Since there is no narrow-feature requirements anymore, the TSV can be made with

relatively lower aspect ratio (ranging from 3:1 to 7:1 [45]).

3. “Via last after BEOL” which means TSVs are formed after the IC is fabricated and

the wafer is thinned [45]. In this scheme, the wafer is already bonded with adhesive

onto the wafer carrier. To protect the wafer ever fabricated and the adhesive, the

temperature needs to be specially controlled to be not above 200 degrees. Also during

fabrication of TSVs, chemical materials need to be selected such that they wouldn’t

(or slowly) attack the IC layer.

Generally speaking, fabricating TSVs in different schemes may require different tech-

niques to be used in the five steps of TSV fabrication mentioned above.

Before bonding, only one end of the TSV is connected to active circuitry. If the other

end of a TSV is completely insulated by surrounding oxide before thinning or exposed after

thinning, then the TSV is called blind TSV [12, 42]. If the other end is surrounded by and

shorted to bulk silicon before thinning, then the TSV is called open-sleeve TSV [12, 42].

The characteristics of blind and open-sleeve TSVs are different and thus require different

testing strategies. Figure 1.2 shows the RC circuit model of blind and open-sleeve TSV,

respectively. Note that for simplicity the barrier and seed layer are not shown in these

figures. The resistance R of an experimental copper TSV with 2-5 µm diameter and 5 µm

height is 80-200 µΩ [42].The capacitance C of an experimental copper TSV with 1-10 µm

diameter and 30-100 µm height is 10-200 fF [42].

5

Substrate

Insulator

RTSV

CTSV

Substrate

Insulator

RTSV

CTSV

Substrate

Insulator

RTSV

CTSV

(a) Buried blind TSV (b) Exposed blind TSV (c) Open-sleeve TSV

Figure 1.2: RC circuit model of defect-free blind and open-sleeve TSVs.

Defects can be introduced during manufacturing process of TSVs (pre-bond defects) or

during the die assembly process (post-bond defects). Thus, testing of TSVs is important as

a single irreparable defective TSV may cause the entire stack to fail. TSVs can be tested

before die bonding (pre-bond) or after die bonding (post-bond). Post-bond testing targets

defects caused by TSV misalignment, mechanical stress, thermal issues, etc. Post-bond TSV

test has been extensively studied [26, 35, 37, 47] and TSVs after bonding are basically treated

as wires. Post-bond TSV testing can also be easily conducted by employing the developing

IEEE P1838 standard [35, 37, 42].

Pre-bond TSV test is much more challenging. Also, the majority of TSV defects can

happen before bonding. For example, reference [11] illustrates 11 possible defect types of

TSVs where 6 of them occur before bonding. We focus on introducing pre-bond TSV defects

for the rest of this section.

According to [11], pre-bond TSV defects include:

1) Micro-void in the TSV pillar, caused by electronic migration and will increase the TSV

resistance.

2) Complete breakage in TSV pillar, caused by improper handling of thinned wafers and

will results in an open path within the TSV.

6

Substrate

InsulatorRTSV1

CTSV2

RTSV2

CTSV1

Rvoid

(a) Resistance-defective TSV

Substrate

Insulator

CTSV

RTSV

Rleak

(b) Capacitance-defective TSV

Figure 1.3: RC model of resistance defective TSV and capacitance defective TSVs.

3) TSV pillar filling failure, i.e., the TSV pillar is not fully filled. For example, only the

left half cylinder is filled by copper. This defect can happen if the seed layer is not

deposited uniformly in the third step of TSV fabrication process. Partially filled TSV

pillar has larger resistance than the nominal value.

4) Impurity (like foreign particle) between TSV and the micro-bump. This will increase

the contact resistance between TSV and its micro-bump.

5) TSV pillar is delaminated from the substrate, which may be caused by thermal stress

of fabrication process. This defect will form an open path between TSV pillar and the

microbump.

6) Pinhole within the insulation layer, which forms a conducting path from TSV to the

substrate. This leakage path largely increases the capacitance between the TSV and

the substrate.

Of the six listed defects, five of them are resistive in nature, i.e., increasing the TSV

resistance. Only the last one, i.e., the pinhole defect results in capacitance changes. Fig-

ure 1.3(a) shows the RC circuit model for the resistance defective TSVs. Figure 1.3(b) shows

the RC model of the capacitance defective TSV with pinhole defect [42].

7

TSV

Bulk Silicon

Face (tier 2)Bonding

pad

Face (tier 1)

C4 bump Face (tier 2)

Face (tier 1)

C4 bump

TSV

landing

pads

TSV

TSV

TSV

landing

pads

C4 bump

Bulk Silicon

Face (tier 1)

Face (tier 2)

Face (tier 3)

(a) Face-to-Face (b) Back-to-Back (c) Face-to-Back

Figure 1.4: Illustration of different die stacking orientations.

1.2.2 3D IC Stacking Orientations and Stacking scales

To stack a die on another die in 3D IC fabrication, the stacking orientation can be of

multiple options. In other words, we can stack two dies face-to-face, back-to-back, or face-

to-back. Here, face refers to the front side of a die containing active circuitry. Back refers to

the back side of the die containing bulk silicon. TSVs are buried in the back side and can

be exposed by wafer grinding.

Figure 1.4 illustrates these three different stacking orientations. In the figure, we assume

the fabricated 3D IC has flip-chip package, i.e., the communications to the outside world are

provided by the flip-chip C4 bumps locating at the face side of the bottom die.

Face-to-face stacking offers the highest via density between two dies since the face-side

bonding pads can be much smaller than TSV landing pads. Compared to face-to-face stack-

ing, the via density of back-to-back stacking is much smaller. Moreover, instead of fabricating

TSVs in only one layer, the back-to-back stacking requires TSVs to be fabricated in both

layers. Fabrication of additional TSVs incurs higher cost and increase the risk of having

defective TSVs. Thus, back-to-back stacking is not likely to be used in practice. Neither

face-to-face nor back-to-back scales well to stacks with more than two layers. However, in

face-to-back stacking, additional layer can be added to the stack in a repeated way, i.e., the

exposed TSV tips on the back side of lower layer are bonded to dedicated TSV landing pads

on the face side of a layer higher in stack. Thus, any number of layers can be accommodated

8

1 1

1 1

2 2

2 2

Figure 1.5: Illustration of Die-on-Die stacking.

1 1

1 1

2 2

2 2

Figure 1.6: Illustration of Die-on-Wafer stacking.

in face-to-back stacking. Because of this flexibility of multiple layer stacking, face-to-back

stacking is most likely to be utilized in practice. In Figure 1.4, we show copper-to-copper

direct bonding between two layers. Sometimes microbumps are sticked to TSV landing pads

for bonding purpose.

To fabricate a 3D IC, the stacking scales can vary. There are 3 difference stacking scales,

namely, die-on-die stacking, die-on-wafer stacking, and wafer-on-wafer stacking. For the later

two stacking scales, wafer dicing is required to obtain individual 3D stack. Figures 1.5, 1.6,

and 1.7 illustrate these 3 stacking scales, respectively. For all 3 stacking scales, pre-bond

wafer test is necessary to provide known-good-die (KGD) information. The KGD information

helps improve the yield by avoiding stacking a bad die on a good die (or good stack) and

9

1 1

1 1

2 2

2 2

1 1

1 1

Figure 1.7: Illustration of Wafer-on-Wafer stacking.

wasting the good die (or good stack). Without pre-bond test, yield of 3D IC can decrease

exponentially with the number of stacked layers, and 3D IC will never be commercialized.

Among these three stacking scales, wafer-on-wafer stacking is very attractive. It offers

the highest production throughput since each stacking produces a large number of stacked

ICs. Wafer-on-wafer stacking also avoids the costly process of pick-and-place required for the

other two stacking scales. Other advantages of wafer-on-wafer stacking include smaller die

sizes, thinner wafers, and higher TSV density [48, 55, 66]. Although the other two stacking

scales offer higher final yield, they are harder to handle, stack, and process, besides being

more expensive [18, 52]. The biggest drawback of wafer-on-wafer stacking is that even with

KGD information sometimes we cannot avoid stacking a good die on a bad die. Thus, the

yield of wafer-on-wafer stacking is a bottle neck. Nonetheless, this weakness can be compen-

sated by developing advanced wafer matching algorithms or advanced wafer manipulation

methods. More details of wafer-on-wafer stacking will be illustrated in section 5.

1.3 3D IC Testing Issues and Emerging Solutions

1.3.1 2D Versus 3D Test Moments

There are 2 test moments of conventional 2D chips. The first is wafer probing test. The

second is final test after chip assembly and packaging. 3D IC testing is more complex with

10

Wafer

Wafer

probing test

Assembly &

Package

Final test

(a) 2D test moments

Wafer 1

Pre-bond

wafer test

Wafer 2

Pre-bond

wafer test

Wafer n

Pre-bond

wafer test

Stacking

1+2

Partial

stack test

Stacking

1+2+...

Partial

stack test

Stacking

1+2+…+n

Post-bond

test

Assembly

& Package

Final test

(b) 3D test moments

Figure 1.8: Illustration of test moments of 2D and 3D ICs.

more test moments. Figure 1.8 illustrates the various test moments of 2D and 3D chips,

respectively.

Seen from Figure 1.8(b), for a 3D IC containing n layers, there can be 2n test moments.

1) n pre-bond test moments. Pre-bond test is necessary as it helps avoid the situation

where a single bad die pollutes a complete 3D stack.

2) n− 2 partial stack test moments (also called mid-bond test moments).

3) One post-bond test moment of the complete stack before assembly and packaging.

Post-bond test avoids bad stack to be packaged.

4) One final test moment of the packaged 3D IC. Final test assures the quality of 3D

chips shipped to customers.

Each of these 2n test moments includes two test conditions, i.e. the TSV test and the

circuitry test. Thus in total, there are 2× 2n = 4n test conditions for a n-layer 3D IC.

11

1.3.2 Pre-bond TSV Test

As mentioned in section 1.3.1, pre-bond testing contains circuit level testing and TSV

testing. Pre-bond circuit level testing can be handled by the IEEE P1838 standard as will

be illustrated in the next section. Moreover, P1838 standard facilitates TSV test and circuit

test after die bonding as well. Among the 4n test conditions of a 3D IC, all except the n

pre-bond TSV test conditions can be handled by the developing standard. Thus, in this

section, we focus on the more challenging problem of pre-bond TSV testing.

Pre-bond TSV test targets defects arising during wafer manufacturing, such as a void

within a TSV, a complete break in a TSV, a pinhole creating a leakage path between TSV

and substrate, etc. Pre-bond TSV testing is important as it helps identify defective dies early

in the process and avoid situations where one single bad die causes entire 3D stack to be

discarded. It is also necessary in providing known good die (KGD) information for die-to-die

or die-to-wafer fabrication process. Even for wafer-on-wafer stacking, pre-bond TSV test

helps in better wafer matching and thus improves the yield [76, 81, 48, 52, 53, 55, 59, 61, 66].

The pre-bond TSV testing is challenging mainly because before-bonding a TSV is single

ended, i.e., one of its ends is not connected to any circuitry. For pre-bond TSV test, we can

test on a still thick wafer. In that case, the TSVs are deeply buried in the wafer substrate

without any test access. This requires special per-TSV DFT circuit (e.g., BIST) to test

the TSVs with only single-sided access. Several built-in self-test (BIST) techniques have

been proposed for buried TSVs, such as, the use of a voltage division circuit to measure

the leakage resistance of TSVs and detect pinhole defects [13], or a DRAM and ROM-like

test to determine the RC time constant and resistance of blind TSVs and open-sleeve TSVs,

respectively [12]. Ring Oscillators have been widely used to characterize the propagation

delay of TSVs and thus diagnose possible resistive open or leakage defects [16, 74]. All

BIST approaches require dedicated circuit to be added for each individual TSV, and the

area overhead is huge since there can be tens of thousands of TSVs on a chip [29, 68].

Moreover, the BIST circuits themselves suffer from process variation, which may render them

12

totally useless. An alternative is to test thinned wafers where TSV tips are exposed. This

requires special facilities to probe thinned wafers (about 50 µm thick) without damaging

them. However, the relatively large pitch (40 µm) of current probing technology [54, 70]

prohibits individual TSV probing with a realistic pitch of 10 µm [29, 44].

A pre-bond TSV probing method has been recently proposed [41] where several TSVs are

contacted by a single probe needle defining a TSV network. The number T of TSVs within

a network is typically less than 20 and depends on the relative diameter of the probe needle

and the pitch of TSVs [29, 42, 44, 54, 70]. TSV parametric test can be conducted by adding

an active driver in the probe needle and forming a charge sharing circuit between single (or

multiple) TSV(s) and the probe needle. This probing method offers robustness to process

variation, requires less hardware overhead, provides accurate measurement of TSV resistance,

and has many more benefits as explained in the original proposal [40, 41, 42]. One possible

concern for current utilization of this technique is that the planarity of TSV tips may not be

consistent and could prevent a large probe needle from making good electrical contacts with

all TSVs in a network, simultaneously. However, the great benefits offered by the probing

method serves as a driving force for both foundry and test equipment manufacturer to work

together and find a solution.

Figure 1.9 illustrates how a probe needle contacts two TSVs on the backside of a thinned

die. As can be seen, gated scan flip-flops (GSF) are inserted between system logic and TSVs

which is in accordance with the developing IEEE P1838 standard [37, 42]. Among the two

TSVs, the left side TSV is a receiving TSV which receives signal from the other die and

drives the on-chip logic while the right side one is a sending TSV which is driven by the

on-chip logic and sends a signal to the other die. In the normal mode, all GSFs are made

transparent by opening B2 and closing B1 switches by a “bypass” signal. Then, the receiving

TSV in Figure 1.9 feeds signal from the other die to the input of an OR gate, and the sending

TSV is driven by the output of an AND gate on the current die.

13

Substrate

Face (active circuitry)

B1

B2GSF

Sub

stra

te

Fac

e

B2

B1

GSF

Scan chain

Probe needle

Sending

TSV

Receiving

TSV

Q D

D Q

Figure 1.9: Illustration of pre-bond TSV probing.

Figure 1.10 shows the circuit model of the probing test set up [41, 42] for a example

4-TSV network. TSV i is represented by its resistance Ri and capacitance Ci. Rc represents

the contact resistance between TSV and the probe. Rp represents probe needle resistance.

A gated scan flip-flop is inserted between TSV i and the system logic. All GSFs can be

loaded up or read out through a boundary scan mechanism. In the normal mode, all GSFs

are made transparent. In the pre-bond TSV test mode, all GSFs drive respective TSVs. In

Figure 1.10, TSVs 1 and 2 are receiving TSVs and TSVs 3 and 4 are sending TSVs. A GSF

in scan mode drives a receiving TSV during pre-bond TSV probing when both B1 and B2

switches are closed. A GSF drives a sending TSV when B1 is opened and B2 is closed.

The above technique facilities both TSV resistance measurement and capacitance mea-

surement. For example, pre-bond TSV resistance measurement starts by scanning in all

GSFs with “1.” Ccharge and all TSVs are then discharged through the probe needle. By

configuring the switches of a GSF, a charge sharing circuit is constructed between that GSF

and Ccharge through its corresponding TSV (either sending or receiving TSV). The charging

rate of Ccharge is compared to a calibrated curve of a good TSV to determine the resistance

14

Sy

stem

lo

gic

TSV 1

TSV 2

TSV 3

TSV 4

C1

C2

C3

C4

R1

R2

R3

R4

Rc

Rc

Rc

Rc

Rp

Volt

Meter

Ccharge

S1 S2

V1

Probe

Voltage

Source

B1

B2

B1

B2

GSF

GSF

GSF

GSF

Scan

chain

B1

B2

B1

B2

D

D

D

D

Q

Q

Q

Q

TSVsOn-chip circuitry Probe head and ATE

Figure 1.10: Circuit model for pre-bond TSV probing.

of the TSV under test. The discharging and charging process continues for each TSV which

can be completed quickly by sequentially configuring the switches of one GSF at a time so

that there is always one GSF driving one TSV. The probe needle remains contacted with the

corresponding TSV network, and the charging and discharging process continues until either

all TSVs within the network are identified or a certain number of TSVs with resistive defects

are pinpointed within the network. All TSV networks are tested in two groups. Networks

in a group are tested simultaneously by a probe head containing a large number of needles,

each making contact with a single network. Once all contacted networks are tested, the

probe head is lifted and repositioned to test the remaining group [41, 42]. Thus, all TSVs

on chip can be tested by just two touch downs [41, 42]

1.3.3 Emerging Test Standard for 3D ICs

In order to provide a standard test access of 3D stacked ICs, the IEEE P1838 work-group

is developing test access architecture and die wrappers specific for 3D IC [35, 37, 42]. This

standard assumes the circuit is partitioned in module level and thus enables modular testing

of a 3D IC. Modular testing refers to an approach in which the various modules constituting

15

Figure 1.11: Conceptual illustration of IEEE P1838 standard architecture and wrapper fora 3-die stack with flip chip bumps on the bottom die [42].

an IC product can be tested separately. The various modules of a 3D IC include each die, its

embedded cores, TSVs between two dies, and external pins mounted on printed circuit board

(PCB). By enabling modular testing, scheduling of pre-bond test, mid-bond test, post-bond

test, and final test can be completely flexible. This flexibility makes it easier to find the

most cost-effective test flow for a specific 3D IC manufacturing process.

A conceptual example of a 3-die stack wrapped in accordance to P1838 test standard is

shown in Figure 1.11 [42]. Based on the standard, a die wrapper is added to each die in the

stack, which is the additional DFT architecture that most characterizes P1838 standard. The

die wrapper can be compatible with the IEEE 1500 standard. Note that for the bottom die,

besides the IEEE 1500 die wrapper, there is also an IEEE 1149.1 TAP controller to enable

board level testing after 3D IC is mounted on PCB. The wrapper instruction registers of

all 1500 die wrappers are controlled by the bottom IEEE 1149.1 TAP controller. Each die

16

may contain several embedded cores, these cores are wrapped by IEEE 1500 wrappers as

well. There exists a hierarchical relationship between a die wrapper and its embedded core

wrappers so that the test mode of a core wrapper can be controlled by the up-level die

wrapper [35, 42].

Seen from Figure 1.11, there are large probe pads added on each die except for the

bottom die. These pads enables individual contact to a probe needle. The probe pads

together with the die wrapper enables pre-bond circuit level testing for each non-bottom

die. For the bottom die, there are already large flip chip bumps which directly enables

pre-bond probing, thus no large pads are needed.

In this paragraph, we introduced how P1838 standard supports mid-bond testing. If a

upper die is bonded to a lower die, e.g. die 2 is bonded to die 1 in Figure 1.11, the probe pads

of die 2 are not available anymore. To test die 2, instead of applying test stimuli through die

2 pads, dedicated test TSVs (TTSVs in Figure 1.11, also called test elevators) are used to

carry data from die 1 pads all the way up to die 2 and also route test data back to the pads

of die 1. The arrows in Figure 1.11 shows the data flow direction throughout the stack. Note

that to enable circuitry testing of die 2, the die 1 wrapper need to be set in Bypass mode so

that test data can bypass die 1 and be routed to die 2 directly. To test die 1 in this mid-bond

phase, the die 1 wrapper need to be set in Test Turn mode which means the test data will

be directly applied to die 1 without moving upward to die 2. P1838 wrapper also enables

mid-bond TSV testing. By setting the die wrappers of both die 1 and die 2 to Extest mode,

all TTSVs as well as functional TSVs (FTSVs in Figure 1.11) between these 2 dies can also

be tested to detect any TSV defects occur during bonding. Specifically, test data is shifted

in the wrapper boundary registers (WBR) of both die 1 and die 2, forming a daisy chain.

From WBRs, the data is then applied to the TSVs between these two dies and responses are

latched in WBRs. The latched responses are then shifted out to the dedicated probing pads

on die 1 for faulty TSV diagnosis. To sum up, the TTSVs, probe pads, altogether with the

die wrappers enables both mid-bond circuitry testing and TSV testing.

17

Pre-bond testMid-bond, Post-bond, and

Final testBoard-level test

Circuit test

(Intest)

Circuit test

(Intest)

TSV test

(Extest)

PCB interconnect test

(Extest)

IEEE P1838 Standard

Figure 1.12: Various test moments supported by P1838 standard.

After all dies are stacked, post-bond test is conducted. Post-bond circuitry test and

TSV test resembles mid-bond test a lot. For example, to test die 1 in Figure 1.11, die 0

wrapper need to be set in Bypass mode, and die 1 wrapper need to be set in Test Turn mode.

The only difference between post-bond and mid-bond test is that for post-bond testing test

data must come from and also be routed down to the flip chip bumps on the bottom die.

This is not always the case for mid-bond testing unless the bottom die is also bonded during

the mid-bond phase. Final test after packaging is conducted in exactly the same way as

post-bond test.

Figure 1.12 shows all possible test moments supported by P1838 standard. Note again

P1838 standard cannot directly support pre-bond TSV test. The probing technique men-

tioned in section 1.3.2 provides a practical way for pre-bond TSV testing. It is compatible

with P1838 standard since it utilizes the wrapper boundary registers (WBRs) within the die

wrapper. The TSV probing technique in section 1.3.2 served as the basis for our discussions

in chapter 2, 3 and 4.

1.4 Other Challenges of 3D Stacking Technology

There are still many challenges to commercialize 3D IC technology. For wafer-on-wafer

stacking, wafer need to be thinned down to be bonded to another wafer. New intra-die

defects may occur during grinding, alignment, and bonding processes which are unique to

3D IC fabrication. Thus new fault models and test patterns need to be created accordingly

to identify the new defects [31, 38].

18

Resolving the thermal issues of 3D IC is another challenge [14, 31, 38]. A typical 3D

IC consists of multiple dies and has smaller footprint than the 2D version. Thus the area

for heat radiation becomes smaller for a 3D IC. The heat accumulation inside the stack may

severely increase circuit delay and thus outweighs the benefit of small interconnect delay a

3D IC offers.

Test access mechanism design and test scheduling has been extensively studied for 2D

SOCs [36, 22, 63]. However, for 3D IC containing core-based dies, new constraints need to be

considered during the test architecture design. One important constraint is that the number

of TSVs used for test access (TTSVs) should not exceed a certain value, because TSVs have

area overhead and are potential source of defects [69, 43].

As mentioned, for a n-tier 3D IC, there are 2n test moments. Each test moment can

include just TSV test, or just circuit test, or both of them, or none of them. This makes

the search space for most cost-effective test flow overwhelming. For a specific manufacturing

process, it would be very challenging but important to not only decide which test moments

need to be included in the entire test flow but also to decide what should be tested (TSVs,

or circuit, or both, or none) for each test moment. Finding an optimal test flow helps greatly

reduce the cost of 3D ICs, and progresses are making in this area [59, 24, 60, 66].

Since the number of TSVs on-chip can reach tens of thousands [29, 68], the DFT engi-

neers need to keep in mind that there are probably several faulty TSVs after die bonding.

To avoid discarding the stack with faulty TSVs, implementing an efficient TSV redundancy

architecture to replace faulty TSVs with redundant good ones is pretty important and also

challenging [73, 28, 82, 25]. There are lots of rules to follow when designing the TSV re-

dundancy architecture. First, the total number of redundant TSVs cannot be too large

since the keep-out zone of a TSV occupy a large silicon area and is thus costly. Second,

the associated circuit overhead for faulty TSVs replacement and signal rerouting should be

low within the architecture. Third, the architecture should put higher priority on rescuing

signal TSVs instead of power or clock TSVs. TSVs for power delivery and clock distribution

19

always form a connected graph and are more immune to defects [31]. Last but not least, the

architecture need to be able to replace faulty TSVs which are likely to be clustered in local

silicon area [28, 82].

1.5 Organization of Dissertaion

The rest of this dissertation is organized as follows. Chapter 2, 3, and 4 focus on

minimizing the identification time of faulty TSVs during pre-bond TSV probing. To be more

specific, chapter 2 addresses the problem of test session generation for pre-bond TSV probing.

An ILP (integer linear programming) based method for near-optimal test session generation

is proposed. Chapter 3 proposed a fast TSV identification algorithm which identifies faulty

TSVs based on the generated test sessions. In chapter 4, we first proposed an iterative

greedy procedure to sort the order of test sessions. Then, this iterative session sorting

procedure is combined with the ILP method in chapter 2 and the fast TSV identification

algorithm in chapter 3. The combination of these 3 pieces of work form a framework called

“3-Step test time Optimization Simulator (SOS3)” which greatly speeds up pre-bond faulty

TSV identification process. Chapter 5 introduced a novel wafer manipulation method called

“Sector Symmetry and Cut n (SSCn)” which improves the compound yield and reduces the

cost of wafer-on-wafer stacking. The work of chapter 2 to chapter 4 serves as the basis of

chapter 5 since it helps provide known good die (KGD) information for wafer matching in

chapter 5. Finally, chapter 6 concludes this dissertation.

20

Chapter 2

Test Session Optimization for Pre-bond TSV Probing in 3D Stacked ICs

2.1 Introduction

The bulk of TSV defects that can be tested before bonding result in increase of TSV

resistance [11], so pinpointing TSV resistive defects is very important. Considering the

relative sizes of typical test probes and TSVs, an earlier proposal [41] uses a large probe

needle with active driver to contact multiple TSVs at a time, as illustrated in section 1.3.2.

In section 1.3.2, it is stated that TSV before bonding can be tested individually using

the probing technique by configuring one GSF to drive one TSV at a time. However, parallel

TSV test can also be conducted by configuring multiple GSFs at a time so that multiple

GSFs can drive multiple TSVs simultaneously. In parallel testing, Ccharge is charged faster

and the measurement terminates even quicker [41, 42]. However, there is also a constraint,

i.e. the number of TSVs tested in parallel cannot exceed a constant “r” due to minimum

measurement resolution requirement [41, 42]. This resolution of measurement refers to the

minimum change in TSV resistance that can be detected by the probing technique and it

is adversely affected by the number of TSVs tested in parallel. We call the TSVs tested in

parallel within the same TSV network a test session. Based on the probing technique in

section 1.3.2 [41, 42], any faulty TSV within a session will cause the session test to fail but

we cannot tell which TSV(s) is (are) faulty. On the other hand, a good parallel test implies

that all TSVs within the session are fault-free.

SPICE simulation of a TSV probe setup was done using the PTM (predictive technology

model [4]) 45nm technology [40, 41, 42, 50], and the capacitance charging time as a function

of the number of TSVs tested in parallel is recorded in Table 2.1. Note that test time in this

work only refers to the time to charge the capacitor Ccharge, same as [40].

21

Table 2.1: Capacitor charging time of parallel TSV test [50].

Number of TSVs tested Charging timein parallel (q) t(q) (µs)

1 0.802 0.533 0.424 0.38

The goal of TSV probing is to identify up to a certain number, m, of faulty TSVs

within a T TSV network where m is the number of redundant TSVs in the TSV network

being tested. If the number of identified faulty TSVs exceeds m, then not all faulty TSVs

in the network can be repaired, and the chip would be discarded. Otherwise, the on-chip

redundant TSVs are sufficient to replace all identified faulty ones. This goal of TSV probing

can be achieved by testing one TSV at a time with highest resistance measurement resolution.

However such a high resolution is unnecessary. Besides, the single-TSV session takes longer

test time, according to Table 2.1. Moreover, instead of identifying all faulty TSVs, only up

to m faulty TSVs need to be pinpointed in a network. Significant test time saving is possible

if we test TSVs in parallel without losing the capability of identifying up to m faulty TSVs,

and also guarantee that the size of each test session does not exceed the resolution constraint

r.

Reference [40] proposes a heuristic to generate such test sessions. However, the results

are far from being optimal due to the greedy nature of the heuristic. For example, to pinpoint

1 faulty TSV in a 6-TSV network with minimum resolution constraint of r = 4, the heuristic

based sessions are 1,2,3,4, 1,5,6, 2,5, 3,6, 4 [40]. A careful examination shows the

last session 4 is useless as the first 4 sessions uniquely identify any single faulty TSV. After

removing 4, the remaining sessions are still non-optimal as an optimal result is 1,2,3,

1,4,5, 2,4,6, 3,5,6, which further reduces test time by 9.7%, according to Table 2.1.

The above example motivates us to find a way to generate optimal set of test sessions with

minimum test time.

22

In this chapter, we address the problem of test session generation for pre-bond TSV

probing, with focus on minimizing the identification time of faulty TSVs. We propose an

integer linear programming (ILP) based method for session generation that can greatly

reduce test time compared to the heuristic method [40]. For example, to locate up to 2

faulty TSVs in a 11-TSV network, our method can reduce test time by 38.2% over the

heuristic method [40].

We define the following terminologies.

1) TSV network. A TSV network is formed by all the TSVs that are simultaneously

contacted to the same probe needle.

2) Test session. During pre-bond TSV probing, TSVs tested in parallel within the same

TSV network form a test session.

3) Session size. Session size q is defined as the number of TSVs within a session.

4) Resolution constraint. Resolution constraint r indicates that the session size should

never exceed r.

5) Test time of a session. Test time of a session in this paper only refers to the charging

time of Ccharge. It is related to the session size (refer to Table 2.1).

6) Maximum number of faulty TSVs to identify within a network. This number m equals

to the number of redundant TSVs in the TSV network being tested.

2.2 ILP Model for Test Session Generation with Specified Identification Capa-

bility

In this section, we propose an integer linear programming (ILP) model (named ILP

model 1) to find near-optimal set of test sessions. The problem is formulated as follow:

Problem 2.2.1. Given the test time t(q) for test session size q, q ∈ [1, r], and the

maximum number m of faulty TSVs within a T -TSV network, determine a series of test

23

sessions (each of size less than r) so that up to m faulty TSVs can be uniquely identified

and the total test time is minimized.

A sufficient condition to solve Problem 2.2.1 is as follows.

Condition 2.2.1. If each TSV (TSVi) is put inm+1 test sessions, S1, S2, · · · , Sm+1, and

the intersection of any two out of these m+1 sessions contain only TSVi, i.e., Sj⋂Sk = TSVi

for j 6= k ∈ [1,m+1], then up tom faulty TSVs within the network can be uniquely identified.

We refer to those m+ 1 sessions satisfying condition 1 as m+ 1 unique test sessions for

TSVi. A unique test session for TSVi is defined as a session whose intersection with any other

session containing TSVi consists of only TSVi. We prove the sufficiency of Condition 2.2.1

by first stating the following theorem.

Theorem 2.2.1. Given that there are no more than m faulty TSVs within a network.

If a good TSV, TSVi, belongs to m + 1 unique test sessions, then we can find at least one

out of these m+ 1 sessions which consists of only good TSVs.

We prove Theorem 2.2.1 by contraposition.

Proof of theorem 2.2.1. Given there are up to m faulty TSVs within a network.

Suppose each unique test session for TSVi contains at least one faulty TSV. Because of the

“unique” identity of these m + 1 sessions, the faulty TSVs within each session should be

different. We conclude that there will be at least m + 1 faulty TSVs within the network,

which is obviously a contradiction to the given condition that says there are at most m faulty

TSVs. In other words, at least one unique session for TSVi would contain only good TSVs.

Next, we prove Condition 2.2.1 is a sufficient condition for solving Problem 2.2.1.

Proof of sufficiency. According to Theorem 2.2.1, Condition 2.2.1 will guarantee that

for any good TSV (let’s say TSVi) there will be at least one unique session (let’s say session

Sj) consists of only good TSVs. The testing result of Sj would suggest that all TSVs within

Sj to be fault-free. Thus, we uniquely identify TSVi as a good TSV. If all good TSVs are

identified, then all defective TSVs are too.

24

Proof of non-necessity. The non-necessity of Condition 2.2.1 is proved by considering

a simple example. In sequential testing, all TSVs can be uniquely identified but each TSV

resides in only one session.

The ILP model proposed in this section is based on Condition 2.2.1. We first summarize

all general constraints for our ILP model as follows:

1. C1. Each TSV should reside in at least m+ 1 sessions.

2. C2. The size of a test session ranges anywhere from 0 (empty session) to r.

3. C3. We suppose any non-empty session is a unique session for any TSV within it.

An upper bound Nup on total number of sessions can be calculated as,

Nup =⌈t(1)

t(r)· T⌉

(2.1)

where r is resolution constraint, t(1) and t(r) are test times for sessions with sizes 1 and r,

respectively. If the total number of sessions N is larger than Nup, then even if all sessions

have size r the total test time is still larger than that of sequential testing. This upper bound

constrains the maximum number of sessions produced by the ILP model presented next.

A binary variable xij (1 ≤ i ≤ T, 1 ≤ j ≤ Nup) is defined as follows:

xij =

1 if TSVi is assigned to session Sj

0 otherwise

(2.2)

From C1, we haveNup∑j=1

xij ≥ m+ 1 (2.3)

We define an integer variable Lj, which denotes the size of session Sj,

Lj =T∑i=1

xij (2.4)

25

From C2, we have

0 ≤ Lj ≤ r (2.5)

Based on C3, if ∃ xij · xik = 1 for any i and any j 6= k ∈ [1, Nup], thenT∑i=1

xij · xik = 1. C3

also implies that the intersection of any two different sessions Sj and Sk should contain no

more than a single TSV, thus,

∣∣∣Sj⋂Sk

∣∣∣ =T∑i=1

xij · xik ≤ 1 (2.6)

Constraint (2.6) is obviously nonlinear. To linearize it, we further introduce a binary variable

zijk = xij · xik and two more linear constraints:

xij + xik − zijk ≤ 1 (2.7)

xij + xik − 2 · zijk ≥ 0 (2.8)

According to these constraints if xij = 0, then zijk ≤ xik2

. Since both xik and zijk are binary

variables, zijk has to be zero. If xij = 1, xik ≤ zijk ≤ 0.5 + 0.5xik, and we conclude, zijk = xik.

Thus, constraints (2.7) and (2.8) guarantee zijk = xij ·xik. With zijk, constraint (2.6) becomes

T∑i=1

zijk ≤ 1 (2.9)

The objective of the ILP model is to minimize the total test time of all sessions:

Minimize

Nup∑j=1

t(Lj) (2.10)

Both Lj and t(Lj) are variables, we need to linearize the objective function so that any

commercial ILP solver can be used. A new binary variable δjq (1 ≤ j ≤ Nup, 0 ≤ q ≤ r) is

26

introduced:

δjq =

1 if session Sj contains q TSVs

0 otherwise

(2.11)

With equation (2.11), t(Lj) =r∑q=0

δjq · t(q). In addition, the following two constraints should

be included in the model:

Lj =r∑q=0

q · δjq (2.12)

which indicates that a session can have 0 to r TSVs. Also,

r∑q=0

δjq = 1 (2.13)

indicating that the size of a session should be unique. For every session Sj, there will be

exactly one value of q for which δjq = 1. Therefore, δjq determines the size of Sj. We can

rewrite the objective function as

Minimize

Nup∑j=1

r∑q=0

δjq · t(q) (2.14)

The testing time for different session size t(q) is a constant obtained from SPICE sim-

ulation as shown in Table 2.1. Thus, the objective function is linearized.

The complete ILP model is summarized in Figure 2.1. Both the number of variables

and number of constraints (a measure of the complexity of the problem) of the ILP model

is O(N2upT ). For the example of Section 2.1, the ILP model produces 4 optimal test sessions

in less than 3 seconds. Note that a globally optimal set of sessions is not guaranteed by this

ILP model since the model is based on Condition 2.2.1 which is a non-necessary condition

for solving Problem 2.2.1.

Obviously, the sessions generated by ILP model 1 guarantee that all TSVs can be

identified if the total number of faulty TSVs in a TSV network does not exceed m. If there

27

1; [1, ], [1, ]ij ik ijk upx x z i T j k N ! " # $ # % $

Objective:

Subject to:1 0

Minimize ( )upN r

jq

j q

t q ! !

"##

2 0; [1, ], [1, ]ij ik ijk upx x z i T j k N ! " # $ # % $

1

1; [1, ]T

ijk up

i

z j k N

! " # $%

1

; [1, ]T

j ij up

i

L x j N

! "#

0 ; [1, ]j upL r j N ! "

1

1; [1, ]upN

ij

j

x m i T

! " # $%

0

; [1, ]r

j jq up

q

L q j N !

! " # $%

0

1; [1, ]r

jq up

q

j N !

! " #$

1)

2)

3)

4)

5)

6)

7)

8)

Figure 2.1: ILP model 1 for finding near-optimal test sessions with specified identificationcapability.

are more than m faulty TSVs within a network, by testing the sessions produced by ILP

model 1, two possible situations may occur. First, not all TSVs can be uniquely identified

as either being good or bad. Second, all TSVs are identified but the number of faulty TSVs

is larger than m. In both situations, we conclude that there are more than m faulty TSVs

within the network and the chip can be discarded. Therefore, the sessions provided by ILP

model 1 can always help make the right decision to either replace the identified bad TSVs

or discard the chip as having too many faulty TSVs within a local silicon area.

2.3 Experimental Results

In this section, we compare the total test time and total number of sessions for the

proposed ILP model 1, the heuristic method [40], and sequential TSV testing. Sequential

TSV testing refers to testing each TSV within a network sequentially and individually. For

ease of comparison, same as [40], we just simply assume all the generated sessions need to

be tested. The relative test time ratio in this section refers to the ratio of total test time

28

r=2 r=3 r=4 r=2 r=3 r=4 r=3 r=4 r=40%

20%

40%

60%

80%

100%

Rela

tiv

e T

est

Tim

e R

ati

o

Heuristics [11]

ILP model

Maximum Number of Faulty TSVs to Identify

m=1 m=2 m=3 m=4

4.3%

13.5%

5.0%

0.0%

11.0%

24.7%

13.0%

25.8%

25.3%

1

Figure 2.2: Test time comparison between ILP model 1 and heuristic [40] for a 20-TSVnetwork.

to the total time of sequential TSV testing. Note again the test time in this work considers

only the time to charge the capacitor and does not account for the time to move the probe

card [40]. In all the figures, we only show the cases where relative test time ratio is smaller

than 100%. For the cases not shown, sequential testing each TSV is more time-efficient than

the other two methods. The ILP model 1 is solved using a commercial solver named CPLEX

from IBM [3]. In all situations, the solver outputs the results in less than 40 seconds.

Figure 2.2 shows the relative test time ratio for both ILP model 1 and heuristic method

considering different resolution constraint r ∈ [2, 4] and different value of m ∈ [1, 4] in a 20-

TSV network. Note the results of ILP model 1 is always less than the results of heuristics.

The number corresponding to each bar pair represents the relative test time improvement

of ILP model 1 over heuristic. As can be seen from Figure 2.2, for a given r, the relative

test time ratio for both methods increases as m increases since pinpointing larger number

of defective TSVs requires more sessions and takes longer time. For the same m, larger

r offers smaller test time ratio because now a session can hold more TSVs with less test

time. Moreover, the total number of sessions generally decreases for larger r. Also, note that

ILP model 1 always helps reduce test time further compared to the heuristic method, and

29

the improvement generally increases as m increases. This demonstrates that for small m,

the heuristic may behave well but as m increases, outputs of the heuristic method deviate

farther away from the optimal results. The largest improvement of ILP model 1 over heuristic

method reaches 25.8% which happens when T = 20, m = 3 and r = 4.

Figure 2.3 examines the impact of number of TSVs within a network T on relative test

time ratio. We simulate 4 networks of different sizes with m ∈ [1, 4] and r fixed at 3. As can

be seen the ILP model 1 reduces test time further compared to heuristics regardless of the

value of T . This relative improvement can reach as large as 38.2% as shown on top of the bar

pair corresponding to T = 11, m = 2. It is also interesting to observe that the relative test

time ratio of ILP model 1 remains pretty consistent across different values of T for a given

m. While for the heuristics, the test time ratio varies a lot for different network sizes. For

example, when m = 2, the relative test time ratio of heuristics for a 11-TSV network is much

larger than those for other networks. The unstable performance of the heuristic method is

mainly due to its greedy nature in generating test sessions. These observations suggest that

the proposed ILP model 1 is more robust across variations of TSV network parameters, and

thus could eliminate the need for redesign and optimization of each individual TSV network

on chip as required in the heuristic method [40].

We show the total number of test sessions generated by the two methods for 4 different

networks in Figure 2.4 where r is fixed at 4 and m ∈ [1, 4]. The number on top of each bar

T=7 T=9 T=11 T=15 T=7 T=9 T=11 T=15 T=9 T=11 T=15 T=150%

20%

40%

60%

80%

100%

Rela

tiv

e T

est

Tim

e R

ati

o

Heuristics [11]

ILP model

m=1 m=2 m=3 m=4

Maximum Number of Faulty TSVs to Identify

17.0% 23.9%8.0% 16.7%

3.0%18.0%

38.2%

9.5%

23.7%26.2%

18.6%5.4%

1

Figure 2.3: Test time comparison between ILP model 1 and heuristic [40] for resolutionconstraint r = 3.

30

T=8 T=12 T=16 T=20 T=8 T=12 T=16 T=20 T=12 T=16 T=20 T=16 T=200

10

20

30

Nu

mb

er

of

Test

Sess

ion

s

Heuristics [11]

ILP model

m=1 m=2 m=3 m=4

Maximum Number of Faulty TSVs to Identify

11.1%11.8%

20.0% 0.0%

0.0%14.3%

13.0% 16.7%

10.7%

0.0%

0.0% 0.0%

14.3%

1

Figure 2.4: Comparison of number of sessions between ILP model 1 and heuristic [40] forresolution constraint r = 4.

pair represents the relative reduction of total session number of ILP model 1 over heuristics.

As expected, generally a smaller number of sessions is produced for smaller m. For a larger

TSV network, it is possible to reduce test time with number of test sessions larger than the

total number of TSVs (i.e., T ). As can be seen, the ILP model 1 sometimes produces the

same number of sessions as the heuristic. However, our experimental results demonstrate

that though the number of sessions produced by both methods can be the same, the sessions

themselves are different. Sessions produced by ILP model 1 is guaranteed to be more time-

efficient. For example, for T = 8,m = 1, r = 4 and T = 8,m = 2, r = 4, ILP model

1 produces same number of sessions as the heuristic but with test time reduced by 5.8%

and 12.5%, respectively. In most cases, ILP model 1 helps reduce total number of sessions

compared to the heuristic. For example, for T = 16,m = 4, r = 4, 4 out of 24 sessions can

be further eliminated representing 16.7% relative reduction.

2.4 Conclusion

An ILP based model is proposed to generate near-optimal set of test sessions for pre-

bond TSV probing. Extensive experiments demonstrate that ILP model 1 always reduces

pre-bond TSV identification time compared to previous heuristic method. Moreover, the

test time reduction of the ILP model remain consistent for various TSV networks, and thus

eliminates the need for separately designing and optimizing the test for each TSV network

31

as required by previous work. The proposed ILP model 1 is expected to significantly reduce

pre-bond TSV test cost in real silicon. Our model is based on a sufficient but non-necessary

condition for test session generation which still leaves space for future explorations, such

as, possibly finding a necessary and sufficient condition to generate globally optimal set of

sessions.

32

Chapter 3

An Optimal Probing Method of Pre-Bond TSV Fault Identification in 3D Stacked ICs

3.1 Introduction

For ease of the following illustration, let us first define the following terminologies.

1) Fault map ρ. Fault map ρ represents positions of all defective TSVs within the network.

2) Worst fault map. Worst faulty map for a given TSV network refers to a fault map

which takes most sessions to identify.

We define |ρ| as the number of faulty TSVs within a fault map ρ. Test sessions generated

by ILP model 1 are near-optimal which guarantee that all fault maps with |ρ| ≤ m can be

uniquely identified. However, a careful observation [77] shows that for identifying most of

the fault maps with |ρ| ≤ m, only a small portion of the total sessions need to be tested.

Let’s mention the example in section 2.1 again. For T = 6, m = 1, r = 4, ILP model 1

generated four optimal test sessions which are 1,2,3, 1,4,5, 2,4,6, 3,5,6. if TSV1

is faulty, all 4 sessions need to be tested to identify it, but if TSV6 is faulty only the first

3 sessions need to be tested to pinpoint it. By testing only 3 out of 4 sessions, test time

is further save by 25%. This observation further motivates us to develop an algorithm to

terminate the test as soon as our goal of identification is reached.

In this chapter, we proposes a fast dynamically optimized TSV identification algorithm

to further speed up pre-bond TSV test from two aspects. First, during the identification

process, any “currently unnecessary” session is skipped. Second, TSV test is terminated as

soon as either all TSVs have been identified or the number of identified faulty TSV exceeds

m as the chip can be discarded due to lack of redundant TSVs and further test is useless.

33

Algorithm Fast_TSV_Identification (All_sessions, T, m, t)

1. Good=[ ]; Bad=[ ]; F_C=[ ]; test_time=0; tested_sessions=0;

2. foreach session in All_sessions

// Skip any currently unnecessary test session

3. if (all TSVs in session have been identified) or

(there is at least one bad TSV in session)

4. Continue;

5. test_time+=t(session); // Test time accumulation

6. tested_sessions+=1; // Test session accumulation

// Handle a passing session

7. if session is tested as being good

8. Add all TSVs in session to Good;

9. foreach FC_session in F_C

10. Remove any good TSV from FC_session;

11. if length(FC_session)==1

12. Add the TSV in FC_session to Bad;

13. Remove the entire FC_session from F_C;

// Handle a failing session

14. else if session is tested as being bad

15. Remove any good TSV from session;

16. if length(session)==1

17. Add the TSV in session to Bad;

18. else

19. Append session to F_C;

// Termination conditions

20. if ((length(Good)+length(Bad))==T or (length(Bad)>=m+1)

21. Break;

22. Return test_time, tested_sessions;

Figure 3.1: A dynamically optimized TSV identification algorithm.

3.2 A Dynamically Optimized TSV Identification Algorithm

The pseudo-code of the algorithm is shown in Figure 3.1 where argument t represents

the test time of sessions. Test time of a session in this work only refers to the charging

time of Ccharge, and it is related to the session size as seen from Table 2.1 [40, 42, 79]. The

algorithm starts by initializing 3 empty lists named “Good”, “Bad”, and “F C”, respectively.

The “Good” and “Bad” lists are used to contain the identified good and faulty TSVs, respec-

tively. The faulty candidate list “F C” is used to contain any failing session. The algorithm

enumerates all the sessions generated by [42] or [79] and skip any “currently unnecessary”

session which refers to a session where either all TSVs in the session have been identified

so far or there is at least one identified bad TSV in the session. “currently unnecessary”

34

session does not provide any information of TSV identification. Although a session may

be “currently unnecessary” for identifying some fault maps of a TSV network, it could be

essential for identifying other fault maps of the same TSV network. So, none of the “cur-

rently unnecessary” sessions can be deleted. If a session is not skipped, it will be tested.

If a session passes the test, all TSVs in the session are added to “Good”, and we then use

“Good” to refine “F C.” Here, the refinement refers to removing any identified good TSV

from the targeted session (see line 10 of Figure 3.1). If after refinement any failing session

in “F C” contains only one TSV, that TSV is identified as defective and added to “Bad.”

If a session fails the test, “Good” is again utilized to refine this failing session (line 15 of

Figure 3.1). If the session after refinement contains only one TSV, that TSV is added to

“Bad.” Otherwise, the refined failing session is appended to “F C.” The above procedure

terminates as soon as any condition shown on line 20 in Figure 3.1 is satisfied.

3.3 Experimental Results

Table 3.1 shows the results of the proposed algorithm applied to various TSV networks.

Column 1 shows parameters T (network size), m (redundant TSVs in network) and r (res-

olution constraint). Column 2 gives the number of faulty TSVs (φ) within the network.

Column 3 shows the total number of sessions and total test time (in µs) for exhaustive ap-

plication of sessions optimized by ILP model 1 [79]. The test time calculation is detailed

in references [40, 42] and [79]. For a given value of φ, we enumerate all possible fault maps

and obtain the test time and number of tested sessions using the proposed algorithm of

Figure 3.1. Column 4 shows the average number of tested sessions and average test time for

identifying all fault maps containing φ faulty TSVs. Column 5 shows the relative reduction

in column 4 over column 3. Column 6 shows the maximum number of sessions tested and the

corresponding test time for identifying a fault map. Column 7 shows the relative reduction

in column 6 over column 3.

35

Tab

le3.

1:E

xhau

stiv

ean

ddynam

ical

lyop

tim

ized

(Fig

ure

3.1)

applica

tion

ofT

SV

test

sess

ions

const

ruct

edby

ILP

model

1.

Para

met

ers

Nu

mb

erof

Op

tim

um

exh

au

stiv

eD

yn

am

ically

op

tim

ized

test

fau

lty

TS

Vs

test

[79]

Av.

test

sess

ion

sA

ver

age

red

uct

ion

Wors

tca

sese

ssio

ns

Wors

tca

sere

du

ctio

n

T,m

,r

(φ)

(#se

ssio

ns,

tim

einµ

s)(#

use

d,

tim

einµ

s)(s

essi

on

s,ti

me)

(#u

sed

,ti

me

inµ

s)(s

essi

on

s,ti

me)

0(5

.0,

2.1

0)

(37.5

%,

37.5

%)

(5,

2.1

0)

(37.5

%,

37.5

%)

8,

2,

31

(8,

3.3

6)

(5.3

,2.2

5)

(32.8

%,

32.8

%)

(6,

2.5

2)

(25.0

%,

25.0

%)

2(6

.4,

2.7

1)

(19.1

%,

19.1

%)

(8,

3.3

6)

(0.0

%,

0.0

%)

3(7

.5,

3.1

7)

(5.3

%,

5.3

%)

(8,

3.3

6)

(0.0

%,

0.0

%)

0(7

.0,

2.9

4)

(56.2

%,

56.2

%)

(7,

2.9

4)

(56.2

%,

56.2

%)

1(7

.5,

3.1

4)

(53.1

%,

53.1

%)

(9,

3.7

8)

(43.7

%,

43.7

%)

12,

3,

32

(16,

6.7

2)

(8.7

,3.6

5)

(45.5

%,

45.5

%)

(12,

5.0

4)

(25.0

%,

25.0

%)

3(1

0.3

,4.3

2)

(35.5

%,

35.5

%)

(14,

5.8

8)

(12.5

%,

12.4

%)

4(1

1.8

,4.9

7)

(25.9

%,

25.9

%)

(16,

6.7

2)

(0.0

%,

0.0

%)

0(8

.0,

3.3

6)

(68.0

%,

68.0

%)

(8,

3.3

6)

(68.0

%,

68.0

%)

1(9

.6,

4.0

3)

(61.6

%,

61.6

%)

(14,

5.8

8)

(44.0

%,

44.0

%)

15,

4,

32

(25,

10.5

0)

(11.1

,4.6

8)

(55.3

%,

55.3

%)

(17,

7.1

4)

(32.0

%,

32.0

%)

3(1

2.6

,5.3

3)

(49.2

%,

49.2

%)

(20,

8.4

0)

(20.0

%,

20.0

%)

4(1

4.3

,6.0

3)

(42.5

%,

42.5

%)

(23,

9.6

6)

(8.0

%,

8.0

%)

5(1

5.8

,6.6

6)

(36.5

%,

36.5

%)

(25,

10.5

0)

(0.0

%,

0.0

%)

0(9

.0,

3.4

2)

(64.0

%,

63.9

%)

(9,

3.4

2)

(64.0

%,

63.9

%)

1(1

0.8

,4.1

0)

(56.8

%,

56.7

%)

(15,

5.6

9)

(40.0

%,

39.9

%)

20,

4,

42

(25,

9.5

0)

(12.3

,4.6

8)

(50.6

%,

50.6

%)

(18,

6.8

3)

(28.0

%,

27.9

%)

3(1

3.9

,5.3

1)

(44.0

%,

44.0

%)

(21,

7.9

7)

(16.0

%,

15.9

%)

4(1

5.1

,5.7

6)

(39.3

%,

39.3

%)

(24,

9.1

1)

(4.0

%,

3.9

%)

5(1

8.0

,6.8

5)

(27.8

%,

27.8

%)

(25,

9.4

9)

(0.0

%,

0.0

%)

36

We made four observations from Table 3.1. First, the average number of tested sessions

and average test time is much less than the total number of sessions and total test time for

any φ ≤ m (reparable TSV network) or any φ > m (irreparable TSV network). For example,

the average percentage reduction reaches 68.0% for parameters T = 15, m = 4, r = 3, and

φ = 0. On average, the proposed algorithm greatly speeds up pre-bond TSV identification

process. Second, as φ increases the average percentage reduction decreases. This is expected

as pinpointing larger number of faulty TSVs within a TSV network generally requires more

sessions to be tested and cost more time. Third, in most cases even the maximum number of

tested sessions is less than the total number of sessions. Fourth, as expected, the maximum

number of tested sessions increases as φ increases for a given TSV network. From column 7,

reduction in the worst case can be small for large φ, requiring all sessions to identify a fault

map. This scenario occurs when fault map contains m or more faulty TSVs. The probability

of such large number of faulty TSVs within a small localized silicon area may be negligible

for a mature manufacturing process. Thus, the worst case percentage test time reduction

could be quite significant.

3.4 Conclusion

The proposed TSV identification algorithm has two main advantages. First, the average

number of tested sessions and test time are guaranteed to be small factions of total sessions

and test time. Second, even for the worst fault map, for which most sessions are needed, not

all sessions may be used, i.e., time saving can occur even in worst case scenarios. Reducing

pre-bond TSV test time reduces pre-bond test cost.

37

Chapter 4

SOS3: Three-Step Optimization of Pre-Bond TSV Test for 3D Stacked ICs

4.1 Introduction

In real silicon, TSV yield is expected to be more than 99% [5]. We calculated the

probability of different number of failing TSVs within a TSV network considering different

TSV defect distributions. The results suggest that the probability of φ faults within a TSV

network decreases dramatically as φ increases. This observation motivates us to emphasize

the application order of test sessions so that pre-bond TSV test can be terminated as soon as

possible. We make two contributions in this chapter. First, we propose an iterative greedy

procedure for session sorting. Second, we combine the iterative greedy procedure with the

ILP model 1 in chapter 2 and the TSV identification algorithm in chapter 3 and form a 3-

Step test time Optimization Simulator (“SOS3”) [78]. SOS3 consists of three steps, namely,

ILP-based session generation, iterative greedy procedure for session sorting, and fast TSV

identification algorithm for early test termination. Each step provides inputs to the next. In

the experimental section, we calculate the test time expectation for various TSV networks.

The results demonstrate that session sorting procedure plays an important role in SOS3 as

it helps further reduce test time expectation by as large as 31.8%. We also observe that with

SOS3 the expectation of TSV identification time is much less than the total time of testing

all sessions.

4.2 Probabilistic Analysis of Number of Faulty TSVs Within a TSV Network

In this section, we analyze the probability of different number of faulty TSVs within a

network. TSV defect distributions can be broadly classified as two types, namely independent

38

defect distribution [82] and clustered defect distribution [58, 82]. For independent TSV

defect distribution, the failing probability of a TSV is independent from each other. And

the probability of φ faulty TSVs within a T -TSV network can be calculated as:

P (φ) =

T

φ

pφ(1− p)T−φ (4.1)

where p is average TSV failing probability.

Defects clustering effect tries to model the scenario where the presence of a defective TSV

increases the probability of more defects in close vicinity [58, 82]. Reference [82] formulates

this clustering effect by considering 1) a defect cluster center [58, 82] only consists of one

single defective TSV, 2) the failing rate of TSVi is inversely proportional to the distance

from the existing cluster center. This formulation is shown in equation 4.2.

p(TSVi) = p · (1 + (1

dic)α) (4.2)

where p(TSVi) represents the failing probability of TSVi, dic represents the distance between

TSVi and the cluster center. α is the clustering coefficient. Larger value of α implies less

clustering. As α→∞, the defect distribution becomes independent defect distribution.

The clustered model need to take the TSV location information into account. Since the

number of TSVs within a network is typically less than 20, we consider each TSV network

as a 5-by-5 matrix. The value 5 is chosen based on the ratio of the pitch of current probe

needle and the pitch of realistic TSVs [44, 54]. We randomly put T TSVs on the integral

coordinates of the matrix to obtain the location information of each TSV. After that, we

employ equation 4.2 to analyze the probability of different number of defective TSVs (φ)

within a network. Same as [82], we assume each TSV network has only one defect cluster

and defect clusters within different networks do not interfere with each other.

39

Table 4.1: Probability of different number of failing TSVs φ within a 15-TSV network.

Defect TSV Number of faulty TSVs φ

distribution yield 0 1 2 ≥3

99.5% 92.76% 6.99% 0.25% 0.00%

Independent 99.0% 86.01% 13.03% 0.92% 0.04%

98.0% 73.86% 22.60% 3.23% 0.31%

Clustered 99.5% 92.76% 6.70% 0.35% 0.19%

α=1 99.0% 86.01% 12.07% 1.26% 0.66%

98.0% 73.86% 19.55% 4.16% 2.43%

Clustered 99.5% 92.76% 6.78% 0.31% 0.15%

α=2 99.0% 86.01% 12.39% 1.13% 0.47%

98.0% 73.86% 20.60% 3.81% 1.73%

Table 4.1 shows the probability of different values of φ for a 15-TSV network. We

vary the TSV yield from 98% to 99.5% to accommodate different levels of maturity of the

manufacturing processes. The clustering coefficient α is set as 1 and 2, similar as the settings

in [82] and [28]. Note the values under clustered defect distribution are averaged results of 100

Monte Carlo runs, with each run randomly placing 15 TSVs on the 5-by-5 matrix. By doing

this, we try to simulate all possible TSV placements in real silicon. Three observations are

summarized from Table 4.1. First, no matter what defect distribution it is, the probability

of φ = 0 is the largest and even much larger than the sum of the rest situations with φ > 0.

Second, the summed probabilities of φ = 0 and φ = 1 is almost 1 in all situations, and

the probability of φ ≥ 3 is pretty low. Third, as TSV yield decreases, probability of φ = 0

decreases. Motivated by the above observations, we propose to sort the order of test sessions

to reduce the expectation of pre-bond TSV test time, as explained in the next section.

4.3 An Iterative Greedy Procedure for Test Session Scheduling

We express the expectation E(Γ) of test time (Γ) of a TSV network as follows:

E(Γ) =∑Anyρ

γ(ρ)P (ρ) (4.3)

where γ(ρ) is the identification time to determine ρ using the fast TSV identification al-

gorithm in section 3.2 [77], and P (ρ) is the occurrence probability of ρ. Note that ρ = ∅

40

or |ρ| = φ = 0 means that all TSVs within the network are fault-free. We formulate two

problems to be solved.

Problem 4.3.1. Given a series of N test sessions that can uniquely identify up to m

faulty TSVs within a TSV network of T TSVs, find an optimal order to apply those sessions

so that the expectation of pre-bond TSV test time is minimized for this TSV network.

To solve Problem 4.3.1, a straightforward method is to find all permutations of test

sessions, and for each permutation calculate the test time expectation using equation 4.3.

The permutation which yields minimum E(Γ) would be the selected choice. However, there

can be N ! permutations and 2T − 1 fault maps. So the identification algorithm [77] must

be run by N ! · (2T − 1) times, which is highly time-consuming even for a small network.

Fortunately, we notice that the probability of different number of faulty TSVs is inversely

proportional to φ. Specifically,

∑|ρ|=i

P (ρ)∑|ρ|=j

P (ρ) for any i < j (4.4)

where∑|ρ|=i

P (ρ) = P (φ = i) and∑|ρ|=j

P (ρ) = P (φ = j).

Motivated by the fact that P (ρ) is large for small |ρ| and decreases dramatically as |ρ|

increases, if we can reduce γ(ρ) for small |ρ| the test time expectation should be greatly

reduced. For example, the probability of P (ρ = ∅) (all TSVs being good in a network)

dominates. In case of ρ = ∅, all TSVs are identified as good TSVs as long as the already

tested sessions covered all TSVs. Based on this observation, Problem 4.3.2 is formulated as

follows.

Problem 4.3.2. Given N test sessions that can uniquely identify up to m faulty TSVs

within a network of T TSVs, select M out of N sessions such that these M sessions cover

each TSV at least once and the total test time of the selected M sessions is minimum.

41

Problem 4.3.2 can be solved by constructing an ILP model (named “ILP model 2” to

differentiate it from ILP model 1 in section 2.2). We introduce a variable Pj, j ∈ [1, N ],

where

Pj =

1 if session Sj is selected (or picked)

0 otherwise

(4.5)

Then, the ILP model 2 is described as follows:

Objective: MinimizeN∑j=1

t(Lj) · Pj

Subject to constraint: each TSVi, i ∈ [1, T ], is tested at least once by the selected sessions.

Lj represents the size of session Sj, and t(Lj) the test time of Sj, which is a constant

for a given Lj. The number of variables and constraints for ILP model 2 is O(NT ) and

O(T ), respectively. In all our experiments, ILP model 2 is solved in 1 second or less. The

M sessions covering all TSVs with minimal time will be sorted and tested before the rest of

the sessions. This will reduce γ(ρ = ∅) and thus reduce the test time expectation.

As can be seen from Table 4.1, P (φ = 1) is also outstanding. If we can further reduce

γ(ρ) with |ρ| = 1, the test time expectation should be further reduced. The N test sessions

in Problems 4.3.1 and 4.3.2 can be produced by either the ILP model 1 [79] or the heuristic

method [40]. Sessions produced by both methods have characteristics such that if each TSV is

covered (or tested) by at least two sessions, any single faulty TSV can be uniquely identified.

To reduce γ(ρ) with |ρ| = 1, we can hold the M sessions produced by ILP model 2, and find

M1 sessions from the rest N −M session such that these M + M1 sessions will cover each

TSV at lease twice and the test time of the M1 sessions is the minimum. Next we explain

how ILP model 2 can be again utilized to find these M1 sessions. We first count the times

each TSV is covered by the first M sessions, and put the TSVs which have been covered

only once to a list named “TSV set”. ILP model 2 can be utilized to find M1 sessions out of

the N −M sessions such that each TSVi, i ∈ TSV set is covered (or tested) at least once by

42

Initialization:

Original_sessions = All the sessions;

TSV_set = All the TSVs within network;

Sorted_sessions = [ ];

Stop_index = any integer [1, m+1];

k=1;

Iterative Execution:

while (k <= Stop_index) do

Step1: Use ILP model 2 to find a subset of sessions from

Original_sessions which cover each TSV within

TSV_set at least once with minimum test time;

Step2: Append all sessions produced by Step1 to the end

of Sorted_sessions;

Step3: Remove these sessions produced by Step1 from

Original_sessions;

Step4: Based on Sorted_sessions, calculate the times each

TSV is covered;

Step5: Set TSV_set TSVs which have been covered by

only k times;

Step6: k++;

Return Final Results:

Append Original_sessions to the end of Sorted_sessions;

Return Sorted_sessions;

Procedure Test_session_sorting

Figure 4.1: Pseudo-code for iterative test session sorting.

these M1 sessions and the total test time of these M1 sessions is the minimum. The produced

M1 sessions will be sorted and tested directly after the M sessions. These M +M1 sessions

first guarantee γ(ρ = ∅) is minimized and based on this premise further minimize γ(ρ) with

|ρ| = 1 (simply represented as γ(|ρ| = 1)). Similar procedure can be repeated for further

reduction of γ(|ρ| = 2), γ(|ρ| = 3), · · · , until γ(|ρ| = m).

We summarize the overall procedure for session sorting in Figure 4.1. ILP model 2

is iteratively utilized in Test session sorting procedure with each execution tries to find a

subset of sessions from “Original sessions” so as to cover all the TSVs within “TSV set” at

least once with minimum time. The greedy nature of our procedure is obvious since it puts

higher priority on reducing γ(ρ) with smaller |ρ|. The run time of the procedure is (almost)

equal to the run time of ILP model 2 times how many times ILP model 2 is executed which

43

is determined by “Stop index” in Figure 4.1. Note “Stop index” can be set as any value

from 1 to m + 1. When “Stop index” is 1, Test session sorting will only reduce γ(ρ = ∅)

by finding M sessions which covered all TSVs at least once with minimum time. When

“Stop index” is m+ 1, the procedure will first reduce γ(ρ = ∅), and then reduce γ(|ρ| = 1),

and then reduce γ(|ρ| = 2), · · · , all the way up to reducing γ(|ρ| = m).

4.4 A Three-step Test Time Optimization Simulator

In this section we proposed a 3-Step test time Optimization Simulator (SOS3). The

first step of SOS3 is ILP model 1 [79] introduced in chapter 2 for test session generation.

Note that we choose ILP model 1 instead of the heuristic method [40] because test sessions

generated by both methods have exactly the same TSV identification capability, however,

the ILP model generates fewer sessions and is more time-efficient. The second step of SOS3

is the proposed iterative greedy procedure for session sorting. This procedure accepts the

N sessions from step 1 as the inputs and sort the sessions to reduce test time expectation.

The last step is the fast TSV identification algorithm [77] introduced in chapter 3. This

algorithm takes the sorted list of sessions as the inputs and finish the identification process

as soon as any termination condition happens. By integrating session sorting procedure and

fast TSV identification algorithm in SOS3, the pre-bond TSV probing can be terminated as

soon as possible with largely reduced test time expectation.

Figure 4.2 illustrates the overall diagram of SOS3. The inputs to SOS3 contain 3

pieces of information: 1) the TSV and TSV network information, 2) the probing technology

information, and 3) the on-chip TSV redundancy information. The outputs of SOS3 are: 1)

the sorted list of sessions, 2) identified TSVs, 3) test time expectation, and 4) expectation

of number of tested sessions.

44

ILP model 1

Iterative session sorting

Fast TSV identification

algorithm

3-S

tep

tes

t ti

me

Op

tim

izat

ion

Sim

ula

tor

(SO

S3

)

1. Sorted list of test sessions; 2. Identified good and bad TSVs;

3. Test time expectation; 4. Expectation of number of tested sessions;

Outputs of SOS3

1. Resolution constraint

r;

2. Test time for different

session size, t;

Probing technology

information

1. Maximum faulty TSV

to be pinpointed

within network, m;

On-chip TSV

redundancy information

1. TSV defect distribution

2. Number of TSVs, T;

3. TSV yield;

4. TSV physical layout

within network;

TSV and TSV network

information

Figure 4.2: Three-step test time optimization simulator.

4.5 Experimental Results

In this section we compare both the expectation of test time and number of tested

sessions between two different simulators: SOS3 and SOS2 (2-Step test time Optimization

Simulator). The only difference between SOS2 and SOS3 is that the iterative session sorting

procedure is eliminated in the former. By comparing these two simulators, we try to illustrate

the importance of session sorting for test time reduction. Note we did not compare the test

time expectation of SOS3 to that of the heuristic method [40] due to the following two

reasons. First, ILP model 1 returns smaller number of sessions and less test time; Second,

the session sorting procedure in combination with the identification algorithm helps reduce

test time expectation further.

45

In this section, the expectation of test time E(Γ) is estimated as follows.

E(Γ) =

∑|ρ|<2

γ(ρ)P (ρ) + TT∑|ρ|≥2

P (ρ) if m = 1

∑|ρ|≤2

γ(ρ)P (ρ) + TT∑|ρ|≥3

P (ρ) if m ≥ 2

(4.6)

where TT represents the total time of testing all the sessions produced by ILP model 1 [79].

Similarly the expectation of number of tested sessions E(S) in this section is estimated

as follows:

E(S) =

∑|ρ|<2

η(ρ)P (ρ) +N∑|ρ|≥2

P (ρ) if m = 1

∑|ρ|≤2

η(ρ)P (ρ) +N∑|ρ|≥3

P (ρ) if m ≥ 2

(4.7)

where η(ρ) represents the number of tested sessions for identification of fault map ρ using

TSV identification algorithm [77]. N represents the total number of sessions produced by

ILP model 1 [79].

Equations 4.6 and 4.7 are explained as follows. For TSV network with m = 1, we

simply assume any fault map with |ρ| ≥ 2 will cause the entire sessions to be tested. This

is because sessions generated for m = 1 is not intended for identifying more than one faulty

TSV. Moreover, P (φ ≥ 2) =∑|ρ|≥2

P (ρ) is low. Such a low probability has negligible impact

on expectation calculation. For TSV networks with m ≥ 2, we assume the entire sessions

need to be tested to identify fault maps with |ρ| ≥ 3. This is because it generally takes

most of the sessions to identify large number of defective TSVs (like |ρ| ≥ 3). Moreover,

P (φ ≥ 3) =∑|ρ|≥3

P (ρ) is pretty low as referring to Table 4.1. Such a low probability has little

impact on expectation calculation.

Based on equations 4.6 and 4.7, we compare SOS2 and SOS3 for various values of T ,

m, r. The commercial ILP solver CPLEX [3] is again used in our experiments. For all

simulations, SOS3 and SOS2 provide the outputs in less than one minute. The expectation

46

Table 4.2: Expectation of number of tested sessions, defect clustering coefficient α = 1, datashows (sessions for SOS2, sessions for SOS3, reduction by SOS3).

Parameters Total number Expected number of tested sessions, E(S)

T , m, r of sessions, N TSV yield = 99.5% TSV yield = 99.0% TSV yield = 98.0%

8, 1, 2 8 (5.0, 4.0, 19.3%) (5.1, 4.1, 18.7%) (5.2, 4.3, 17.4%)

8, 2, 3 8 (5.0, 4.0, 19.4%) (5.0, 4.1, 18.8%) (5.1, 4.2, 17.6%)

11, 1, 2 11 (8.0, 6.0, 24.2%) (8.1, 6.2, 23.5%) (8.2, 6.4, 21.8%)

11, 2, 3 11 (6.0, 4.1, 31.6%) (6.1, 4.3, 30.0%) (6.3, 4.6, 26.8%)

15, 2, 2 23 (10.0, 8.1, 19.3%) (10.2, 8.3, 18.6%) (10.6, 8.7, 17.0%)

15, 3, 3 20 (7.1, 6.1, 13.5%) (7.3, 6.4, 12.8%) (7.8, 6.9, 11.2%)

16, 3, 4 16 (6.1, 5.2, 15.3%) (6.4, 5.5, 14.0%) (6.9, 6.1, 11.6%)

16, 4, 4 20 (5.2, 4.3, 17.9%) (5.6, 4.7, 16.0%) (6.2, 5.4, 12.8%)

20, 3, 4 20 (9.1, 6.3, 31.1%) (9.4, 6.7, 28.8%) (9.9, 7.5, 24.2%)

20, 4, 4 25 (9.2, 6.3, 31.3%) (9.5, 6.7, 29.1%) (10.3, 7.8, 24.5%)

Table 4.3: Expectation of test time (µs), defect clustering coefficient α = 1, data shows (testtime for SOS2, test time for SOS3, reduction by SOS3).

Parameters Test time of all Expectation of test time, E(Γ)

T , m, r sessions, TT TSV yield = 99.5% TSV yield = 99.0% TSV yield = 98.0%

8, 1, 2 4.24 (2.66, 2.15, 19.3%) (2.71, 2.20, 18.7%) (2.76, 2.28, 17.4%)

8, 2, 3 3.36 (2.10, 1.69, 19.4%) (2.13, 1.73, 18.8%) (2.15, 1.77, 17.6%)

11, 1, 2 5.83 (4.25, 3.21, 24.2%) (4.31, 3.29, 23.5%) (4.36, 3.41, 21.8%)

11, 2, 3 4.62 (2.54, 1.73, 31.6%) (2.58, 1.81, 30.0%) (2.64, 1.93, 26.8%)

15, 2, 2 12.19 (5.33, 4.30, 19.3%) (5.44, 4.42, 18.6%) (5.61, 4.65, 17.0%)

15, 3, 3 8.40 (2.99, 2.58, 13.5%) (3.09, 2.69, 12.8%) (3.27, 2.90, 11.2%)

16, 3, 4 6.08 (2.34, 1.98, 15.3%) (2.44, 2.10, 14.0%) (2.63, 2.32, 11.6%)

16, 4, 4 7.60 (1.99, 1.63, 17.9%) (2.12, 1.78, 16.0%) (2.38, 2.08, 12.8%)

20, 3, 4 7.60 (3.47, 2.39, 31.1%) (3.58, 2.55, 28.8%) (3.79, 2.87, 24.2%)

20, 4, 4 9.50 (3.50, 2.40, 31.3%) (3.64, 2.58, 29.1%) (3.93, 2.97, 24.5%)

of number of tested sessions and test time for both SOS2 and SOS3 are shown in Tables 4.2

and 4.3, respectively. We provide an insightful evaluation of SOS3 by varying TSV yield

from a low value of 98.0% to a practically expected value of 99.5%. Note we only show the

results under clustered defect distribution with α = 1, since the results are very similar for

the rest two defect distributions in Table 4.1.

The first column of both tables show various TSV networks with different T , m, r. The

second column of Table 4.2 and Table 4.3 show the total number of sessions and total test

time of all sessions produced by ILP model 1 [79], respectively. Column 3, 4 and 5 of both

tables consist of elements with each element consisting of 3 values, i.e., (the expectation

47

value of SOS2, the expectation value of SOS3, the relative percentage improvement of SOS3

over SOS2). Note that all values are the averaged results of 100 Monte Carlo runs, with each

run corresponding to a different TSV placement in a 5-by-5 matrix. By doing this we try to

simulate all possible TSV layouts in real silicon.

We made four observations from Table 4.2 and 4.3. First, both the expectation of

number of tested sessions and the expectation of test time is only a small portion of total

number of sessions and total test time, respectively. This demonstrates that SOS2 and SOS3

greatly speed up the pre-bond TSV identification process and thus reduce pre-bond TSV

test cost. As can be seen from Table 4.2, the total number of sessions can reach as high as

25, but the expectation of number of tested sessions is always no more than 8.7 for SOS3.

For TSV network with T = 20, m = 4, r = 4, the test time expectation of SOS3 is only

31.3% of the total test time, considering 98.0% TSV yield. Second, both the expectation of

test time and number of tested sessions increases for lower TSV yield. This is because the

probability of having larger number of defective TSVs within a network increases as TSV

yield decreases. Identifying larger number of faulty TSVs typically takes more sessions and

longer test time for both SOS2 and SOS3. Third, SOS3 helps further reduce the expectation

value compared to SOS2. For example, for T = 11, m = 2, r = 3, SOS3 further reduces

test time expectation by 31.6% compared to SOS2 considering 99.5% TSV yield. Fourth,

the improvement of SOS3 over SOS2 decreases as TSV yield decreases. This is because

the session sorting procedure within SOS3 puts higher priority on reducing the identification

time for smaller value of |ρ|. To identify fault map with large |ρ| (like |ρ| ≥ 2), SOS3 does not

have much advantage over SOS2. As TSV yield decreases, P (φ ≥ 2) =∑|ρ|≥2

P (ρ) increases

and the advantage of SOS3 also slightly decreases. However, even the smallest improvement

of SOS3 over SOS2 is 11.2% in both tables. The large differences between SOS2 and SOS3

illustrate the significance of session sorting in reducing test time expectation.

48

4.6 Conclusion

In this chapter, a session sorting procedure is proposed to sequence test sessions in such a

way that the pre-bond TSV test can terminate as soon as possible for small number of faulty

TSVs within a network. This session sorting procedure, although greedy in nature, is based

on iterative execution of an ILP model. We also propose a 3-step test time optimization

simulator (SOS3) to reduce pre-bond test time expectation. In SOS3, an existing ILP model

is first used to generate a series of test sessions with certain identification capability. Then,

session sorting is conducted based on the generated sessions. Lastly, an existing fast TSV

identification algorithm is used for early test termination. Extensive experimental results

for various TSV networks demonstrate the benefit of session sorting on reducing test time

expectation. We also show how SOS3 guarantees that the test time expectation is always a

small portion of the total time of testing all the sessions. As a framework, SOS3 is expected

to greatly reduce pre-bond TSV test cost in real silicon.

49

Chapter 5

A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D

Wafer-on-Wafer Stacked ICs

5.1 Introduction

In this chapter, we introduced a novel wafer manipulation method for yield improvement

and cost reduction of 3D wafer-on-wafer stacked ICs. The pre-bond TSV testing methods

introduced in chapter 2 to 4 serve as the basis and provide useful known-good-die information

for wafer matching.

A bottleneck in the wafer-on-wafer stacking is its relatively low compound yield, es-

pecially for large number of stacked layers and low wafer yields. Here, compound yield is

defined as the final yield of the 3D IC, ignoring any defect induced during fabrication process

such as stacking, bonding, interconnect formation, packaging, etc. It is a theoretical value

based on the simple assumption that a pre-bond tested good die stacked on another pre-bond

tested good die (or good partial stack) would definitely produce a good stack (or good 3D

IC). Without any matching, compound yield of randomly stacked wafers will decrease ex-

ponentially as more die are stacked, thus dramatically increasing the cost of wafer-on-wafer

fabricated 3D ICs. To improve the compound yield two kinds of previous efforts are worth

mentioning:

1) Matching algorithms have been proposed so as to select the best matching wafers to

stack instead of stacking them randomly [48, 52, 53, 55, 59, 61, 66].

2) Exploiting empirically observed defect distribution models (e.g., wafer maps with ra-

dially clustered defects [53]) or special layouts of wafers (such as fabricating wafer

50

with rotational symmetry so that two wafers can be matched in more ways than

one [52, 80, 75, 81]) have been proposed.

Our effort in this chapter has five parts:

1) A hybrid wafer-on-wafer stacking procedure is proposed in Section 5.3.5, which com-

bines advantages from several methods [52, 59, 61]. With a combination of best prac-

tices in the existing work, this hybrid procedure serves as a reference for comparing

with the novel sector symmetry and cut method, which is the core contribution of this

work.

2) A novel manipulation scheme of wafers is introduced. To be specific, wafers fabricated

with rotational symmetry are cut into identical sectors (called subwafers). We refer to

two subwafers as identical if they have the same die distribution and die orientation.

These identical subwafers are then used to replenish the repository. A repository

consists of wafers corresponding to a specific layer of a 3D IC stack. The simulation

results show that sector symmetry and cut method produces much higher compound

yield than that of existing methods [48, 52, 53, 55, 59, 61, 66]. For example, compared

with the work in [53, 59, 61], the relative improvement of compound yield can reach

as high as 189%.

3) We derive mathematical formulations for die per wafer (DPW) calculation consider-

ing rotational symmetric wafers. We demonstrate that larger capability of rotation

produces more flexibility of wafer matching, but also increases the number of die lost

due to the sector symmetry. Extensive experiments (parts of experimental results are

shown in the appendix) have been done to find the optimal number of cuts.

4) We compare the compound yield of different stacking procedures under various defect

distribution models.

51

5) We construct a cost model of SSCn and conduct detailed cost analysis of SSC4. We

demonstrate that compared to conventional method, SSC4 largely reduces the 3D

IC cost under various defect distribution models, especially for situations where the

number of stacked layers is large.

The rest of this chapter is organized as follows. Section 5.2 introduces the background

and motivation for this work. Section 5.3 discusses various aspects of wafer-on-wafer stacking

closely related to this work. An original contribution is given in Section 5.4 that proposes

a novel wafer manipulation method named sector symmetry and cut (SSCn). Simulation

results are presented in Section 5.5 where yield comparison with related work [53, 59, 61] is

given. The cost-effectiveness of SSCn is analyzed in Section 5.6. Section 5.7 concludes this

chapter.

5.2 Background and Motivation

Since a major bottleneck in wafer-on-wafer stacking is the low compound yield, many

researchers have proposed optimal matching algorithms to improve the yield. Smith et

al. [55] stack wafers with same or similar wafer maps from different repositories. Reda

et al. [48] propose several matching algorithms including a globally greedy matching, an

iterative matching heuristic (IMH), and a global optimal matching based on integer linear

programming (ILP). Verbree et al. [66] propose an iterative greedy matching algorithm, which

applies globally greedy matching to only two repositories at a time. Both proposals [48, 66]

are based on static repositories, which means none of the repositories will be replenished

until they run out of wafers. Contrary to the static repository scheme, Taouil et al. [59, 61]

propose the concept of running repositories. After a wafer leaves a repository, a new wafer

immediately enters that repository so the repository will always be full of wafers. This

new scheme of replenishing repositories is proven to offer higher compound yield and, more

importantly, lower run time complexity than the static repository system.

52

All of the above methods consider only wafer maps with uniform defect distribution,

which is not a good model for describing defect distribution in the real world. It is well known

that the defects on wafers are clustered [23, 62, 71, 72]. A clustered defect distribution model

was first applied by Singh [53] to wafer-on-wafer stacking. Singh’s work shows that with the

same stacking procedure, more practical wafer maps generate higher compound yield than

wafer maps with uniformly distributed defects. However, the matching algorithm [53] is

based on a static repository instead of running repository, which may not fully exploit the

advantage of the clustered defect model. Also, in industry, there may be various kinds of

defect distribution models on the wafer.

Singh [52] proposes a way to fabricate wafers with rotational symmetry such that two

wafers can be matched four ways to find the best match. The rotational symmetry offers a

new strategy regardless of what matching algorithm is used. With rotations the repository

size is virtually multiplied by the rotation number (4 in this case), which is helpful for the

improvement of compound yield. Weaknesses of the contribution [52] include an impractical

assumption of uniform defect distribution and the use of only a static repository.

Figure 5.1 shows four different aspects of the stacking procedures: defect distribution

models, wafer manipulations, repository replenishment schemes, and matching algorithms.

Notice that these aspects are generally independent of each other and any alternative can be

generally selected for one aspect without interfering with choices for others. In Figure 5.1,

a top to bottom path shows the choices made by a referenced work. For example, the

leftmost path [48] means that uses a uniform defect distribution model, takes no action for

wafer manipulation, and uses greedy, IMH, and an ILP matching algorithms based on static

repository replenishment scheme. Viewed horizontally, Figure 5.1 arranges existing works in

an ascending order of their publication date.

To express the motivating factors for the present work, let us examine the two rightmost

paths in Figure 5.1:

53

Defect

Distribution Models

Wafer Manipulations

Repository

Replenishment Schemes

Matching Algorithms

Unif

orm

Rad

ial

clu

ster

ed

Non

e

Rotation N

one

Sta

tic

Running

Static

Static

[14] [21, 23] [16] [17][27]

Gre

edy,

IMH

, IL

P IterativeG

reedy

FIF

O, B

est-pair

Iterative G

reedy

Iterative G

reedy

Publication year (2009 - )

Wa

fer-on

-wa

fer stack

ing p

roced

ure

Ro

tati

on

Cut

Ru

nnin

g

Run

nin

g

Best-p

air

Best-p

air

Sector Symmetry & CutHybrid

Vario

us

distrib

utio

ns

Figure 5.1: Wafer-on-wafer stacking procedures.

1) If we consider the manipulation of wafer rotation [52], and wafer matching based on

a running repository scheme [59, 61], the compound yield should be improved. That

motivates the hybrid scheme.

2) The motivation for a sector symmetry and cut strategy comes from the realization that

compared with die-on-die and die-on-wafer stacking, the low yield of wafer-on-wafer

stacking is due to the restriction that a die on a wafer must be matched with exactly

one die on another wafer. In other words, any pair of dies to be bonded together

must occupy the same geometric position on respective wafers. If the wafers are cut

into smaller parts of identical shape, then the effect of this restriction can be reduced.

Moreover, if the wafers being cut are fabricated with rotationally symmetric sectors,

then each cut sector (subwafer) will look identical. As will be illustrated in this chapter,

greater matching flexibility and higher compound yield can be achieved. Cost analysis

of this manipulation method also shows large reduction of 3D IC cost.

54

5.3 Preliminaries

5.3.1 Defect Distributions on a Wafer

A negative binomial defect distribution model [10, 49, 56, 57] has been widely used to

estimate the die yield as a function of defect density, die area, and a clustering parameter.

However, this model does not provide enough information for us to generate wafer maps with

certain observed patterns like radial symmetry, periodicity, offset, etc. Because of the strict

confidentiality in the industry, data on real wafers are not always exposed. This explains

why most publications assume a uniform distribution of defects [48, 52, 55, 59, 61, 66]. The

problem with this assumption is that the unrealistic uniform distribution model always leads

to a pessimistic compound yield in the wafer-on-wafer stacking procedure [53].

Based on previous literature [15, 17], nine patterns of wafer maps corresponding to

different defect distributions are generated for the yield analysis of wafer-on-wafer stacking

procedure. The spatial probability functions of these nine patterns are shown in Figure 5.2

where different gray levels correspond to different levels of yield ranging from zero (black

pixel) to one (white pixel).

Briefly, the nine defect distribution patterns are:

• Pattern 1: A large central spot showing the low yield at the center of the wafer.

• Pattern 2: A shifted semi-ring showing higher yield at the lower right corner of the

wafer.

• Pattern 3: A slightly shifted small spot.

• Pattern 4: A very thin centered ring showing radial yield degradation.

• Pattern 5: A mixed pattern of repetitive rows and shifted semi-ring.

• Pattern 6: A shifted semi-ring showing higher yield level at the right corner of the

wafer.

55

Pattern 1 Pattern 2 Pattern 3

Pattern 4 Pattern 5 Pattern 6

Pattern 7 Pattern 8 Pattern 9

Figure 5.2: Gray maps showing the yield level distribution on the wafer.

• Pattern 7: A shifted semi-ring showing higher yield level at the lower part of the wafer.

• Pattern 8: A thick centered ring showing radial yield degradation.

• Pattern 9: A relatively thin centered ring showing radial yield degradation.

In this paper, experiments are conducted based on the wafer maps generated from

Figure 5.2.

56

(a) Four-fold rotation (b) Double rotation

Figure 5.3: Wafer maps showing rotational symmetry.

5.3.2 Wafers with Rotational Symmetry

An example of a wafer with rotational symmetry is illustrated in Figure 5.3(a) where the

die distribution on the wafer is symmetric with respect to both the horizontal and vertical

lines. The die orientation in (a) has 90° difference between adjacent quadrants. If wafers

in all repositories have this characteristic, then any pair of wafers drawn from two different

repositories can be matched in four ways where one wafer is rotated with respect to the

other by 0, 90, 180 or 270 degrees. This virtually enlarges the physical repository size four

times. The wafer map introduced in [52] is only capable of such four fold rotation. We also

consider wafers capable of two fold rotation. As shown in Figure 5.3(b), the wafer will look

identical after each 180° rotation if the die distribution is anti-symmetric across the vertical

line, i.e., two halves of the die are oriented with 180° rotation.

5.3.3 Running Repository Based Best-pair Matching Algorithm

Running repository scheme is considered in all experiments in this paper since it provably

produces higher yield and lower run time complexity than the static repository. Based on

such a scheme, the matching algorithm is chosen as the best-pair based algorithm [59, 61]

due to its high yield. Thus, wafers from the first two repositories are matched without any

57

restriction, and the pair producing maximum yield is selected (best-pair match). Then the

pair of wafers as a whole is matched with every wafer from the next repository to find the

best one (best-one match), and the same process iterates until the last repository. After one

complete stack is formed, each repository is replenished immediately. This process is repeated

until the production size (total number of stacks fabricated in production) is reached. Note

that in the matching algorithm, the matching criterion can produce multiple choices.

5.3.4 Matching Criteria

The purpose of wafer matching is to get the maximum final compound yield for a given

production size. Given two pre-bond tested wafers, there are basically three criteria to find

how well they match [59, 61]: (1) the number of matching good dies (MGD); (2) the number

of matching bad dies (MBD); (3) the number of unmatched faulty dies (UFD). An UFD is

formed either by a good die overlapping a bad die or a bad die overlapping a good die. Since

most publications on wafer matching consider only MGD as the criteria [48, 52, 53, 55, 66]

we also use MGD, given that evaluating the best matching criterion is not our focus here.

Wafers are tested prior to bonding. To determine the matching yield of wafer bonding,

the state of a tested wafer is represented by a h × v test matrix of h columns and v rows,

where h and v are the maximum number of chips on the wafer along two perpendicular axes

termed as horizontal and vertical, respectively. Elements of the test matrix are [0,1] integers.

A “1” means a good device and “0” means a bad or non-existing device. Thus, the sum of

all elements normalized with respect to the number of device sites on the wafer gives the

wafer yield.

When two wafers are stacked, a stacking matrix for the wafer stack is another h × v

matrix whose elements are products of the corresponding elements of test matrices of wafers.

The stacking matrix assumes an ideal stacking, i.e., two good devices produce a good stack.

It provides the stacking yield in the same way as the test matrix of a wafer gives the wafer

yield. Adding wafers to a partial stack combines test matrices of wafers with the stacking

58

matrix of the previous stack in a similar way. Depending on the manufacturing procedure,

whenever a complete or partial stack is tested, the stacking matrix is converted into a test

matrix by changing the entries for failed stacks to “0”.

5.3.5 A Hybrid Wafer-on-Wafer Stacking Procedure

Based on previous work, we propose a hybrid wafer-on-wafer stacking procedure, which

incorporates the rotational symmetry of wafers [52] and running repository based best-pair

matching algorithm [59, 61]. This procedure combines the merits of several practices shown

in Figure 5.1.

It has been proven [52] that by simple rotation the compound yield can be improved.

The reason is quite straightforward: each rotation of a symmetric wafer actually produces

a new wafer map, and the repository size is virtually enlarged by as many times as the

wafer can be rotated (Figure 5.3). Therefore, we choose a rotationally symmetric wafer in

this work. We further select the running repository replenishment scheme and a best-pair

matching algorithm to construct a hybrid procedure. We evaluate this hybrid procedure for

various defect distribution models.

The initial expectation from this hybrid stacking procedure was that it would produce

a considerable compound yield improvement. However, detailed experimental results in

Section 5.5 actually show only trivial improvement. Nevertheless, the hybrid procedure serves

as a reference for comparison to the work in the next section which is the core contribution

of this paper.

5.4 Sector Symmetry and Cut for Yield Improvement

The hybrid procedure does not adequately overcome the restrictions of flexibility in

matching good dies in wafer stacking. In this section, a novel manipulation scheme of sector

symmetry and cut is presented to help ease such restrictions.

59

Cut

Figure 5.4: A conventional wafer cut into four sectors.

5.4.1 Wafers Cut into Sectors

Compared with just rotating the wafer, a more flexible manipulation is to cut each

individual wafer to several sectors (called subwafers). If all wafers can be cut to subwafers,

then a subwafer can match with any subwafer cut from the same wafer location in another

repository. Previously, all subwafers of a wafer were kept together (uncut) during wafer

matching. Because by cutting the wafer, the restriction of matching a sector from one wafer

with another sector of another wafer applied. Figure 5.4 shows four 90° sectors cut from a

conventional wafer where the arrow indicates the die orientation within a sector. Similarly,

we can cut the wafer into halves (180° sectors) or any number of sectors.

Cutting the wafer into sectors offers an adaptive method between wafer-on-wafer stack-

ing and die-on-die stacking. Comparing with die-on-die stacking, the throughput is largely

increased because now each stack produces a sector of 3D ICs. Comparing with wafer-on-

wafer-stacking, the yield should be improved because of reduced restrictions in matching

sectors rather than matching wafers.

It is quite obvious that extreme cutting (too many sectors) will start losing the advantage

because it will get closer to die-on-die stacking, which has highest yield but has a high

60

Cut

Figure 5.5: Cutting a rotationally symmetric wafer into identical subwafers.

assembly cost too. Compared to wafer stacking a downside of sector stacking is that stacking

and bonding of individual sectors requires larger amount of effort. Besides, the sector oriented

wafer layout causes a loss of chip sites that increases with the number of sectors. With a

properly selected sector size, the benefit of matching flexibility, higher yield, and lower cost

can outweigh the disadvantages.

5.4.2 Sector Symmetry and Cut

After cutting the wafers into subwafers (sectors), each subwafer can only be matched

to another subwafer located at the same position within the wafer. For example, the top-

left subwafer (second subwafer in Figure 5.4) from repository 1 can only be matched to the

top-left subwafer from repository 2. If all subwafers look identical, the restriction due to

subwafer location on wafer is eliminated and matching will become more flexible. The idea

to obtain identical subwafers from a wafer is straightforward. If subwafers are cut from a

wafer fabricated with rotational symmetry, all subwafers will look identical.

Figure 5.5 illustrates the sector symmetry and cut manipulation to the wafer in Fig-

ure 5.3(a). Similarly, the wafer can be cut to halves to get two identical subwafers. Now, any

subwafer from one repository can be matched to any subwafer from another repository. The

61

Figure 5.6: Illustration of die loss for cutting the wafer into 6 sectors.

sector symmetry and cut method provides more choices for subwafer stacking in matching

algorithms.

5.4.3 Discussion on the Number of Cuts

It is natural to think about cutting wafers with rotational symmetry to more sectors

than just 2 or 4. However, if a wafer is cut to either 3 or more than 4 sectors, new challenges

appear. We make two observations. First, dies on the wafer cannot be arranged as compactly

as in the case of 2 or 4 sectors. In other words, there will be space wasted at the edges of

each sector due to the square or rectangular shape of the chip. Second, cutting a wafer to too

many small sectors will generate a circular area of certain radius inside which chips cannot

be printed, i.e., the area within the circle will be too small to accommodate a complete die.

Figure 5.6 illustrates this point where the wafer is divided into 6 equal sectors. The

dotted areas indicate where there is not enough space to accommodate a full die. These

areas are either at the edge of the sector or near the center of the wafer. The dotted central

area form a small circle where no single die can be placed within a sector.

Thus, cutting a wafer into sectors when the number of sectors is neither 2 nor 4 will

waste some wafer area and reduce the number of dies per wafer (DPW). Correspondingly,

62

(a) Placement method 1 (b) Placement method 2

Figure 5.7: Two different ways of placing dies on a rotationally symmetric wafer.

Table 5.1: Geometrical parameters for dies per wafer (DPW) calculation.

Variable Definition

r Radius of wafer excluding edge clearancecutnum Number of cuts per wafer

H Height of dieL Length or width of dieα Angle of sector

the cost of producing a 3D IC will increase which must be compensated for by the increased

stacking yield.

Rotationally symmetric wafers can use two alternative die placements as illustrated

in Figure 5.7. The two placements yield different DPW. Geometrical parameters used for

computing DPW are defined in Table 5.1. Note the vertical and horizontal spacings between

dies on the wafer are already included in the die height H and die width L.

Figure 5.8 shows a sector with die orientation of Figure 5.7(a). We call this placement

method 1. Number of rows N11 of die that can be placed below the dotted line in Figure 5.8

is computed as,

N11 =⌊rcosα

2− L

2tanα2

H

⌋(5.1)

63

2 tan( )2

L

L

H

cos( )2

r

112 tan( )

2

Lr N H

! !

Figure 5.8: Calculation of DPW1 for sector placement method 1.

Note that the triangle of height L2tanα

2part at the tip of the sector cannot hold any die.

Number of die per sector DPS11 in N11 rows is obtained as,

DPS11 =

N11∑i=1

⌊1 + 2(i− 1)

H

Ltan

α

2

⌋(5.2)

Number of rows N12 of die that can be placed above the dotted line in Figure 5.8 is computed

as,

N12 =⌊r −N11H − L

2tanα2

H

⌋(5.3)

and the number of die per sector DPS12 accommodated in these N12 rows is,

DPS12 =

N12∑i=1

⌊2√r2 − (N11H + iH + L

2tanα2

)2

L

⌋(5.4)

Thus, total number of die per sector DPS1 in Figure 5.8 is obtained as,

DPS1 = DPS11 +DPS12 (5.5)

64

iH

sin( )r

L

H

Figure 5.9: Calculation of DPW2 for sector placement method 2.

Figure 5.9 shows a sector from Figure 5.7(b). We refer to this as placement method 2.

Number N2 of rows of die that can be placed in this sector is,

N2 =⌊rsin(α)

H

⌋(5.6)

A careful examination of method 2 shows that the case for 3 cuts need to be examined

separately. Die distribution on a sector with 2 cuts is basically a combination of two sectors

from the 4 cut placement. For 4 or more cuts, we obtain the number of die per sector as,

DPS2 =N2∑i=1

⌊√r2 − (iH)2 − iHtan(α)

L

⌋(5.7)

Figure 5.10 shows the die placement of 3-cuts in placement method 2. N21 and N22 are

the numbers of rows of die that can be placed below and above the dotted line, respectively,

in Figure 5.10. Numbers of die per sector DPS21 and DPS22 for these sections are computed

as follows:

N21 =⌊rsin(α)

H

⌋(5.8)

65

sin( )r

12r N H L

H

Figure 5.10: Calculation of DPW2 of 3-cuts for sector placement method 2.

DPS21 =

N21∑i=1

⌊√r2 − (iH)2 − (i−1)Hcot(α)

L

⌋(5.9)

N22 =⌊r −N21H

H

⌋(5.10)

DPS22 =

N22∑i=1

⌊2√r2 − [(N21 + i)H]2

L

⌋(5.11)

Thus, total number of die per sector DPS2 for method 2 in Figure 5.10 is obtained as,

DPS2 = DPS21 +DPS22 (5.12)

Number of die per wafer DPWq for cutnum cuts, where q = 1 or 2 refers to the placement

method 1 or 2, is calculated as,

DPWq = DPSq × cutnum (5.13)

We consider 8 inch wafers with 5-mm edge clearance and square die of size 31.8 mm ×

31.8 mm. A die spacing of 0.04 mm is assumed. For the selected wafer size and die area,

66

5 10 15 20600

650

700

750

800

850

Number of cuts per wafer

Tot

al n

umbe

r of

die

s pe

r w

afer

Method 1Method2

Figure 5.11: DPW1 and DPW2 versus number of cuts for placement methods 1 and 2.

the number of die per wafer is 812 for normal wafers. This number is obtained by using

equation 5.7 and 5.13 for 4 cuts in placement method 2.

Figure 5.11 compares the two placement methods for various numbers of cuts. We see

a general trend that as the number of cuts increases (larger capability of rotation) the DPW

decreases. Also, placement method 2 always outperforms method 1 from DPW point of

view. Actually, through large amount of experiments considering different wafer sizes, die

sizes, and chip aspect ratios, we find placement method 2 outperforms method 1 most of

the time. That is why we consider placement method 2 in this work. Note that DPW for

2-cuts and 4-cuts with placement method 2 have the DPW of a conventional wafer without

cutting. Equations 5.1 to 5.13 are derived for calculating DPW of rotational symmetry

wafers, however, like previous work on DPW calculation [20, 67], they can also be applied

to DPW calculation of conventional wafers.

5.4.4 Summing it up

Figure 5.12 shows the complete stacking procedure of the sector symmetry and cut

method applied to an example of 3 stacking levels. Initially all repositories are filled with

subwafers. For a given repository size k, there will be either 2k or 4k subwafers within each

67

Back-up wafer

with rotational

symmetry

Back-up wafer

with rotational

symmetry

Back-up wafer

with rotational

symmetry

Pre-bond test Pre-bond test Pre-bond test

Cut Cut Cut

Running

repository consists

of subwafers

Best-pair match

Best-one match

Stack of two

subwafers

Final stack for post-

bond processing

Running

repository consists

of subwafers

Running

repository consists

of subwafers

Figure 5.12: Process flow of sector symmetry and cut method.

repository, depending on whether a wafer is cut into 2 or 4 pieces. The best-pair match

between the first two repositories and the best match for the rest of the repositories are

conducted afterwards. Consider for now that the matching is with respect to subwafers

instead of wafers. For each repository replenishment, there is a back-up wafer which is cut

and rotated. As one subwafer leaves a repository, a new subwafer from the back-up wafer

will replenish the repository, immediately. Once the back-up wafer is used up, a new back-up

wafer will replace it. Since running repository based best-pair matching algorithm is used

in Figure 5.12, the run time complexity is O(cutnum × k × p × n) [59, 61] where cutnum, k,

p and n are number of cuts, repository size, production size and number of stacked layers,

respectively.

68

Table 5.2: Wafer manipulation methods.

Names Explanations

Basic Wafers without rotational symmetry are matched.Rotation 4 Wafers are matched using 4-way rotational

symmetry.Rotation 2 Wafers are matched using 2-way rotational

symmetry.Sector Symmetry Sectors are matched after 4-way symmetricand Cut 4 (SSC4) wafers are cut into 4 sectors.Sector Symmetry Sectors are matched after 2-way symmetricand Cut 2 (SSC2) wafers are cut into 2 sectors.

We have done extensive Monte Carlo experiments based on different defect models, wafer

sizes, and die sizes. The results show that in most cases 4-cuts yield the maximum number

of good 3D ICs compared to other numbers of cuts. So a rule-of-thumb is to cut wafer into 4

quadrants. Part of our experiment results are shown in the appendix to illustrate this point.

In this work, we emphasize on introducing the significance of wafer cut methodology, and

only consider cutting wafers into 2 or 4 sectors (where no die loss occurs) in the next section.

We summarize five types of manipulations of wafers in Table 5.2.

5.5 Experimental Results

5.5.1 Experimental Setup

Same wafer and die as in Section 5.4.3 were used in this experiment. Figure 5.2 is used

to generate the nine different patterns of wafer maps. If not specified explicitly, a default

production size of 100,000 3D ICs is targeted in the experiments. All the experiments are

repeated 1,000 times and results are averaged to remove noise.

The running repository based best-pair matching algorithm was used [59, 61]. Initially,

k′2 (k′ = cutnum × k) comparisons provide the match information for all wafer (subwafer)

pairs from the first two repositories. To speed up the matching algorithm, a heap structure

is used to store the match information. Each time a pair of wafers (subwafers) leaves the

69

first two repositories, the corresponding elements are pruned from the heap. As two new

wafers (subwafers) enter the first two repositories, their relationships with the existing wafers

(subwafers) are constructed and added to the heap. Once the heap is constructed, only 2k′−1

comparisons are needed each time to replenish the heap.

Five manipulations of Table 5.2 are combined with running repository based best-pair

matching algorithm. The names of these manipulations refer to the complete stacking proce-

dures depending on the context. Recall that the rotation manipulation in Table 5.2 combined

with running repository based best pair matching algorithm is the hybrid stacking procedure

proposed in Section 5.3.5. Thus, Rotation in this section represents the hybrid procedure.

5.5.2 Comparison of Various Stacking Procedures for Different Defect Distri-

butions

In this section we examine the compound yields of final 3D ICs with different stacking

procedures under nine different defect distribution models. Initially, the yield of basic pro-

cedure with repository size 1 (i.e., random stacking without matching) is calculated for nine

types of defect patterns. Subsequently, for each type of pattern, yields for all procedures are

normalized with respect to the corresponding random stacking yield. The normalized yield

versus repository size for different stacking procedures and defect distributions are shown in

Figure 5.13 for 3 stacked layers.

The legends in Figure 5.13 indicate different stacking procedures. For example, basic

(see Table 5.2) means the procedure uses running repository based best-pair matching algo-

rithm, without any manipulation to wafers. As mentioned in Section 5.5.1, Rotation is the

hybrid procedure in Figure 5.1.

Next, we compare the performance of different stacking procedures. Regardless of what

defect model is used, yield of SSCn procedure is always higher than that of others. The

reason for superiority of the SSCn procedure is that the restrictions among subwafers are

reduced while in Rotation and basic all subwafers are bonded together. In SSCn, subwafers

70

0 10 20 30 40 501

1.2

1.4

1.6

1.8

2

2.2

2.4

Repository size

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 10 20 30 40 501

1.1

1.2

1.3

1.4

1.5

1.6

1.7

Repository size

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 10 20 30 40 500.95

1

1.05

1.1

1.15

1.2

1.25

Repository size

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

(a) Pattern 1 (b) Pattern 2 (c) Pattern 3

0 10 20 30 40 501

1.05

1.1

1.15

Repository size

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 10 20 30 40 501

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

Repository size

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 10 20 30 40 501

1.1

1.2

1.3

1.4

1.5

Repository size

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

(d) Pattern 4 (e) Pattern 5 (f) Pattern 6

0 10 20 30 40 501

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

Repository size

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 10 20 30 40 501

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

Repository size

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 10 20 30 40 501

1.05

1.1

1.15

1.2

1.25

Repository size

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

(g) Pattern 7 (h) Pattern 8 (i) Pattern 9

Figure 5.13: Yield improvement by various stacking procedures for different defect distribu-tion patterns of Figure 5.2.

71

selected from the same repository are not necessarily from the same wafer. The differences

between SSCn and Rotation become more obvious as the repository size grows from 1 to 50.

As shown in Figures 5.13, there are up to 50% differences in normalized yield between SSC4

and Rotation 4 when repository size reaches 50.

We evaluate the impact of number n of cuts on the yield of SSCn procedure. It is obvious

from Figure 5.13 that SSC4 always has a higher yield than SSC2. The reason for the yield

difference between these two is that in both cases there is no die loss and greater flexibility

is provided in SSC4. In SSC4, each wafer is cut to 4 pieces reducing restrictions between

subwafers and this produces a virtual repository twice the size of the virtual repository of

SSC2.

We further evaluate the impact of rotation number n on the yield of proposed hybrid

procedure. As can be seen from Figure 5.13, for patterns 1, 4, 8 and 9, yield of Rotation 4

is better than those for Rotation 2 and basic, but the improvement is slight. Why does

larger rotation number not help the hybrid procedure significantly? A possible explanation

is that under patterns 1, 4, 8 and 9, bad dies are already clustered either at the center or

near the edge of wafers, in which case rotating the wafer does little for aligning good dies.

For the rest of the patterns, we can see the yield of Rotation and basic are the same. To

explain this phenomenon, let’s re-examine the nine patterns. Of the nine patterns, only

four of them (namely, patterns 1, 4, 8, 9) are symmetric to the wafer center while the rest

of them are all shifted by some amount. It is obvious that given two wafer maps with

the same probabilistically non-symmetric defect distribution, the best way to match them

is not to rotate them at all. So even the wafer maps used in our experiments have the

capability of four-fold rotation, the rotation method will automatically avoid any rotation.

Our observations suggest that for practical wafers with various defect distributions, benefits

gained from simple rotation are rather trivial.

Another interesting phenomenon is that the yield for all stacking procedures increases

as repository size gets larger. This indicates relatively large repository is preferable for yield

72

improvement. The explanation is that larger repository size provides more candidates for

matching algorithms thus increasing the compound yield. Considering the extremely small

repository with size 1, the wafers are stacked without any freedom for selection. However,

larger repository will consume more time in matching algorithms, which correspondingly

reduces the throughput.

5.5.3 Impact of Number of Stacked Layers on Compound Yield

In this section the impact of number of stacked layers on final compound yield is studied.

The experimental results are shown in Figure 5.14 where y axis indicates normalized yield

with respect to the yield of the Basic procedure under the same condition. In Figure 5.14,

the repository size is set to 50.

Though not shown in Figure 5.14, the compound yields of all procedures decrease for

larger number of stacked layers. However, as can be seen, higher improvement is gained for

SSC4, SSC2 over Rotation 4, Rotation 2, and basic. SSC4 and SSC2 always outperform

Rotation 4, Rotation 2 and basic especially for situations where compound yield becomes

poorer (Figure 5.14(b) is an exception). For example, in Figure 5.14(a), for 7-level stacks the

normalized yield increases from 1.00 for basic [53, 59, 61] and 1.25 for Rotation 4 to almost

2.89 for SSC4, which indicates 189% and 131% relative increases, respectively. Note again,

compared with basic the rotation procedure does not help at all for patterns 2, 3, 5, 6 and

7 regardless of the number of stacked layers.

5.5.4 Impact of Production Size on Compound Yield

Since running repository scheme is utilized in our work, repository pollution is unavoid-

able [59, 61]. Figure 5.15 shows how the yield decreases as the production size increases for

different types of patterns. Note the x-axis indicates the number of wafers consumed for a

single layer in production. The repository size is set to 25 and the number of stacked layers

is selected as 3. Initially, the yield of SSC4 procedure using only one wafer per repository

73

2 3 4 5 6 71

1.5

2

2.5

3

Number of stacked layers

Nor

mal

ized

yie

ld

SSC4SSC2Rotation4Rotation2

2 3 4 5 6 71

1.1

1.2

1.3

1.4

Number of stacked layers

Nor

mal

ized

yie

ld

SSC4SSC2Rotation4Rotation2

2 3 4 5 6 7

1

1.05

1.1

1.15

1.2

1.25

1.3

Number of stacked layers

Nor

mal

ized

yie

ld

SSC4SSC2Rotation4Rotation2

(a) Pattern 1 (b) Pattern 2 (c) Pattern 3

2 3 4 5 6 7

1

1.05

1.1

1.15

1.2

1.25

1.3

Number of stacked layers

Nor

mal

ized

yie

ld

SSC4SSC2Rotation4Rotation2

2 3 4 5 6 7

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

Number of stacked layers

Nor

mal

ized

yie

ld

SSC4SSC2Rotation4Rotation2

2 3 4 5 6 71

1.1

1.2

1.3

1.4

1.5

1.6

Number of stacked layers

Nor

mal

ized

yie

ld

SSC4SSC2Rotation4Rotation2

(d) Pattern 4 (e) Pattern 5 (f) Pattern 6

2 3 4 5 6 71

1.1

1.2

1.3

1.4

1.5

Number of stacked layers

Nor

mal

ized

yie

ld

SSC4SSC2Rotation4Rotation2

2 3 4 5 6 7

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

Number of stacked layers

Nor

mal

ized

yie

ld

SSC4SSC2Rotation4Rotation2

2 3 4 5 6 7

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

Number of stacked layers

Nor

mal

ized

yie

ld

SSC4SSC2Rotation4Rotation2

(g) Pattern 7 (h) Pattern 8 (i) Pattern 9

Figure 5.14: Normalized yield for various stacking methods versus number of stacked layersfor different defect distribution patterns of Figure 5.2.

74

0 200 400 600 800 1000

0.6

0.7

0.8

0.9

1

Number of wafers consumed in production

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 200 400 600 800 10000.2

0.4

0.6

0.8

1

Number of wafers consumed in production

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 200 400 600 800 10000.65

0.7

0.75

0.8

0.85

0.9

0.95

1

Number of wafers consumed in production

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

(a) Pattern 1 (b) Pattern 2 (c) Pattern 3

0 200 400 600 800 10000.8

0.85

0.9

0.95

1

Number of wafers consumed in production

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 200 400 600 800 10000.5

0.6

0.7

0.8

0.9

1

Number of wafers consumed in production

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 200 400 600 800 10000.4

0.5

0.6

0.7

0.8

0.9

1

Number of wafers consumed in production

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

(d) Pattern 4 (e) Pattern 5 (f) Pattern 6

0 200 400 600 800 10000.5

0.6

0.7

0.8

0.9

1

Number of wafers consumed in production

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 200 400 600 800 10000.65

0.7

0.75

0.8

0.85

0.9

0.95

1

Number of wafers consumed in production

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

0 200 400 600 800 10000.75

0.8

0.85

0.9

0.95

1

Number of wafers consumed in production

Nor

mal

ized

yie

ld

SSC4Rotation4SSC2Rotation2Basic

(g) Pattern 7 (h) Pattern 8 (i) Pattern 9

Figure 5.15: Yield reduction for various defect distributions (Figure 5.2) as production sizeincreases.

75

is pre-calculated for each type of defect distribution pattern. Then for each defect pattern,

the yields for all procedures are normalized with respect to the corresponding pre-calculated

values.

In Figure 5.15, as the production size increases, the normalized yield for all procedures

decreases and finally stabilizes. Interestingly, though yields of SSC4 and SSC2 still outper-

form Rotation 4 and basic, the yield advantages become less obvious for larger production

size, especially for patterns with non-symmetric defect probability distributions. One pos-

sible explanation is that pollution is more severe for non-symmetric wafer patterns. In the

later phase of the manufacturing process, the repository will be always somehow polluted.

However, for symmetric defect patterns, a new incoming sector is more likely to match the

rest of the unattractive sectors in the repository. For non-symmetric patterns, it is harder to

get alignment of good dies. In other words, the compound yield of the selected best pair will

be low. That is why the yield benefits of SSCn drops quickly for non-symmetric patterns.

To effectively eliminate pollution and better utilize the SSCn method, a new mechanism

to force the unattractive wafers to leave the repository in a timely manner is needed. To our

knowledge, no remedy has been proposed. Some possible solutions to reduce pollution could

be:

1) Conduct running repository based matching and static repository based matching,

alternatively.

2) Expunge poor wafers (quadrants) from the repository if they have not been used after

a certain number of tries. Send them to a die stacking process to make some use of

them.

5.6 Cost Effectiveness of Sector Symmetry and Cut Method

Previous sections demonstrated the benefits of SSCn method from aspect of com-

pound yield. However, to decide whether SSCn is applicable, we need to determine the

76

cost-effectiveness of SSCn method, since SSCn would require extra effort in wafer cutting

and bonding, increasing the cost from a manufacturing perspective. The question remains

whether the additional cost of wafer cutting and bonding in manufacturing can be compen-

sated for by yield increase? We analyze the cost of a 3D IC in 3 phases: 1) testing, 2)

manufacturing, and 3) packaging.

First, we consider the testing cost of 3D IC. There can be many different kinds of test

flows for 3D ICs [60]. We assume an optimized testing flow from [66] to carry out the analysis.

This test flow consists of three stages, 1) pre-bond test, 2) post-bond test during which only

the newly-formed interconnects are tested, and 3) final test after packaging assumed to cover

all interconnects and dies to assure the quality of the final 3D ICs.

Costs of pre-bond test Costpretest, post-bond test Costpostest, and final test Costfinaltest

are given by equations 5.14 through 5.16. These equations have similar format, i.e., number

of items tested multiplied by test cost per item.

Costpretest = DPW · l · tdie (5.14)

where tdie denotes the test cost of a single die. l is the number of stacked layers.

Costpostest = DPW · Y (l, k) · (l − 1) · tint (5.15)

where Y (l, k) is the compound yield for a stack of l layers and a repository size of k wafers.

tint is the test cost of the interconnect between two layers.

Costfinaltest = DPW · Y (l, k) · Y l−1int · (l · tdie + (l − 1) · tint) (5.16)

where Yint denotes the passing yield of interconnect test between two layers. The total testing

77

cost is:

Costtest = Costpretest + Costpostest + Costfinaltest (5.17)

Next, we analyze the impact of wafer cutting on 3D manufacturing cost and find,

Costmanu = l · Cw + (l − 1) · C3D · (1 + cutnum · β) (5.18)

where Cw is the wafer cost, and C3D [59] is the cost related to 3D stacking process including

through silicon via (TSV), wafer thinning, wafer bonding, etc. A fraction β accounts for

the overhead of wafer cutting. Larger β indicates larger overhead caused by wafer cut and

bonding. Note for the basic method in which the wafer is not cut before stacking, cutnum = 1

and β = 0.

The packaging cost is,

Costpack = DPW · Y (l, k) · Y l−1int · tpack (5.19)

where tpack denotes the cost of packaging a 3D IC.

The total cost is the sum of testing cost, manufacturing cost, and packaging cost:

Costtotal = Costtest + Costmanu + Costpack (5.20)

Notice that the total cost need to be distributed over all functional 3D ICs. Here, the

number of functional 3D ICs after final testing is,

Num3DIC = DPW · Y (l, k) · Y l−1int · Y l

die (5.21)

Therefore, the cost of a single functional 3D IC is,

Cost3DIC =CosttotalNum3DIC

(5.22)

78

Based on the above cost model, we compare the 3D IC cost of SSC4 and basic for nine

different wafer patterns. The parameters substituted in the cost model are as follows [10,

59, 66]: cutnum = 4, DPW = 812, tdie = $0.23, tint = $0.023, Ydie = 99%, Yint = 97%,

Cw = $1000, tpack = CwDPW

· 0.5.

Table 5.3 shows the cost analysis result. All positive numbers are in boldface, which

indicate the percentage of cost improvement with SSC4 over basic. Negative numbers indicate

cases where cost of SSC4 is higher. We make three observations from Table 5.3. First, given

a certain β and number of stacking layers (l), the cost improvement of SSC4 increases as

C3D

Cwdecreases. This is because the negative impact of SSC4 on manufacturing cost becomes

smaller as C3D

Cwdecreases. Second, given a certain C3D

Cwand number of stacking layers, the

cost improvement of SSC4 increases as β decreases, which is also evident in equation 5.18.

These two observations suggest that the cost benefits of SSC4 become larger as the cost

overhead of SSC4 become smaller. As the infrastructure of handling sectors of wafers in 3D

manufacturing becomes mature, both C3D

Cwand β will decrease, and reduced manufacturing

overhead of SSC4 can be expected. Third, given certain β and C3D

Cw, the cost improvement

becomes more significant as the number of layers (l) increases. This is because the yield

improvement of SSC4 over basic becomes much larger when l increases as indicated by

Figure 5.14. At large l, the final number of good 3D ICs is much larger, thus compensating

for the larger manufacturing overhead of SSC4 over basic.

As can seen from Table 5.3, for most defect distributions, SSC4 behaves very well even

for very large C3D

Cwand β. Note that β = 0.25 indicates 100% 3D manufacturing overhead

of SSC4. For defect distributions 3, 4, and 9, there is a larger portion of negative numbers

when C3D

Cw= 0.9, which is of course the worst case condition. But as 3D technology matures,

we expect smaller C3D

Cwand β in which case SSC4 is more cost-effective.

79

Tab

le5.

3:C

ost

impro

vem

ent

per

centa

gefo

rSSC

4ov

erbasic

under

vari

ous

def

ect

dis

trib

uti

ons

(Fig

ure

5.2)

and

for

num

ber

ofst

akin

gla

yers

(l)

rangi

ng

from

2to

6.

Def

ect

Over

hea

dC

3D

Cw

=0.3

C3D

Cw

=0.6

C3D

Cw

=0.9

patt

ern

βl

=2

34

56

23

45

62

34

56

0.0

514.1

27.7

40.6

50.8

58.3

12.7

26.3

39.3

49.7

57.3

11.6

25.2

38.3

48.8

56.6

0.1

012.3

25.8

38.8

49.2

56.9

9.5

22.8

36.2

46.9

54.9

7.2

20.6

34.2

45.3

53.5

Patt

ern

0.1

510.5

23.8

37.0

47.6

55.5

6.3

19.4

33.1

44.2

52.6

2.8

15.9

30.1

41.7

50.4

10.2

08.8

21.8

35.1

46.0

54.1

3.0

15.9

29.9

41.5

50.2

−1.7

11.3

26.0

38.1

47.3

0.2

57.0

19.8

33.3

44.4

52.7

−0.2

12.4

26.8

38.8

47.8

−6.1

6.7

21.8

34.6

44.2

0.0

522.8

22.3

21.1

19.5

18.0

21.7

20.8

19.4

17.7

16.1

20.7

19.6

18.1

16.4

14.7

0.1

021.3

20.2

18.7

16.9

15.3

18.8

17.1

15.3

13.3

11.5

16.8

14.7

12.7

10.6

8.7

Patt

ern

0.1

519.7

18.1

16.3

14.4

12.6

16.0

13.5

11.2

8.9

6.9

12.9

9.8

7.3

4.8

2.6

20.2

018.1

16.0

13.9

11.8

9.9

13.1

9.8

7.1

4.5

2.2

9.0

4.9

1.8

−1.0

−3.4

0.2

516.5

13.9

11.6

9.2

7.2

10.2

6.1

3.0

0.1

−2.4

5.1

0.0

−3.6

−6.8

−9.5

0.0

55.4

7.1

9.0

10.5

12.1

4.0

5.5

7.1

8.7

10.3

2.9

4.2

5.7

7.3

8.9

0.1

03.6

4.8

6.3

7.8

9.4

0.9

1.4

2.6

4.0

5.5

−1.5

−1.3

−0.2

1.1

2.6

Patt

ern

0.1

51.9

2.5

3.8

5.1

6.6

−2.3

−2.7

−1.8

−0.7

0.7

−5.9

−6.8

−6.2

−5.1

−3.7

30.2

00.1

0.2

1.2

2.4

3.8

−5.5

−6.8

−6.3

−5.4

−4.0

−10.2

−12.3

−12.1

−11.3

−9.9

0.2

5−

1.6

−2.1

−1.4

−0.3

1.1

−8.7

−10.9

−10.8

−10.0

−8.8

−14.6

−17.9

−18.1

−17.4

−16.2

0.0

51.5

3.7

6.4

9.0

11.6

0.1

2.0

4.5

7.1

9.7

−1.1

0.6

3.1

5.6

8.3

0.1

0−

0.3

1.4

3.7

6.2

8.8

−3.2

−2.2

−0.1

2.3

5.0

−5.6

−5.1

−3.0

−0.6

2.0

Patt

ern

0.1

5−

2.1

−1.0

1.1

3.5

6.0

−6.4

−6.4

−4.7

−2.4

0.2

−10.1

−10.7

−9.1

−6.9

−4.3

40.2

0−

3.8

−3.4

−1.5

0.7

3.3

−9.7

−10.6

−9.3

−7.1

−4.6

−14.6

−16.4

−15.2

−13.1

−10.5

0.2

5−

5.6

−5.7

−4.2

−2.0

0.5

−13.0

−14.8

−13.8

−11.9

−9.4

−19.2

−22.1

−21.3

−19.4

−16.8

0.0

59.5

13.4

16.5

18.5

20.3

8.1

11.7

14.7

16.7

18.5

6.9

10.3

13.4

15.4

17.1

0.1

07.7

11.0

14.0

15.9

17.7

4.8

7.6

10.4

12.3

14.0

2.3

4.8

7.6

9.5

11.2

Patt

ern

0.1

55.8

8.7

11.5

13.3

15.0

1.4

3.5

6.0

7.8

9.5

−2.3

−0.6

1.9

3.6

5.3

50.2

04.0

6.3

9.0

10.7

12.4

−2.0

−0.7

1.7

3.3

5.0

−6.9

−6.1

−3.9

−2.2

−0.6

0.2

52.1

4.0

6.5

8.1

9.7

−5.3

−4.8

−2.7

−1.1

0.5

−11.4

−11.6

−9.6

−8.1

−6.5

80

Tab

le5.

3–

Con

tinued

.

Def

ect

Over

hea

dC

3D

Cw

=0.3

C3D

Cw

=0.6

C3D

Cw

=0.9

patt

ern

βl

=2

34

56

23

45

62

34

56

0.0

517.2

20.4

21.8

22.3

22.6

16.1

19.0

20.3

20.7

21.0

15.2

17.9

19.1

19.5

19.7

0.1

015.6

18.3

19.5

19.9

20.1

13.2

15.4

16.4

16.5

16.7

11.2

13.1

13.9

14.0

14.1

Patt

ern

0.1

514.0

16.3

17.3

17.5

17.6

10.3

11.8

12.4

12.4

12.4

7.2

8.3

8.7

8.5

8.5

60.2

012.4

14.3

15.0

15.0

15.1

7.4

8.2

8.5

8.2

8.1

3.3

3.4

3.5

3.1

2.9

0.2

510.8

12.2

12.7

12.6

12.6

4.5

4.6

4.5

4.1

3.8

−0.7

−1.4

−1.8

−2.4

−2.7

0.0

514.5

18.1

20.2

21.1

21.8

13.4

16.7

18.6

19.5

20.1

12.4

15.6

17.5

18.2

18.8

0.1

012.9

16.0

17.9

18.6

19.2

10.4

13.0

14.6

15.3

15.8

8.4

10.6

12.2

12.7

13.2

Patt

ern

0.1

511.3

13.9

15.6

16.2

16.7

7.5

9.3

10.6

11.1

11.5

4.4

5.7

6.9

7.2

7.5

70.2

09.7

11.8

13.3

13.8

14.2

4.6

5.6

6.7

6.9

7.2

0.3

0.7

1.6

1.7

1.9

0.2

58.0

9.7

11.0

11.3

11.7

1.6

2.0

2.7

2.7

2.9

−3.7

−4.2

−3.7

−3.8

−3.8

0.0

56.9

11.8

16.2

19.6

22.8

5.4

10.1

14.4

17.8

21.1

4.2

8.7

13.1

16.5

19.8

0.1

05.0

9.4

13.7

17.0

20.3

2.0

5.9

10.1

13.4

16.7

−0.5

3.2

7.3

10.7

14.1

Patt

ern

0.1

53.1

7.1

11.2

14.5

17.7

−1.4

1.8

5.8

9.1

12.4

−5.1

−2.3

1.6

5.0

8.4

80.2

01.2

4.7

8.7

11.9

15.2

−4.8

−2.3

1.4

4.7

8.1

−9.8

−7.9

−4.1

−0.7

2.8

0.2

5−

0.6

2.4

6.2

9.4

12.7

−8.2

−6.5

−2.9

0.3

3.7

−14.4

−13.4

−9.8

−6.5

−2.9

0.0

53.2

6.8

10.2

13.5

16.3

1.8

5.0

8.4

11.7

14.4

0.6

3.7

7.0

10.3

13.1

0.1

01.4

4.4

7.7

10.9

13.6

−1.5

0.8

3.9

7.1

9.8

−4.0

−2.0

1.1

4.3

7.0

Patt

ern

0.1

5−

0.4

2.0

5.1

8.2

10.9

−4.9

−3.4

−0.6

2.5

5.2

−8.6

−7.6

−4.9

−1.8

1.0

90.2

0−

2.3

−0.4

2.5

5.5

8.2

−8.2

−7.6

−5.1

−2.1

0.6

−13.2

−13.3

−10.9

−7.8

−5.1

0.2

5−

4.1

−2.8

−0.1

2.9

5.5

−11.5

−11.8

−9.6

−6.7

−4.0

−17.8

−18.9

−16.9

−13.9

−11.2

81

5.7 Conclusion

This chapter deals with the problem of low compound yield in wafer-on-wafer stacking.

We propose a manipulation method involving sector symmetry and cut (SSCn). In this

manipulation method, each wafer is cut into n identical sectors that are used to replenish

the repository for matching. By wafer cut, the matching restrictions for dies on a wafer are

reduced and correspondingly the compound yield is improved. Extensive experiments are

conducted to compare the compound yield of the proposed hybrid and SSCn procedures with

existing works under various defect distributions. It is demonstrated that SSCn procedure

improves the compound yield significantly irrespective of the type of defect distribution.

We derive mathematical formulas for DPS and DPW calculation for rotationally sym-

metric wafers. We find greater flexibility of wafer matching by sector symmetry and cut,

which on the other hand induces larger die loss in turn reducing the total number of final

good 3D ICs. Based on experiments, we conclude that SSC4 should be a rule-of-thumb in

practice to maximize the benefit of the proposed technique. A cost model of 3D IC manu-

facturing is constructed and cost-effectiveness of SSCn is analyzed. It is demonstrated that

SSC4 largely reduces the 3D IC cost under various defect models especially for situations

where number of stacked layers is large. As 3D technology reaches maturity, even larger cost

benefits of SSC4 may be expected.

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Chapter 6

Conclusions and Future Work

This dissertation mainly focuses on the topics of speeding up pre-bond TSV test and

improving the compound yield of wafer-on-wafer stacked 3D ICs. The emerging IEEE P1838

standard supports all other test moments except for pre-bond TSV test, which makes pre-

bond TSV test very challenging and important. Chapter 2, 3, and 4 form a complete piece

of work on speeding up pre-bond TSV test. The fabrication of a 3D IC using wafer-on-wafer

stacking has its irreplaceable advantages and is widely used in memory on memory stacking.

Thus, chapter 5 focuses on how to improve wafer-on-wafer stacking yield and reduce the cost

of 3D wafer-on-wafer stacked ICs.

Chapter 1 gives the reader a broad view of various existing 3D technologies, 3D IC fab-

rication process, 3D IC test moments, test solutions, and challenges. In chapter 1, we mainly

focus on three topics. The first topic is about TSV, including its fabrication process, possible

defects, and the electrical models of both normal and defective TSVs. The introduction of

TSV characteristics makes the illustration of the pre-bond TSV probing technology clearer.

The second topic is on introducing the state-of-the-art TSV probing technique which serves

as the basis for our work presented in chapter 2 to chapter 4. The third topic is on the

developing IEEE P1838 standard. We introduce the standard for two reasons. First, it gives

the reader the pre-knowledge of the up-to-date test solutions for 3D ICs. The other reason

is the pre-bond TSV probing technique is actually compatible with the standard, utilizing

boundary scan registers to drive TSVs during probing.

In chapter 2, we proposed an ILP model to generate near-optimal set of test sessions

for pre-bond TSV probing. There are advantages of our ILP model over existing heuristic

methods. First, the total test time of all the sessions is always less for the ILP model.

83

Second, the total number of generated test sessions are smaller in most of the cases. For

cases where the number of sessions is the same as that of heuristic method, we demonstrated

that the total test time is still much less. Third, for various TSV networks with different

parameters, the test time reduction of the ILP model remain pretty consistent, and thus

eliminates the need for separately designing and optimizing the test for each TSV network

as required by previous work. There is still space for future work on test session generation,

such as possibly finding a necessary and sufficient condition to generate globally optimal set

of sessions.

The ILP model in chapter 2 constructs test sessions but it doesn’t provide any infor-

mation on how to identify faulty TSVs based on the sessions. In chapter 3, we proposed a

fast TSV identification algorithm which actually identifies the faulty TSVs based on given

test sessions. This algorithm speeds up pre-bond TSV probing from two aspects. First, any

unnecessary session during the test is skipped. Second, the test terminates as soon as either

all TSVs have been identified or a pre-specified maximum number of faulty TSVs have been

identified. Extensive experiments are done, and the benefits of the algorithm are explained

in details.

In chapter 4, we first proposed a session sorting procedure to sequence test sessions in

such a way that the pre-bond TSV test can terminate as soon as possible for small number

of faulty TSVs within a network. The motivation of our proposal is based on the observation

that TSV yield is pretty high in practice and the probability of small number of faulty TSVs

(less than 2) within a network approaches 100%. After the introduction of session-sorting

procedure, we combine it with the work presented in chapter 2 and 3, and further propose

a 3-Step test time Optimization Simulator (SOS3). In SOS3, the ILP model in chapter 2

is first used to generate a series of test sessions with certain fault identification capability.

Then, these test sessions are sorted to reduce the expectation of test time. Lastly, the fast

TSV identification algorithm is used for early test termination. SOS3 as a framework is

84

demonstrated to greatly reduce pre-bond faulty TSV identification time. SOS3 is expected

to greatly reduce pre-bond TSV test cost in real silicon.

The work on pre-bond TSV testing provides necessary known good die information for

wafer-on-wafer stacking which is the topic of chapter 5. Chapter 5 proposed to design rota-

tionally symmetric wafers and cut each wafer into several identical sub-wafers during wafer

matching process. Our proposal named sector symmetry and cut n (SSCn) is demonstrated

to largely improve the wafer-on-wafer stacking yield and reduce the 3D IC cost for various

defect distributions. Since wafer-on-wafer stacking has its unreplaceable advantages and is

widely used in memory on memory stacking, the achieved yield improvement and cost reduc-

tion of our work could be pretty significant. Note some future work can still be done. The

reported experiments assume that wafers used in the same stack all have the same kind of

defect distribution. This may not be the case in practice since wafers from different vendors

may be used for 3D stacking. Even for the same manufacturer, the fabricated wafers may

have different defect distributions. More experiments are needed to study the compound

yield of stacking wafers with different defect distributions. Another direction of future re-

search is to develop a mechanism that can effectively force the unattractive wafers to leave

repositories so as to reduce repository pollution. Once the problem of pollution is solved,

the SSCn procedure is likely to reveal larger advantages.

85

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Appendix A

Impact of Number of Cuts on Final Production Size of Good 3D ICs

Figure A.1 shows the final production size of good 3D ICs considering different numberof cuts. Same setup as in Section 5.5.1 applies here. As we can see, in most cases four-cuts produces the largest number of good 3D ICs. Note that 2 cuts are not used in theseexperiments because DPW of 2 cuts is identical to that for 4 cuts. However, 2-cuts provideless flexibility in matching and will definitely yield fewer good 3D ICs than 4 cuts. Also notethat 3 cuts are not used either because the DPW for 3 cuts is lower than that for 4 cuts.Besides, 3 cuts provide less flexibility in wafer matching. More experiments have been doneconsidering different wafer sizes, die sizes, defect models, etc. Since results are similar, theyare not duplicated here.

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Figure A.1: Exploring the impact of number n of cuts on final production size of good 3DICs produced by the sector symmetry and cut (SSCn) procedure.

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