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On-Chip Multi-Channel Waveform Monitoring forDiagnostics of Mixed-Signal VLSI Circuits

Koichiro Noguchi, Makoto Nagata

To cite this version:Koichiro Noguchi, Makoto Nagata. On-Chip Multi-Channel Waveform Monitoring for Diagnostics ofMixed-Signal VLSI Circuits. DATE’05, Mar 2005, Munich, Germany. pp.146-151. �hal-00181508�

On-Chip Multi-Channel Waveform Monitoring forDiagnostics of Mixed-Signal VLSI Circuits

Koichiro Noguchi and Makoto NagataDepartment of Computer and Systems Engineering, Kobe University

1-1 Rokkodai-cho, Nada-ku, Kobe 657-8501, Japan{noguchi,nagata}@cs26.scitec.kobe-u.ac.jp

Abstract

Multi-channel waveform monitoring technique enhancesbuilt-in test and diagnostic capability of mixed-signal VLSIcircuits. An 8-channel prototype system incorporates adap-tive sample time generation with a 10-bit variable step de-lay generator and algorithmic digitization with a 10-bit in-cremental reference voltage generator. The prototype ina 0.18-µm CMOS technology demonstrated on-chip wave-form acquisition at 40-ps and 200-µV resolutions. Thewaveforms were as accurate as those by an off-chip mea-surement technique, while more than 95 % reduction of thewaste time in waveform monitoring was achieved. The areaof 700µm × 600µm was occupied by a single waveform ac-quisition kernel that was shared with 8 front-end modules of60µm × 200µm each. The developed on-chip multi-channelwaveform monitoring technique is waveform accurate, areaefficient, and low cost, which are all requisite factors fordiagnosing methodology toward mixed analog and digitalsignal integrity in a systems-on-a-chip era.

1 Introduction

Capturing signal waveforms on-chip is the most straight-forward measure of in-depth diagnostics in a mixed-signalintegrated circuit. As recent growth of systems-on-a-chip(SoC) markets forces to locate much more functionality andperformance on a single die, most of chips appear to bemixed-signal. However, there are various physical issuesthat influence dynamic circuit behaviors in advanced SoCs,which finally degrades chip performance or even leads tomalfunction. Examples include spurs in analog-to-digital ordigital-to-analog conversion, jitters in phase-locked loops,and unstable skew variations in clock distribution networkor among critical paths. Embedding signal monitoring cir-cuitry within SoC chips provides the functionality of run-time test of circuit performance as a part of built-in self-test

mechanisms as well as diagnostics of invasive factors suchas noise, which is strongly helpful for calibration, valida-tion, and improvement of physical design flow. This ap-proach will be getting common as the integration capacityincreases, where die area occupied by the embedding cir-cuitry can trade off directly with the cost of mixed-signaltest facility and also indirectly with the effective use of elec-tric design automation (EDA) tools.

This paper proposes an architecture of on-chip waveformmonitoring that realizes multi-channel waveform-accurateprobing at low area consumption and with minimum off-chip measurement equipments. Enabled waveform acqui-sition at various locations on-chip provides extended diag-nostics and testability over previous works. On-chip ana-log test signal generation and analog signal capturing inenhancing testability of analog / mixed-signal circuits wasdiscussed in [1]. As for more diagnostic purposes, on-chiposcilloscope macros targeting wide-bandwidth signal cap-turing within high-speed digital signaling have appeared in[2][3]. In addition, on-chip measurements of power-supplyand ground dynamic noises [4]-[9], signals [10], and clockjitters [11][12] has also been reported.

Section 2 describes a proposed architecture of on-chipwaveform monitoring and discusses flow and cost of mea-surements, followed by details of enabling circuit tech-niques in Section 3. Section 4 presents design and mea-surement results of a 0.18-µm CMOS prototype chip, andfinally, conclusions will be given in Section 5.

2 Architecture

2.1 OverviewFigure 1 shows a chip structure embedding a multi-channelwaveform monitoring function, where tiny probing front-end modules locate adjacent to each circuit block to monitorand probe wiring is drawn from the module to the point ofinterest within the block, and every module shares a singlewaveform acquisition kernel that locates on the top. This ar-

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Figure 1. Chip embedding on-chip multi-channel probing.

chitecture has the flexibility in placing the waveform mon-itor modules into open spaces after the completion of SoClayout, and therefore minimizes the cost of embedding.

In order to materialize the chip structure, we have par-titioned an entire monitor circuitry as shown in Figure 2.A probing front-end module (PFE) consists of a source fol-lower (SF) and a latch comparator (LC), where probe wiringfrom a target signal of interest is input to SF and its DC-level-shifted output voltage Vsf is compared with referencevoltage Vref by LC, immediately within PFE when sam-pling clock Tck is given. Therefore, output of PFE, Dout,is a single bit binary digital stream. Another input signal toPFE is bias voltage Vbsf given to SF. On the other hand, awaveform acquisition kernel includes a reference level gen-erator (VG) supplying Vref from a 10-bit R-2R ladder, asampling timing generator (TG) providing Tck from a 10-bit variable step delay generator, and a data processing unit(DPU) producing a series 10-bit digital word from Dout.

This partitioning allows to connect multiple PFEs to thesingle kernel with multiplexing only digital signals, Tck andDout, while distributing common analog signals, Vref andVbsf . Compared with a conventional architecture consistingof compatible circuit components given in Figure 3 whereS/H signals are multiplexed at the input to analog-to-digitalconverter (ADC) with a successive approximation regis-ter (SAR), the proposed architecture eliminates the neces-sity of multiplexing analog signals of interest and thereforeachieves multiple channel probing without degrading wave-form acquisition performance. Here, while one of PFEs isactivated during waveform acquisition, all the others are cutoff from power-supply through logical control accordinglyto a state register. Another key difference from SAR-ADCis found in the monotonously incremental DAC operation ofVG, which also eliminates the feed-back processing neededby SA operation. Finally, since our waveform acquisitionworks on the basis of sampling principle, an explicit sam-

Figure 2. Architecture of on-chip multi-channel probing.

Figure 3. Conventional architecture multiplex-ing inputs to ADC.

pling capacitor was equivalently replaced with repetitivecomparison of Vsf against Vref at LC with statistical pro-cessing, as will be discussed in the next section.

2.2 Flow and cost of waveform acquisitionFigure 4 shows the flow of waveform monitoring by the pro-posed architecture, based on sampling principle. The flowhas dual loop operations where reference voltage loop isnested by sample timing loop, and premises that VG andTG generate incrementally stepwise voltage and samplingtiming, respectively. Here, TG generates Tck for every neg-ative edge of Mck that is initially located at a certain cycleof system clock (Sck), Tsck, as shown in Figure 5(a). Then,VG generates Vref and LC repetitively compares it with Vsf

thus the probed voltage at this timing. After 210 iteration,average of LC decision is output from DPU as probabil-ity, Pcmp, and then Vref increased step-wisely. When VGgoes through every 10-bit steps, digitized Vsf is determinedas the bit number of Vref at the highest slope of ∆Pcmp /∆Vref in the comparator transition region. Then, TG setsforward Tck as shown in Figure 5(b) and again the 2nd loopis going. When TG goes through every 10-bit steps, TGis reset and Mck thus the first edge from TG is placed rel-atively to the next cycle of Sck as shown in Figure 5(c),

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Figure 4. Flow of waveform acquisition.

Figure 5. Timing generation.

and VG is also reset and resumes Vref loop. The operationcontinues until user-specified loop count, and then a sig-nal waveform at the probe is reproduced from time-seriesdata of the digitized Vsf . Here, one can also acquire anon-chip signal waveform by embedding a PFE alone as hasbeen achieved in previous works [5][8], if the necessary in-put signals to PFE is provided from off-chip measurementequipments that are automatically controlled by PC. How-ever, since the total loop count in the proposed waveform-acquisition flow reaches the order of 109, accumulated ac-cess time to the measurement equipments from the PC cannot be negligible. Figure 6 roughly compares the total timeof acquiring 1024 measurement points. For the cases withembedding PFE alone, the time for the simple incremen-tal algorithm same as Figure 4 explodes while successive-approximation like algorithm reduces it in 1/10, however,still more than 5 hours is required. On the other hand, thenative time of 4 minutes is only left when embedding thewhole of the system of Figure 2 that is running at 4 MHz.

Figure 6. Estimated cost of waveform acqui-sition.

Figure 7. Probing front-end module, (a) N-channel SF, (b) P-channel SF, (c) latch com-parator.

This is the clear motivation of the development of on-chipmulti-channel waveform monitoring, where the cost of mea-surement time can be traded-off with that of die area.

3 Circuit description

3.1 Probing front-end moduleOne from two types of PFEs using P-channel or N-channelSF shown in Figure 7 is selectively applied to the signal ofinterest, depending on the DC voltage level of the signal.P-channel SF works for voltage ranging from below 0 V toV dd − V thp, where V dd and V thp are the supply voltageand the threshold voltage of P-type MOSFET, respectively.On the other hand, N-channel SF works for voltage rang-ing from above V dd to V thn, where V thn represents thethreshold voltage of N-type MOSFET. While AC small sig-nals with DC voltage at half V dd, which is often equal tothe bias point of analog circuits, can be covered either P-channel or N-channel SF, the full voltage range in a low-voltage digital circuit with V dd of the degree of 1.2 V canbe sensed by a single P-channel SF based PFE using high-voltage, for instance, 3.3-V MOSFETs. A simple topologyof Figure 7(c) was chosen as LC in order to minimize thearea of PFE. The entire PFE was designed to retain the gain

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Figure 8. Reference voltage generator. (a)schematic and (b) voltage steps.

Figure 9. Variable step delay generator.

of 0 dB from DC to 1.0 GHz. It should be noticed thatthe unexpected interaction with the circuit under monitor-ing must be minimized in the design of on-chip waveformmonitoring circuit. The SF not only buffers the signal ofinterest to LC but also isolates the waveform monitoringcircuit from the circuit to monitor. Therefore, the proposedPFE can apply for monitoring various kinds of signals oreven noises in a mixed-signal VLSI circuit.

3.2 Reference voltage generatorReference voltage generator, VG, showing in Figure 8(a)consists of R-2R ladder dividing external reference DC volt-ages of Vrefp and Vrefm and a 10-bit binary digital counterthat increments the output value at every positive edge ofDACinc. The switch network of R-2R ladder is designed togenerate Vref that is linear to the output digital code fromthe 10-bit counter. Therefore, VG works as a 10-bit incre-mental digital-to-analog converter (DAC) as shown in Fig-ure 8(b).

3.3 Sampling timing generatorThe most straightforward implementation of TG usesvoltage-controlled delay line (VCDL) for timing genera-tion, however, the size of circuit can easily explode as thenumber of bits of delay step increases, and moreover, it cancreate significant environmental noises since all delay cellsare activated at every input edge. These inappropriatenesscan not be mitigated even if interpolaters between delaycells or Vernier topology are applied. Therefore, we havedeveloped a variable step delay generator (VSDG) shownin Figure 9, where bias current, Ib, is divided by an integer,

Figure 10. Detail of 10-bit variable step delaygenerator.

Figure 11. Replica delay locked loop.

n, corresponding to a digital code and thus the delay time,Tdelay , follows to:

Tdelay(n) = n × Tdelay(0), (1)

where Tdelay is measured from negative edge of input clock,Mck, to positive edge of output clock, Tck, and Tdelay(0) isthe minimum delay. Here, Ib is regulated by a replica DLLthat equates the maximum delay of Tdelay(2m) to the clockperiod of system clock, Sck.

Figures 10 and 11 show actual implementation of 10-bitVSDG and replica DLL, respectively. VSDG is a current-mode circuit and 6-bit MSB delay step is finely tuned byinjecting 4-bit LSB currents. The net maximum delay ofTdelay(210) is defined by subtracting offset delay (T offset

delay )from the maximum delay (T max

delay) of the 6-bit MSB delaysteps as shown in Figure 11, and equated to the clock pe-riod of Sck by the replica DLL. Therefore, TG generatessampling time adaptively to Sck of a target circuit. Theproposed VSDG-based TG is very quiet since only a sin-gle transition occurs for every timing generation along withtwice transitions in replica DLL for every phase adjustment,and therefore suitable for on-chip waveform monitoring.

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Figure 12. Die photo.

Figure 13. Measurement setup.

4 Experiments

4.1 Prototype chip designA prototype chip shown in Figure 12 was developed usinga 0.18-µm CMOS technology, where eight PFEs sharing asingle waveform acquisition kernel probed various wiringswithin a programmable 24-bit digital shift register file (SR).Another identical waveform acquisition kernel is also in-cluded for evaluation. Here, the occupied areas are 700µm× 600µm for the kernel and 60µm × 200µm for each PFEin a 2.8mm × 2.8mm chip. The kernel and PFEs weredesigned with 2.5-V I/O MOSFETs and located within adeep N-type well that was capacitively isolated from a com-mon P-type substrate, on the other hand, all the other cir-cuits used 1.8-V CMOS devices in a conventional twin wellstructure.

4.2 Measurement resultsMeasurement setup is described in Figure 13, consistingof a logic analyzer (LA) fully controlled by PC through

Figure 14. Acquired waveforms on (a) VDDand (b) GND wirings.

Figure 15. Actual cost of waveform acquisi-tion.

TCP/IP interface, power-supply and analog voltage sources,and the prototype chip mounted on a device under test(DUT) board. LA provides a digital vector to SR, DLLincand DACinc signals that force TG and VG to incrementsteps, respectively, and clock signals of Sck and Mck. Italso collects output from the prototype chip.

Figure 14 shows waveforms on power-supply andground wirings in SR running at Sck of 100 MHz. Twofrom the eight PFEs were applied, and moreover, waveformacquisition using the on-chip kernel and also that with thefull use of external equipments as in a conventional waywere compared. Obviously, waveforms in both on-chip andoff-chip signal generation are quite consistent, thus pro-posed architecture of Figure 2 is successfully implemented.In TG, the replica DLL was locked to Sck through a pro-grammable divider with a factor of 4, thus 25 MHz, and 10-bit VSDG generated the delay step of roughly 40 ps. Whilein VG, the center between Vrefp and Vrefm was roughly setat SF’s shift voltage and their voltage difference was 200mV, thus the 10-bit R-2R ladder created the voltage step ofroughly 200 µV.

Actual waste time of the on-chip and off-chip signal gen-

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Figure 16. Results of long-time waveform ac-quisition.

eration with SA algorithm for 1024 point waveform acqui-sition is summarized in Figure 15, which is larger than es-timation in Figure 6 due mainly to additional time of datatransfer from LA to PC in this measurement setup. How-ever, more than 95% reduction of measurement time wasachieved in on-chip waveform monitoring system, as ex-pected.

Figure 16 shows an example of long-time waveformmonitoring on the same power-supply and ground wirings,where Mck input to VSDG relatively moved in 40 ns when-ever the 10-bit step delay generation completed, as wasshown in Figure 5, until waveform acquisition of the total of24 clock cycles of Sck. Each waveform includes 6144 datapoints, which is only possible with the on-chip signal gener-ation, in terms of the measurement time. Apparent 4-clockcycle patterns are seen in the waveforms, resulting from a4-bit repetitive pattern of ”0011” written in SR.

5 Conclusion

Multi-channel waveform monitoring technique was pro-posed and implemented with a 10-bit incremental referencevoltage generator using R-2R ladder and a 10-bit incremen-tal sample timing generator incorporating a variable stepdelay generator. The prototype in a 0.18-µm CMOS tech-nology demonstrated on-chip multi-point waveform acqui-sition at 40-ps and 200-µV resolutions synchronously toa digital test circuit running at 100 MHz. The waveformswere as accurate as those by an off-chip measurement tech-nique, while more than 95% reduction of the waste timein waveform monitoring was achieved. It was obviouslyproven that the developed technique was waveform accu-rate, area efficient, low cost, and capable of monitoring ana-log and digital signals, although limited experiments on adigital test circuit were described. These factors are all req-uisite for diagnosing methodology toward mixed analog anddigital signal integrity in a systems-on-a-chip era.

AcknowledgmentsThis work is supported by Semiconductor Technology Aca-demic Research Center (STARC). The authors would like tothank Masaki Hirata, Shin′ichiro Azuma, Toshihiko Mori, ShiroDoushoh, and Hiroaki Ohkubo for helpful discussions. Test chipswere fabricated by Hitachi Ltd. in the chip fabrication programprovided by VLSI Design and Education Center (VDEC) of theUniversity of Tokyo, in collaboration with Dai Nippon PrintingCorporation.

References[1] G. W. Roberts, “Improving the Testability of Mixed-Signal In-tegrated Circuits,” in Proc. Custom IC Conf., May. 1997, pp.214-221.[2] Y. Zheng and K. Shepard, “On-Chip Oscilloscopes for Nonin-vasive Time-Domain Measurement of Waveforms in Digital Inte-grated Circuits,” IEEE Trans. VLSI Systems, June 2003, pp. 336-344.[3] M. Takamiya, M. Mizuno, and K. Nakamura, “An On-chip100GHz-Sampling Rate 8-channel Sampling Oscilloscope withEmbedded Sampling Clock Generator,” in ISSCC Dig. Tech. Pa-pers, Feb. 2002, pp. 182-183.[4] K. M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura, andM. Hotta, “Voltage-Comparator-Based Measurement of Equiva-lently Sampled Substrate Noise Waveforms in Mixed-Signal Inte-grated Circuits,” IEEE J. Solid-State Circuits, Vol. 31, No. 5, pp.726-731, May. 1996.[5] M. Nagata, J. Nagai, T. Morie, and A. Iwata, “Measurementsand Analyses of Substrate Noise Waveform in Mixed-Signal ICEnvironment,” IEEE Trans. CAD of Integrated Circuits and Sys-tems, June 2000, pp. 671-678.[6] M. Heijningen, J. Compiet, P. Wambacq, S. Donnay,M. G. E. Engels, and I. Bolsens, “Analysis and Experimental Ver-ifi cation of Digital Substrate Noise Generation for Epi-Type Sub-strates,” IEEE J. Solid-State Circuits, July 2000, pp. 1002-1008.[7] A. Muhtaroglu, G. Taylor, and T. Rahal-Arabi, “On-Die DroopDetector for Analog Sensing of Power Supply Noise,” IEEE J.Solid-State Circuits, April 2004, pp. 651-660.[8] K. Shimazaki, M. Nagata, T. Okumoto, S. Hirano, and H. Tsu-jikawa, “Dynamic Power-Supply and Well Noise Measurementand Analysis for High Frequency Body-Biased Circuits,” in Symp.on VLSI Circuits Dig. Tech. Papers, pp. 94-97, June 2004.[9] T. Okumoto, M. Nagata, and K. Taki, “A Built-in Techniquefor Probing Power-Supply Noise Distribution within Large-ScaleDigital Integrated Circuits,” in Symp. on VLSI Circuits Dig. Tech.Papers, pp. 98-101, June 2004.[10] R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, andM. Horowitz, “Applications of On-Chip Samplers for Test andMeasurement of Integrated Circuits,” in Symp. VLSI Circuits Dig.Tech. Papers, June 1998, pp. 138-139.[11] R. Kuppuswamy, K. Callahan, K. Wong, D. Ratchen, andG. Tayloer, “On-die Clock Jitter Detector for High Speed Micro-processors,”in Symp. VLSI Circuits Dig. Tech. Papers, June 2001,pp. 187-190.[12] M. Takamiya, H. Inohara, and M. Mizuno, “On-Chip Jitter-Spectrum-Analyzer for High-Speed Digital Designs,” in ISSCCDig. Tech. Papers, Feb. 2004, pp. 350-351.

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