On-Chip AC–DC Multiple-Power-Supplies Module for...

1724 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 54, NO. 2, MARCH/APRIL 2018

On-Chip AC–DC Multiple-Power-Supplies Modulefor Transcutaneously Powered Wearable

Medical DevicesYen-Chia Chu , Le-Ren Chang-Chien , N. Sertac Artan , Dariusz Czarkowski, Chih-Hsiang Chang, Jialin Zou,

and H. Jonathan Chao

Abstract—Replacing the batteries of wearable medical devices isan inconvenience to the user. Wireless power transfer (WPT) couldbe a solution for this problem. However, the structure should becompact to satisfy the wearable device requirements and the powerefficiency should be as high as possible for prolonging the userexperience. Besides, as algorithms embedded in these devices be-come more complex, the device power consumption also increases.Fulfilling these specifications in a compact structure with betterefficiency is the aim of this research paper. This paper proposesa power processing module for WPT applications. This moduleis embedded within the WPT path to convert receiving end acpower to dc power, and to simultaneously provide multiple dc–dcpower conversion for wearable medical devices. The ac–dc circuitis specifically designed using a compact topology to convert wire-less ac power to stable dc power. The dc power is further regulatedby different mode controls either to perform battery charging orto provide independent voltage supplies to dc loads. The integratedcircuit occupies an area of 1.9 × 2.3 mm when implemented on a0.25 µm high voltage CMOS process.

Index Terms—AC–DC power converter, battery charger, pulse-width modulation (PWM) rectifier, rectifier, transcutaneous powertransmission, wearable medical devices, wireless power transfer(WPT).

I. INTRODUCTION

W EARABLE medical devices have become promisingalternatives to monitor, and treat Parkinson’s disease,epilepsy and a plethora of other diseases and disorders [1]–[4].The devices in medical application are required to be small vol-ume, low noise, and high efficiency. However, there would be

Manuscript received December 13, 2016; revised April 4, 2017, June 5, 2017,August 1, 2017, and September 12, 2017; accepted October 12, 2017. Date ofpublication October 29, 2017; date of current version March 19, 2018. Paper2016-IACC-1399.R4, presented at the 2016 Industry Applications Society An-nual Meeting, Portland, OR, USA, Oct. 2–6, and approved for publication inthe IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Au-tomation and Control Committee of the IEEE Industry Applications Society.(Corresponding author: Le-Ren Chang-Chien.)

Y.-C. Chu, D. Czarkowski, J. Zou, and H. J. Chao are with New York Uni-versity, Brooklyn, NY 11201 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

L.-R. Chang-Chien and C.-H. Chang are with National Cheng KungUniversity No.1, Tainan City 701, Taiwan (e-mail: [email protected];[email protected]).

N. S. Artan is with the New York Institute of Technology, New York, NY10023-7692 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIA.2017.2767549

several challenges to take these three considerations into ac-count. For example, power hungry device could increase theoverall circuit volume to maintain good voltage regulation. Ifone wants to reduce the volume, operating frequency should beraised. This strategy would cause high-frequency noise prob-lem and drop of power efficiency due to the switching loss. Inwireless applications, reliable power to support the wearablemedical devices is further critical due to the extremely stringentpower and high availability requirements. Power consumptionof wearable medical devices varies significantly based on the tar-get function. Recent designs require calculations for signal pro-cessing and/or continuous monitoring via cloud-based health-care services. Power consumption of such circuits is reported tobe in the range between couples of milliwatts to 30 W [5]. Sev-eral medical microsystems consume 10–30 mW or higher [6].For instance, low power microprocessors integrated on chip forreal-time epileptic seizure detection can have maximum currentconsumption reaching 22.7 mA [7].

Wireless power transfer (WPT) is a notable wireless powersupply solution either for directly powering the device or fortranscutaneously charging an implanted rechargeable battery[8]–[18]. Since WPT adopts ac power to transfer energy throughmagnetic coils, ac–dc conversion is essential. The conventionaltopology of ac–dc power path for medical devices usually hasthree stages: (1) rectifier, (2) dc–dc switching converter, and(3) linear regulator. To fit the small volume requirement, therectifier stage can adopt the bootstrapping technique [8]. Be-cause this kind of rectifier has no voltage or current regulationcapability, use of linear regulators and voltage limiters to re-alize a continuous powering system for medical devices wasproposed in [9]–[11]. Regarding the charging method, linearregulators were used after the rectifier to control the chargingcurrent and to reduce the voltage ripple in [12]–[15]. Since theefficiency of the linear regulator is highly dependent upon volt-age drop between input and output, high efficiency is not easyto achieve for linear regulators to deal with the high-voltagedrop. To further improve efficiency, dc–dc buck type convert-ers were placed between the rectifier and the linear regulator[15], [16]. Although switching converters improve efficiency indc–dc conversion, the power line still needs a rectifier to convertthe ac source to a dc source. From the overall power line pointof view, one more circuit stage implies more power conductionloss and larger circuit layout. Naturally, the idea of merging the

0093-9994 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

https://orcid.org/0000-0001-7761-0462https://orcid.org/0000-0001-9310-9352https://orcid.org/0000-0002-2335-0279

CHU et al.: ON-CHIP AC–DC MULTIPLE-POWER-SUPPLIES MODULE FOR TRANSCUTANEOUSLY POWERED WEARABLE MEDICAL DEVICES 1725

Fig. 1. Conventional three-stage power path for implantable medical devices(from secondary (receiving) coil to battery).

three-stage structure into a single-state structure is attractive.However, there are challenges in designing this single-stagestructure. One challenge is the design of the controller, whichneeds to coordinate multiple switches. The other challenge is thestability issue of dual control loops for the charging function.

Regarding the ac–dc power conversion, this paper introducesa single-stage ac–dc converter that integrates the rectifier, dcstep-down, and battery charger, together. Unlike the design in[17], the switches in the proposed power converter are to operateinternally without external drivers for the WPT-based medicaldevices, since these devices usually operate at high input ac fre-quency [9]–[11], [14] and [18]. Compared to the aforementionedresearch works on multistage converters, the proposed circuithas a compact structure but inherits more functions, which in-cludes the ac–dc conversion, fast battery charging ability, andmultiple dc voltage support for standalone operation [19].

This paper is organized as follows. Section II presents thearchitecture of the proposed ac–dc converter and circuit opera-tion. In Section III, the stability of the proposed architecture isinvestigated. Section IV presents the circuit implementation andthe performance results. Section V draws concluding remarksfor this paper.

II. ARCHITECTURE AND CIRCUIT OPERATION

A. Conventional Power Path Structure for Medical Devices

Fig. 1 demonstrates an example of the conventional three-stage WPT topology. The 14 Vp−p ac power is first transmittedthrough the wireless link by electromagnetic induction. Thetransmitted ac power is then rectified to 5 V dc power. The 5 Vdc value is supposed to be further regulated by a linear regulatorfor charging the battery whose voltage ranges between 3 V and4.2 V. The overall efficiency of this circuit arrangement is lowbecause of the high voltage-dropout between input and outputof the linear-regulator-type charger. To solve this high dropoutvoltage issue, a step-down switching converter is supplementedbetween the rectifier and the linear regulator. The linear regula-tor consequently acts as a current source to control the chargingcurrent. This topology improves the efficiency of the linear reg-ulator because it only regulates a very small voltage drop (about0.3 V) in this case. The overall efficiency of the aforementioned

Fig. 2. Proposed single-stage ac–dc converter for the power path from sec-ondary (receiving) coil to the battery.

structure is around 71.2%. This estimation is based on the 89%efficiency of the rectifier [20], 86% efficiency of a step-downswitching converter [16], [21], and [22], and 93% efficiency ofa linear regulator for the case of 4.2 V output voltage and 0.3 Vdropout voltage.

The reason of using a linear regulator in Fig. 1 is itssimple mechanism to control the charging current. If the Buckconverter is able to regulate voltage and give constant voltage(CV) and constant current (CC) modes of charging, there is noreason to use the linear regulator. Thus, the linear regulator canbe removed to boost the overall circuit efficiency. However,using the topology proposed in [16] for WPT purpose still needsa rectifier at its front end to convert ac to dc power. In orderto further reduce the size of the overall power converter, thispaper attempts to eliminate the rectifier stage and realize therectification function in the Buck converter. To integrate rectifierand charger functions into a single Buck converter, more effortsshould be made in the controller design. For example, a currentsensing loop should be supplemented to deal with CC modeoperation. Different switching mechanism to sustain either CVor CC mode should be carefully coordinated. Furthermore,to perform the rectifier function during battery charging, thecoordination of the four switches inside the proposed Buck torectify ac power to dc power is also a challenge.

B. Proposed Single-Stage AC–DC Converter Module

To reduce the multistage power conversion loss, Fig. 2 demon-strates a single-stage ac–dc converter that is connected to abattery and a single-inductor dual-output (SIDO) converter.Compared to the three-stage power path, the efficiency of thesingle-stage ac–dc converter is expected to be higher. The struc-ture of the converter is also compact since several circuit compo-nents are eliminated including one capacitor from the rectifier,one switch as well as one diode from the step-down switchingconverter, and one MOSFET from the linear regulator.

Fig. 3 depicts the operating principle of the single-stage ac–dc converter. When a sinusoidal ac voltage is induced, the twolow-side MOSFETS, MN1 and MN2 connect the higher voltagenode to Vx and the lower voltage node to the system ground. Atthe same time, two high-side MOSFETS, MP1 and MP2 keep on


Fig. 3. Equivalent circuit for the proposed structure showing the current flowin positive and negative periods. (a) Current flow as inductor is charged in thepositive period. (b) Current flow as inductor discharges in the positive period.(c) Current flow as inductor is charged in the negative period. (d) Current flowas inductor discharges in the negative period. (e) Circuit operation waveforms.

switching to adjust the level of the output voltage. During theac positive period, the MOSFET MP1 first turns on to pass thepower from ac source to Vx . This behavior is shown in Fig. 3(a).When MP1 turns off, MP2 turns on to keep the current flowingas shown in Fig. 3(b). These two actions keep on repeatingseveral times until the end of the ac positive period. During theac negative period, MP2 becomes the major switch to deliverpower to the node Vx . When MP2 turns OFF, MP1 turns ON tokeep current flowing. These two steps are shown in Fig. 3(c) and(d). The resulting voltage waveform Vx is shown in Fig. 3(e).The voltage Vx is then filtered by the output filtering circuit,which includes an inductor L and a capacitor C. The outputvoltage Vout is the average value of Vx . The output voltage levelcan be adjusted by changing the pulse-width of the pulse-widthmodulation (PWM) signal that drives MP1 and MP2.

A small resistor (RS ) is added in series with the inductor.The resistor is used to measure the charging current or the loadcurrent. The resistance is only 0.1 Ω to avoid large voltage drop.The detected voltage is amplified by a gain designed in thecontroller. The measured current is used for current control inthe charging mode. This design makes the single-stage circuitsimultaneously rectify ac power to dc and charge a battery withcurrent control.

C. Operating Principle of the SIDO

The ordered power-distributive control (OPDC) method isapplied to this circuit. The OPDC is a type of non-time-

Fig. 4. Power stage of the SIDO. (a) SIDO circuit. (b) Inductor current wave-form.

multiplexing control scheme [23], [24]. Its switching time is lessthan the time-multiplexing control [25]–[28], so its efficiency isbetter. The power stage of the SIDO is shown in Fig. 4(a), andthe inductor current waveform shown in Fig. 4(b) is used to ex-plain the inductor current behavior of the power stage. At first,the inductor is charged at phase A. The slope of inductor currentis the difference of the input and the output voltages of phaseA (Vout A) divided by inductor value. Its slope is marked inFig. 4(b) as well. At that moment, MP7 and MP8 are turned ON.When the energy is charged enough for phase A, MP8 is turnedOFF, and MP9 is then turned ON. Charging would continue untilthe total energy for both outputs A and B is enough. Then, circuitalternate switches to discharge the inductor energy to the load.At that moment, MP7 is turned OFF, and MN3 is turned ON.The circuit repeats the sequence of the aforementioned actionin every cycle.

III. STABILITY ANALYSIS

A. AC–DC Converter Power Stage Model

The single-stage structure can be modeled as a step-downswitching converter because the frequency of the input ac poweris much lower than the switching frequency. The slow-changingac power is viewed as a dc input for the circuit. The operat-ing principle shown in Fig. 3 is similar to that of a step-downswitching converter. Inside the step-down switching converter,the inductor is charged when the high-side MOSFET turns ONand is discharged when the high-side MOSFET turns OFF. Thisaction can be mapped to the positive period and negative period.Equation (1) can be used as the control-to-output transfer func-tion of the ac–dc converter [19], [29]–[32]. In (1), Gvd is thecontrol-to-output gain that depends on the inductor, L, the outputcapacitor, C, the equivalent series resistance on the capacitor,RESR , the dc resistance of the inductor, RL , the equivalent loadresistor, Rload , the corner angular frequency, ω0, and the qual-ity factor, Q. Based on (1), a numerical model is developed in


Fig. 5. Bode diagram of the control-to-output gain for voltage loopwith/without compensation.

MATLAB software to plot the Bode diagram of the open-loopgain, which is shown in Fig. 5. The effect of the Rs on thezero is incorporated but this effect is small and can be safelyignored since Rs value is smaller than RL . The parameter val-ues of the circuit are chosen as follows. The root-mean-squarevalue of the input ac voltage, Vin rms = 5 V; the output volt-age, Vout = 3–4.2 V; the output current, Iload = 1–200 mA;the switching frequency, fsw = 1 MHz; the input ac sourcefrequency fac = 100 kHz; C = 40 μF; RESR = 125 mΩ; L =8.2 μH; RL = 100 mΩ, (3) shown at the bottom of this page.

Gvd (s) =v̂o

d̂= D · Vin rms · 1 + RESR · C · s

L · C · s2 + sQω0 + 1(1)

ω0 =1√

L · C (2)

The Bode diagram in Fig. 5 is the control-to-output gain underlight load. The solid line is the loop gain without compensation,and the dashed line is the loop gain with compensation. There aretwo conjugate poles at 8 kHz. These two poles cause the phase todrop rapidly at that point. Although there is a zero in the system,its location is too far from the poles to have any influence.Generally, an integrator is always needed to eliminate the steady-state error because the dc gain is limited in this system. However,an addition of an integrator to the closed-loop system brings thephase of the system down 90◦, which means that the system isnot stable. A possible solution for this problem is to employ acompensator to provide additional zeros and poles, which canenhance the stability of the system. The dynamic behavior ofthe system is not a major concern in most of the time whenthis ac–dc converter is working solely as a battery charger. Theslow dynamic behavior occurs only when this structure supplies

Fig. 6. Bode diagram of the control-to-inductor-current gain for current loopwith/without LPF before compensation.

power directly to a circuit without a battery. Therefore, using thepower supplies from the SIDO to have fast response if necessary.

Regarding the battery charging function, the amount of cur-rent flowing into the battery is a major concern. In this case, theinductor current is measured and its average value is extracted asan indicator of current flow into the battery. The stability of thecurrent control loop is related to the control-to-inductor-currenttransfer function. Since this single-stage structure is approxi-mated to a step-down switching converter, the model of control-to-inductor-current can be expressed as [33, eq. (4)]. Accordingto (4), the Bode diagram is depicted in Fig. 6. The solid line isthe control-to-inductor-current gain under light load

Gid (s) =îL

d̂

= D · Vin rmsRload

· (1 + Rload · C · s) · (1 + RESR · C · s)L · C · s2 + sQω0 + 1

. (4)

In comparison to the charging current, the inductor currenthas high variation. In order to obtain the information of thecharging current, a low-pass-filter (LPF) is employed to extractthe dc value of the inductor current. The transfer function ofthe LPF circuit in the following equation can be considered asa pole

GLPF (s) =1

1 + RLPF · CLPF · s . (5)

The components in the LPF are selected as: RLPF = 20 kΩand CLPF = 40 nF. These values are selected to determine thepole, which is set to cancel the zero from load and capacitor sothat the gain at high-frequency range can be suppressed. Com-bining Gid and GLPF together, the current control loop gain is

Q =1ω0

· (RL + Rs) + RloadL + C · Rc · (RL + Rs) + C · Rc · Rload + C · (RL + Rs) · Rload . (3)


depicted as the dash line in Fig. 6. The dc gain is negative, whichmeans the current barely changes when the duty signal varies.This situation implies no control of the current. Therefore, acompensator is needed to solve this problem.

B. Voltage Control Loop Compensation for the AC–DCConverter

A compensator is designed in accordance with this powerstage model. To compensate the closed-loop system, a type-II compensator is employed. A typical transfer function of atype-II compensator [34] is shown as follows:

Gc typeII (s) =1

R1 · C1 ·s + 1R2·C2

s ·(s + C1+C2R2·C1·C2

) . (6)

It is composed of an operational amplifier, two resistors, R1and R2, and two capacitors, C1 and C2. It provides one zero,one pole, and an integrator. The zero can be placed on the pointto cancel the effect of one of these poles and boost the phase.To improve the dc gain, an integrator is included to provide adc gain as high as the op-amp gain in the compensator. Thepurpose of the high dc gain is to reduce the static error betweenthe output voltage and the reference voltage. Increasing theswitching frequency reduces the ripple but it also leads to highswitching losses. To make the tradeoff, the switching frequencyof the proposed circuit is selected at 1 MHz. The ac input shouldbe at least 10× lower than the switching frequency to allowenough PWM signals in one ac period to regulate the ac voltageinto dc voltage. To make a better wireless power transfer, thefrequency of the ac source at the primary side should be carefullyconsidered to match the coil design. To reduce the switchingnoise, the cross-over frequency is selected at 18 kHz, which isless than one tenth of the switching frequency. The parametersfor the compensator are: R1 = 300 kΩ; R2 = 150 kΩ; C1 =5 pF; C2 = 1 nF. In Fig. 5, the dc gain is increased from 8 dBto more than 40 dB at 10 Hz. The loop is stable with 50◦ phasemargin when the cross-over frequency is 12 kHz.

C. Current Control Loop Compensation for AC–DC Converter

The same design process for the compensator is applied to thecurrent control loop. The parameter in this type-II compensatoris as follows: R1c = 90 kΩ; R2c = 100 kΩ; C1c = 10 pF; C2c =20 nF. The compensated loop gains under light and heavy loadconditions are shown in Fig. 7. The bandwidth is 5 kHz thatis high enough for controlling charging current. The dc gainis largely boosted compared to the uncompensated loop gain.Therefore, charging current can be well controlled, and the loopis stable.

D. Line-to-Output Analysis for AC–DC Converter

In the proposed circuit, the ac side voltage is directly regulatedto the required dc voltage level at output. Therefore, the line-to-output gain is a major concern in the design of the proposedconverter. Based on the previous assumption, the open-loopline-to-output transfer function can be simplified as (7). It isvery similar to the line-to-output transfer function in [33], but

Fig. 7. Control-to-inductor-current gain with LPF and compensator.

Fig. 8. Bode diagram of the line-to-output model.

an ESR effect is considered in (7). The definitions of all theparameters in the following equation are the same as in (1):

Gvg (s) =v̂ov̂in

= D · RloadRload + (RL + Rs)

· 1 + RESR · C · sL · C · s2 + sQω0 + 1

. (7)

After the loop is compensated, the new line-to-output gain,Gvg comp(s), can be expressed by Gvg , Gvd , and Gc typeII asfollows:

Gvg comp (s) =Gvg (s)

1 + Gvd (s) · Gc typeII (s) . (8)

The Bode diagram of Gvg comp is shown in Fig. 8. The cor-responding gains in all frequency ranges are all below 0 dB,which means the voltage variation from the input-end is sup-pressed. The ac source in this design is 100 kHz, which is 10times lower than the switching frequency so that the switchingtype converter can smoothly convert ac power to dc power. In


Fig. 9. Control-to-output model of SIDO.

addition, the 100 kHz design makes the gain be less than –35 dBto have better voltage ripple suppression.

E. Compensation for SIDO

To make stability analysis of the SIDO converter, a gen-eral model shown in Fig. 9 is analyzed. The transfer functions,Gdaa ,Gdab , Gdba , and Gdbb , are well derived in [24] and [35].The loop gain can be derived as follows:

Tz (s) = FMa · FMb · Gca(s) · Gdba(s) · Gcb(s) · Gdab(s)(9)

T1 (s) = FMa · Gca (s) · Gdaa (s)

− Tz (s)1 + FMb · Gcb (s) · Gdbb (s) (10)

T2 (s) = FMb · Gcb (s) · Gdbb (s)

− Tz (s)1 + FMa · Gca (s) · Gdaa (s) . (11)

According to (10) and (11), the Bode diagram of these twoloops is shown in Fig. 10. T1 is the control loop for energy dis-tribution, and T2 is the control loop for the total energy income.Two type-III compensators are employed for Gca and Gcb ineach loop. Note that T1 and T2 affect each other if the com-pensator in one of the loops is adjusted. After careful tuning,the dc gain is improved to reduce the steady-state error aftercompensation, and the phase margin is enough for both loops.

IV. CIRCUIT DESIGN AND IMPLEMENTATION

The proposed circuits are designed in the laboratory and thentaped-out for testing. All the power MOS transistors and thecontroller are integrated on a single chip. The chip is manu-factured by TSMC 0.25 μm high-voltage CMOS process. Thecircuit schematic of the chip is shown in Fig. 11, and the im-plementation details of the controller circuit are given in thissection.

Fig. 10. Bode diagram of the control-to-output model for SIDO.

A. Implementation Concerns

There are several concerns on the circuit implementation.From the battery charging point of view, the fully charged volt-age of a lithium-ion battery is 4.2 V. The voltage level of thepower stage should be higher than 4.2 V, which means the dutyratio should have some additional margin to make sure that thevoltage can reach 4.2 V when additional current is drained byother loads concurrently. It should be noted that all the compo-nents, i.e., all switches and L are required to be rated for peakpower because the converter directly faces 100 kHz ac power.Therefore, the high-voltage manufacturing process is chosenfor the chip implementation. In the high-voltage process, thepower MOSFETS for ac–dc converter and their gate drivers arewell suited to tolerate high-voltage levels up to 12 V for thisparticular process. The 5 V devices are selected to constructthe MOSFETS for the SIDO. To minimize power consumption,the controller is implemented using low-voltage devices whosesupply voltage is 2.5 V.

B. Dynamic Body Biasing

The control of dynamic body biasing is prone to latch-up andsubstrate problems on the high-side switches. The circuit be-havior is shown in Fig. 12. The body cannot be connected to thesource of the P-channel metal-oxide-semiconductor (PMOS)transistor because the source in this case is connected to acpower, which changes periodically between positive and nega-tive 7 V. A similar situation occurs for the drain terminal, so thePMOS transistor in step 2 in Fig. 12 may not turn OFF properlyand the current can leak through the source and the substrateto the output. Therefore, the dynamic body biasing technique[35], [36] is also applied to MP1 and MP2, which are shown inFigs. 2 and 11. The biasing circuit is constructed by four PMOStransistors, which are MP3, MP4, MP5, and MP6 in Fig. 11.These PMOS transistors turn ON in an alternating fashion. Forexample, when the source of MP1 is at the highest positive volt-age and the source of MP2 is at the lowest negative voltage,MP4 and MP5 turn ON to provide the body voltage for the MP1


Fig. 11. Block diagram of the proposed circuit.

Fig. 12. Illustration of the latch-up and substrate leakage problems whenhigh-side PMOS is switching.

and MP2. For MP1, its body is connected to the highest positivevoltage; the body of MP2 is connected to the inductor, which hashigher voltage potential than the lowest negative voltage. Thisway, the leakage current can be eliminated by keeping the highervoltage on the body of the PMOS transistor and vice versa.

C. Control Circuit for AC–DC Converter

The block diagram of the proposed controller is shown inFig. 11. The components connected to the op-amps, Op 1 toOp 4, form a type-II compensation network. Feedback shouldbe applied to the input of the compensator (Vout in Fig. 11) to

control and stabilize the output voltage. The feedback voltage iscompared with the reference voltage, Vref , to produce the controlsignal, Vc v , for voltage control loop. By the time, a load-currentsensing circuit with a gain of 200 amplifies the voltage on nodeIsense+ and node Isense− to obtain the value of inductor current,IL . This signal is then compared with a current reference signal,Iref , in the compensation network to produce the control signal,Vc c , for current control loop. Vc v and Vc c are the compensatedsignals from the input error. Vc v is used in constant voltagemode, and Vc c is used in constant current mode.

The two aforementioned control signals, Vc v and Vc c , wouldbe selected by an analog multiplexer (MUX) to pass as Vc . Theselection is based on the measured output voltage, Vout . WhenVout reaches the upper threshold, which is set at 4.2 V in thiscase, analog MUX passes Vc v to Vc . On the other hand, analogMUX passes through Vc c to Vc when Vout reaches to the lowerthreshold, which is 3 V in this design. The voltage control signal,Vc , is then compared with a saw-tooth signal, Vramp , to deter-mine the pulse width of the PWM signal. This signal, which isthe main signal to control the power MOSFETS, passes throughthe nonoverlap controller to generate two nonoverlapping sig-nals, duty and duty_bar. Nonoverlapping design is required toavoid a short circuit between the high side PMOS transistors,MP1 and MP2.

D. Zero Current Protection (ZCP)

When the input ac voltage is close to zero, the inductor currentcan go negative because current can flow back from output side


Fig. 13. Switch control circuit and its waveform.

through inductor to ground or to common node. The output ca-pacitor would be discharged and induce the voltage drop on theoutput. To avoid this condition, the current path in Fig. 3(b) and(d) should be cut. Therefore, a zero current protection is neededto turn OFF the MOSFETS, MP1 and MP2 when inductor currentapproaches zero. To achieve this goal, the signal, duty_bar, isrestrained by the ZCP circuit. When the inductor current, IL ,is larger than 0, duty_bar passes through to the switching con-troller. On the other hand, duty_bar stays low when IL is lowerthan 0.

E. Switching Controller

A key component of the proposed circuit is the switchingcontroller, which is shown in Fig. 13. The function of this blockis to create two pulse-width modulated signals, duty1 and duty2,based on the input signal, duty, and to synchronize them withthe ac power source. These two signals control MP1 and MP2following the behavior shown in Fig. 3. The switch controllercompares three signals; (1) the input ac voltage, Vin , (2) thefeedback voltage, VF B , and (3) the pulse-width modulation sig-nal, duty. The signals, Vac P and Vac N , are two nodes of theinput ac voltage, ac Vin . When the ac voltage is positive andis higher than the feedback voltage, VFB , duty1 follows dutyand is passed to MP1. The signal duty2 is the complement ofduty1 at that moment. In this process, MP1 switches at a highfrequency to regulate the passing power. MP2 stays complementto MP1 to keep continuous current for inductor in the positiveperiod. During negative period, similar to the positive period(but in opposite polarity), the duty2 follows duty while keepingduty1 signal the complement of duty2. These two signals, duty1and duty2, are then inverted because MP1 and MP2 are p-typeMOSFETS.

F. SIDO Circuit

The SIDO circuit is shown on the right side of Fig. 11.The voltage of output port B, Vout b , is the feedback to thecompensator to generate the control signal Vcb . This signal isthen compared with a saw-tooth wave to determine the PWMsignal for controlling the total energy of two phases. Likewise,port A output voltage, Vout a , is the feedback to the compensator

Fig. 14. Die photo for the control circuit.

to generate control signal, Vca for PWM signal Da . The PWMsignals, Da and Db , are used to distribute energy to bothphases.

G. Circuit Implementation

The micro-photograph of the controller for the proposed cir-cuit is shown in Fig. 14. The chip size is 1.9 × 2.3 mm in-cluding pads. The chip area includes an ac–dc converter forthe size of 1.1 × 0.794 mm, and a SIDO for the size of the0.739 × 0.692 mm. This chip can be integrated into a 3 × 3 cmmedical module containing passive (capacitor and inductor) andnetwork components.

To differentiate controllers from the components in the powerstages, MOSFETS and controllers are labelled in accordance withthose shown in Fig. 11. The controller includes saw-tooth gener-ators, bias circuits, operational amplifiers, comparators, currentprotection, and logic elements. Those circuits are well deployedin different areas because their voltage specifications are differ-ent.

H. Experimental Results

The ac–dc converter is expected to work either with or with-out a battery. Such design can extend the operating reliabilityonce battery power is low or in need of replacement. Two testswere conducted to evaluate the performance of the designedac–dc converter. When the ac–dc converter is not connected to abattery, it works under CV mode. In CV mode, load transient ismeasured and the results are shown in Fig. 15. In the beginning,


Fig. 15. Load transient test results (Current changes from 1 to 90 mA andvice versa).

Fig. 16. Output voltage waveform of ac–dc converter and SIDO (seriallyconnected).

the 2.1 V dc output voltage is regulated from 12 Vp−p (peak-to-peak) ac-induced voltage to serve to a 90 mA load. The 100 kHzac power is generated by a Class-E Amplifier and then trans-mitted through a transformer. The reason to use a transformeris to eliminate the uncertainties from the coil in this case. Whenload current steps down from 90 to 1 mA within 1 μs, the out-put voltage shows 260 mV voltage overshoot and then recoverswithin 1.2 ms. When the load current steps up from 1 to 90 mAwithin 1 μs, the output voltage has 220 mV undershoot and thenrecovers within 1.2 ms. The test result validates the regulationcapability of the ac–dc converter in response to load changing.

In Fig. 16, the waveform shows that the 14 Vp−p ac source isconverted to a 3.6 V dc voltage. The dc voltage is then connectedto SIDO converter for further voltage regulation. The voltagesof the two output ports are 1.2 V and 1.5 V. Note that the rippleat the output of the SIDO converter is further reduced to 50 mVthat could serve as a standalone power supply without batterysupport. Another load transient is tested at the output ports ofthe SIDO converter. Testing result is shown in Fig. 17. Whenone of the output current steps up or down rapidly between 0and 30 mA, the output voltage, Vout a , shows that the voltagespikes are less than 180 mV and the transient recovers within190 μs. Although there is minor cross regulation between phaseA and phase B, the figure shows that the two outputs of theSIDO are stable.

To evaluate the battery charging operation, the output of theac–dc converter is connected to both SIDO and the battery in

Fig. 17. Load transient test for both output of SIDO converter. (a) Loadtransient on the phase A. (b) Load transient on the phase B.

Fig. 18. Internal signal when charging a battery in the simulation.

parallel for the following tests. The controller detects batteryvoltage to determine the control loop. The behavior can be ex-plained by the internal signal in the simulation result in Fig. 18.A large capacitor is used to model the battery to shorten thesimulation time. In the beginning, the circuit is started fromconstant-current mode to charge the battery. The current modecompensator is selected to generate control signal. The controlsignal is compared with saw-tooth wave, Vramp , to generatePWM signal. During the charging period, the battery voltageincreases at a constant slope until the battery voltage reachesthe upper threshold. Afterwards, charging current drops. At thatmoment, the voltage compensator is selected instead to enableconstant-voltage mode operation.


Fig. 19. Current and voltage in battery charging test with the proposed ac–dcconverter. (a) With charging current 70 mA. (b) With charging current 100 mA.

The experimental result of battery charging is shown inFig. 19. A 110 mAh lithic-ion battery is used in the experiments.When the charging current is 70 mA, it takes about 95 min tocharge the battery from 3 to 4.2 V. When the charging current is100 mA, it takes about 61 min to charge the same battery from3 to 4.2 V. The charging current is kept constant until chargingis complete. The voltage does not increase with a constant slopedue to the variation of the equivalent resistance and inductanceduring charging with a real battery. When battery charging iscomplete, the voltage becomes constant and current drops to 0.

For biomedical applications, the temperature is also a bigconcern. For the temperature measurement, the battery is sealedwith an electrical thermometer by an insulation sleeve. Throughthe charging progress, records of efficiency and temperature areshown in Fig. 20. The efficiency is around 70% under 70 mAcharging current during the charging period, and the tempera-ture of the battery only rises by 1 ◦C. For the second test, theefficiency is around 75% under 100 mA charging current duringthe charging period with the temperature rise less than 1 ◦C.The efficiency of the proposed circuit is also measured in theload current range between a light load of 6 mA, to a heavyload of 250 mA. The results show that the maximum efficiencyis 79.4% under 150 mA load current. The experiments are re-peated 10 times to average a value for each dot in Figs. 19and 20.

In Table I, circuit functionality and performance indices ofthe proposed circuit are compared with those of state-of-the-artac–dc converters. It is noted that the proposed circuit providesdual functions by the delicate control for ac–dc power conver-

Fig. 20. Efficiency and temperature in battery charging test with the proposedac–dc converter. (a) With charging current 70 mA. (b) With charging current100 mA.

sion, which includes battery charging control as well as constantvoltage control.

Regarding the power efficiency issue on battery charging path,most counterparts need a prestage rectifier to provide dc inputvoltage. The optimal efficiency of the rectifier is 89% [8], [36].In [16], the authors adopt a step-down dc–dc converter followingthe rectifier to regulate charger voltage, which needs to countanother 86% efficiency in the overall power path. Therefore, thistwo-stage topology has a combined efficiency of 76%.

Both Sole et al. [10] and Valle et al. [12] use linear regulatorsto enhance the battery charging capability, which do not in-clude the prestage power conversion circuit (rectifier + Buck).To make a proper estimation of the overall power path, 76%prestage efficiency is taken into account.

Table I shows that the performance of the proposed circuitis comparable to those state-of-arts in terms of efficiency, func-tionality, and size. Structure-wise speaking, the physical circuitproposed in this paper is simpler and smaller than that of the con-ventional cascading system. This structure is pretty appealing tothe application of mobile electronic devices because mobile de-vices usually require smaller size and lighter weight. Note thatthis circuit is combined with inductive power transfer (IPT) cir-cuit to achieve resonant condition and make the power transfer.There are some cases discussing about the impedance matchingbetween receiver and active rectifier to reach high efficiency[11]. However, the optimization of the IPT is not within thescope of this paper. This issue could be a future work for thenext phase research.


TABLE ICOMPARISON OF DIFFERENT POWER PATH EFFICIENCIES FOR BATTERY CHARGING

V. CONCLUSION

A highly integrated power processing module is proposed toprovide stable power for WPT-based wearable medical devices.The power processing circuit includes a compact but efficientac–dc converter and a SIDO converter. The single stage ac–dcconverter is demonstrated to show its robust control on reg-ulating dc output voltage. The single stage switches not onlyregulate dc output voltage, but also rectify ac power to dc powersimultaneously. It is noted that the associated control method-ology leads to elimination of the output capacitor in the rectifierstage and the high-side switch in the switching converter stage.Another feature of the single-stage ac–dc converter is that it canserve loads either with or without a battery by CC–CV dualmodes, which can be detected automatically by the output con-dition. The SIDO structure is integrated with ac–dc converter aswell to provide additional voltage levels for the loads. All theexperimental results show that the proposed power module canperform high-efficient and robust voltage regulation for medicalcircuits or battery charger in the wearable devices.

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Yen-Chia Chu received the B.S. and M.S. degrees inelectrical engineering from the Department of Elec-trical Engineering, National Cheng Kung University,Tainan, Taiwan, in 2006 and 2008, respectively, andthe dual Ph.D. degree in electrical engineering fromNational Cheng Kung University, Tainan, Taiwan,and New York University, Brooklyn, NY, USA, in2017.

His research interests include power managementintegrated circuit (IC), analog/digital IC, wirelesspower transfer, power electronics, control, and med-

ical circuit design.

Le-Ren Chang-Chien (SM’12) received the B.S. de-gree in engineering science from National ChengKung University, Tainan, Taiwan, in 1993, theM.S.E.E. degree in electrical engineering from theUniversity of Wisconsin–Madison, Madison, WI,USA, in 1998, and the Ph.D. degree in electrical engi-neering from Purdue University, West Lafayette, IN,USA, in 2002.

He joined the Department of ElectricalEngineering, National Cheng Kung University,as an Assistant Professor in 2003 and became a Full

Professor in 2013. His research interests include power management systems,power electronics, electric machines, and renewable energy applications topower system.

N. Sertac Artan received the Ph.D. degree in electri-cal engineering from New York University (formerlyPolytechnic University), Brooklyn, NY, USA.

He is an Assistant Professor of electrical and com-puter engineering with the School of Engineering andComputing Sciences, New York Institute of Technol-ogy (NYIT), New York, NY. Before joining NYIT, Hewas working as a Faculty Member at the School ofEngineering, New York University. He also workedas an Application Specific Integrated Circuit DesignEngineer and designed integrated circuits for com-

mercial, academic, and military applications.Dr. Artan served on the organizing committees of the Association for Com-

puting Machinery/IEEE Symposium on Architectures for Networking and Com-munications Systems, the IEEE Sarnoff Symposium, and the ACM Conferenceon Security and Privacy in Wireless and Mobile Networks.

Dariusz Czarkowski (M’97) received the M.S. de-gree in electronics from the AGH University of Sci-ence and Technology, Krakow, Poland, the M.S. de-gree in electrical engineering from Wright State Uni-versity, Dayton, OH, USA, 1989 and 1993, respec-tively, and the Ph.D. degree in electrical engineeringfrom the University of Florida, Gainesville, FL, USA,in 1996.

In 1996, he joined the New York University Poly-technic School of Engineering, Brooklyn, NY, USA,where he is currently an Associate Professor of elec-

trical and computer engineering. He is a co-author of the book Resonant PowerConverters (Wiley-IEEE, 2011). His current research interests include powerelectronics and power distribution systems.

Dr. Czarkowski is an Associate Editor of the International Journal of Powerand Energy Systems.

Chih-Hsiang Chang was born in Changhua, Taiwan,in 1988. He received the M.S. degree in electricalengineering from National Cheng Kung University,Tainan, Taiwan, in 2014.

His current work in “Realizing IDEAS Together”interests control and analysis of switching dc–dc con-verters in switching power supplies, especially forgraphics processing unit power applications.


Jialin Zou received the M.S. degree in computer en-gineering from New York University (formerly Poly-technic University), Brooklyn, NY, USA, in 2014.

He is a Data Analyst with Media Storm LLC, NewYork, NY. He is actively working on data mining, ma-chine learning, and software development.

H. Jonathan Chao received the B.S. and M.S. de-grees from National Chiao Tung University, Hsinchu,Taiwan, in 1977 and 1980, respectively, and the Ph.D.degree from Ohio State University, Columbus, OH,USA, in 1985, all in electrical engineering.

In 1992, he joined New York University,Brooklyn, NY, USA, where he is currently a Professorof electrical and computer engineering (ECE), wherehe was the Head of ECE Department from 2004 to2014 and is currently a Director of the High-SpeedNetworking Laboratory. He was doing research in the

areas of software defined networking, network function virtualization, datacen-ter networks, high-speed packet processing/switching/routing, network security,quality of service control, and network on chip. He holds 59 patents and hasauthored or co-authored more than 240 journal and conference papers. Dur-ing 2000–2001, he was a Co-Founder and Chief Technology Officer of CoreeNetworks, NJ, USA. From 1985 to 1992, he was a Member of Technical Staffat Bellcore. He authored three networking books, including High-PerformanceSwitches and Routers (Wiley, 2007).

Dr. Chao is a fellow of the National Academy of Inventors (NAI). He is aco-recipient of the 2001 Best Paper Award from the IEEE TRANSACTIONS ONCIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY.

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