October 21, 2015 Archive - Session 2 · 2015-11-13 · BiTS Shanghai 2015. East Meets West Session...
Transcript of October 21, 2015 Archive - Session 2 · 2015-11-13 · BiTS Shanghai 2015. East Meets West Session...
BiTS Shanghai 2015
October 21, 2015Burn-in & Test Strategies Workshop www.bitsworkshop.org
Proceedings
Archive - Session 2October 21, 2015
© 2015 BiTS Workshop – Image: Zhu Difeng/Dollar Photo Club
BiTS Shanghai 2015
October 21, 2015Burn-in & Test Strategies Workshop www.bitsworkshop.org
Proceedings
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BiTS Shanghai 2015
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Proceedings
Presentation / Copyright NoticeThe presentations in this publication comprise the pre-workshop Proceedings of the BiTS Workshop Shanghai. They reflect the authors’ opinions and are reproduced here as they are planned to be presented at the BiTS Workshop Shanghai. Updates from this version of the papers may occur in the version that is actually presented at the BiTSWorkshop Shanghai. The inclusion of the papers in this publication does not constitute an endorsement by the BiTS Workshop or the sponsors.There is NO copyright protection claimed by this publication. However, each presentation is the work of the authors and their respective companies: as such, it is strongly encouraged that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies.The BiTS logo and ‘Burn-in & Test Strategies Workshop’ are trademarks of BiTS Workshop Shanghai.
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BiTS Shanghai 2015
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Proceedings
Session
Session Chair
BiTS Shanghai
East Meets West
"WLP Probing Technology Opportunity and Challenge"
Clark Liu - PowerTech Technology Inc.
"Pushing the Envelope in DFM (Design for Manufacturing) for 0.2mm Pitch WLCSP Socket"
Colin Koh - Test Tooling Solutions Group
"Signal Integrity & Inpacts by Connector Structures"
Jiachun (Frank) Zhou - Smiths Connectors
"LPDDR4 Signal & Power Performance Optimization By Hardware"
Yuanjun Shi - TwinSolution Technology
2Frank Zhou
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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LPDDR4 Signal & Power
Performance Optimization
By Hardware
Yuanjun Shi / Twinsolution R&D
Xiao Yao / Hisilicon Test Solution R&D
2015 BiTS Workshop
Shanghai
October 21, 2015
Conference Ready
mm/dd/2014
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Contents
• DDR4 JEDEC Standard
• LPDDR4 PCB Channel & Socket SI
Simulation
• LPDDR4 PCB and Socket Power Integrity
Simulation
• Summary
LPDDR4 Signal & Power Performance Optimization By Hardware 2
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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DDR4 JEDEC Standard
3LPDDR4 Signal & Power Performance Optimization By Hardware
JEDEC Standard No. 209-4
2XX-ball 15mm x 15mm
0.4mm pitch, Quad-Channel
POP FBGA (top view)
Partial Enlarge Map of DDR
Symbol Type Description
CK_t_A,CK_c_A,CK_t_B,CK_c_B
Input Clock
CA[5:0]_ACA[5:0]_B
InputCommand/Address Inputs
DQ[15:0]_A,DQ[15:0]_B
I/OData Input/Output: Bi-direction data bus.
DQS[1:0]_t_A,DQS[1:0]_c_A,DQS[1:0]_t_B,DQS[1:0]_c_B
I/O Data Strobe
VDDQ,VDD1,VDD2
Supply Power Supplies
VSS, VSSQ GND GND
This case only study one group signal pin across all four group signal pins, and only include DQ pin.
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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4LPDDR4 Signal & Power Performance Optimization By Hardware
Clock Jitter Specification
DDR4 JEDEC Standard
Eye Diagram Specification
Eye diagrams are a very successful way of quickly and intuitively assessing the quality of a digital signal, for example Overlaying of bit and noise level. So Eye diagrams is a very important tools to analysis signal integrity of high speed interconnectors. On other hand we also can utilize the Eye diagram to minimize the delaying of bit as well as the transmission performance of system.
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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• PCB routing optimization
• Single Bit Performance
• S-Parameter Comparison Across Different Socket
Structure
• Eyediagm analysis across different socket
structure
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LPDDR4 PCB Channel & Socket SI
Simulation
LPDDR4 Signal & Power Performance Optimization By Hardware
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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6LPDDR4 Signal & Power Performance Optimization By Hardware
PCB Routing Optimization
A B
C
1W (1 Time/1倍线宽) 3W (3 Times/3倍线宽)
CPW ( Coplanar
waveguide/共面波导)
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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7LPDDR4 Signal & Power Performance Optimization By Hardware
Cross Talk Simulation Circuitry
Pulse Drive Signal
Measurement
Active Line
Quite Line
Near End Far End
Drive a pulse from active line, and using the voltage measurement probe to check the far end cross talk, and compare with different design.
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-100
-80
-60
-40
-20
0
20
40
60
80
100
0 10 20 30 40 50 60 70 80 90 100 110 120
V(v1) [mV] V(v1) [mV] V(v1) [mV]
8LPDDR4 Signal & Power Performance Optimization By Hardware
PCB Cross Talk
Design A
Design B
Design C
Design C:共面波导的结构有屏蔽,可以屏蔽串扰信号。
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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9LPDDR4 Signal & Power Performance Optimization By Hardware
Single Bit Simulation Circuitry
Pulse DriveMeasurement
0
0.2
0.4
0.6
0.8
1
1.2
0 100 200 300 400 500 600 700 800 900 1000
mag(V(1w)) [V] V(3w) [V] V(cpw) [V]
Design A
Design B
Design C
Design C has higher voltage level and less reflection from the termination.
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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10LPDDR4 Signal & Power Performance Optimization By Hardware
Socket Structure
Short Pin Long Pin Hybrid
SocketCoaxial Shielding
Signal PowerInsulation Material
Insulation Material
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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-1.2
-1
-0.8
-0.6
-0.4
-0.2
00 1 2 3 4 5 6
Short Pin Long Pin Hybrid Coaxial Shielding
11LPDDR4 Signal & Power Performance Optimization By Hardware
Socket S-Parameters
Insertion Loss
GHz
dB
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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-70
-60
-50
-40
-30
-20
-10
00 1 2 3 4 5 6
Short Pin Long Pin Hybrid Coaxial Shielding
12LPDDR4 Signal & Power Performance Optimization By Hardware
Socket S-Parameters
Return Loss
GHz
dB
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
00 1 2 2 3 4 5 5
Short Pin Long Pin Hybrid Coaxial Shielding
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Socket S-Parameters
Cross Talk
GHz
dB
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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14LPDDR4 Signal & Power Performance Optimization By Hardware
Eye Diagram Loop
Pattern
Generator
Pre-emphasis / Driver
Encoder
Board
Package
Package
Channel Adaptation
Socket
DDR Controller
DDR
Eye-Probe
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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15LPDDR4 Signal & Power Performance Optimization By Hardware
Eye diagram Compare
Short Pin
RxMask
Long Pin
RxMask
Hybrid Pin
RxMask
Coaxial
RxMask
Shield
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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16LPDDR4 Signal & Power Performance Optimization By Hardware
Eye diagram Summary
Structure Jitter VdiVW mVShort Pin 0.038 247Long Pin 0.112 7.5Hybrid 0.069 129Coaxial 0.031 298
Shielding 0.117 7.9
Jitter Spec: 0.04
TdivW: 79ps
VdiVW: 140mV
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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17LPDDR4 Signal & Power Performance Optimization By Hardware
High volume manufacturing
sensitivity analysis
Channel Parameters Variation Tx driver impedance (ohm) 34 +/- 10% On-die-termination (ohm) 60 +/- 20%
DRAM Ci (pF) 2 +/- 10% PCB trace impedance (ohm) 55 +/- 15%
Socket Impedance(ohm) 50+/-5%
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18LPDDR4 Signal & Power Performance Optimization By Hardware
High volume manufacturing sensitivity
analysis Taguchi DOE/田中实验
Socket Impedance +/-5% Socket Impedance +/-8%
Socket Impedance +/-12%
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19LPDDR4 Signal & Power Performance Optimization By Hardware
Simulation Vs Measurement Correlation
To ProberTo Prober
Socket Build Base on Pin Map
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-1000
-500
0
500
1000
1500
2000
-200
0
200
400
600
800
1000
1200
1400
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Simulation Vs Measurement Correlation
SimulationMeasurement
Simulation
Measurement
Pulse Configuration A
Pulse Configuration B
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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• PI Basic
• PCB Impedance
• Socket Power Impedance Vs System Impedance
• Impedance Optimization
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LPDDR4 PI Simulations
LPDDR4 Signal & Power Performance Optimization By Hardware
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22LPDDR4 Signal & Power Performance Optimization By Hardware
Power Integrity
GND
PWR
4. TUNABLE MATERIALSFOR RECONFIGURABILITY AND EMI REDUCTION
5. EMBEDDED DIE
1. RECONFIGURABLE MIMO ANTENNAS
3. THIN FILM
PASSIVE
COMPONENTS
R,L,C, TLINES
2. LOW LOSS
SWITCHES
FOR
RECONFIGURABILITY
Signal Line
Memory
Die
RFDie
3D
DigitalProcessor Flip Chip
6. EBG
2.4GHz
5.2GHz
WiMax
FEM
4x4 Tx/Rx5GHz
10GB
Logic+Memory+RF
Maintaining
Signal and Power
Integrity is a
Major bottleneck
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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23LPDDR4 Signal & Power Performance Optimization By Hardware
Jitter caused by SSN for I/O
Uncertainty in Delay due to SSN causing Jitter
Varying Voltage
Droop
on Power
Supply due
to SSN
time
Output driver waveform
Vdd
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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0
20
40
60
80
100
120
1M 20M 39M 58M 77M 96M 115M 134M 153M 172M 191M
mag(Z(Port1,Port1)) [mOhm]
PCB Power Impedance
24LPDDR4 Signal & Power Performance Optimization By Hardware
51.3mohm @ 100MHz
mohm
Target Impedance : 100mohm@100MHz
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0.1
1
10
100
1000
0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90
mag(Z(Port1,Port1)) [mOhm] mag(Z(Port2,Port2)) [ohm]
Socket Power Impedance
25LPDDR4 Signal & Power Performance Optimization By Hardware
Design A
Design B
GHz
mohm
Target Impedance : 100mohm@100MHz
Long pin and short pin has significant difference in terms of power
impedance if only measure socket only.
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0
1
2
3
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
mag(Z(Port1,Port1)) [ohm]
PCB + Socket + Package Impedance
26LPDDR4 Signal & Power Performance Optimization By Hardware
131mohm @ 100MHz
ohm
GHz
Target Impedance : 100mohm@100MHz
0
200
400
600
800
0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90
mag(Z(Port1,Port1)) [mOhm]
81mohm @ 100MHz
Before After optimized
1. Increase the power pane width, and short the distribution length.
2. Optimize the pin length and diameter.
3. Although socket is not the main factor for the power impedance,
however an optimized socket design and contactor selection
also help the power impedance certain.
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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IR Drop
27LPDDR4 Signal & Power Performance Optimization By Hardware
0
20
40
60
0 7 17 27 37 47 57 67 77 87 97
mag(V(V1)-V(V2)) [mV]
nS
mV
Target Drop : <50mV
PCB IR Drop
0
50
100
150
0 8 19 30 41 52 63 74 85 96
Design A Design B
Socket IR Drop
uV
nS
42.1
42.3
42.5
42.7
42.9
0 7 17 27 37 47 57 67 77 87 97
mag(V(V1)-V(V2)) [mV]
PCB + Socket IR Drop
nS
mV
45
45.2
45.4
45.6
45.8
46
46.2
0 7 17 27 37 47 57 67 77 87 97
mag(V(V1)-V(V2)) [mV]
PCB + Socket +
Package IR Drop
nS
mV
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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Power Transient
28LPDDR4 Signal & Power Performance Optimization By Hardware
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.22
1.240 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 108
208
mag(V(V1)) [V] mag(V(V1)) [V]
172B Short Pin
V
ns
Target Drop : <50mV
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
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0
0.5
1
1.5
2
0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
mag(Z(Port1,Port1)) [ohm]
Power Impedance Vs Shmoo
Measurement
29LPDDR4 Signal & Power Performance Optimization By Hardware
1. SHMOO shows the controller fail
curve is quite close to the power
impedance simulation data.
2. The resonance frequency for
simulation and measurement is also
close.
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
October 21, 2015Burn-in & Test Strategies Workshop www.bitsworkshop.org
30LPDDR4 Signal & Power Performance Optimization By Hardware
Future Work
East Meets WestBiTS Shanghai 2015Session 2 Presentation 4
October 21, 2015Burn-in & Test Strategies Workshop www.bitsworkshop.org
Summary
• Discussion one method to study whether the
hardware can meet the LPDDR4 specification.
• Discussion one method to identify the main factor
for the whole SI chain.
• Optimize the socket and pin layout to meet the
power impedance performance.
• Utilize Shmoo to correlate the power impedance
data.
31LPDDR4 Signal & Power Performance Optimization By Hardware