NUC972 Development Board User Manual rev A1 -...

NUC972 DEVELOPMENT BOARD

USER’S MANUAL

The above information is the exclusive intellectual property of NuvoTon Electronics Corp. and shall not be disclosed, distributed, or reproduced without permission from NuvoTon. - 1 - Revision: A1.0

2014/9/15

NUC972 Development Board

User’s Manual

Rev. A1.0


USER’S MANUAL


2014/9/15

TABLE OF CONTENTS 1 General Description ........................................................................... 4

2 Peripheral Device ............................................................................... 4

2.1 Partitioned Block – .................................................................................................... 5

3 Board Description .............................................................................. 5

3.1 Power Block − ........................................................................................................... 5

3.2 JTAG ICE port − ........................................................................................................ 7

3.3 Peripheral Device 2 – ................................................................................................ 7

3.4 Peripheral Device 1 − ................................................................................................ 8

3.5 Peripheral Device 3 – ................................................................................................ 9

3.6 Peripheral Device 4 − ................................................................................................ 9

3.7 Peripheral Device Port 5 − ......................................................................................... 9

4 Pin Function assignment ................................................................... 11

5 Document Revision History ............................................................. 18

6 Schematics ........................................................................................ 19


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2014/9/15

List of Figures

Figure 6-1Block Diagram ................................................................................................ 19

Figure 6-2 System Power ................................................................................................ 20

Figure 6-3 DC/DC ........................................................................................................... 21

Figure 6-4 NUC972 ......................................................................................................... 22

Figure 6-5 Configure, ICE Reset ..................................................................................... 23

Figure 6-6 P_Filter .......................................................................................................... 24

Figure 6-7 GPIO .............................................................................................................. 25

Figure 6-8 EBI, Keys, AV ............................................................................................... 26

Figure 6-9 RMII .............................................................................................................. 27

Figure 6-10 RMII ............................................................................................................ 28

Figure 6-11 IIS ................................................................................................................ 29

Figure 6-12 CAN Bus, SIM card and eMMC ................................................................. 30

Figure 6-13 UART .......................................................................................................... 31

Figure 6-14 USB ............................................................................................................. 32


USER’S MANUAL


2014/9/15

1 General Description

The user’s guide describes the operation and use of the NHS-972DF62Y development

board, NHS-972-1-YA-1M51. The board places NUC972DF62Y’s almost of the functions,

which includes the peripheral interfaces as memory (NAND flash, SPI flash, SD x 2),

UART x5, IIS, 2 x 3 Key matrix, 24-bit LCD interface, Ethernet, USB host/device, CMOS

sensor, SIM card, and reserve EBI port.

In order to easier-check for user, the description is based on the functional block with

the sheet of schematic. User can check out what the function port is they would like to

design on their system. The schematic is attached for the system reference design.

On the NUC972DF6Y development board, almost of the GPIO pin headers are traced

to peripheral device via the dip switches. In which the system designer can easier to verify

their module circuit by wire out from the pin header if the corresponding peripheral

devices are turned off.

Meanwhile, the board reserves a JTAG ICE port for program development and a

UART 0 for debugging message. In which is convenient for the designer to develop their

system.

2 Peripheral Device

Block out the development board as several of the area with the difference line color

and style. According to the block function, user is easier to search out which one of the

function they want to use, and clear the corresponding GPIO has to be setting correctly; the

board outline is attached as below:

Boarder color and line-style Functional Block

Power Block.

JTAG ICE port.

Peripheral Device 2.





USER’S MANUAL


2014/9/15

CPU.



2.1 Partitioned Block –

3 Board Description

3.1 Power Block −−−−

GPIO: SysWkUp, SysPWREn

CON2 is 5VDC power adaptor input jack terminal which provides the system power

for the DC/DC converters, 3.3V is for system I/O and peripheral devices, 1.2V is for


USER’S MANUAL


2014/9/15

CPU’s core power, 1.8V is for CPU’s internal RAM.

Plug the 5Vdc adaptor into the CON2, in which will supply RTC power and system

power DC/DC convertors input. Toggle the RTC key; system power control key, the

RTCWkUp will go low, and then the RTCPWREn output Hi to enable DC/DC convertor

U3 (3.3V for IO power), U8 (1.2V for core power), U4 (1.8V for DDR power). Mine while,

the power LED2 (3.3V), LED8 (1.2V) and LED3 (1.8V) are light, too.

To prevent the input power is over the development board specification, the system

board adds a power protection device U2 (APL3203A). The system power will be

terminated and LED1 lighting when the input voltage is over 5.85V (APL3203A) or the

current is over 1A.

For the over current protection defines formula is as below:

,

CON2, 5V power adaptor input terminal, polarity as below:

1: Center hole is positive for 5V+

2: External ring is negative for ground.

SW2 RTC key for system power control on/off.

SW4 Reset key.

BAT1 Battery socket is for CR2032.


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2014/9/15

3.2 JTAG ICE port −−−−

CON1 is a connector for JATG ICE port which function has to turn on SW6.

ICE port PJ[0:4] SW6 CON1

Note: SW6 on: PJ[0:4] is to ICE port

3.3 Peripheral Device 2 –

Memory block includes eMMC socket, SD socket, NAND flash and SPI flash.

Each one of the device has to be turned on by the corresponding switch which all of

the GPIO and DIP switched are listed as below:

eMMC PC[0:5] SW11 CON3

SD PD[0:7] SW14 CON4

NAND Flash PC[0:14] SW3, SW7,

SW13

U9

SPI Flash PB[6:11] SW8 U6/U7

Note:

1. The PC[0:5] of eMMC conflicts with NAND flash.

2. Only one (U6 or U7) SPI flash can be used.


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2014/9/15

3.4 Peripheral Device 1 −−−−

This partitioned block includes IIS, Ethernet, USB device, USB host, and SIM card

socket.

Add one CODEC chip (NUC8822L) to IIS port which is easier to verify.

For Ethernet port, the NUC972 support RMII interface which add one Ethernet phy to

RJ45.

Either is USB device or host, there is power protection chip is placed on the USB

power bus. The corresponding DIP switches have to be turned on for the power control. If

the USB power control chip isn’t control by GPIO, the system is reserved a switch for

manual control. The OC pin will active low when the USB power is fault, the fault LED

will be turned to red from green.

IIS PG[0:1], PG[10:14],

PE12

SW15 U10

USB

device

USB0_DP/DM/ID, PE14,

PH1

SW30.1 U16,

CON24

USB

host

USB1_DP/DM, PE15,

PH1

SW30.4 U17,

CON20

Ethernet PF[0:9] SW38,

SW21

U14,

CON18

SIM

card

PG[10:14] SW37 CON31

Note: SW34 is USB power chip enable by hardware force and fault LED

setting.


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2014/9/15

3.5 Peripheral Device 3 –

Is only reserved two CAN bus ports with pin headers on the board.

CAN bus 0 CON10[1:2] PH[2:3] SW17[1:2]

CAN bus 1 CON10[3:4] PH[4:5] SW17[3:4]

3.6 Peripheral Device 4 −−−−

This block are is mainly for external bus which includes the 24-bit LCD panel,

resister-type touch panel ADC, CMOS sensor , external bus interface (EBI) port and a 3 by

2 matrix keypads. PWM is only reserved with pin header. The LCD backlight could be

controlled by the PWM if one of the PWM switch is switched on.

Key pads PH[4:6], PH[9:10] SW26 K[1:6]

PWM PB[2:3], PH[2:3] SW18 CON23.27

LCD PG[2:9], PD[8:15], PA[0:15] SW20, 23, 29, 25 CON23

Touch ADC ADC[3:7] SW36 CON23

CMOS

sensor

PI[0:15], PB[0:1] SW24, 22 CON16

EBI PD[15:8], PH[4:15], PI[0:15], SW37 CON31

3.7 Peripheral Device Port 5 −−−−

CPU will recognize the state as the port setting in power on initial. The system

designer has to know which one of the state want to use by oneself. Causing there is a

scanning time; these pins are in input mode. If possible, the system designer should

prevent to use these pins as input mode in this period. All of the configuration setting is

listed as below.


USER’S MANUAL


2014/9/15

Configure Bit Configured Function SW

Cfg[1:0] = 00 : Boot from USB.

01 : Boor from eMMC.

10 : Boot from NANA Flash.

11 : Boot from SPI Flash.

SW31.2, SW31.1

Cfg2 = 0 : System clock is from 12 MHz crystal.

1 : System clock is from UPLL output.

SW31.3

Cfg3 = 0 : WDT is OFF after power-on.

1 : WDT is ON after power-on.

SW31.4

Cfg4 = 0 : Pin PJ[4:0] used as GPIO pin.

1 : Pin PJ[4:0] used as JTAG interface.

SW31.5

Cfg5 = 0 : UART 0 debug message output ON.

1 : UART 0 debug message output OFF

SW35.1

Cfg[7:6] = 00 : NAND Flash page size is 2KB.

01 : NAND Flash page size is 4KB.


11 : Ignore Power-On Setting.

SW35.3, SW35.2

Cfg[9:8] = 00 : NAND Flash ECC type is BCH T12.

01 : NAND Flash ECC type is BCH T15.



SW35.5, SW35.4

Note: The configured pin should be pulled low with a 10KΩ.


USER’S MANUAL


2014/9/15

4 Pin Function assignment

Pin No. NUC972 1st Function 2

nd Function 3

rd Function

1 PG.3 LCD BL En

2 PG.2 LCD En

3 PG.1 IIC0SDA

4 PG.0 IIC0SCK

5 PG.14 IIS LRCk SMC0 CD

6 PG.13 IIS BClk SMC0 PWR

7 PG.12 IIS Di SMC0 DAT

8 PG.11 IIS Do SMC0 CLK

9 PG.10 IIS MClk SMC0 RST

10 VDD33

11 VSS

12 VDD12

13 MVSS

14 MVDD

15 MVSS

16 MVDD

17 MVSS

18 MVDD

19 MVSS

20 VDD33

21 VDD12

22 PF.14 UR2CTS

23 PF.13 UR2RTS

24 PF.12 UR2Rx

25 PF.11 UR2Tx

26 PG.9 LCD DEN

27 PG.8 LCD Vsync

28 PG.7 LCD Hsync

29 PG.6 LCD Clk

30 PD.15 LCD D23 EBI nWait


USER’S MANUAL


2014/9/15

31 PD.14 LCD D22 EBI nOE

32 PD.13 LCD D21 EBI nWE

33 PD.12 LCD D20 EBI nCS4





38 PA.15 LCD D15

39 PA.14 LCD D14

40 PA.13 LCD D13

41 PA.12 LCD D12

42 PA.11 LCD D11

43 PA.10 LCD D10

44 VDD33

45 PA.9 LCD D9

46 PA.8 LCD D8

47 PA.7 LCD D7

48 PA.6 LCD D6

49 PA.5 LCD D5

50 PA.4 LCD D4

51 PA.3 LCD D3

52 PA.2 LCD D2

53 PA.1 LCD D1

54 PA.0 LCD D0

55 ADC0

56 ADC6

57 ADC4

58 AVSS

59 AVDD

60 ADC7

61 ADC5

62 ADC1

63 ADC3


USER’S MANUAL


2014/9/15

64 ADC2

65 VREF

66 RTC_VDD

67 SYS_PWREn

68 SYS_nWkUp

69 X32_IN

70 X32_OUT

71 PH.4 Key Row0 EBI Add0



74 PH.7 EBI Add3

75 PH.8 Key Col0 EBI Add4

76 PH.9 Key Col1 EBI Add5

77 PH.10 EBI Add6

78 PH.11 EBI Add7

79 PH.12 EBI Add8

80 VDD33

81 VSS

82 VDD12

83 PH.13 EBI Add9

84 PH.14 CAN1Rx EBI nBE0

85 PH.15 CAN1Tx EBI nBE1

86 PI.0 VCAP PwDn EBI D0

87 PI.1 EBI D1

88 PI.2 EBI D2

89 PI.3 VCAP SCLKo EBI D3

90 PI.4 VCAP SPCLK EBI D4

91 PI.5 VCAP SHsync EBI D5

92 PI.6 VCAP SVsync EBI D6

93 PI.7 VCAP SField EBI D7

94 PI.8 VCAP SD0 EBI D8




USER’S MANUAL


2014/9/15






102 VDD12

103 VSS

104 VDD33

105 PB.0 IIC1SCK

106 PB.1 IIC1SDA

107 PB.2 UR6Tx PWM0

108 PB.3 UR6Rx PWM1

109 PB.4 UR6RTS

110 PB.5 UR6CTS

111 PB.6 SPI0 CS0

112 PB.7 SPI0 CLK

113 PB.8 SPI0 DoD0

114 PB.9 SPI0 DiD1

115 PB.10 SPI0 D2

116 PB.11 SPI0 D3

117 PB.12 UR10Tx

118 PB.13 UR10Rx

119 PB.14 UR10RTS

120 PB.15 UR10CTS

121 PG.4

122 PG.5

123 PC.0 ND0 eMMC D0




127 PC.4 ND4 eMMC CMD

128 PC.5 ND5 eMMC CLK

129 PC.6 ND6


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2014/9/15

130 PC.7 ND7

131 PC.8 NCS0

132 PC.9 NALE

133 PC.10 NCLE

134 PC.11 NWE

135 PC.12 NRE

136 PC.13 NRDY0

137 PC.14 NWP

138 PJ.3 TDO

139 PJ.0 TCK

140 PJ.1 TMS

141 PJ.2 TDI

142 PJ.4 nTRST

143 nRESET

144 VDD33

145 VSS

146 VDD12

147 MVSS

148 MVDD

149 MVSS

150 MVDD

151 MVSS

152 MVDD

153 VSS

154 VDD33

155 PD.0 SD0 CMD

156 PD.1 SD0 CLK

157 PD.2 SD0 D0

158 PD.3 SD0 D1

159 PD.4 SD0 D2

160 PD.5 SD0 D3

161 PD.6 SD0 CD

162 PD.7 SD0 PWR


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2014/9/15

163 VDD12

164 PLL_VDD12

165 PLL_VSS

166 VDD12

167 PH.3 CAN0Tx PWM3

168 PH.2 CAN0Rx PWM2

169 PE.13

170 PE.12 I2S CS

171 PE.11

172 PE.10

173 PE.9

174 PE.8

175 PE.7

176 PE.6

177 PE.5 UR1CTS

178 PE.4 UR1RTS

179 PE.3 UR1Rx

180 PE.2 UR1Tx

181 PE.1 UR0Rx

182 PE.0 UR0Tx

183 VDD33

184 MainXi

185 MainXo

186 VSS

187 PF.9 RMII0 RxErr

188 PF.8 RMII0 CRSDV

189 PF.7 RMII0 RxD1

190 PF.6 RMII0 RxD0

191 PF.5 RMII0 RefCLK

192 PF.4 RMII0 TxEn

193 PF.3 RMII0 TxD1

194 PF.2 RMII0 TxD0

195 PF.1 RMII0 MDio


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2014/9/15

196 PF.0 RMII0 MDC

197 PH.1 USB0 OC

198 PH.0 USB0 VbusDet

199 PF.10 USB0 PWREn

200 PE.15 USB1 PWREn

201 PE.14 USB0 PWREn

202 VSS

203 VDD12

204 USBPll1

VDD 1.2Vusb

205 USB1 VSS

206 USB1 DM Host DM

207 USB1 DP Host DP

208 USB1 VDD 3.3Vusb

209 USB1 REXT 12.1K

210 USBPll0

VDD 1.2Vusb

211 USB0 VSS

212 USB0 DM OTG DM

213 USB0 DP OTG DP

214 USB0 VDD

215 USB0 REXT 12.1K

216 USB0 ID OTG ID


USER’S MANUAL


2014/9/15

5 Document Revision History

Important Notice

NuvoTon products are not designed, intended, authorized or warranted for use as components in systems or

equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship

instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for

other applications intended to support or sustain life. Furthermore, NuvoTon products are not intended for

applications wherein failure of NuvoTon products could result or lead to a situation wherein personal injury,

death or severe property or environmental damage could occur.

NuvoTon customers using or selling these products for use in such applications do so at their own risk and

agree to fully indemnify NuvoTon for any damages resulting from such improper use or sales.

Date Revision Remarks

09/10/2014 A1.0 Release version A1.0.

The above information is the exclusive intellectual property of NuvoTon Electronics Corp. and shall not be disclosed, distributed, or reproduced without permission from NuvoTon. - 19 -

Revision: A1.0 2014/9/15

6 Schematics

PJ[0:4]

PD[8:15]

Sy sPwrEn

PA[0:15]

nRst

X1[0:1]X2[0:1]

X2[0:1]X1[0:1]

PJ[0:4]

PH[0:15]PI[0:15]

GPIO

Schem atic06

PC[0:14]PD[0:15]PE[0:15]PF[0:14]

PH[0:15]

PA[0:15]PB[0:15]PG[0:14]

PI[0:15]

PJ[0:4]ADC[0:7]

DC/DC

Schem atic02

Sy sPwrEnRTCWkUp

Sy sPwrEn

Sy sWkUp

Sy sWkUp

PF[0:9]

PA[0:15]

PI[0:15]PH[2:15]ADC[3:7]

PE[14:15]

PG[0:1]

PE[2:5]

PE[0:1]

PB[6:11]

nRstPF10

M em ory

Schem atic08

PB[6:11] PC[0:14]PD[0:7]

PB[0:15]

PC[0:14]

ADC[0:7]

PA[0:15]

PE[0:15]PD[0:15]

PH[2:3]PC[0:5]

PH[14:15]

PG[10:14]

PG[10:14]

PG[0:14]PJ[0:4]

PC[0:14]

PA[0:9]

PF[0:14]

PB[0:15] PB[12:15]PB[2:5]PF[11:14]

PH[0:1]

UDH[0:1]UDO[0:2]

PD[0:7]

PD[8:15]PG[6:9]PG[2:3]

PB[0:3]

Size Document Number Rev

Date: Sheet of

Custom

1 14Monday, September 01, 2014

1.0System Block

NHS-972-1-YS-1M51

SysPower

Schem atic01

X1[0:1]X2[0:1]

NUC972

SCHEM AT IC03

PD[0:7]PH[0:3]

PE[0:15]

X1[0:1]

PB[0:15]PC[0:14]PH[8:13]PH[4:7]

UDH[0:1]

PH[14:15]

UDO[0:2]

X2[0:1]

PF[0:14]PI[0:2]PI[3:15]

PJ[0:4]

nRst

PG[0:14]

PD[8:15]PA[0:15]

Sy sWkUpSy sPwrEn

ADC[0:7]

Configure , ICE, Reset

Schem atic04

PJ[0:4] nRstPA[0:9] PF10

P_Fi l ter

Schem atic05

EBIKeyAV

Schem atic07

PA[0:15]PD[8:15]PG[6:9]PG[2:3]ADC[3:7]PH[2:15]PI[0:15]PB[0:3]

RM II

Schem atic09

PF[0:9]nRst

IIS

Schem atic10

PG[0:1]PG[10:14]PE12

CAN Bus, SIM and eM M C Card

Schem atic11

PG[10:14]PH[14:15]

PH[2:3]PC[0:5]

UART

Schem atic12

PE[0:1]PF[11:14]

PB[2:5]PB[12:15]

PE[2:5]

USB

Schem atic13

PE[14:15]

UDO[0:2]UDH[0:1]

PH[0:1]

nRst

PE12

PH[0:3]

PC[0:14]PH[8:13]PH[4:7]

PH[14:15]

UDH[0:1]UDO[0:2]

PF[0:14]

PI[3:15]PI[0:2]

PG[0:14]

ADC[0:7]

PD[0:7]

PE[0:15]

Figure 6-1Block Diagram


Revision: A1.0 2014/9/15

X20

R82N.C.

X3T XC-9H T 9 SM D 32.768KHz 30ppm

C3415pF

C3515pF

VS

X21

VS

VS VS

VS

VS VS

VS VS

VS

RTC Crystal

Power Protection.

Q22N3904

LED41V2

R81K

VD33

R17 24K

VS

VD12

VD33

Q12N3904

R14 51K

VD18

VS

R131K

LED31V8

LED23V3

VS

R71K

VD33

CT 1810uF

VS

CT 1210uF

VS

System Main Crystal

J3

5Vin

1 2

J2

Vin

1 2

VSVSVS

VS

5Vin

CB10.1uF

R81 1M

C3315pF

C3215pF

X11

U1APL3203A

Vin1

GND2

N.C.3

#Fault4

#En5Bat6Ilimit7Vout8

C11u

X2

12M HzTXC7m-3.2x2.5mm

XIN1

GND2

GND4

XOUT3

CT 210uF

R1 24K

VSX[10:11]X2[0:1]

R801608-221T

R310K

5Vin

LED1P_Faul t

R5 2.7K

R79330

Vin

CT 110uF

R6100K

R2 N.C.

5Vin

CON2DC-PLUG

3

1

2

X10


Date: Sheet of

Custom


1.0Power Input, Crystal

NHS-972-1-YS-1M51

Figure 6-2 System Power


Revision: A1.0 2014/9/15

CT 1110uF

D2RB521S-30

1 2

BT 1CR2032

VS

C3102pF

C10103pF

CT 5710uF

R2351K

L2 4.7uH

CT 610uF

VD18

R12220K

CB70.1uF

VD33

Sy sPwrEn

C5N.C.

R11100K

Sy sPwrEn

Vin

Vin

Vin

CT 910uF

CT 1710uF

CT 1010uF

CT 710uF

CT 5610uF

CT 5910uF

CT 5410uF

U3

ZT 7103TTSOT-25

EN1

GND2

SW3

Vin4

FB5

VS

VSVS

CT 510uF

VS VS

VS VS

CT 810uF

CT 1310uF

C13102p

C2 470p

R10680K

Cx?1uF

Ux?NCT 3705U-ASOT23-5

SET4

GN

D2

OUT5

IN1

SHDN3

Rx?150K

Rx?

120KVS


Date: Sheet of

Custom

3 14Wednesday, September 03, 2014

1.0System Power

NHS-972-1-YS-1M51

Jx?VRT C

123

SW2RTC Key

VS

C61N.C.

R96100K

RTCWkUp

VS

Sys. Power

Switch

C8102p

RTCWkUp

VS

Vin

VS

VS

VSVSVS

VS

VS

VS

VSVS

VS

VS

VSVS

VS

U8

ZT 7103TTSOT-25

EN1

GND2

SW3

Vin4

FB5

U4

ZT 7103TTSOT-25

EN1

GND2

SW3

Vin4

FB5

RTCVD

RTCVD

3.3V IO power

1.8V DRAM power

1.2V core power

RTC power

R9150K

CT 5810uF

VD12

VD33

C9N.C.

C7102pF

R22120K

R2191K

L1 4.7uH

L4 4.7uH

R20100

CT 1410uF

C4N.C.

SW9VD33

1 2

SW12VD12

1 2

SW10VD18

1 2

Figure 6-3 DC/DC


Revision: A1.0 2014/9/15

PG14PG13

X2

0X

21

VS

R8612.1K

PF12


Date: Sheet of

Custom


1.0NUC972

NHS-972-1-YS-1M51

Sy sWkUpSy sPwrEn

Sy sWkUpSy sPwrEn

ADC[0:7]

AVS

AVSAVS

PLLVD12

PLLVS

CT 7510uF

VS

CB250.1uF

UPL1VD12

VS

CB110.1uF

CB290.1uF

AVD33

UPL0VD12

VS

CB100.1uF

VS

CB300.1uF

UOVD33

VS

PG1PG0

PE

8P

E7

VD33

PE

9

PE

11

PE

10

VD

12

VD

12

PE

12

PL

LV

D1

2

PE[10:13]PE[2:9]

PE

13

PLL

VS

PD[0:7]

PH

2

PH[0:1]

PF11

PH

3

VD

33

VS

VS

PH[2:3]PF[0:9]

PE[0:1]

PE[14:15]

VS

PF10

UP

L1

VD

12

UP

L0

VD

12

VS

UH

VD

33

UO

VD

33

VD

12

VS

PG2

X1[0:1]

PG3

PE

14

X1

0X

11

R8512.1K

VS

PF

10

PE

15

PH

1

UD

H1

PH

0CB260.1uF P

F1

PF

0

PF

3P

F2

UD

H0

PF

5P

F4

PF

7P

F6

PE

0

PF

8P

F9

PE

2P

E1

PE

5

PE

3

PE

6

PE

4

UHVD33

AD

C6

PA1PA0

PD4

PD6PD7

PD5

AD

C0

AD

C4

VS

VS

AD

C7

VS

AD

C5

AD

C1

PD0

AD

C3

AD

C2

PD3

Sy

sW

kU

p

nRst

PD2PD1

PJ4

PB[12:15]

PB[6:11]

PJ0PJ1PJ2

PC14PJ3

PC11PC12PC13

PC[0:14]

PD11

PH[8:13]PH[4:7]

PG[4:5]

PC10

PC7PC8PC9

VD33VD33

PC6PC5PC4

PG5

PC3

PG4

AV

D33

VD33VS

VD12

PC0

PC2PC1

Sy

sP

wrE

n

UDH[0:1]

C671uF

PH[14:15]

UDO[0:2]

MVS

MVS

MVS

PA15

PB15

X2[0:1]

PB14

PA14

PB13

VD12

PB10PB11

PB12

PF[11:14]

PB9

VD

33

VD

12

PB7

PA13

PB6

PB8

PA12

PB5

PD10

PA11

PB

0P

B1

PB4

PB

3P

B2

PA10

VD

33

PA9

VD

12

PI[0:2]PI[3:15]

PD8

PA6

PD9

PD12

PA7PA8

PD13

PA5PA4

PD14PD15

PB[0:1]

PA2PA3

PI1

2

PB[2:5]P

I15

PI1

4

VD18

PI8

PI1

3

VD18

PG6

VD18VD18

PI1

0P

I9

VD18

PI1

1

VD18

PI5 P

I7P

I6

PG7

PI3

PI2

PI1

VD

33

PI4

VD

12

nRst

PJ[0:4]

PG8

VS

PG[10:14]

PG[0:3]

PG9

VD12

PG[6:9]

PD[8:15]

PG10

PH

13

UDO2UDO1UDO0

RT

CV

D

RTCVD

U15NUC970

PG.3/IIC1SDA1

PG.2/IIC1SCL2

PG.1/IIC0SDA3

PG.0/IIC0SCL4

PG.14/IIS_LRCK/SC0CD/UR6CTS5

PG.13/IIS_BCLK/SC0PWR/UR6RTS6

PG.12/IIS_DI/SC0_DAT/UR6Rx7

PG.11/IIS_DO/SC0_CLK/UR6Tx8

PG.10/IIS_MClk/SC0_RST9

VDD3310

VSS11

VDD1212

MVSS13

MVDD14

MVSS15

MVDD16

MVSS17

MVDD18

VSS19

VDD3320

VDD1221

PF.14/UR2CTS/TM3CAP/Int322

PF.13/UR2RTS/TM3TGL/Int223

PF.12/UR2Rx/TM2CAP/Int124

PF.11/UR2Tx/TM2TGL/Int025

PG.9/LDEN26

PG.8/LVsy nc27

PG.7/LHsy nc28

PG.6/LClk29

PD.15/LD23/UR9Rx/PWM3/EBI_nWait30

PD.14/LD22/UR9Tx/PWM2/EBI_nOE31

PD.13/LD21/PWM1/EBI_nWE32

PD.12/LD20/UR9Rx/PWM0/EBI_nCS433

PD.11/LD19/UR9Tx/EBI_nCS334

PD.10/LD18/EBI_nCS235



PA.15/LD15/KPI_Col7/PWM338




PA.11/LD11/KPI_Col342

PA.10/LD10/KPI_Col243

VDD3344

PA.9/LD9/KPI_Col1/RMII0_RxErr45

PA.8/LD8/KPI_Col0/RMII0_CRSDV46

PA.7/LD7/KPI_Row3/RMII0_RxD147

PA.6/LD6/KPI_Row2/RMII0_RxD048

PA.5/LD5/KPI_Row1RMII0_Ref Clk49

PA.4/LD4/KPI_Row0/RMII0_TxEn50

PA.3/LD3/RMII0_TxD151

PA.2/LD2/RMII0_TxD052

PA.1/LD1/RMII0_MDio53

PA.0/LD0/RMII0_MDC54

PD.7/SD0PWR162

PB.4/UR6RTS109PB.5/UR6CTS110PB.6/SPI0CS0111

PB.9/SPI0Di(D1)114

PB.8/SPI0Do(D0)113

PB.7/SPI0Clk112

PB.15/UR10CTS/SPI1Di(D1)120

PB.14/UR10RTS/SPI1Do(D0)119

PB.13/UR10Rx/SPI1Clk118

PB.12/UR10Tx/SPI1CS0117

PB.11/UR10Rx/SPI0D3/CAN0Tx116

PB.10/UR10Tx/SPI0D2/CAN0Rx115

PG.4/NCS1/UR7Tx/SPI1D2121

PJ.3/TDO138PJ.0/TCK139PJ.1/TMS140PJ.2/TDI141PJ.4/nTRST142nRESET143VDD33144VSS145VDD12146MVSS147

PG.5/NRDY1/UR7Rx/SPI1D3122

VSS153

MVDD150MVSS151

MVDD148MVSS149

VDD33154PD.0/SD0CMD155PD.1/SD0CLK156

PC.14/NWP/PWM0137

PC.13/NRDY0/UR4CTS/TM3CAP136

PC.12/NRE/UR4RTS/TM3TGL135

PC.11/NWE/UR4Rx/TM2CAP134

PC.10/NCLE/UR4Tx/TM2TGL133

PC.9/NALE/UR10CTS/TM1CAP132

PC.8/NCS0/UR10RTS/TM1TGL131

PC.7/ND7/UR10Tx/TM0CAP130

PC.6/ND6/UR10Tx/TM0TGL129

PC.5/ND5/eMMC_CLK128

PC.4/ND4/eMMC_CMD127

PC.3/ND3/eMMC_D3126

PC.2/ND2/eMMC_D2125

PC.1/ND1/eMMC_D1124

PC.0/ND0/eMMC_D0123

PD.2/SD0D0157PD.3/SD0D1158PD.4/SD0D2159PD.5/SD0D3160PD.6/SD0CD161

MVDD152

AD

C0

55

AD

C6

56

AD

C4

57

AV

SS

58

AV

DD

59

AD

C7

60

AD

C5

61

AD

C1

62

AD

C3

63

AD

C2

64

Vre

f65

RT

C_V

DD

66

Sy

sP

WR

En

67

Sy

snW

kU

p68

RT

CX

i69

RT

CX

o70

PH

.4/K

PI_

Row

0/U

R1

Tx

/EB

I_A

dd

0/I

nt4

71

PH

.5/K

PI_

Row

1/U

R1

Rx/E

BI_

Ad

d1/I

nt5

72

PH

.6/K

PI_

Row

2/S

D1C

md

/UR

1R

TS

/EB

I_A

dd2/I

nt6

73

PH

.7/K

PI_

Row

3/S

D1C

lk/U

R1C

TS

/EB

I_A

dd3

/In

t774

PH

.8/K

PI_

Col0

/SD

1D

0/U

R4T

x/E

BI_

Ad

d4

75

PH

.9/K

PI_

Col1

/SD

1D

1/U

R4R

x/E

BI_

Add5

76

PH

.10

/KP

I_C

ol2

/SD

1D

2/U

R4R

TS

/EB

I_A

dd6

77

PH

.11

/KP

I_C

ol3

/SD

1D

3/U

R4C

TS

/EB

I_A

dd7

78

PH

.12

/KP

I_C

l4/S

D1

CD

/UR

8T

x/S

PI0

CS

1/E

BI_

Add

879

VD

D33

80

VS

S81

VD

D12

82

PH

.13

/KP

I_C

ol5

/SD

1P

WR

/UR

8R

x/S

PI1

CS

1/E

BI_

Add9

83

PH

.14

/KP

I_C

ol6

/UR

8R

TS

/CA

N1R

x/E

BI_

nB

E0

84

PH

.15

/KP

I_C

ol7

/UR

8C

TS

/CA

N1T

x/E

BI_

nB

E1

85

PI.

0/E

BI_

D0

86

PI.

1/N

CS

0/U

R7

Tx

/EB

I_D

1/I

nt6

87

PI.

2/N

WP

/UR

7R

x/E

BI_

D2

/Int7

88

PI.

3/S

Clk

o/N

ALE

/IIC

1S

CL

/EB

I_D

389

PI.

4/S

PC

lk/N

CLE

/IIC

1S

DA

/EB

I_D

490

PI.

5/S

Hs

ync

/NW

E/e

MM

C_C

md

/EB

I_D

5/S

D1

CM

D91

PI.

6/S

Vsy

nc/N

RE

/eM

MC

_C

lk/S

C1_

Rs

t/E

BI_

D6

/SD

1C

LK

92

PI.

7/S

Fie

ld/N

RD

Y0/e

MM

C_

D3/S

C1_

Clk

/EB

I_D

7/S

D1D

093

PI.

8/S

D0

/ND

0/e

MM

C_D

0/S

C1_

DA

T/E

BI_

D8

/SD

1D

194

PI.

9/S

D1

/ND

1/e

MM

C_D

1/S

C1_

PW

R/E

BI_

D9/S

D1D

295

PI.

10/S

D2/N

D2

/eM

MC

_D

2/S

C1

_C

D/E

BI_

D1

0/S

D1D

396

PI.

11/S

D3/N

D3

/SC

0_R

st/

EB

I_D

11

97

PI.

12/S

D4/N

D4

/UR

8T

x/S

C0_

Clk

/EB

I_D

12

/SD

1C

D98

PI.

13/S

D5/N

D5

/UR

8R

x/S

C0_D

AT

/EB

I_D

13

/SD

1P

WR

99

PI.

14/S

D6/N

D6

/UR

8R

TS

/SC

0_

PW

R/E

BI_

D14

100

PI.

15/S

D7/N

D7

/UR

8C

TS

/SC

0_

CD

/EB

I_D

15

101

VD

D12

102

VS

S1

03

VD

D33

104

PB

.0/N

CS

1/I

IC1S

CL/U

R5

Tx/S

PI0

CS

1/T

M1T

GL

105

PB

.1/N

RD

Y1

/IIC

1S

DA

/UR

5R

x/S

PI1

CS

1/T

M1

CA

P1

06

PB

.2/U

R6

Tx

/PW

M0

/TM

0T

GL

107

PB

.3/U

R6

Rx/P

WM

1/T

M0

CA

P1

08

US

B0_

ID2

16

US

B0

_R

ext

215

US

B0

_V

DD

214

US

B0_D

P2

13

US

B0_D

M2

12

US

B0

_V

SS

211

US

BP

LL0

_V

DD

210

US

B1

_R

ext

209

US

B1

_V

DD

208

US

B1_D

P2

07

US

B1_D

M2

06

US

B1

_V

SS

205

US

BP

LL1

_V

DD

204

VD

D12

203

VS

S2

02

PE

.14

/US

B0

PW

RE

n2

01

PE

.15

/US

B1

PW

RE

n2

00

PF

.10/U

SB

PW

RE

n/W

DT

_nR

st

199

PH

.0/U

SB

0V

bus

VLD

/In

t01

98

PH

.1/U

SB

OC

/In

t11

97

PF

.0/R

MII

0_M

DC

196

PF

.1/R

MII

0_M

Dio

195

PF

.2/R

MII

0_

Tx

D0

194

PF

.3/R

MII

0_

Tx

D1

193

PF

.4/R

MII

0_T

xE

n1

92

PF

.5/R

MII

0_

RefC

lk1

91

PF

.6/R

MII

0_R

xD

01

90

PF

.7/R

MII

0_R

xD

11

89

PF

.8/R

MII

0_

CR

SD

V1

88

PF

.9/R

MII

0_R

xE

rr1

87

VS

S1

86

Main

Xo

185

Main

Xi

184

VD

D33

183

PE

.0/U

R0T

x1

82

PE

.1/U

R0

Rx

181

PE

.2/R

MII

1_

MD

C/S

D1C

MD

/UR

1T

x1

80

PE

.3/R

MII

1_

MD

IO/S

D1

CLK

/UR

1R

x1

79

PE

.4/R

MII

1_T

xD

0/S

D1D

0/U

R1R

TS

178

PE

.5/R

MII

1_T

xD

1/S

D1D

1/U

R1C

TS

177

PE

.6/R

MII

1_T

xE

n/S

D1

D2/U

R1D

TR

176

PE

.7/R

MII

1_

RefC

lk/S

D1

D3/U

R1D

SR

175

PE

.8/R

MII

1_R

xD

0/S

D1C

D/U

R1R

i1

74

PE

.9/R

MII

1_R

xD

1/S

D1

PW

R/U

R1

CD

173

PE

.10

/RM

II1

_C

RS

DV

/UR

8T

x1

72

PE

.11/R

MII

1_

Rx

Err

/UR

8R

x1

71

PE

.12/U

R8

RT

S/U

R3T

x1

70

PE

.13

/UR

8C

TS

/UR

3R

x1

69

PH

.2/I

IC1S

CL

/UR

9T

x/C

AN

0R

x/P

WM

2/I

nt2

168

PH

.3/I

IC1S

DA

/UR

9R

x/C

AN

0T

x/P

WM

3/I

nt3

167

VD

D12

166

PLL

_V

SS

165

PLL

_V

DD

12

164

VD

D12

163

PA[0:15]

PI0P

H1

5

PG11

PH

9

PH

14

VD33

MVS

PG12

PF14

PH

10

PH

12

PH

11

MVS

PH

8P

H7

PH

6P

H5

MVS

PF13

PH

4

Figure 6-4 NUC972


Revision: A1.0 2014/9/15

System Reset

ICE I/F

VS

PJ1

PJ4

PJ0

R15100K

VS

SW4WDTRst

VS

VD33

PJ[0:4]

SW6

ICE

12345

109876

PJ2

nRst

PJ3

ICEnRst

SW31

Cfg[0:4]

12345

109876

SW35

Cfg[5 :9 ]

12345

109876

VS

TCK CT 5110uF

CT 5210uF

RN8 10K1 23 45 67 8

RN9 10K1 23 45 67 8

R119 10K

R118 10K

Cfg1:0] =

00 : Boot from USB.

01 : Boor from eMMC.

10 : Boot from NANA Flash.

11 : Boot from SPI Flash.

Cfg2 =

0 : System clock is from 12 MHz crystal.

1 : System clock is from UPLL output.

VD33

TDI

Cfg3 =

0 : WDT is OFF after power-on.

1 : WDT is ON after power-on.

Cfg5 =

0 : UART 0 debug message output ON.

1 : UART 0 debug message output OFF.

Cfg[7:6] =





Cfg[9:8] =




11 : Ignore Power-On Setting.Cfg4 =

0 : Pin PJ[4:0] used as GPIO pin.

1 : Pin PJ[4:0] used as JTAG interface.

JT AG ICE

CON1

3

9

21

857

4

10

6

11 1213 1415 1617 1819 20

nTRST

TMS

VS

VS

nRst

PA8

PA3PA2PA1PA0

PA4

PA5

PA7PA6

PA9

VD33

RN3N.C.

12

34

56

78

VS

VS

PA[0:9]

VD33


Date: Sheet of

Custom

5 14Wednesday, September 03, 2014

1.0Configure, ICE, Reset

NHS-972-1-YS-1M51

PF10

ICEnRst

Note:

Normally, J4 is short.

J4ICERst

12

TDO

C61uF

Figure 6-5 Configure, ICE Reset


Revision: A1.0 2014/9/15

AVS

PLLVSPLLVS

PLLVSVSRG1 0

PLLVD12

AVD33

L13 1608-221T

CT 7410uF

RG20

CT 9010uF

CB310.1uF

L14 1608-221T

VS

VD12

VD33

CT 8310uF

VS

VD12

CT 4110uF

CB120.1uF

R112 0

VS

CT 8110uF

CB330.1uF

CT 9510uF

CB230.1uF

CT 7910uF

CB200.1uF

CT 7110uF

CB140.1uF

UPL0VD12

CT 7010uF

CB150.1uF

UHVD33

VS

CT 8410uF

R114 0

VS

CT 7610uF

VD33

CB170.1uF

CT 9210uF

VD33

R116 0

UPL1VD12

UOVD33

CT 8610uF

VS

VD12

R113 0

CT 7710uF

CB180.1uF

CT 8210uF

CB220.1uF

VD12

VD33

VD18

VS

VS

CT 8510uF

VD33

R115 0

CB240.1uF

VS

UDVD33

CM 50.22uF

CM 40.22uF

RG3 0

CT 9410uF

CB320.1uF

CT 6910uF

CM 20.22uF

CM 10.22uF

CM 30.22uF

CM 60.22uF

CT 7310uF

MVS

CT 8810uF

CT 6710uF

CT 9310uF

R1170 R110

0

CB270.1uF

CT 8910uFMVS

CT 8710uF

VS

VS

CB280.1uF

CT 8010uF

CB210.1uF

R1090 R111

0

CT 7210uF

CB160.1uF

CT 7810uF

CB190.1uF


Date: Sheet of

Custom


1.0P_Filter

NHS-972-1-YS-1M51

Figure 6-6 P_Filter


Revision: A1.0 2014/9/15

CT 6210uF

CT 6310uF

CON12

PD[0:7 ]

1357911

2468

1012

PC0PC2PC4PC6

PC[0:14]

PC10PC8

PC12PC14

PC1

PC7

PC3PC5

PC9PC11PC13

PD6

VD33VD33

VS

PD7

CON13

PC[0:14]

135791113151719

2468

101214161820

VS

PD[0:15]

CT 4010uF

CT 4710uF

VS

VD33

CT 6810uF

CT 3710uF

CT 3910uF

PE[0:15]

PE4PE2PE0

PE10PE8PE6

PE14PE12

PE3PE1

PE7PE5

VD33

PE11PE9

VS

VD33

CON21

PE[0:15]

135791113151719

2468

101214161820

PE13

VS

PE15

CON32

PD[8:15]

1357911

2468

1012

PD14 PD15

VD33VD33PD9PD8PD11PD13

PD10PD12

VSVS

PF4PF2PF0

PF10PF8PF6

CON22

PI[0 :15]

135791113151719

2468

101214161820

PF13PF11

PF3PF1

PF7PF5

PF14PF12

PF9

VD33 VD33

VS VS

PF[0:14]

CON27

PF[0:10]

13579111315

2468

10121416

CON30

PF[11:14]

1357

2468

VSVS

VD33 VD33

CT 4910uF

CT 3810uF

VS

VD33

CT 9610uF

CT 5010uF

CT 4810uF

VS

CT 3610uF

VD33

VS

CT 3510uF

VD33

CON19

PH[0:3]

1357

2468

PH0PH2

VD33

PH3PH1

VS

VD33

VS

VD33

PH[0:15]

VS VS

PH6PH4

PH12PH10PH8

PH7PH5

PH14

PH11PH9

PH15PH13

PA[0:15]

PA0PA2PA4

PA8PA10

PA6

PA14PA12 CON25

PH[4:15]

13579111315

2468

10121416

PA1PA3

VD33

PA5PA7PA9

PA15PA13PA11

VD33VD33

CON33

PA[0:15]

135791113151719

2468

101214161820

VSVS

PB2PB0

PB[0:15]

PB4PB6PB8PB10PB12PB14

PB1PB3

PB7PB9

PB5

PB13PB11

VD33VD33

PB15

VS

CON14

PB[0:15]

135791113151719

2468

101214161820

VS

CON29

ADC[0:7 ]

1357

2468

ADC0

ADC6ADC4ADC2 ADC3

ADC1

ADC7ADC5

VD33VD33

VS VS

PG7PG6PG8 PG9

CON35

PG[6:9 ]

1357

2468

VS

VD33

VS

VD33

VD33

CON17

PG[4:5 ]

135

246

VD33

VSVS

PG5PG4

VD33

VSVS

VD33

PG2PG0

VD33

PG1PG3

VD33

VS VS

PG10PG12 PG13

PG11

PG14

PG[0:14]

CON28

PG[0:3 ]

1357

2468

CON34

PG[10:14]

13579

2468

10

PI2PI0

PI6PI4

PI12PI10PI8

PI3PI1

PI14

PI7PI5

PI13PI11PI9

PI[0:15]

PI15

VD33

VS

VD33

VS

PJ2PJ0

PJ3PJ1

PJ4

PJ[0:4]

CON16

PJ[0:4]

13579

2468

10

ADC[0:7]

VD33 VD33PD1PD3PD5

PD0PD2PD4

VSVS

VS

VD33

CT 2910uF

CT 6510uF

CT 3010uF


Date: Sheet of

Custom


1.0GPIO

NHS-972-1-YS-1M51

Figure 6-7 GPIO


Revision: A1.0 2014/9/15

D0D2

D6D4

D10

SW25

LCDD[8:15]

12345678

161514131211109

PA13

PA11

PA15

PA9

PA14

PA12

PA8

PA10

LD15

LD13

LD11

D14D12

LD14

LD12

LD9

D8

LD10

LD8

Add0

Add5Add3Add1

Add4Add2

Add6 Add7

LD15LD13LD11

LD9

LD14

LD10LD12

LD8LD7LD5LD3LD1

LD2

LD6LD4

LD0

Add9nBE0Add8

nBE1

SW23

LCDD[16:23]

12345678

161514131211109

VS VS

VD33

PD8PD9PD10PD11PD12

PD14PD15

PD13

LD16

LD18LD19LD20

LD17

LD23

LD21LD22

CT 9110uFCT 61

10uF

SW20

LCDCtrl

123456

121110987

CT 6010uF

CT 6410uF

LD16LD18

LD17

LD21LD19

LD20LD22LD23

SW26

KPI

12345

109876

PI14

PI12

PI6

PI8

PB0

PI0

PI4

VD33

S_D3S_D1

S_nRst

S_D7S_D5

SIICSDA

S_Clk

S_Hsy nc

VSVS

VS

SW18

PWM

1234

8765

CON15

CM OS Sensor

1357911131517192123

2468

1012141618202224

VS

VD33

S_D2

VD33

S_D6S_Vsy nc

S_D4

S_D0S_PClk

S_PwDn

VD33

SIICClk

VD33

LDEN

LCS

LHsy nc

BLEnLClk

LVsy nc

nCS1nCS3

nWaitnWe

PI9

PI11

PI13

PI15

PI5

PI7

PI3

PB1

CON26

EBI

13579111315171921232527293133353739

2468

10121416182022242628303234363840

VS

VD33

VS

SW27

EBIAdd[8:9]/Ctrl

1234

8765

PWM

PA[0:15]

VS

PD[8:15]

LCS BLEnLDENLHsy nc LClk

LVsy nc

PG[6:9]

SW28

EBICtrl

12345678

161514131211109

PG[2:3]

D10D11D12D13D14D15

D0D1D2

D4D5D6

SW36

LCD T ouch

12345

109876

D7

D3

D8D9

ADC[3:7]

nCS0

Row0Row1Row2Col0Col1

nCS2nCS4nOE

SW33

EBIAdd[0:7]

12345678

161514131211109

SW32

EBID[0:7]

12345678

161514131211109

PI10

VS

SW24

CM OSCtrl /D[0:1]

12345678

161514131211109

SW22

CM OSD[2:7]/IIC

12345678

161514131211109

K1 Lef t

K2 Up

S_D6

K5 Dwn

K6 EnterS_D0

K3 Right

S_D4

S_Vsy nc

S_PwDn

S_PClk

S_D1

S_D5

SIICClk

K4 ExitS_Hsy nc

S_D7

S_D3

S_Clk

S_nRst

S_D2

ADC4

SIICSDA

ADC5ADC6ADC7

YMYP

XPXM

VsenADC3

PD14PD15

PD13PD12PD11

PD9PD10

SW29

LCDD[0:7]

12345678

161514131211109

PI11

PD8

PI10

PI13PI12

PI15PI14

PG2

PG7

PG9

nWait

PA7

nOE

PA3

nWe

nCS3nCS4

PA1

nCS2

PA5

nCS1nCS0

PG8

PG6PG3

PA6

PA4

PA2

PA0

PH4

PI0

PH6PH5

PH9PH10

PI1PI2

PI4

Row0

PI6

PI3

PI5

Row2

Row1

PI7

PH4

PH7

PH9

PH5

PH11

PH6

PH8

Add0Add1

PH10

Add3

Add5

Add7

Add2

Add4

Add6

PI8

PH[2:15]

PI9

Add9nBE0

Add8

nBE1

PH12

PH14PH15

PH13

PWMPH2

PB2PH3

PB3

PI[0:15]

PB[0:3]

SW39

EBID[8:15]

12345678

161514131211109

VSVS

VD33

2x3 KeypadsCMOS sensor

Port

EBI port

RGB888 LCD Port

CON23

LCD

13579111315171921232527293133353739

2468

10121416182022242628303234363840

41 4243 4445 4647 4849 5051 5253 5455 5657 5859 6061 6263 64

XM YMYP

VsenXP


Date: Sheet of

Custom


1.0EBI, Keypads, LCD and CMOS sensor

NHS-972-1-YS-1M51

VS VS

LD7

LD3

LD5

LD1

LD6

LD4

LD2

LD0

D1

D5D7

D3

D13D11

D15

D9

Figure 6-8 EBI, Keys, AV


Revision: A1.0 2014/9/15

U7

W25Q128BV

Hld/D31

VCC2

/Rst3

NC4

NC5

NC6

CS7

Do/D18

Wp/D29 GND

10 NC11 NC12 NC13 NC14 Di/D015 CLK16

CON4SD Card

DAT18 DAT07 VSS6 CLK5 VDD4 VSS3 CMD2 DAT31 DAT29

WP11

GND12

CD#10

HO

LD

14

HO

LD

13

SPICLKSPIDo/D0

SPIDi/D1SPICLK

SPICS

SPIDo/D0

R38

10K

N_RE

R40

10K

N_CS0

N_ALEN_CLE

N_WE

VS

VS

VS

N_CS1N_R/B1

U9NAND Flash

R/B17

RE8

CE19

CLE16

ALE17

WE18

N.C.19

I/O029

I/O130

I/O231

I/O332

I/O441

I/O542

I/O643

I/O744

R/B26

/CE210

VC

C12

VC

C37

VS

S36

VS

S25

PRE38

VC

C1

VC

C24

VC

C34

VS

S2

VS

S13

VS

S23

VS

S48

PSL39

R39 33

VD33

VD33

PB[6:11]

VD33

R37 33

PC[0:14]

SPICSSPIDi/D1

RV1 0

R1810K

SW5PSL

12

3

N_R/B1

PSLN_CS1

N_R/B0

NVD33

N_D7

N_D2N_D3

N_D1N_D0

N_D5N_D4

N_D6

U6W55X16

/CS1

Do/D12

Wp/D23

GND4

Di/D05CLK6Hld/D37VCC8

PAD2SDWP

SDWP

VS

CT 1910uF

SPIHld/D3

SPIWp/D2

Note:Only one SPI

Flash is used.

N_WP

PD[0:7]

VS

CT 1510uF

SW7NANDD[5:7]/Ctrl

12345

109876

VD33

VS

SW8

SPI

123456

121110987

SDVD33

R30100K

VS

CB60.1uF

CB20.1uF

NVD33

VS

SDCmd

SDD0

SDWP

SDD3

VD33

SDD2

SDD1

RN2 331 23 45 67 8

SW3NANDD[0:4]

12345

109876

R28 33

SDCLK

VS

C12N.C.

VSVS

RN4 33

1 23 45 67 8

VS

LED6SD_IndR32 1K


Date: Sheet of

Custom


1.0Memory

NHS-972-1-YS-1M51

SDVD33

RN7 10K1 23 45 67 8

SDCmd

SDD3SDD2

SDD0SDD1

R29 10K

SDPwr

VD33

R99 10K

SDCdNAND Flash

SPI Falsh

SD card

R35 10K

PAD3N_Pre

PC4

PC7PC6PC5

R31 10K

PC3PC2

PC0PC1

R27 47K

VD33

Q3SI2303CDS

D

G

S

PC9PC8

PC11PC10

PC14PC13PC12

SW14

SD

12345678

161514131211109

VS

CB50.1uF CT 20

10uF

CON7

NANDM LC

12

PB6

PB8

PD0

PB7

PD2

PB9

PD1

PD4PD3

PD7PD6PD5

SDCmd

SDD1SDD0

SDCLK

SDD2SDD3SDCdSDPwr

SW13NANDCtrl

12345

109876

SPIDo/D0SPIDi/D1

SPICLKSPICS

RN6 331 23 45 67 8

RN5 33

1 23 45 67 8

N_D2N_D1N_D0

N_D5N_D4

N_D3

N_D7N_D6

N_ALEN_CS0

N_RE

N_WEN_CLE

N_WPN_R/B0

PB10 SPIWp/D2PB11 SPIHld/D3

SDVD33

R1610K

R3410K

Figure 6-9 RMII


Revision: A1.0 2014/9/15

50MClki

C280.01uF/2KV

Phy AVD33

PF0SW38

Ethernet

12345

109876

PF1

SW21

Ethernet

12345

109876

RMii0TxEn

RMii0Ref Clk

PF4PF3PF2

RMii0MDC

PF9PF8PF7PF6PF5

RMii0RxD1RMii0RxD0

RMii0TxD1RMii0TxD0RMii0MDio

RMiiRxErrRMii0CRSDV

RX+

TX-

nRst

RX-

PF[0:9]

nRst

CON18RJ-45 8P8C_LED R/A

TX+1

TX-2

RX+3

NC4

NC5

RX-6

NC7

NC8Shield

13

Shield14

LED-9 LED+

10

LED-11 LED+12

TX+

MDI_TN

MDI_TP

VS

R62 1K

R71 1K

Phy IOVD33

Phy Test

Phy AD3

R105 75

R106 75

R66N.C.

R65N.C.

R10775

R63 75

R77N.C.

R7610K

VS

R68N.C.

CRSR6710K

RMii0CRSDV R705.1K

VS

R69N.C.

CRS

Col

Col

U13

T S8121C

TX+16

TX-14

NC13

TD-3

TD+1

RD+6

RD-8

NC5

RX-9

RX+11

CT2

NC4

CT7

CT10

NC12

CT15

C630.01uF

VS

CT 3410uF

VS

R73 5.1K

C660.1uF

VS

Phy AD3

C65 0.01uF

VS

R64 5.1KVS

VS

VS

MDI_RP

MDI_RN

C62 0.1uF

VS

C64 0.01uF

VS

CB130.1uF

CT 6610uF

RegOut

VS

RegOut

CB90.1uF

VS

U14

IP101GR

TxEr/FxSD1

Xi2

Xo3

Col/RMII4

TxEn5

TxD36

TxD27

TxD18

TxD09

TxClk/50MClki10

LED0/Phy AD011

LED3/Phy AD312

IOVDD13

RxClk/50M_Clko14

RxD315

RxD216

TestOn24

MDIO23

MDC22

RxEr/Int3221

CRS/LEDMod20

RxDV/CRS_DV19

RxD018

RxD117

nRst32

AVD3331

MDiTp30

MDiTn29

RegOut28

MDiRp27

MDiRn26

Iset25

EP

ad

33

RMii0CRSDV

RMii0RxD1RMii0RxD0

RMii0TxD1RMii0TxD0

RMii0MDC

MDI_TNMDI_TP

RMii0TxEn

RMii0MDio

RMiiRxErr

VS

MDI_RPMDI_RN

VS VSVS

EthX1R74 1M

C307pF

R751608-221T

X1

25M HzSOT-143

XIN1

GND2

GND4

XOUT3

R78330

EthX0

C317pF

EthX0EthX1

R1086.19K +/-1%

VS

Phy Test

L12 1608-221T

Phy AD3Phy AD0

VS

VD33

CT 3310uF

Phy IOVD33

Phy IOVD33

Phy AVD33

CT 3210uF

VS

L11 1608-221T

VS

VD33

CT 3110uF


Date: Sheet of

Custom


1.0Ethernet

NHS-972-1-YS-1M51

Phy AD0VD33

Phy AD0VD33

50MClki

VS

C29N.C.

RMii0Ref Clk

R72

0

VS

Figure 6-10 RMII


Revision: A1.0 2014/9/15

Rx? 4.7K

Rx? 4.7K

L31608-221T

CDCVs

CDCVs

SDASCK

MCLK

FSBCLK

R42 33

VDDB

R41 33

CDCVs

R45 33

CDCVs

CDCVs

CDCVs

CDCVs

CT 2810uF

CD

CV

sC

DC

Vs

J8SpkVD

123

MicBias

CDCVs

AUXo2RSPKOUT

CDCAVs

CDCAVs

AUXo1

SDA

LAUXi

Mic01Mic00

Mic11

CDCVs

Lin0

Lin1Mic10Mic11

Vin

BCLKFS

Mic10

(EPAD = VSSA)

VD

DA

CD

CA

Vs

DA

C1

DA

C0

LS

PK

OU

TS

pkV

D

J7VDDB

123

Lin1

Lin0

CT 2110uF

CDAVs

EPAD

U10NCU8822L

LMICP1

LMICN2

LLIN/GPIO23

RMICP4

RMICN5

RLIN/GPIO36

FS7

BCLK8

AD

CO

UT

9

DA

CIN

10

MC

LK

11

VS

SD

12

VD

DC

13

VD

DB

14

CS

B/G

PIO

115

SC

LK

16

SDIO17MODE18LAUXIN19RAUXIN20AUXOUT121AUXOUT222NC23VSSSPK24

NC

25

VD

DS

PK

26

VR

EF

27

VS

SA

28

RH

P2

9LH

P3

0V

DD

A3

1M

ICB

IAS

32

EP

AD

33

MC

LK

AD

Co

VD

DC

VS

SD

DA

Ci

CS

BV

DD

B

SC

K

J6VDDC

123

R521K

Mic00

Mic01

VS

MicBias

R43 0

C19 1uF

R44 0CDCVs

VS

R57 0

R56 0

DACi

CDCAVs

ADCo

C21 1uF

C17 1uF

C15 1uF

C18 1uF

C20 1uF

C16 1uF

C14 1uF

RAUXi

MODE

AUXo1

AUXo2

R47 R

R53 R

R511K

R50 100K

R49 100K

VREFSpkVD

MODE

VDDAVDDA

SpkVDR58 680

CON9

AUXo

12

VDDB

CSB

VDDBVDDB

CON8

Spko

12

CON5

IIC M ode

12

PE12

VDDC

PE12

VDDC

R3310K

1

6

3

4

7

5

2

PJK-691

8

VDDB

M 2 MIC

9.7D2.54mm

R551.1K

Mode

2-wire IIC.

Description

1

0

R461.1K

3-wire IIC.

M 1 MIC

9.7D2.54mm

R361.1K

LSPKOUTRSPKOUT

R481.1K

C234.7uF

CON6

AUXi

12


Date: Sheet of

Custom

11 14Tuesday, September 09, 2014

1.0IIS

NHS-972-1-YS-1M51

NC: 10, 19~23, 25 (NUA8501)

NC: 23, 25 (NUA8520)

RAUXiLAUXi

CDCVs

CDAVs

CT 2710uF

CDAVs

CDAVs

CDCVs

CB80.1uF

L80

L90

C25N.C.

DAC0

C261uF

R6110

SW15

IIS

12345678

161514131211109

DAC1

C241uF

R6010

C27N.C.

C22N.C.

L100

CON11EARPhone

6

73

48

5

1

2

PG[0:1]

VS

CT 2510uF

VD33

SpkVD

L61608-221T

PG0

CT 2310uF

CDAVs

PG1

CT 2610uF

VD33VDDA

L71608-221T

CDAVs

VD33

CT 2210uF

VD18

VDDB

SDASCK

PG14

CT 1610uF

VD33

VDDC

VD18

PG[10:14]PG10PG11

L51608-221T

PG12PG13

Figure 6-11 IIS


Revision: A1.0 2014/9/15

CAN0RsCAN0HVS

U11

SN65HVD230

D1

GND2

VCC3

R4

Rs8

CANH7

CANL6

Vref5

CAN0LCAN0Rx

CAN0Tx

SW37

SIM Card

12345

109876

SC0ClkSC0Rst

SC0CdSC0PwrSC0Dat

PG10

PG14PG13

PG11PG12

CON31

SIM CARD SLOT

C11

C22

C33

C44

C55

C66

C77

C88SC0Rst

SC0Pwr

SC0Cd

SC0Clk SC0DatVSVS

R12010K

R9510K

R12110K

R12310K

Q7

SI2303CDSD

G

S

VS

VS

VS

VD33


Date: Sheet of

Custom


1.0CAN Bus, SIM and eMC Card

NHS-972-1-YS-1M51

VD33

VS

CON10

CAN0/1

13

24

CAN0L

R59 120

R54 120

CAN0H

VD33

VS

VD33

CAN1LCAN1H

R101 10KR102 100K CB3

0.1uFR103 10KR104 100K

VS

CB40.1uF

SW19

CAN 0/1 Cfg

123456

121110987

CAN0Rs

CB340.1uF

CAN1RsVS CAN1H

U12

SN65HVD230

D1

GND2

VCC3

R4

Rs8

CANH7

CANL6

Vref5

VD33

CAN1Tx

CAN1RxCAN1L

CB350.1uF

CT 9710uF

SW17

CAN Bus0/1

1234

8765 CAN1Rs

PG[10:14]

PH[14:15]PH[2:3]

PH2PH3PH14PH15

CAN0RxCAN0Tx

CAN1TxCAN1Rx

CON3eM M C Card

DAT18 DAT07 VSS6 CLK5 VDD4 VSS3 CMD2 DAT31 DAT29

WP11

GND12

CD#10

HO

LD

14

HO

LD

13

PAD1eM WP

VS

eMWP

CT 5510uF

VS

CT 5310uF

eMVD33

R100100K

VS

VD33

eMWP

R25 33

VS

C11N.C.

VS

VS

VS

LED5SD_InR24 1K

R9710K

R98

100K

VD33

Q6 SI2303CDSD

G

S

SDVD33

RN1 10K1 23 45 67 8

eMCmd

R26 10K

eMMC card

SIM card

CAN bus1

CAN bus0

eMVD33

PC[0:5]

SW11

eM M C

123456

121110987

PC0PC1PC2

PC4PC3

PC5

eMD0

eMCmdeMD3eMD2eMD1

eMClk

eMD1eMD0

eMClk

eMCmdeMD3eMD2

eMD3eMD2eMD1eMD0

R122 33

Figure 6-12 CAN Bus, SIM card and eMMC


Revision: A1.0 2014/9/15

C44 0.47uF

C42 0.47uF

C38 0.47uF

C36 0.47uF C40 0.47uF

CON41UART 4

162738495 10

11

UR1CTSoUR1RTSiUR1RxoUR1Txi PE2

PE5PE4

VS

VS

PE3

VS

PF11

PF14PF13PF12

SW41

UART 2

1234

8765

PB4

PB2

PB5

PB3

SW43

UART 3

1234

8765

CON38UART 2

162738495 10

11

VS

VS

VS

UR1CTSoUR1RTSi

UR1RxoUR1Txi

UR0Tx

VS

UR0Rx

VS

VS

CON39UART 0

162738495 10

11

UR2TxiUR2Rxo

U19T RS3232EC

C1+1

V+2

C1-3

C2+4

C2-5

V-6

T2o7

R2in8

VCC16

GND15

T1o14

R1in13

R1o12

T1in11

T2in10

R2o9

UR2RTSi

VD33

UR2CTSo

VS

U21T RS3232EC

C1+1

V+2

C1-3

C2+4

C2-5

V-6

T2o7

R2in8

VCC16

GND15

T1o14

R1in13

R1o12

T1in11

T2in10

R2o9

VS

VD33

VS

VS

UR4TxUR4Rx

U22T RS3232EC

C1+1

V+2

C1-3

C2+4

C2-5

V-6

T2o7

R2in8

VCC16

GND15

T1o14

R1in13

R1o12

T1in11

T2in10

R2o9

UR4RTS

UR1Tx

UR4CTS

UR1Rx

VD33

VS

VS

U18T RS3232EC

C1+1

V+2

C1-3

C2+4

C2-5

V-6

T2o7

R2in8

VCC16

GND15

T1o14

R1in13

R1o12

T1in11

T2in10

R2o9

UR1RTSUR1CTS

VD33

VS

UR1TxUR1CTS

UR1RTS

UR2RTS

UR1Rx

UR2Rx

UR2TxUR2CTS

UR2Tx

UR2CTSUR2RTS

VS

UR2Rx

UR2RTSiUR2RxoUR2Txi

UR3CTS

UR3RTS

UR2CTSo

UR3Rx

UR3Tx

UR4TxUR4CTS

UR4RTSUR4Rx

UR0Tx

UR0Txi

UR0RxUR0Rxo

U20T RS3232EC

C1+1

V+2

C1-3

C2+4

C2-5

V-6

T2o7

R2in8

VCC16

GND15

T1o14

R1in13

R1o12

T1in11

T2in10

R2o9

UR3CTSUR3RTS

UR3RxUR3Tx

VD33

VS

VS

UR6RxoUR6Txi

UR6CTSoUR6RTSi

PE[0:1]

PF[11:14]

PE[2:5]

PB[12:15]

PB[2:5]

PB12

PB15PB14PB13

UR6Txi

UR6CTSoUR6RTSiUR6Rxo

UR10RTSiUR10RxoUR10Txi

UR10TxiUR10CTSo

UR10CTSoUR10RTSi

UR10Rxo

CON40UART 3

162738495 10

11

VS

VS

VS

UR0RxoPE1PE0 UR0Txi

CON37UART 1

162738495 10

11

VS

VS

VS

SW40

UART 1

1234

8765

CON36

CON4A

13

24

SW42

UART 0

1234

8765


Date: Sheet of

Custom


1.0UART

NHS-972-1-YS-1M51

C371uF

SW44

UART 4

1234

8765

C391uF

C431uF

C451uF

C411uF

C460.1uF

C510.47uF

C470.1uF

C520.47uF

C490.1uF

C540.47uF

C500.1uF

C550.47uF

C480.1uF

C530.47uF

C560.47uF

C570.47uF

C590.47uF

C600.47uF

C580.47uF

Figure 6-13 UART


Revision: A1.0 2014/9/15

CT 4610uF

VSR871K

VD33

R8851K

VS

SW30

USB P_Ctrl

1234

8765

UCtrl0

USBOC1USBOC0

VS

VS

R921K

R941K

UCtrl0

UCtrl1

R9151K

PE[14:15]

R9351K

UDH[0:1]

UDO[0:2]

VD33

PH[0:1]

CT 4210uF

VS

UCtrl1

PE14

PE15

5Vin

PH1

VS

CT 4410uF


Date: Sheet of

Custom


1.0USB

NHS-972-1-YS-1M51

OTG power

indicator

USB Host/Device

HOST power

indicator

LED7LED_G

LED10LED_R

LED8LED_R

LED9LED_G

U16NCT 3520W-H10

GND1

Vin2

Vin3

En4

OC5Vout6Vout7Vout8VS

5VinUVO

UVO

UVH UVHUVO UVO

UVH

U17NCT 3520W-H10

GND1

Vin2

Vin3

En4

OC5Vout6Vout7Vout8

5Vin

VS

USB Host

VS

CT 4310uF

UDO1UDO2

UDO0

CON24USB m iniAB RECEP.

V+1

D-2

D+3

ID4

GND5

6 789

VS

CT 410uF

UVH

VS

CT 4510uF

VS

VS

SW34

USB P_Ind

1234

8765

VS

UDH0UDH1

CON20

USB

1234

VS

USBOC1

R83390K

R84200K

VS

USBOC0

UVO

Q52N3904

Q42N3904

R891K

PH0

VD33

R9051K

VS

CT 310uF

VS

Figure 6-14 USB

NUC972 Development Board User Manual rev A1 -...

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