NSF- NIRT: "Surface State Engineering" Charge Storage and Conduction in Organo-Silicon Heterostructures as a Basis for

Nanoscale Devices

John C. Bean (PI)1, Avik Ghosh1, Lloyd R. Harriott1, Lin Pu2, Keith Williams3

1Department of Electrical and Computer Engineering, 2Department of Chemistry, 3Department of PhysicsUniversity of Virginia, Charlottesville Virginia

Basic Idea:

Create highly-pure, highly-ordered bound organo-silicon hybrids

Molecules bound so intimately that electron waves pass easily between components

Yielding:

1) Precise charge transfer into and out of Si surfaces

2) Conduction based on quantum mechanical resonance

In nanoscale MOSFETs this could:

1) Supplant trace donor/acceptor charge creation

2) Minimize ionized impurity scattering => Enhanced transport

3) Enable devices based on quantum interference phenomenon

Dual pronged first year NIRT strategy:

CNT FET experiments to hone characterization + modeling tools

Parallel development of full quasi 1D Molecular-SOI FET

“Fingerprinting” of Charge Centers in CNT FETs

Based on phenomenon of “random telegraph signals” (RTS):

In quasi 1D FET, charged trap can act as gate

As that charge center charges & discharges, FET current flickers

Details of flicker vs. FET bias => Spectroscopy of charge centers?

Quasi 1D FET realized

with carbon nanotube:

Yielding “classic” And a form of RTS signal

single Level RTS: not previously observed

Explaining newly observed CNT RTS signals

As effect of two closely

spaced charge centers

Preparing for full Molecular-SOI FET device where:

MOST exposed Si surface sites must first be molecularly passivated

So SELECTED sites can then be molecularly activated

Molecular attachment to Si measured with ATR-FTIR

Molecular passivation of Si measured using pulsed photoconductance:

Passivation Minimal surface recombination Maximum carrier lifetime

State-of-the-art passivation

demonstrated for acetylene

attached via UV-hydrosilylation:

Completing toolset necessary to meet up with . . .

Parallel development of full FET device structure

Side-gated Silicon on Insulator FET:

Side gated design to vary effective channel width

Based on double lift-off e-beam patterning

New e-beam system acquired and installed

Contact metallization and resists developed

Key sub-structures recently produced:

Now in process of combining these into full SOI FET Device

Which will then be ready to test molecular passivation & activation

+ Education and Outreach building upon:

1999 NSF CCLI => “UVA Virtual Lab” Science Education Website

Website traffic now approaching 4.5 million hits! (www.virlab.virginia.edu)

2005 NSF NUE => “Hands-on Introduction to Nanoscience” Class

Our VR recreation of class's AFMs and STMs

Together => 2009 IEEE Undergraduate Teaching Medal

To bring Nanoscience into Virginia Public Schools:

- Helped Danville CC create and fund Nano curriculum

Including successful grants to build their own ATM / STM lab

- Worked with Science Museum of Virginia to develop Nano exhibits

- Created for K-12 teacher workshop / class on teaching Nano:

For which teachers received UVA credits

With ongoing follow-up activities

Addressed by Multiscale Modeling:

Coupling weak and strong quantum correlation (wires vs. dots):

Density Functional Theory (Si) / Extended Hückel (molecules)

Within framework of Non-Equilibrium Green's Functions

Applied to molecular SURFETs data:

Successfully modeling observed threshold shifts as:

Vasudevan et al, IEEE-Sens. ’08 and Cond-Mat ‘08

Validated modeling techniques then applied to our CNT RTS data

QuickTime™ and a decompressor

are needed to see this picture.

Aluminum channel side gates with 92 nm gap

50 nm wide silicon on insulator channel

29 nm wide silicon on insulator channel

Tour et al (JACS 2006)

J.Chan et al, in review

Acetylene / Si

Thermal Oxide / Si

Native Oxide / Si

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