NN EQU 1234H ; a sixteen bit numberN EQU 56H ; an eight bit number

NOP ; 00 LD BC,NN ; 01 XX XX LD (BC),A ; 02 INC BC ; 03 INC B ; 04 DEC B ; 05 LD B,N ; 06 XX RLCA ; 07 EX AF,AF' ; 08 ADD HL,BC ; 09 LD A,(BC) ; 0A DEC BC ; 0B INC C ; 0C DEC C ; 0D LD C,N ; 0E XX RRCA ; 0F DJNZ $+2 ; 10 LD DE,NN ; 11 XX XX LD (DE),A ; 12 INC DE ; 13 INC D ; 14 DEC D ; 15 LD D,N ; 16 XX RLA ; 17 JR $+2 ; 18 ADD HL,DE ; 19 LD A,(DE) ; 1A DEC DE ; 1B INC E ; 1C DEC E ; 1D LD E,N ; 1E XX RRA ; 1F JR NZ,$+2 ; 20 LD HL,NN ; 21 XX XX LD (NN),HL ; 22 XX XX INC HL ; 23 INC H ; 24 DEC H ; 25 LD H,N ; 26 XX DAA ; 27 JR Z,$+2 ; 28 ADD HL,HL ; 29 LD HL,(NN) ; 2A XX XX DEC HL ; 2B INC L ; 2C DEC L ; 2D LD L,N ; 2E XX CPL ; 2F JR NC,$+2 ; 30 LD SP,NN ; 31 XX XX LD (NN),A ; 32 XX XX INC SP ; 33 INC (HL) ; 34 DEC (HL) ; 35

LD (HL),N ; 36 XX SCF ; 37 JR C,$+2 ; 38 ADD HL,SP ; 39 LD A,(NN) ; 3A XX XX DEC SP ; 3B INC A ; 3C DEC A ; 3D LD A,N ; 3E XX CCF ; 3F LD B,B ; 40 LD B,C ; 41 LD B,D ; 42 LD B,E ; 43 LD B,H ; 44 LD B,L ; 45 LD B,(HL) ; 46 LD B,A ; 47 LD C,B ; 48 LD C,C ; 49 LD C,D ; 4A LD C,E ; 4B LD C,H ; 4C LD C,L ; 4D LD C,(HL) ; 4E LD C,A ; 4F LD D,B ; 50 LD D,C ; 51 LD D,D ; 52 LD D,E ; 53 LD D,H ; 54 LD D,L ; 55 LD D,(HL) ; 56 LD D,A ; 57 LD E,B ; 58 LD E,C ; 59 LD E,D ; 5A LD E,E ; 5B LD E,H ; 5C LD E,L ; 5D LD E,(HL) ; 5E LD E,A ; 5F LD H,B ; 60 LD H,C ; 61 LD H,D ; 62 LD H,E ; 63 LD H,H ; 64 LD H,L ; 65 LD H,(HL) ; 66 LD H,A ; 67 LD L,B ; 68 LD L,C ; 69 LD L,D ; 6A LD L,E ; 6B LD L,H ; 6C LD L,L ; 6D LD L,(HL) ; 6E

LD L,A ; 6F LD (HL),B ; 70 LD (HL),C ; 71 LD (HL),D ; 72 LD (HL),E ; 73 LD (HL),H ; 74 LD (HL),L ; 75 HALT ; 76 LD (HL),A ; 77 LD A,B ; 78 LD A,C ; 79 LD A,D ; 7A LD A,E ; 7B LD A,H ; 7C LD A,L ; 7D LD A,(HL) ; 7E LD A,A ; 7F ADD A,B ; 80 ADD A,C ; 81 ADD A,D ; 82 ADD A,E ; 83 ADD A,H ; 84 ADD A,L ; 85 ADD A,(HL) ; 86 ADD A,A ; 87 ADC A,B ; 88 ADC A,C ; 89 ADC A,D ; 8A ADC A,E ; 8B ADC A,H ; 8C ADC A,L ; 8D ADC A,(HL) ; 8E ADC A,A ; 8F SUB B ; 90 SUB C ; 91 SUB D ; 92 SUB E ; 93 SUB H ; 94 SUB L ; 95 SUB (HL) ; 96 SUB A ; 97 SBC B ; 98 SBC C ; 99 SBC D ; 9A SBC E ; 9B SBC H ; 9C SBC L ; 9D SBC (HL) ; 9E SBC A ; 9F AND B ; A0 AND C ; A1 AND D ; A2 AND E ; A3 AND H ; A4 AND L ; A5 AND (HL) ; A6 AND A ; A7

XOR B ; A8 XOR C ; A9 XOR D ; AA XOR E ; AB XOR H ; AC XOR L ; AD XOR (HL) ; AE XOR A ; AF OR B ; B0 OR C ; B1 OR D ; B2 OR E ; B3 OR H ; B4 OR L ; B5 OR (HL) ; B6 OR A ; B7 CP B ; B8 CP C ; B9 CP D ; BA CP E ; BB CP H ; BC CP L ; BD CP (HL) ; BE CP A ; BF RET NZ ; C0 POP BC ; C1 JP NZ,$+3 ; C2 JP $+3 ; C3 CALL NZ,NN ; C4 XX XX PUSH BC ; C5 ADD A,N ; C6 XX RST 0 ; C7 RET Z ; C8 RET ; C9 JP Z,$+3 ; CA RLC B ; CB 00 RLC C ; CB 01 RLC D ; CB 02 RLC E ; CB 03 RLC H ; CB 04 RLC L ; CB 05 RLC (HL) ; CB 06 RLC A ; CB 07 RRC B ; CB 08 RRC C ; CB 09 RRC D ; CB 0A RRC E ; CB 0B RRC H ; CB 0C RRC L ; CB 0D RRC (HL) ; CB 0E RRC A ; CB 0F RL B ; CB 10 RL C ; CB 11 RL D ; CB 12 RL E ; CB 13 RL H ; CB 14 RL L ; CB 15

RL (HL) ; CB 16 RL A ; CB 17 RR B ; CB 18 RR C ; CB 19 RR D ; CB 1A RR E ; CB 1B RR H ; CB 1C RR L ; CB 1D RR (HL) ; CB 1E RR A ; CB 1F SLA B ; CB 20 SLA C ; CB 21 SLA D ; CB 22 SLA E ; CB 23 SLA H ; CB 24 SLA L ; CB 25 SLA (HL) ; CB 26 SLA A ; CB 27 SRA B ; CB 28 SRA C ; CB 29 SRA D ; CB 2A SRA E ; CB 2B SRA H ; CB 2C SRA L ; CB 2D SRA (HL) ; CB 2E SRA A ; CB 2F SRL B ; CB 38 SRL C ; CB 39 SRL D ; CB 3A SRL E ; CB 3B SRL H ; CB 3C SRL L ; CB 3D SRL (HL) ; CB 3E SRL A ; CB 3F BIT 0,B ; CB 40 BIT 0,C ; CB 41 BIT 0,D ; CB 42 BIT 0,E ; CB 43 BIT 0,H ; CB 44 BIT 0,L ; CB 45 BIT 0,(HL) ; CB 46 BIT 0,A ; CB 47 BIT 1,B ; CB 48 BIT 1,C ; CB 49 BIT 1,D ; CB 4A BIT 1,E ; CB 4B BIT 1,H ; CB 4C BIT 1,L ; CB 4D BIT 1,(HL) ; CB 4E BIT 1,A ; CB 4F BIT 2,B ; CB 50 BIT 2,C ; CB 51 BIT 2,D ; CB 52 BIT 2,E ; CB 53 BIT 2,H ; CB 54 BIT 2,L ; CB 55 BIT 2,(HL) ; CB 56

BIT 2,A ; CB 57 BIT 3,B ; CB 58 BIT 3,C ; CB 59 BIT 3,D ; CB 5A BIT 3,E ; CB 5B BIT 3,H ; CB 5C BIT 3,L ; CB 5D BIT 3,(HL) ; CB 5E BIT 3,A ; CB 5F BIT 4,B ; CB 60 BIT 4,C ; CB 61 BIT 4,D ; CB 62 BIT 4,E ; CB 63 BIT 4,H ; CB 64 BIT 4,L ; CB 65 BIT 4,(HL) ; CB 66 BIT 4,A ; CB 67 BIT 5,B ; CB 68 BIT 5,C ; CB 69 BIT 5,D ; CB 6A BIT 5,E ; CB 6B BIT 5,H ; CB 6C BIT 5,L ; CB 6D BIT 5,(HL) ; CB 6E BIT 5,A ; CB 6F BIT 6,B ; CB 70 BIT 6,C ; CB 71 BIT 6,D ; CB 72 BIT 6,E ; CB 73 BIT 6,H ; CB 74 BIT 6,L ; CB 75 BIT 6,(HL) ; CB 76 BIT 6,A ; CB 77 BIT 7,B ; CB 78 BIT 7,C ; CB 79 BIT 7,D ; CB 7A BIT 7,E ; CB 7B BIT 7,H ; CB 7C BIT 7,L ; CB 7D BIT 7,(HL) ; CB 7E BIT 7,A ; CB 7F RES 0,B ; CB 80 RES 0,C ; CB 81 RES 0,D ; CB 82 RES 0,E ; CB 83 RES 0,H ; CB 84 RES 0,L ; CB 85 RES 0,(HL) ; CB 86 RES 0,A ; CB 87 RES 1,B ; CB 88 RES 1,C ; CB 89 RES 1,D ; CB 8A RES 1,E ; CB 8B RES 1,H ; CB 8C RES 1,L ; CB 8D RES 1,(HL) ; CB 8E RES 1,A ; CB 8F

RES 2,B ; CB 90 RES 2,C ; CB 91 RES 2,D ; CB 92 RES 2,E ; CB 93 RES 2,H ; CB 94 RES 2,L ; CB 95 RES 2,(HL) ; CB 96 RES 2,A ; CB 97 RES 3,B ; CB 98 RES 3,C ; CB 99 RES 3,D ; CB 9A RES 3,E ; CB 9B RES 3,H ; CB 9C RES 3,L ; CB 9D RES 3,(HL) ; CB 9E RES 3,A ; CB 9F RES 4,B ; CB A0 RES 4,C ; CB A1 RES 4,D ; CB A2 RES 4,E ; CB A3 RES 4,H ; CB A4 RES 4,L ; CB A5 RES 4,(HL) ; CB A6 RES 4,A ; CB A7 RES 5,B ; CB A8 RES 5,C ; CB A9 RES 5,D ; CB AA RES 5,E ; CB AB RES 5,H ; CB AC RES 5,L ; CB AD RES 5,(HL) ; CB AE RES 5,A ; CB AF RES 6,B ; CB B0 RES 6,C ; CB B1 RES 6,D ; CB B2 RES 6,E ; CB B3 RES 6,H ; CB B4 RES 6,L ; CB B5 RES 6,(HL) ; CB B6 RES 6,A ; CB B7 RES 7,B ; CB B8 RES 7,C ; CB B9 RES 7,D ; CB BA RES 7,E ; CB BB RES 7,H ; CB BC RES 7,L ; CB BD RES 7,(HL) ; CB BE RES 7,A ; CB BF SET 0,B ; CB C0 SET 0,C ; CB C1 SET 0,D ; CB C2 SET 0,E ; CB C3 SET 0,H ; CB C4 SET 0,L ; CB C5 SET 0,(HL) ; CB C6 SET 0,A ; CB C7 SET 1,B ; CB C8

SET 1,C ; CB C9 SET 1,D ; CB CA SET 1,E ; CB CB SET 1,H ; CB CC SET 1,L ; CB CD SET 1,(HL) ; CB CE SET 1,A ; CB CF SET 2,B ; CB D0 SET 2,C ; CB D1 SET 2,D ; CB D2 SET 2,E ; CB D3 SET 2,H ; CB D4 SET 2,L ; CB D5 SET 2,(HL) ; CB D6 SET 2,A ; CB D7 SET 3,B ; CB D8 SET 3,C ; CB D9 SET 3,D ; CB DA SET 3,E ; CB DB SET 3,H ; CB DC SET 3,L ; CB DD SET 3,(HL) ; CB DE SET 3,A ; CB DF SET 4,B ; CB E0 SET 4,C ; CB E1 SET 4,D ; CB E2 SET 4,E ; CB E3 SET 4,H ; CB E4 SET 4,L ; CB E5 SET 4,(HL) ; CB E6 SET 4,A ; CB E7 SET 5,B ; CB E8 SET 5,C ; CB E9 SET 5,D ; CB EA SET 5,E ; CB EB SET 5,H ; CB EC SET 5,L ; CB ED SET 5,(HL) ; CB EE SET 5,A ; CB EF SET 6,B ; CB F0 SET 6,C ; CB F1 SET 6,D ; CB F2 SET 6,E ; CB F3 SET 6,H ; CB F4 SET 6,L ; CB F5 SET 6,(HL) ; CB F6 SET 6,A ; CB F7 SET 7,B ; CB F8 SET 7,C ; CB F9 SET 7,D ; CB FA SET 7,E ; CB FB SET 7,H ; CB FC SET 7,L ; CB FD SET 7,(HL) ; CB FE SET 7,A ; CB FF CALL Z,NN ; CC XX XX CALL NN ; CD XX XX

ADC A,N ; CE XX RST 8H ; CF RET NC ; D0 POP DE ; D1 JP NC,$+3 ; D2 OUT (N),A ; D3 XX CALL NC,NN ; D4 XX XX CALL NC,NN ; D4 XX XX PUSH DE ; D5 SUB N ; D6 XX RST 10H ; D7 RET C ; D8 EXX ; D9 JP C,$+3 ; DA IN A,(N) ; DB XX CALL C,NN ; DC XX XX ADD IX,BC ; DD 09 ADD IX,DE ; DD 19 LD IX,NN ; DD 21 XX XX LD (NN),IX ; DD 22 XX XX INC IX ; DD 23 ADD IX,IX ; DD 29 LD IX,(NN) ; DD 2A XX XX DEC IX ; DD 2B INC (IX+N) ; DD 34 XX DEC (IX+N) ; DD 35 XX LD (IX+N),N ; DD 36 XX XX ADD IX,SP ; DD 39 LD B,(IX+N) ; DD 46 XX LD C,(IX+N) ; DD 4E XX LD D,(IX+N) ; DD 56 XX LD E,(IX+N) ; DD 5E XX LD H,(IX+N) ; DD 66 XX LD L,(IX+N) ; DD 6E XX LD (IX+N),B ; DD 70 XX LD (IX+N),C ; DD 71 XX LD (IX+N),D ; DD 72 XX LD (IX+N),E ; DD 73 XX LD (IX+N),H ; DD 74 XX LD (IX+N),L ; DD 75 XX LD (IX+N),A ; DD 77 XX LD A,(IX+N) ; DD 7E XX ADD A,(IX+N) ; DD 86 XX ADC A,(IX+N) ; DD 8E XX SUB (IX+N) ; DD 96 XX SBC A,(IX+N) ; DD 9E XX AND (IX+N) ; DD A6 XX XOR (IX+N) ; DD AE XX OR (IX+N) ; DD B6 XX CP (IX+N) ; DD BE XX RLC (IX+N) ; DD CB XX 06 RRC (IX+N) ; DD CB XX 0E RL (IX+N) ; DD CB XX 16 RR (IX+N) ; DD CB XX 1E SLA (IX+N) ; DD CB XX 26 SRA (IX+N) ; DD CB XX 2E BIT 0,(IX+N) ; DD CB XX 46

BIT 1,(IX+N) ; DD CB XX 4E BIT 2,(IX+N) ; DD CB XX 56 BIT 3,(IX+N) ; DD CB XX 5E BIT 4,(IX+N) ; DD CB XX 66 BIT 5,(IX+N) ; DD CB XX 6E BIT 6,(IX+N) ; DD CB XX 76 BIT 7,(IX+N) ; DD CB XX 7E RES 0,(IX+N) ; DD CB XX 86 RES 1,(IX+N) ; DD CB XX 8E RES 2,(IX+N) ; DD CB XX 96 RES 3,(IX+N) ; DD CB XX 9E RES 4,(IX+N) ; DD CB XX A6 RES 5,(IX+N) ; DD CB XX AE RES 6,(IX+N) ; DD CB XX B6 RES 7,(IX+N) ; DD CB XX BE SET 0,(IX+N) ; DD CB XX C6 SET 1,(IX+N) ; DD CB XX CE SET 2,(IX+N) ; DD CB XX D6 SET 3,(IX+N) ; DD CB XX DE SET 4,(IX+N) ; DD CB XX E6 SET 5,(IX+N) ; DD CB XX EE SET 6,(IX+N) ; DD CB XX F6 SET 7,(IX+N) ; DD CB XX FE POP IX ; DD E1 EX (SP),IX ; DD E3 PUSH IX ; DD E5 JP (IX) ; DD E9 LD SP,IX ; DD F9 SBC A,N ; DE XX RST 18H ; DF RET PO ; E0 POP HL ; E1 JP PO,$+3 ; E2 EX (SP),HL ; E3 CALL PO,NN ; E4 XX XX PUSH HL ; E5 AND N ; E6 XX RST 20H ; E7 RET PE ; E8 JP (HL) ; E9 JP PE,$+3 ; EA EX DE,HL ; EB CALL PE,NN ; EC XX XX IN B,(C) ; ED 40 OUT (C),B ; ED 41 SBC HL,BC ; ED 42 LD (NN),BC ; ED 43 XX XX NEG ; ED 44 RETN ; ED 45 IM 0 ; ED 46 LD I,A ; ED 47 IN C,(C) ; ED 48 OUT (C),C ; ED 49 ADC HL,BC ; ED 4A LD BC,(NN) ; ED 4B XX XX RETI ; ED 4D IN D,(C) ; ED 50

OUT (C),D ; ED 51 SBC HL,DE ; ED 52 LD (NN),DE ; ED 53 XX XX IM 1 ; ED 56 LD A,I ; ED 57 IN E,(C) ; ED 58 OUT (C),E ; ED 59 ADC HL,DE ; ED 5A LD DE,(NN) ; ED 5B XX XX IM 2 ; ED 5E IN H,(C) ; ED 60 OUT (C),H ; ED 61 SBC HL,HL ; ED 62 RRD ; ED 67 IN L,(C) ; ED 68 OUT (C),L ; ED 69 ADC HL,HL ; ED 6A RLD ; ED 6F SBC HL,SP ; ED 72 LD (NN),SP ; ED 73 XX XX IN A,(C) ; ED 78 OUT (C),A ; ED 79 ADC HL,SP ; ED 7A LD SP,(NN) ; ED 7B XX XX LDI ; ED A0 CPI ; ED A1 INI ; ED A2 OUTI ; ED A3 LDD ; ED A8 CPD ; ED A9 IND ; ED AA OUTD ; ED AB LDIR ; ED B0 CPIR ; ED B1 INIR ; ED B2 OTIR ; ED B3 LDDR ; ED B8 CPDR ; ED B9 INDR ; ED BA OTDR ; ED BB XOR N ; EE XX RST 28H ; EF RET P ; F0 POP AF ; F1 JP P,$+3 ; F2 DI ; F3 CALL P,NN ; F4 XX XX PUSH AF ; F5 OR N ; F6 XX RST 30H ; F7 RET M ; F8 LD SP,HL ; F9 JP M,$+3 ; FA EI ; FB CALL M,NN ; FC XX XX ADD IY,BC ; FD 09 ADD IY,DE ; FD 19

LD IY,NN ; FD 21 XX XX LD (NN),IY ; FD 22 XX XX INC IY ; FD 23 ADD IY,IY ; FD 29 LD IY,(NN) ; FD 2A XX XX DEC IY ; FD 2B INC (IY+N) ; FD 34 XX DEC (IY+N) ; FD 35 XX LD (IY+N),N ; FD 36 XX XX ADD IY,SP ; FD 39 LD B,(IY+N) ; FD 46 XX LD C,(IY+N) ; FD 4E XX LD D,(IY+N) ; FD 56 XX LD E,(IY+N) ; FD 5E XX LD H,(IY+N) ; FD 66 XX LD L,(IY+N) ; FD 6E XX LD (IY+N),B ; FD 70 XX LD (IY+N),C ; FD 71 XX LD (IY+N),D ; FD 72 XX LD (IY+N),E ; FD 73 XX LD (IY+N),H ; FD 74 XX LD (IY+N),L ; FD 75 XX LD (IY+N),A ; FD 77 XX LD A,(IY+N) ; FD 7E XX ADD A,(IY+N) ; FD 86 XX ADC A,(IY+N) ; FD 8E XX SUB (IY+N) ; FD 96 XX SBC A,(IY+N) ; FD 9E XX AND (IY+N) ; FD A6 XX XOR (IY+N) ; FD AE XX OR (IY+N) ; FD B6 XX CP (IY+N) ; FD BE XX RLC (IY+N) ; FD CB XX 06 RRC (IY+N) ; FD CB XX 0E RL (IY+N) ; FD CB XX 16 RR (IY+N) ; FD CB XX 1E SLA (IY+N) ; FD CB XX 26 SRA (IY+N) ; FD CB XX 2E BIT 0,(IY+N) ; FD CB XX 46 BIT 1,(IY+N) ; FD CB XX 4E BIT 2,(IY+N) ; FD CB XX 56 BIT 3,(IY+N) ; FD CB XX 5E BIT 4,(IY+N) ; FD CB XX 66 BIT 5,(IY+N) ; FD CB XX 6E BIT 6,(IY+N) ; FD CB XX 76 BIT 7,(IY+N) ; FD CB XX 7E RES 0,(IY+N) ; FD CB XX 86 RES 1,(IY+N) ; FD CB XX 8E RES 2,(IY+N) ; FD CB XX 96 RES 3,(IY+N) ; FD CB XX 9E RES 4,(IY+N) ; FD CB XX A6 RES 5,(IY+N) ; FD CB XX AE RES 6,(IY+N) ; FD CB XX B6 RES 7,(IY+N) ; FD CB XX BE SET 0,(IY+N) ; FD CB XX C6 SET 1,(IY+N) ; FD CB XX CE SET 2,(IY+N) ; FD CB XX D6

SET 3,(IY+N) ; FD CB XX DE SET 4,(IY+N) ; FD CB XX E6 SET 5,(IY+N) ; FD CB XX EE SET 6,(IY+N) ; FD CB XX F6 SET 7,(IY+N) ; FD CB XX FE POP IY ; FD E1 EX (SP),IY ; FD E3 PUSH IY ; FD E5 JP (IY) ; FD E9 LD SP,IY ; FD F9 CP N ; FE XX RST 38H ; FF

Z80 Hardware Reference---------------------------------------------------------------------------Contents

* Registers * Addressing methods * Flags * Symbol descriptions * Instructions---------------------------------------------------------------------------Registers

The following registers are available:

A,B,C,D,E 8-bit registersAF 16-bit register containing A and flagsBC 16-bit register containing B and CDE 16-bit register containing D and EHL 16-bit register used for addressingF 8-bit Flag registerI 8-bit Interrupt Page address registerIX,IY 16-bit index registersPC 16-bit Program Counter registerR 8-bit Memory Refresh registerSP 16-bit Stack Pointer register

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Addressing methods

The following addressing methods are available:

Mnemonic Descriptionn Immediate addressing (8-bit)nn Immediate extending addressing (16-bit)e Relative addressing (8-bit; PC=PC+2+offset)[nn] Extended addressing (16-bit)[xx+d] Indexed addressing (16-bit + 8-bit)r Register addressing (8-bit)[rr] Register indirect addressing (16-bit)b Bit addressingp Modified page 0 addressing

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Flags

The following flags are available:

S Sign flag (bit 7)Z Zero flag (bit 6)H Half Carry flag (bit 4)P Parity/Overflow flag (bit 2)N Add/Subtract flag (bit 1)C Carry flag (bit 0)

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Symbol descriptions

Here is a short description of the symbols that are used in the instructionlist:

b One bit (0 to 7)cc Condition (C,M,NC,NZ,P,PE,PO,Z)d One-byte expression (-128 to +127)dst Destination s, ss, [BC], [DE], [HL], [nn]e One-byte expression (-126 to +129)m Any register r, [HL] or [xx+d]n One-byte expression (0 to 255)nn Two-byte expression (0 to 65535)pp Register pair BC, DE, IX or SPqq Register pair AF, BC, DE or HLqq' Alternative register pair AF, BC, DE or HLr Register A, B, C, D, E, H or Lrr Register pair BC, DE, IY or SPs Any register r, value n, [HL] or [xx+d]src Source s, ss, [BC], [DE], [HL], nn, [nn]ss Register pair BC, DE, HL or SPxx Index register IX or IY

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Instructions

The flag field contains one of the following:

- Flag unaffected* Flag affected0 Flag reset1 Flag set? Unknown

The following instructions are available:

Mnemonic Flags Description Notes SZHPNC

ADC A,s ***V0* Add with Carry A=A+s+CYADC HL,ss **?V0* Add with Carry HL=HL+ss+CYADD A,s ***V0* Add A=A+sADD HL,ss --?-0* Add HL=HL+ssADD IX,pp --?-0* Add IX=IX+ppADD IY,rr --?-0* Add IY=IY+rrAND s ***P00 Logical AND A=A&sBIT b,m ?*1?0- Test Bit m&{2^b}CALL cc,nn ------ Conditional Call If cc CALLCALL nn ------ Unconditional Call -[SP]=PC,PC=nnCCF --?-0* Complement Carry Flag CY=~CYCP s ***V1* Compare A-sCPD ****1- Compare and Decrement A-[HL],HL=HL-1,BC=BC-1CPDR ****1- Compare, Dec., Repeat CPD till A=[HL]or BC=0CPI ****1- Compare and Increment A-[HL],HL=HL+1,BC=BC-1CPIR ****1- Compare, Inc., Repeat CPI till A=[HL]or BC=0CPL --1-1- Complement A=~A

DAA ***P-* Decimal Adjust Acc. A=BCD formatDEC s ***V1- Decrement s=s-1DEC xx ------ Decrement xx=xx-1DEC ss ------ Decrement ss=ss-1DI ------ Disable InterruptsDJNZ e ------ Dec., Jump Non-Zero B=B-1 till B=0EI ------ Enable InterruptsEX [SP],HL ------ Exchange [SP]<->HLEX [SP],xx ------ Exchange [SP]<->xxEX AF,AF' ------ Exchange AF<->AF'EX DE,HL ------ Exchange DE<->HLEXX ------ Exchange qq<->qq' (except AF)HALT ------ HaltIM n ------ Interrupt Mode (n=0,1,2)IN A,[n] ------ Input A=[n]IN r,[C] ***P0- Input r=[C]INC r ***V0- Increment r=r+1INC [HL] ***V0- Increment [HL]=[HL]+1INC xx ------ Increment xx=xx+1INC [xx+d] ***V0- Increment [xx+d]=[xx+d]+1INC ss ------ Increment ss=ss+1IND ?*??1- Input and Decrement [HL]=[C],HL=HL-1,B=B-1INDR ?1??1- Input, Dec., Repeat IND till B=0INI ?*??1- Input and Increment [HL]=[C],HL=HL+1,B=B-1INIR ?1??1- Input, Inc., Repeat INI till B=0JP [HL] ------ Unconditional Jump PC=[HL]JP [xx] ------ Unconditional Jump PC=[xx]JP nn ------ Unconditional Jump PC=nnJP cc,nn ------ Conditional Jump If cc JPJR e ------ Unconditional Jump PC=PC+eJR cc,e ------ Conditional Jump If cc JR(cc=C,NC,NZ,Z)LD dst,src ------ Load dst=srcLD A,i **0*0- Load A=i (i=I,R)LDD --0*0- Load and Decrement [DE]=[HL],HL=HL-1,#LDDR --000- Load, Dec., Repeat LDD till BC=0LDI --0*0- Load and Increment [DE]=[HL],HL=HL+1,#LDIR --000- Load, Inc., Repeat LDI till BC=0NEG ***V1* Negate A=-ANOP ------ No OperationOR s ***P00 Logical inclusive OR A=AvsOTDR ?1??1- Output, Dec., Repeat OUTD till B=0OTIR ?1??1- Output, Inc., Repeat OUTI till B=0OUT [C],r ------ Output [C]=rOUT [n],A ------ Output [n]=AOUTD ?*??1- Output and Decrement [C]=[HL],HL=HL-1,B=B-1OUTI ?*??1- Output and Increment [C]=[HL],HL=HL+1,B=B-1POP xx ------ Pop xx=[SP]+POP qq ------ Pop qq=[SP]+PUSH xx ------ Push -[SP]=xxPUSH qq ------ Push -[SP]=qqRES b,m ------ Reset bit m=m&{~2^b}RET ------ Return PC=[SP]+RET cc ------ Conditional Return If cc RETRETI ------ Return from Interrupt PC=[SP]+RETN ------ Return from NMI PC=[SP]+RL m **0P0* Rotate Left m={CY,m}<-RLA --0-0* Rotate Left Acc. A={CY,A}<-

RLC m **0P0* Rotate Left Circular m=m<-RLCA --0-0* Rotate Left Circular A=A<-RLD **0P0- Rotate Left 4 bits {A,[HL]}={A,[HL]}<- ##RR m **0P0* Rotate Right m=->{CY,m}RRA --0-0* Rotate Right Acc. A=->{CY,A}RRC m **0P0* Rotate Right Circular m=->mRRCA --0-0* Rotate Right Circular A=->ARRD **0P0- Rotate Right 4 bits {A,[HL]}=->{A,[HL]} ##RST p ------ Restart (p=0H,8H,10H,...,38H)SBC A,s ***V1* Subtract with Carry A=A-s-CYSBC HL,ss **?V1* Subtract with Carry HL=HL-ss-CYSCF --0-01 Set Carry Flag CY=1SET b,m ------ Set bit m=mv{2^b}SLA m **0P0* Shift Left Arithmetic m=m*2SRA m **0P0* Shift Right Arith. m=m/2SRL m **0P0* Shift Right Logical m=->{0,m,CY}SUB s ***V1* Subtract A=A-sXOR s ***P00 Logical Exclusive OR A=Axs

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Z80 CPU Instruction Set

Mnemonic T-states Explanation

ADC A,r 4 Add with carry register r to accumulator.ADC A,n 7 Add with carry value n to accumulator.ADC A,(HL) 7 Add with carry location (HL) to acccumulator.ADC A,(IX+d) 19 Add with carry location (IX+d) to accumulator.ADC A,(IY+d) 19 Add with carry location (IY+d) to accumulator.

ADC HL,BC 15 Add with carry register pair BC to HL.ADC HL,DE 15 Add with carry register pair DE to HL.ADC HL,HL 15 Add with carry register pair HL to HL.ADC HL,SP 15 Add with carry register pair SP to HL.

ADD A,r 4 Add register r to accumulator.ADD A,n 7 Add value n to accumulator.ADD A,(HL) 7 Add location (HL) to acccumulator.ADD A,(IX+d) 19 Add location (IX+d) to accumulator.ADD A,(IY+d) 19 Add location (IY+d) to accumulator.

ADD HL,BC 11 Add register pair BC to HL.ADD HL,DE 11 Add register pair DE to HL.ADD HL,HL 11 Add register pair HL to HL.ADD HL,SP 11 Add register pair SP to HL.

ADD IX,BC 15 Add register pair BC to IX.ADD IX,DE 15 Add register pair DE to IX.ADD IX,IX 15 Add register pair IX to IX.ADD IX,SP 15 Add register pair SP to IX.

ADD IY,BC 15 Add register pair BC to IY.ADD IY,DE 15 Add register pair DE to IY.ADD IY,IY 15 Add register pair IY to IY.ADD IY,SP 15 Add register pair SP to IY.

AND r 4 Logical AND of register r to accumulator.AND n 7 Logical AND of value n to accumulator.AND (HL) 7 Logical AND of value at location (HL) to accumulator.AND (IX+d) 19 Logical AND of value at location (IX+d) to accumulator.AND (IY+d) 19 Logical AND of value at location (IY+d) to accumulator.

BIT b,(HL) 12 Test bit b of location (HL).BIT b,(IX+d) 20 Test bit b of location (IX+d).BIT b,(IY+d) 20 Test bit b of location (IY+d).BIT b,r 8 Test bit b of register r.CALL nn 17 Call subroutine at location.CALL cc,nn 17,10 Call subroutine at location nn if condition CC is true.CCF 4 Complement carry flag.

CP r 4 Compare register r with accumulator.CP n 7 Compare value n with accumulator.CP (HL) 7 Compare value at location (HL) with accumulator.CP (IX+d) 19 Compare value at location (IX+d) with accumulator.CP (IY+d) 19 Compare value at location (IY+d) with accumulator.

CPD 16 Comapre location (HL) and acc., decrement HL and BC,CPDR 21,16 Perform a CPD and repeat until BC=0.CPI 16 Compare location (HL) and acc., incr HL, decr BC.CPIR 21,16 Perform a CPI and repeat until BC=0.CPL 4 Complement accumulator (1's complement).DAA 4 Decimal adjust accumulator.

DEC r 4 Decrement register r.DEC (HL) 11 Decrement value at location (HL).DEC (IX+d) 23 Decrement value at location (IX+d).DEC (IY+d) 23 Decrement value at location (IY+d).

DEC IX 10 Decrement IX.DEC IY 10 Decrement IY.DEC BC 6 Decrement register pair BC.DEC DE 6 Decrement register pair DE.DEC HL 6 Decrement register pair HL.DEC SP 6 Decrement register pair SP.

DI 4 Disable interrupts. (except NMI at 0066h)

DJNZ n 13,8 Decrement B and jump relative if B<>0.

EI 4 Enable interrupts.EX (SP),HL 19 Exchange the location (SP) and HL.EX (SP),IX 23 Exchange the location (SP) and IX.EX (SP),IY 23 Exchange the location (SP) and IY.EX AF,AF' 4 Exchange the contents of AF and AF'.EX DE,HL 4 Exchange the contents of DE and HL.EXX 4 Exchange the contents of BC,DE,HL with BC',DE',HL'.HALT 4 Halt computer and wait for interrupt.IM 0 8 Set interrupt mode 0. (instruction on data bus by int device)IM 1 8 Set interrupt mode 1. (rst 38)IM 2 8 Set interrupt mode 2. (vector jump)

IN A,(n) 11 Load the accumulator with input from device n.IN r,(c) 12 Load the register r with input from device (C).

INC r 4 Increment register r.INC (HL) 11 Increment location (HL).INC (IX+d) 23 Increment location (IX+d).INC (IY+d) 23 Increment location (IY+d).

INC IX 10 Increment IX.INC IY 10 Increment IY.INC BC 6 Increment register pair BC.INC DE 6 Increment register pair DE.INC HL 6 Increment register pair HL.INC SP 6 Increment register pair SP.

IND 16 (HL)=Input from port (C). Decrement HL and B.INDR 21,16 Perform an IND and repeat until B=0.INI 16 (HL)=Input from port (C). HL=HL+1. B=B-1.INIR 21,16 Perform an INI and repeat until B=0.

JP nn 10 Unconditional jump to location nnJP cc,nn 10 Jump to location nn if condition cc is true.JP (HL) 4 Unconditional jump to location (HL).JP (IX) 8 Unconditional jump to location (IX).JP (IY) 8 Unconditional jump to location (IY).

JR C,n 12,7 Jump relative to PC+n if carry=1.JR n 12 Unconditional jump relative to PC+n.JR NC,n 12,7 Jump relative to PC+n if carry=0.JR NZ,n 12,7 Jump relative to PC+n if non zero (Z=0).JR Z,n 12,7 Jump relative to PC+n if zero (Z=1).

LD A,(BC) 7 Load accumulator with value at location (BC).LD A,(DE) 7 Load accumulator with value at location (DE).LD A,I 9 Load accumulator with I.(interrupt vector register)LD A,(nn) 13 Load accumulator with value at location nn.LD A,R 9 Load accumulator with R.(memory refresh register)LD (BC),A 7 Load location (BC) with accumulator.LD (DE),A 7 Load location (DE) with accumulator.LD (HL),n 10 Load location (HL) with value n.LD (IX+d),n 19 Load location (IX+d) with value n.LD (IY+d),n 19 Load location (IY+d) with value n.LD (nn),A 13 Load location (nn) with accumulator.

LD (nn),BC 20 Load location (nn) with register pair BC.LD (nn),DE 20 Load location (nn) with register pair DE.LD (nn),HL 16 Load location (nn) with HL.LD (nn),SP 20 Load location (nn) with register pair SP.

LD (nn),IX 20 Load location (nn) with IX.LD (nn),IY 20 Load location (nn) with IY.

LD BC,nn 10 Load register pair BC with nn.LD DE,nn 10 Load register pair DE with nn.LD HL,nn 10 Load register pair HL with nn.LD SP,nn 10 Load register pair SP with nn.

LD BC,(nn) 20 Load register pair BC with value at location (nn).LD DE,(nn) 20 Load register pair DE with value at location (nn).LD HL,(nn) 16 Load HL with value at location (nn). (L-first)LD SP,(nn) 20 Load register pair SP with value at location (nn).

LD (HL),r 7 Load location (HL) with register r.LD (IX+d),r 19 Load location (IX+d) with register r.LD (IY+d),r 19 Load location (IY+d) with register r.LD I,A 9 Load I with accumulator.LD IX,nn 14 Load IX with value nn.LD IX,(nn) 20 Load IX with value at location (nn).LD IY,nn 14 Load IY with value nn.LD IY,(nn) 20 Load IY with value at location (nn).LD R,A 9 Load R with accumulator.LD r,(HL) 7 Load register r with value at location (HL).LD r,(IX+d) 19 Load register r with value at location (IX+d).LD r,(IY+d) 19 Load register r with value at location (IY+d).LD r,n 7 Load register r with value n.LD r,r' 4 Load register r with register r'.

LD SP,HL 6 Load SP with HL.LD SP,IX 10 Load SP with IX.LD SP,IY 10 Load SP with IY.LDD 16 Load location (DE) with location (HL), decrement DE,HL,BC.LDDR 21,16 Perform an LDD and repeat until BC=0.LDI 16 Load location (DE) with location (HL), incr DE,HL; decr BC.LDIR 21,17 Perform an LDI and repeat until BC=0.NEG 8 Negate accumulator (2's complement).NOP 4 No operation.

OR r 4 Logical OR of register r and accumulator.OR n 7 Logical OR of value n and accumulator.OR (HL) 7 Logical OR of value at location (HL) and accumulator.OR (IX+d) 19 Logical OR of value at location (IX+d) and accumulator.OR (IY+d) 19 Logical OR of value at location (IY+d) and accumulator.

OTDR 21,16 Perform an OUTD and repeat until B=0.OTIR 21,16 Perform an OTI and repeat until B=0.OUT (C),r 12 Load output port (C) with register r.OUT (n),A 11 Load output port (n) with accumulator.OUTD 16 Load output port (C) with (HL), decrement HL and B.OUTI 16 Load output port (C) with (HL), incr HL, decr B.POP IX 14 Load IX with top of stack.POP IY 14 Load IY with top of stack.POP BC 10 Load register pair BC with top of stack.POP DE 10 Load register pair DE with top of stack.POP HL 10 Load register pair HL with top of stack.POP AF 10 Load register pair AF with top of stack.

PUSH IX 15 Load IX onto stack.PUSH IY 15 Load IY onto stack.PUSH BC 11 Load register pair BC onto stack.PUSH DE 11 Load register pair DE onto stack.PUSH HL 11 Load register pair HL onto stack.PUSH AF 11 Load register pair AF onto stack.

RES b,r 8 Reset bit b of register r.RES b,(HL) 15 Reset bit b in value at location (HL).RES b,(IX+d) 23 Reset bit b in value at location (IX+d).RES b,(IY+d) 23 Reset bit b in value at location (IY+d).

RET 10 Return from subroutine.RET cc 11,5 Return from subroutine if condition cc is true.RETI 14 Return from interrupt.RETN 14 Return from non-maskable interrupt.

RL r 8 Rotate left through register r.RL (HL) 15 Rotate left through value at location (HL).RL (IX+d) 23 Rotate left through value at location (IX+d).RL (IY+d) 23 Rotate left through value at location (IY+d).RLA 4 Rotate left accumulator through carry.

RLC (HL) 15 Rotate location (HL) left circular.RLC (IX+d) 23 Rotate location (IX+d) left circular.RLC (IY+d) 23 Rotate location (IY+d) left circular.RLC r 8 Rotate register r left circular.

RLCA 4 Rotate left circular accumulator.RLD 18 Rotate digit left and right between accumulator and (HL).

RR r 8 Rotate right through carry register r.RR (HL) 15 Rotate right through carry location (HL).RR (IX+d) 23 Rotate right through carry location (IX+d).RR (IY+d) 23 Rotate right through carry location (IY+d).

RRA 4 Rotate right accumulator through carry.

RRC r 8 Rotate register r right circular.RRC (HL) 15 Rotate value at location (HL) right circular.RRC (IX+d) 23 Rotate value at location (IX+d) right circular.RRC (IY+d) 23 Rotate value at location (HL+d) right circular.

RRCA 4 Rotate right circular accumulator.RRD 18 Rotate digit right and left between accumulator and (HL).

RST 00h 11 Restart to location 0000h.RST 08h 11 Restart to location 0008h.RST 10h 11 Restart to location 0010h.RST 18h 11 Restart to location 0018h.RST 20h 11 Restart to location 0020h.RST 28h 11 Restart to location 0028h.RST 30h 11 Restart to location 0030h.RST 38h 11 Restart to location 0038h.

SBC A,r 4 Subtract register r from accumulator with carry.SBC A,n 7 Subtract value n from accumulator with carry.SBC A,(HL) 7 Subtract value at location (HL) from accu. with carry.SBC A,(IX+d) 19 Subtract value at location (IX+d) from accu. with carry.SBC A,(IY+d) 19 Subtract value at location (IY+d) from accu. with carry.SBC HL,BC 15 Subtract register pair BC from HL with carry.SBC HL,DE 15 Subtract register pair DE from HL with carry.SBC HL,HL 15 Subtract register pair HL from HL with carry.SBC HL,SP 15 Subtract register pair SP from HL with carry.

SCF 4 Set carry flag (C=1).

SET b,r 8 Set bit b of register r.SET b,(HL) 15 Set bit b of location (HL).SET b,(IX+d) 23 Set bit b of location (IX+d).SET b,(IY+d) 23 Set bit b of location (IY+d).

SLA r 8 Shift register r left arithmetic.SLA (HL) 15 Shift value at location (HL) left arithmetic.SLA (IX+d) 23 Shift value at location (IX+d) left arithmetic.SLA (IY+d) 23 Shift value at location (IY+d) left arithmetic.

SRA r 8 Shift register r right arithmetic.SRA (HL) 15 Shift value at location (HL) right arithmetic.SRA (IX+d) 23 Shift value at location (IX+d) right arithmetic.SRA (IY+d) 23 Shift value at location (IY+d) right arithmetic.

SRL r 8 Shift register r right logical.SRL (HL) 15 Shift value at location (HL) right logical.SRL (IX+d) 23 Shift value at location (IX+d) right logical.

SRL (IY+d) 23 Shift value at location (IY+d) right logical.

SUB r 4 Subtract register r from accumulator.SUB n 7 Subtract value n from accumulator.SUB (HL) 7 Subtract location (HL) from accumulator.SUB (IX+d) 19 Subtract location (IX+d) from accumulator.SUB (IY+d) 19 Subtract location (IY+d) from accumulator.

XOR r 4 Exclusive OR register r and accumulator.XOR n 7 Exclusive OR value n and accumulator.XOR (HL) 7 Exclusive OR value at location (HL) and accumulator.XOR (IX+d) 19 Exclusive OR value at location (IX+d) and accumulator.XOR (IY+d) 19 Exclusive OR value at location (IY+d) and accumulator.

The flag register has the following structure:

Bit 7 6 5 4 3 2 1 0Flag S Z F5 H F3 P/V N C

The flags are set according to the result of the last instruction. The standard behaviour is:

S - Sign flag Set if the 2-complement value is negative (copy of MSB)

Z - Zero flag Set if the value is zero

F5 - undocumented flag Copy of bit 5

H - Half Carry Carry from bit 3 to bit 4

F3 - undocumented flag Copy of bit 3

P/V - Parity or Overflow Parity set if even number of bits set Overflow set if the 2-complement result does not fit in the register

N - Subtract Set if the last operation was a subtraction

C - Carry Set if the result did not fit in the register

Z80 MICROPROCESSOR Instruction Set Summary ----------------------------------------------------------------|Mnemonic |SZHPNC|Description |Notes ||----------+------+---------------------+----------------------||ADC A,s |***V0*|Add with Carry |A=A+s+CY ||ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY ||ADD A,s |***V0*|Add |A=A+s ||ADD HL,ss |--?-0*|Add |HL=HL+ss ||ADD IX,pp |--?-0*|Add |IX=IX+pp ||ADD IY,rr |--?-0*|Add |IY=IY+rr ||AND s |***P00|Logical AND |A=A&s ||BIT b,m |?*1?0-|Test Bit |m&{2^b} ||CALL cc,nn|------|Conditional Call |If cc CALL ||CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn ||CCF |--?-0*|Complement Carry Flag|CY=~CY ||CP s |***V1*|Compare |A-s ||CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1||CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0||CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1||CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0||CPL |--1-1-|Complement |A=~A ||DAA |***P-*|Decimal Adjust Acc. |A=BCD format ||DEC s |***V1-|Decrement |s=s-1 ||DEC xx |------|Decrement |xx=xx-1 ||DEC ss |------|Decrement |ss=ss-1 ||DI |------|Disable Interrupts | ||DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 ||EI |------|Enable Interrupts | ||EX [SP],HL|------|Exchange |[SP]<->HL ||EX [SP],xx|------|Exchange |[SP]<->xx ||EX AF,AF' |------|Exchange |AF<->AF' ||EX DE,HL |------|Exchange |DE<->HL ||EXX |------|Exchange |qq<->qq' (except AF)||HALT |------|Halt | ||IM n |------|Interrupt Mode | (n=0,1,2)||IN A,[n] |------|Input |A=[n] ||IN r,[C] |***P0-|Input |r=[C] ||INC r |***V0-|Increment |r=r+1 ||INC [HL] |***V0-|Increment |[HL]=[HL]+1 ||INC xx |------|Increment |xx=xx+1 ||INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 ||INC ss |------|Increment |ss=ss+1 ||IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1||INDR |?1??1-|Input, Dec., Repeat |IND till B=0 ||INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1||INIR |?1??1-|Input, Inc., Repeat |INI till B=0 ||JP [HL] |------|Unconditional Jump |PC=[HL] ||JP [xx] |------|Unconditional Jump |PC=[xx] ||JP nn |------|Unconditional Jump |PC=nn ||JP cc,nn |------|Conditional Jump |If cc JP ||JR e |------|Unconditional Jump |PC=PC+e ||JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)||LD dst,src|------|Load |dst=src ||LD A,i |**0*0-|Load |A=i (i=I,R)||LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# ||LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |

|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# ||LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 ||NEG |***V1*|Negate |A=-A ||NOP |------|No Operation | ||OR s |***P00|Logical inclusive OR |A=Avs ||OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 ||OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 ||OUT [C],r |------|Output |[C]=r ||OUT [n],A |------|Output |[n]=A ||OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1||OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1||POP xx |------|Pop |xx=[SP]+ ||POP qq |------|Pop |qq=[SP]+ ||PUSH xx |------|Push |-[SP]=xx ||PUSH qq |------|Push |-[SP]=qq ||RES b,m |------|Reset bit |m=m&{~2^b} ||RET |------|Return |PC=[SP]+ ||RET cc |------|Conditional Return |If cc RET ||RETI |------|Return from Interrupt|PC=[SP]+ ||RETN |------|Return from NMI |PC=[SP]+ ||RL m |**0P0*|Rotate Left |m={CY,m}<- ||RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- ||RLC m |**0P0*|Rotate Left Circular |m=m<- ||RLCA |--0-0*|Rotate Left Circular |A=A<- ||RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##||RR m |**0P0*|Rotate Right |m=->{CY,m} ||RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} ||RRC m |**0P0*|Rotate Right Circular|m=->m ||RRCA |--0-0*|Rotate Right Circular|A=->A ||RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##||RST p |------|Restart | (p=0H,8H,10H,...,38H)||SBC A,s |***V1*|Subtract with Carry |A=A-s-CY ||SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY ||SCF |--0-01|Set Carry Flag |CY=1 ||SET b,m |------|Set bit |m=mv{2^b} ||SLA m |**0P0*|Shift Left Arithmetic|m=m*2 ||SRA m |**0P0*|Shift Right Arith. |m=m/2 ||SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} ||SUB s |***V1*|Subtract |A=A-s ||XOR s |***P00|Logical Exclusive OR |A=Axs ||----------+------+--------------------------------------------|| F |-*01? |Flag unaffected/affected/reset/set/unknown || S |S |Sign flag (Bit 7) || Z | Z |Zero flag (Bit 6) || HC | H |Half Carry flag (Bit 4) || P/V | P |Parity/Overflow flag (Bit 2, V=overflow) || N | N |Add/Subtract flag (Bit 1) || CY | C|Carry flag (Bit 0) ||-----------------+--------------------------------------------|| n |Immediate addressing || nn |Immediate extended addressing || e |Relative addressing (PC=PC+2+offset) || [nn] |Extended addressing || [xx+d] |Indexed addressing || r |Register addressing || [rr] |Register indirect addressing || |Implied addressing |

| b |Bit addressing || p |Modified page zero addressing (see RST) ||-----------------+--------------------------------------------||DEFB n(,...) |Define Byte(s) ||DEFB 'str'(,...) |Define Byte ASCII string(s) ||DEFS nn |Define Storage Block ||DEFW nn(,...) |Define Word(s) ||-----------------+--------------------------------------------|| A B C D E |Registers (8-bit) || AF BC DE HL |Register pairs (16-bit) || F |Flag register (8-bit) || I |Interrupt page address register (8-bit) || IX IY |Index registers (16-bit) || PC |Program Counter register (16-bit) || R |Memory Refresh register || SP |Stack Pointer register (16-bit) ||-----------------+--------------------------------------------|| b |One bit (0 to 7) || cc |Condition (C,M,NC,NZ,P,PE,PO,Z) || d |One-byte expression (-128 to +127) || dst |Destination s, ss, [BC], [DE], [HL], [nn] || e |One-byte expression (-126 to +129) || m |Any register r, [HL] or [xx+d] || n |One-byte expression (0 to 255) || nn |Two-byte expression (0 to 65535) || pp |Register pair BC, DE, IX or SP || qq |Register pair AF, BC, DE or HL || qq' |Alternative register pair AF, BC, DE or HL || r |Register A, B, C, D, E, H or L || rr |Register pair BC, DE, IY or SP || s |Any register r, value n, [HL] or [xx+d] || src |Source s, ss, [BC], [DE], [HL], nn, [nn] || ss |Register pair BC, DE, HL or SP || xx |Index register IX or IY ||-----------------+--------------------------------------------|| + - * / ^ |Add/subtract/multiply/divide/exponent || & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR || <- -> |Rotate left/right || [ ] |Indirect addressing || [ ]+ -[ ] |Indirect addressing auto-increment/decrement|| { } |Combination of operands || # |Also BC=BC-1,DE=DE-1 || ## |Only lower 4 bits of accumulator A used |----------------------------------------------------------------

FlagsMnemonic Size OP-Code Clock SZHPNC Effect ADC A,(HL) 1 8E 7 ***V0* A=A+[HL]+CYADC A,(IX+n) 3 DD 8E XX 19 ***V0* A=A+[IX+n]+CYADC A,(IY+n) 3 FD 8E XX 19 ***V0* A=A+[IY+n]+CYADC A,r 1 88+rb 4 ***V0* A=A+r+CYADC A,N 2 CE XX 7 ***V0* A=A+N+CYADC HL,BC 2 ED 4A 15 ***V0* HL=HL+BC+CYADC HL,DE 2 ED 5A 15 ***V0* HL=HL+DE+CYADC HL,HL 2 ED 6A 15 ***V0* HL=HL+HL+CYADC HL,SP 2 ED 7A 15 ***V0* HL=HL+SP+CYADD A,(HL) 1 86 7 ***V0* A=A+[HL]ADD A,(IX+n) 3 DD 86 XX 19 ***V0* A=A+[IX+n]ADD A,(IY+n) 3 FD 86 XX 19 ***V0* A=A+[IY+n]ADD A,r 1 80+rb 4 ***V0* A=A+rADD A,N 2 C6 XX 7 ***V0* A=A+NADD HL,BC 1 09 11 --*-0* HL=HL+BCADD HL,DE 1 19 11 --*-0* HL=HL+DEADD HL,HL 1 29 11 --*-0* HL=HL+HLADD HL,SP 1 39 11 --*-0* HL=HL+SPADD IX,BC 2 DD 09 15 --*-0* IX=IX+BCADD IX,DE 2 DD 19 15 --*-0* IX=IX+DEADD IX,IX 2 DD 29 15 --*-0* IX=IX+IXADD IX,SP 2 DD 39 15 --*-0* IX=IX+SPADD IY,BC 2 FD 09 15 --*-0* IY=IY+BCADD IY,DE 2 FD 19 15 --*-0* IY=IY+DEADD IY,IY 2 FD 29 15 --*-0* IY=IY+IYADD IY,SP 2 FD 39 15 --*-0* IY=IY+SPAND (HL) 1 A6 7 ***P00 A=A&[HL]AND (IX+n) 3 DD A6 XX 19 ***P00 A=A&[IX+n]AND (IY+n) 3 FD A6 XX 19 ***P00 A=A&[IY+n]AND r 1 A0+rb 4 ***P00 A=A&rAND N 2 E6 XX 7 ***P00 A=A&NBIT b,(HL) 2 CB 46+8*b 12 **1*0- [HL]&{2^b}BIT b,(IX+n) 4 DD CB XX 46+8*b 20 **1*0- [IX+n]&{2^b}BIT b,(IY+n) 4 FD CB XX 46+8*b 20 **1*0- [IY+n]&{2^b}BIT b,r 2 CB 40+8*b+rb 8 **1*0- r&{2^b}CALL C,NN 3 DC XX XX 17/10 ------ If CY then [SP-=2]=PC,PC=NNCALL M,NN 3 FC XX XX 17/10 ------ If S then [SP-=2]=PC,PC=NNCALL NC,NN 3 D4 XX XX 17/10 ------ If !CY then [SP-=2]=PC,PC=NNCALL NN 3 CD XX XX 17 ------ SP-=2,[SP+1,SP]=PC,PC=NNCALL NZ,NN 3 C4 XX XX 17/10 ------ If !Z then [SP-=2]=PC,PC=NNCALL P,NN 3 F4 XX XX 17/10 ------ If !S then [SP-=2]=PC,PC=NNCALL PE,NN 3 EC XX XX 17/10 ------ If !P then [SP-=2]=PC,PC=NNCALL PO,NN 3 E4 XX XX 17/10 ------ If P then [SP-=2]=PC,PC=NNCALL Z,NN 3 CC XX XX 17/10 ------ If Z then [SP-=2]=PC,PC=NNCCF 1 3F 4 --*-00 CY=~CYCP (HL) 1 BE 7 ***V1* A-[HL]CP (IX+n) 3 DD BE XX 19 ***V1* A-[IX+n]CP (IY+n) 3 FD BE XX 19 ***V1* A-[IY+n]CP r 1 B8+rb 4 ***V1* A-rCP N 2 FE XX 7 ***V1* A-NCPD 2 ED A9 16 ****1- A-[HL],HL=HL-1,BC=BC-1CPDR 2 ED B9 21/16 ****1- CPD until A=[HL] or BC=0CPI 2 ED A1 16 ****1- A-[HL],HL=HL+1,BC=BC-1CPIR 2 ED B1 21/16 ****1- CPI until A=[HL] or BC=0

CPL 1 2F 4 --1-1- A=~ADAA 1 27 4 ***P-* A=adjust result to BCD-formatDEC (HL) 1 35 11 ***V1- [HL]=[HL]-1DEC (IX+n) 3 DD 35 XX 23 ***V1- [IX+n]=[IX+n]-1DEC (IY+n) 3 FD 35 XX 23 ***V1- [IY+n]=[IY+n]-1DEC A 1 3D 4 ***V1- A=A-1DEC B 1 05 4 ***V1- B=B-1DEC BC 1 0B 6 ------ BC=BC-1DEC C 1 0D 4 ***V1- C=C-1DEC D 1 15 4 ***V1- D=D-1DEC DE 1 1B 6 ------ DE=DE-1DEC E 1 1D 4 ***V1- E=E-1DEC H 1 25 4 ***V1- H=H-1DEC HL 1 2B 6 ------ HL=HL-1DEC IX 2 DD 2B 10 ------ IX=IX-1DEC IY 2 FD 2B 10 ------ IY=IY-1DEC L 2 2D 4 ***V1- L=L-1DEC SP 1 3B 6 ------ SP=SP-1DI 1 F3 4 ------ disable interruptsDJNZ n 1 10 13/8 ------ B=B-1, if B != 0 then PC+=nEI 1 FB 4 ------ enable interruptsEX (SP),HL 1 E3 19 ------ [SP]<->HLEX (SP),IX 2 DD E3 23 ------ [SP]<->IXEX (SP),IY 2 FD E3 23 ------ [SP]<->IYEX AF,AF' 1 08 4 ****** AF<->AF'EX DE,HL 1 EB 4 ------ DE<->HLEXX 1 D9 4 ------ BC<->BC',DE<->DE',HL<->HL'HALT 1 76 4 ------ repeat NOP until interruptIM 0 2 ED 46 8 ------ set interrupt 0IM 1 2 ED 56 8 ------ set interrupt 1IM 2 2 ED 5E 8 ------ set interrupt 2IN A,(C) 2 ED 78 12 ***P0- A=[C]IN A,(N) 2 DB XX 11 ------ A=[N]IN B,(C) 2 ED 40 12 ***P0- B=[C]IN C,(C) 2 ED 48 12 ***P0- C=[C]IN D,(C) 2 ED 50 12 ***P0- D=[C]IN E,(C) 2 ED 58 12 ***P0- E=[C]IN H,(C) 2 ED 60 12 ***P0- H=[C]IN L,(C) 2 ED 68 12 ***P0- L=[C]INC (HL) 1 34 11 ***V0- [HL]=[HL]+1INC (IX+n) 3 DD 34 XX 23 ***V0- [IY+n]=[IX+n]+1INC (IY+n) 3 FD 34 XX 23 ***V0- [IY+n]=[IY+n]+1INC A 1 3C 4 ***V0- A=A+1INC B 1 04 4 ***V0- B=B+1INC BC 1 03 6 ------ BC=BC+1INC C 1 0C 4 ***V0- C=C+1INC D 1 14 4 ***V0- D=D+1INC DE 1 13 6 ------ DE=DE+1INC E 1 1C 4 ***V0- E=E+1INC H 1 24 4 ***V0- H=H+1INC HL 1 23 6 ------ HL=HL+1INC IX 2 DD 23 10 ------ IX=IX+1INC IY 2 FD 23 10 ------ IY=IY+1INC L 1 2C 4 ***V0- L=L+1INC SP 1 33 6 ------ SP=SP+1IND 2 ED AA 16 ***?1- [HL]=[C],HL=HL-1,B=B-1INDR 2 ED BA 21/16 01*?1- IND until B=0

INI 2 ED A2 16 ***?1- [HL]=[C],HL=HL+1,B=B-1INIR 2 ED B2 21/16 01*?1- INI until B=0JP NN 3 C3 XX XX 10 ------ PC=NNJP (HL) 1 E9 4 ------ PC=HLJP (IX) 2 DD E9 8 ------ PC=IXJP (IY) 2 FD E9 8 ------ PC=IYJP C,NN 3 DA XX XX 10/10 ------ If CY then PC=NNJP M,NN 3 FA XX XX 10/10 ------ If S then PC=NNJP NC,NN 3 D2 XX XX 10/10 ------ If !CY then PC=NNJP NZ,NN 3 C2 XX XX 10/10 ------ If !Z then PC=NNJP P,NN 3 F2 XX XX 10/10 ------ If !S then PC=NNJP PE,NN 3 EA XX XX 10/10 ------ If !P then PC=NNJP PO,NN 3 E2 XX XX 10/10 ------ If P then PC=NNJP Z,NN 3 CA XX XX 10/10 ------ If Z then PC=NNJR n 2 18 XX 12 ------ PC=PC+nJR C,n 2 38 XX 12/7 ------ If CY then PC=PC+nJR NC,n 2 30 XX 12/7 ------ If !CY then PC=PC+nJR NZ,n 2 20 XX 12/7 ------ If !Z then PC=PC+nJR Z,n 2 28 XX 12/7 ------ If Z then PC=PC+nLD (BC),A 1 02 7 ------ [BC]=ALD (DE),A 1 12 7 ------ [DE]=ALD (HL),r 1 70+rb 7 ------ [HL]=rLD (HL),N 2 36 XX 10 ------ [HL]=NLD (IX+n),r 3 DD 70+rb XX 19 ------ [IX+n]=rLD (IX+n),N 4 DD 36 XX XX 19 ------ [IX+n]=NLD (IY+n),r 3 FD 70+rb XX 19 ------ [IY+n]=rLD (IY+n),N 4 FD 36 XX XX 19 ------ [IY+n]=NLD (NN),A 3 32 XX XX 13 ------ [NN]=ALD (NN),BC 4 ED 43 XX XX 20 ------ [NN]=C, (NN+1)=BLD (NN),DE 4 ED 53 XX XX 20 ------ [NN]=E, (NN+1)=DLD (NN),HL 3 22 XX XX 16 ------ [NN]=L, (NN+1)=HLD (NN),IX 4 DD 22 XX XX 20 ------ [NN,NN+1]=IXLD (NN),IY 4 FD 22 XX XX 20 ------ [NN,NN+1]=IYLD (NN),SP 4 ED 73 XX XX 20 ------ [NN,NN+1]=SPLD A,(BC) 1 0A 7 ------ A=[BC]LD A,(DE) 1 1A 7 ------ A=[DE]LD A,(HL) 1 7E 7 ------ A=[HL]LD A,(IX+n) 3 DD 7E XX 19 ------ A=[IX+n]LD A,(IY+n) 3 FD 7E XX 19 ------ A=[IY+n]LD A,(NN) 3 3A XX XX 13 ------ A=[NN]LD A,r 1 78+rb 4 ------ A=rLD A,I 2 ED 57 9 **0*0- A=ILD A,N 2 3E XX 7 ------ A=NLD A,R 2 ED 5F 9 **0*0- A=RLD B,(HL) 1 46 7 ------ B=[HL]LD B,(IX+n) 3 DD 46 XX 19 ------ B=[IX+n]LD B,(IY+n) 3 FD 46 XX 19 ------ B=[IY+n]LD B,r 1 40+rb 4 ------ B=rLD B,N 2 06 XX 7 ------ B=NLD BC,(NN) 4 ED 4B XX XX 20 ------ C=[NN],B=[NN+1]LD BC,NN 3 01 XX XX 10 ------ BC=NNLD C,(HL) 1 4E 7 ------ C=[HL] LD C,(IX+n) 3 DD 4E XX 19 ------ C=[IX+n]LD C,(IY+n) 3 FD 4E XX 19 ------ C=[IY+n]LD C,r 1 48+rb 4 ------ C=rLD C,N 2 0E XX 7 ------ C=NLD D,(HL) 1 56 7 ------ D=[HL]

LD D,(IX+n) 3 DD 56 XX 19 ------ D=[IX+n]LD D,(IY+n) 3 FD 56 XX 19 ------ D=[IY+n]LD D,r 1 50+rb 4 ------ D=rLD D,N 2 16 XX 7 ------ D=NLD DE,(NN) 4 ED 5B XX XX 20 ------ E=[NN],D=[NN+1]LD DE,NN 3 11 XX XX 10 ------ DE=NNLD E,(HL) 1 5E 7 ------ E=[HL] LD E,(IX+n) 3 DD 5E XX 19 ------ E=[IX+n]LD E,(IY+n) 3 FD 5E XX 19 ------ E=[IY+n]LD E,r 1 58+rb 4 ------ E=rLD E,N 2 1E XX 7 ------ E=NLD H,(HL) 1 66 7 ------ H=[HL]LD H,(IX+n) 3 DD 66 XX 19 ------ H=[IX+n]LD H,(IY+n) 3 FD 66 XX 19 ------ H=[IY+n]LD H,r 1 60+rb 4 ------ H=rLD H,N 2 26 XX 7 ------ H=NLD HL,(NN) 3 2A XX XX 16 ------ L=[NN],H=[NN+1]LD HL,(NN) 4 ED 6B XX XX 20 ------ L=[NN],H=[NN+1]LD HL,NN 3 21 XX XX 10 ------ HL=NNLD I,A 2 ED 47 9 ------ I=ALD IX,(NN) 4 DD 2A XX XX 20 ------ IX=[NN,NN+1]LD IX,NN 4 DD 21 XX XX 14 ------ IX=NNLD IY,(NN) 4 FD 2A XX XX 20 ------ IY=[NN,NN+1]LD IY,NN 4 FD 21 XX XX 14 ------ IY=NNLD L,(HL) 1 6E 7 ------ L=[HL] LD L,(IX+n) 3 DD 6E XX 19 ------ L=[IX+n]LD L,(IY+n) 3 FD 6E XX 19 ------ L=[IY+n]LD L,r 1 68+rb 4 ------ L=rLD L,N 2 2E XX 7 ------ L=NLD R,A 2 ED 4F 9 ------ R=ALD SP,(NN) 4 ED 7B XX XX 20 ------ SP=[NN,NN+1]LD SP,HL 1 F9 6 ------ SP=HLLD SP,IX 2 DD F9 10 ------ SP=IXLD SP,IY 2 FD F9 10 ------ SP=IYLD SP,NN 3 31 XX XX 10 ------ SP=NNLDD 2 ED A8 16 --0*0- [DE]=[HL],HL-=1,DE-=1,BC-=1LDDR 2 ED B8 21/16 --000- LDD until BC=0LDI 2 ED A0 16 --0*0- [DE]=[HL],HL+=1,DE+=1,BC=-1LDIR 2 ED B0 21/16 --000- LDI until BC=0NEG 2 ED 44 8 ***V1* A=-ANOP 1 00 4 ------ OR (HL) 1 B6 7 ***P00 A=Av[HL]OR (IX+n) 3 DD B6 XX 19 ***P00 A=Av[IX+n]OR (IY+n) 3 FD B6 XX 19 ***P00 A=Av[IY+n]OR r 1 B0+rb 4 ***P00 A=AvrOR N 2 F6 XX 7 ***P00 A=AvNOTDR 2 ED BB 21/16 01*?1- OUTD until B=0OTIR 2 ED B3 21/16 01*?1- OUTI until B=0OUT (C),A 2 ED 79 12 ------ [C]=AOUT (C),B 2 ED 41 12 ------ [C]=BOUT (C),C 2 ED 49 12 ------ [C]=COUT (C),D 2 ED 51 12 ------ [C]=DOUT (C),E 2 ED 59 12 ------ [C]=EOUT (C),H 2 ED 61 12 ------ [C]=HOUT (C),L 2 ED 69 12 ------ [C]=LOUT (N),A 2 D3 XX 11 ------ [N]=AOUTD 2 ED AB 16 ***?1- [C]=[HL],HL=HL-1,B=B-1

OUTI 2 ED A3 16 ***?1- [C]=[HL],HL=HL+1,B=B-1POP AF 1 F1 10 ****** F=[SP],SP+,A=[SP],SP+POP BC 1 C1 10 ------ C=[SP],SP+,B=[SP],SP+POP DE 1 D1 10 ------ E=[SP],SP+,D=[SP],SP+POP HL 1 E1 10 ------ L=[SP],SP+,H=[SP],SP+POP IX 2 DD E1 14 ------ IX=[SP,SP+1],SP+,SP+POP IY 2 FD E1 14 ------ IY=[SP,SP+1],SP+,SP+PUSH AF 1 F5 11 ------ -SP,[SP]=A,-SP,[SP]=FPUSH BC 1 C5 11 ------ -SP,[SP]=B,-SP,[SP]=CPUSH DE 1 D5 11 ------ -SP,[SP]=D,-SP,[SP]=EPUSH HL 1 E5 11 ------ -SP,[SP]=H,-SP,[SP]=LPUSH IX 2 DD E5 15 ------ -SP,-SP,[SP,SP+1]=IXPUSH IY 2 FD E5 15 ------ -SP,-SP,[SP,SP+1]=IYRES b,(HL) 2 CB 86+8*b 15 ------ [HL]=[HL]&{~2^b}RES b,(IX+n) 4 DD CB XX 86+8*b 23 ------ [IX+n]=[IX+n]&{~2^b}RES b,(IY+n) 4 FD CB XX 86+8*b 23 ------ [IY+n]=[IY+n]&{~2^b}RES b,r 2 CB 80+8*b+rb 8 ------ r=r&{~2^b}RET 1 C9 10 ------ PC=[SP,SP+1],SP+,SP+RET C 1 D8 11/5 ------ If CY then PC=[SP,SP+1],SP+=2RET M 1 F8 11/5 ------ If S then PC=[SP,SP+1],SP+=2RET NC 1 D0 11/5 ------ If !CY then PC=[SP,SP+1],SP+=2RET NZ 1 C0 11/5 ------ If !Z then PC=[SP,SP+1],SP+=2RET P 1 F0 11/5 ------ If !S then PC=[SP,SP+1],SP+=2RET PE 1 E8 11/5 ------ If !P then PC=[SP,SP+1],SP+=2RET PO 1 E0 11/5 ------ If P then PC=[SP,SP+1],SP+=2RET Z 1 C8 11/5 ------ If Z then PC=[SP,SP+1],SP+=2RETI 2 ED 4D 14 ------ PC=[SP,SP+1],SP+,SP+RETN 2 ED 45 14 ------ PC=[SP,SP+1],SP+,SP+RL (HL) 2 CB 16 15 **0P0* [HL]={CY,[HL]}<<CYRL (IX+n) 4 DD CB XX 16 23 **0P0* [IX+n]={CY,[IX+n]}<<CYRL (IY+n) 4 FD CB XX 16 23 **0P0* [IY+n]={CY,[IY+n]}<<CYRL r 2 CB 10+rb 8 **0P0* r={CY,r}<<CYRLA 1 17 4 --0-0* A={CY,A}<<CYRLC (HL) 2 CB 06 15 **0P0* [HL]={[HL]}<<RLC (IX+n) 4 DD CB XX 06 23 **0P0* [IX+n]={[IX+n]}<<RLC (IY+n) 4 FD CB XX 06 23 **0P0* [IY+n]={[IY+n]}<<RLC r 2 CB 00+rb 8 **0P0* r={r}<<RLCA 1 07 4 --0-0* A={A}<<RLD 2 ED 6F 18 **0P0- {A,[HL]}={A,[HL]}<-4RR (HL) 2 CB 1E 15 **0P0* [HL]=CY>>{CY,[HL]}RR (IX+n) 4 DD CB XX 1E 23 **0P0* [IX+n]=CY>>{CY,[IX+n]}RR (IY+n) 4 FD CB XX 1E 23 **0P0* [IT+n]=CY>>{CY,[IY+n]}RR r 2 CB 18+rb 8 **0P0* r=CY>>{CY,r}RRA 1 1F 4 --0-0* A=CY>>{CY,A}RRC (HL) 2 CB 0E 15 **0P0* [HL]=>>{[HL]}RRC (IX+n) 4 DD CB XX 0E 23 **0P0* [IX+n]=>>{[IX+n]}RRC (IY+n) 4 FD CB XX 0E 23 **0P0* [IY+n]=>>{[IY+n]}RRC r 2 CB 08+rb 8 **0P0* r=>>{r}RRCA 1 0F 4 --0-0* A=>>{A}RRD 2 ED 67 18 **0P0- {A,[HL]}=4->{A,[HL]}RST 0 1 C7 11 ------ -SP,-SP,[SP+1,SP]=PC,PC=00RST 8H 1 CF 11 ------ -SP,-SP,[SP+1,SP]=PC,PC=08RST 10H 1 D7 11 ------ -SP,-SP,[SP+1,SP]=PC,PC=10RST 18H 1 DF 11 ------ -SP,-SP,[SP+1,SP]=PC,PC=18RST 20H 1 E7 11 ------ -SP,-SP,[SP+1,SP]=PC,PC=20RST 28H 1 EF 11 ------ -SP,-SP,[SP+1,SP]=PC,PC=28

RST 30H 1 F7 11 ------ -SP,-SP,[SP+1,SP]=PC,PC=30RST 38H 1 FF 11 ------ -SP,-SP,[SP+1,SP]=PC,PC=38SBC (HL) 1 9E 7 ***V1* A=A-[HL]-CY SBC A,(IX+n) 3 DD 9E XX 19 ***V1* A=A-[IX+n]-CYSBC A,(IY+n) 3 FD 9E XX 19 ***V1* A=A-[IY+n]-CYSBC A,N 2 DE XX 7 ***V1* A=A-r-CY SBC r 1 98+rb 4 ***V1* A=A-N-CY SBC HL,BC 2 ED 42 15 ***V1* HL=HL-BC-CYSBC HL,DE 2 ED 52 15 ***V1* HL=HL-DE-CYSBC HL,HL 2 ED 62 15 ***V1* HL=HL-HL-CYSBC HL,SP 2 ED 72 15 ***V1* HL=HL-SP-CYSCF 1 37 4 --0-01 CY=1SET b,(HL) 2 CB C6+8*b 15 ------ [HL]=[HL]v{2^b}SET b,(IX+n) 4 DD CB XX C6+8*b 23 ------ [IX+n]=[IX+n]v{2^b}SET b,(IY+n) 4 FD CB XX C6+8*b 23 ------ [IY+n]=[IY+n]v{2^b}SET b,r 2 CB C0+8*b+rb 8 ------ r=rv{2^b}SLA (HL) 2 CB 26 15 **0P0* [HL]=[HL]*2SLA (IX+n) 4 DD CB XX 26 23 **0P0* [IX+n]=[IX+n]*2SLA (IY+n) 4 FD CB XX 26 23 **0P0* [IY+n]=[IY+n]*2SLA r 2 CB 20+rb 8 **0P0* r=r*2SLL (HL) 2 CB 36 15 **0P0* [HL]=[HL]*2+1SLL (IX+n) 4 DD CB XX 36 23 **0P0* [IX+n]=[IX+n]*2+1SLL (IY+n) 4 FD CB XX 36 23 **0P0* [IY+n]=[IY+n]*2+1SLL r 2 CB 30+rb 8 **0P0* r=r*2+1SRA (HL) 2 CB 2E 15 **0P0* [HL]=(signed)[HL]/2SRA (IX+n) 4 DD CB XX 2E 23 **0P0* [IX+n]=(signed)[IX+n]/2SRA (IY+n) 4 FD CB XX 2E 23 **0P0* [IY+n]=(signed)[IY+n]/2SRA r 2 CB 28+rb 8 **0P0* r=(signed)r/2SRL (HL) 2 CB 3E 15 **0P0* [HL]=(unsigned)[HL]/2SRL (IX+n) 4 DD CB XX 3E 23 **0P0* [IX+n]=(unsigned)[IX+n]/2SRL (IY+n) 4 FD CB XX 3E 23 **0P0* [IY+n]=(unsigned)[IY+n]/2SRL r 2 CB 38+rb 8 **0P0* r=(unsigned)r/2SUB (HL) 1 96 7 ***V1* A=A-[HL]SUB (IX+n) 3 DD 96 XX 19 ***V1* A=A-[IX+n]SUB (IY+n) 3 FD 96 XX 19 ***V1* A=A-[IY+n]SUB r 1 90+rb 4 ***V1* A=A-rSUB N 2 D6 XX 7 ***V1* A=A-NXOR (HL) 1 AE 7 ***P00 A=Ax[HL]XOR (IX+n) 3 DD AE XX 19 ***P00 A=Ax[IX+n]XOR (IY+n) 3 FD AE XX 19 ***P00 A=Ax[IY+n]XOR r 1 A8+rb 4 ***P00 A=AxrXOR N 2 EE XX 7 ***P00 A=AxN

The flag field contains one of the following:

- Flag unaffected* Flag affected0 Flag reset1 Flag set? UnknownP Parity-Flag used as ParityV Parity-Flag used as Overflow-flag

r means register. Can be B,C,D,E,H,L or A.Add this to last byte of OP-code:Reg regbitsB 0C 1D 2E 3H 4L 5A 7

On >LD (IX+n),r< and >LD (IY+n),r< youadd it to the byte before the last.

b means bit. Can be 0-7. Increase thelast byte of OP-code with 8*b.Used in SET, BIT and RES.

If there is two numbers given at Clock,then the highest is when the jump istaken.

Instruction Timing Opcode Size

ADC A,(HL) 7 8E 1ADC A,(IX+o) 19 DD 8E oo 3

Instruction Timing Opcode Size

ADC A,(IY+o) 19 FD 8E oo 3ADC A,n 7 CE nn 2ADC A,r 4 88+r 1ADC A,IXp 8 DD 88+p 2ADC A,IYq 8 FD 88+q 2ADC HL,BC 15 ED 4A 2ADC HL,DE 15 ED 5A 2ADC HL,HL 15 ED 6A 2ADC HL,SP 15 ED 7A 2ADD A,(HL) 7 86 1ADD A,(IX+o) 19 DD 86 oo 3ADD A,(IY+o) 19 FD 86 oo 3ADD A,n 7 C6 nn 2ADD A,r 4 80+r 1ADD A,IXp 8 DD 80+p 2ADD A,IYq 8 FD 80+q 2ADD HL,BC 11 09 1ADD HL,DE 11 19 1ADD HL,HL 11 29 1ADD HL,SP 11 39 1ADD IX,BC 15 DD 09 2ADD IX,DE 15 DD 19 2ADD IX,IX 15 DD 29 2ADD IX,SP 15 DD 39 2ADD IY,BC 15 FD 09 2ADD IY,DE 15 FD 19 2ADD IY,IY 15 FD 29 2ADD IY,SP 15 FD 39 2AND (HL) 7 A6 1AND (IX+o) 19 DD A6 oo 3AND (IY+o) 19 FD A6 oo 3AND n 7 E6 nn 2AND r 4 A0+r 1AND IXp 8 DD A0+p 2AND IYq 8 FD A0+q 2BIT b,(HL) 12 CB 46+8*b 2BIT b,(IX+o) 20 DD CB oo 46+8*b 4BIT b,(IY+o) 20 FD CB oo 46+8*b 4BIT b,r 8 CB 40+8*b+r 2CALL nn 17 CD nn nn 3CALL C,nn 17/10 DC nn nn 3CALL M,nn 17/10 FC nn nn 3CALL NC,nn 17/10 D4 nn nn 3

Instruction Timing Opcode Size

CALL NZ,nn 17/10 C4 nn nn 3CALL P,nn 17/10 F4 nn nn 3CALL PE,nn 17/10 EC nn nn 3CALL PO,nn 17/10 E4 nn nn 3CALL Z,nn 17/10 CC nn nn 3CCF 4 3F 1CP (HL) 7 BE 1CP (IX+o) 19 DD BE oo 3CP (IY+o) 19 FD BE oo 3CP n 7 FE nn 2CP r 4 B8+r 1CP IXp 8 DD B8+p 2CP IYq 8 FD B8+q 2CPD 16 ED A9 2CPDR 21/16 ED B9 2CPI 16 ED A1 2CPIR 21/16 ED B1 2CPL 4 2F 1DAA 4 27 1DEC (HL) 11 35 1DEC (IX+o) 23 DD 35 oo 3DEC (IY+o) 23 FD 35 oo 3DEC A 4 3D 1DEC B 4 05 1DEC BC 6 0B 1DEC C 4 0D 1DEC D 4 15 1DEC DE 6 1B 1DEC E 4 1D 1DEC H 4 25 1DEC HL 6 2B 1DEC IX 10 DD 2B 2DEC IY 10 FD 2B 2DEC IXp 8 DD 05+8*p 2DEC IYq 8 FD 05+8*q 2DEC L 4 2D 2DEC SP 6 3B 1DI 4 F3 1DJNZ o 13/8 10 oo 2EI 4 FB 1EX (SP),HL 19 E3 1EX (SP),IX 23 DD E3 2EX (SP),IY 23 FD E3 2

Instruction Timing Opcode Size

EX AF,AF' 4 08 1EX DE,HL 4 EB 1EXX 4 D9 1HALT 4 76 1IM 0 8 ED 46 2IM 1 8 ED 56 2IM 2 8 ED 5E 2IN A,(C) 12 ED 78 2IN A,(n) 11 DB nn 2IN B,(C) 12 ED 40 2IN C,(C) 12 ED 48 2IN D,(C) 12 ED 50 2IN E,(C) 12 ED 58 2IN H,(C) 12 ED 60 2IN L,(C) 12 ED 68 2IN F,(C) 12 ED 70 3INC (HL) 11 34 1INC (IX+o) 23 DD 34 oo 3INC (IY+o) 23 FD 34 oo 3INC A 4 3C 1INC B 4 04 1INC BC 6 03 1INC C 4 0C 1INC D 4 14 1INC DE 6 13 1INC E 4 1C 1INC H 4 24 1INC HL 6 23 1INC IX 10 DD 23 2INC IY 10 FD 23 2INC IXp 8 DD 04+8*p 2INC IYq 8 FD 04+8*q 2INC L 4 2C 1INC SP 6 33 1IND 16 ED AA 2INDR 21/16 ED BA 2INI 16 ED A2 2INIR 21/16 ED B2 2JP nn 10 C3 nn nn 3JP (HL) 4 E9 1JP (IX) 8 DD E9 2JP (IY) 8 FD E9 2JP C,nn 10 DA nn nn 3

Instruction Timing Opcode Size

JP M,nn 10 FA nn nn 3JP NC,nn 10 D2 nn nn 3JP NZ,nn 10 C2 nn nn 3JP P,nn 10 F2 nn nn 3JP PE,nn 10 EA nn nn 3JP PO,nn 10 E2 nn nn 3JP Z,nn 10 CA nn nn 3JR o 12 18 oo 2JR C,o 12/7 38 oo 2JR NC,o 12/7 30 oo 2JR NZ,o 12/7 20 oo 2JR Z,o 12/7 28 oo 2LD (BC),A 7 02 1LD (DE),A 7 12 1LD (HL),n 10 36 nn 2LD (HL),r 7 70+r 1LD (IX+o),n 19 DD 36 oo nn 4LD (IX+o),r 19 DD 70+r oo 3LD (IY+o),n 19 FD 36 oo nn 4LD (IY+o),r 19 FD 70+r oo 3LD (nn),A 13 32 nn nn 3LD (nn),BC 20 ED 43 nn nn 4LD (nn),DE 20 ED 53 nn nn 4LD (nn),HL 16 22 nn nn 3LD (nn),IX 20 DD 22 nn nn 4LD (nn),IY 20 FD 22 nn nn 4LD (nn),SP 20 ED 73 nn nn 4LD A,(BC) 7 0A 1LD A,(DE) 7 1A 1LD A,(HL) 7 7E 1LD A,(IX+o) 19 DD 7E oo 3LD A,(IY+o) 19 FD 7E oo 3LD A,(nn) 13 3A nn nn 3LD A,n 7 3E nn 2LD A,r 4 78+r 1LD A,IXp 8 DD 78+p 2LD A,IYq 8 FD 78+q 2LD A,I 9 ED 57 2LD A,R 9 ED 5F 2LD B,(HL) 7 46 1LD B,(IX+o) 19 DD 46 oo 3LD B,(IY+o) 19 FD 46 oo 3LD B,n 7 06 nn 2

Instruction Timing Opcode Size

LD B,r 4 40+r 1LD B,IXp 8 DD 40+p 2LD B,IYq 8 FD 40+q 2LD BC,(nn) 20 ED 4B nn nn 4LD BC,nn 10 01 nn nn 3LD C,(HL) 7 4E 1LD C,(IX+o) 19 DD 4E oo 3LD C,(IY+o) 19 FD 4E oo 3LD C,n 7 0E nn 2LD C,r 4 48+r 1LD C,IXp 8 DD 48+p 2LD C,IYq 8 FD 48+q 2LD D,(HL) 7 56 1LD D,(IX+o) 19 DD 56 oo 3LD D,(IY+o) 19 FD 56 oo 3LD D,n 7 16 nn 2LD D,r 4 50+r 1LD D,IXp 8 DD 50+p 2LD D,IYq 8 FD 50+q 2LD DE,(nn) 20 ED 5B nn nn 4LD DE,nn 10 11 nn nn 3LD E,(HL) 7 5E 1LD E,(IX+o) 19 DD 5E oo 3LD E,(IY+o) 19 FD 5E oo 3LD E,n 7 1E nn 2LD E,r 4 58+r 1LD E,IXp 8 DD 58+p 2LD E,IYq 8 FD 58+q 2LD H,(HL) 7 66 1LD H,(IX+o) 19 DD 66 oo 3LD H,(IY+o) 19 FD 66 oo 3LD H,n 7 26 nn 2LD H,r 4 60+r 1LD HL,(nn) 16 2A nn nn 5LD HL,nn 10 21 nn nn 3LD I,A 9 ED 47 2LD IX,(nn) 20 DD 2A nn nn 4LD IX,nn 14 DD 21 nn nn 4LD IXh,n 11 DD 26 nn 2LD IXh,p 8 DD 60+p 2LD IXl,n 11 DD 2E nn 2LD IXl,p 8 DD 68+p 2LD IY,(nn) 20 FD 2A nn nn 4

Instruction Timing Opcode Size

LD IY,nn 14 FD 21 nn nn 4LD IYh,n 11 FD 26 nn 2LD IYh,q 8 FD 60+q 2LD IYl,n 11 FD 2E nn 2LD IYl,q 8 FD 68+q 2LD L,(HL) 7 6E 1LD L,(IX+o) 19 DD 6E oo 3LD L,(IY+o) 19 FD 6E oo 3LD L,n 7 2E nn 2LD L,r 4 68+r 1LD R,A 9 ED 4F 2LD SP,(nn) 20 ED 7B nn nn 4LD SP,HL 6 F9 1LD SP,IX 10 DD F9 2LD SP,IY 10 FD F9 2LD SP,nn 10 31 nn nn 3LDD 16 ED A8 2LDDR 21/16 ED B8 2LDI 16 ED A0 2LDIR 21/16 ED B0 2MULUB A,r ED C1+8*r 2MULUW HL,BC ED C3 2MULUW HL,SP ED F3 2NEG 8 ED 44 2NOP 4 00 1OR (HL) 7 B6 1OR (IX+o) 19 DD B6 oo 3OR (IY+o) 19 FD B6 oo 3OR n 7 F6 nn 2OR r 4 B0+r 1OR IXp 8 DD B0+p 2OR IYq 8 FD B0+q 2OTDR 21/16 ED BB 2OTIR 21/16 ED B3 2OUT (C),A 12 ED 79 2OUT (C),B 12 ED 41 2OUT (C),C 12 ED 49 2OUT (C),D 12 ED 51 2OUT (C),E 12 ED 59 2OUT (C),H 12 ED 61 2OUT (C),L 12 ED 69 2OUT (n),A 11 D3 nn 2OUTD 16 ED AB 2

Instruction Timing Opcode Size

OUTI 16 ED A3 2POP AF 10 F1 1POP BC 10 C1 1POP DE 10 D1 1POP HL 10 E1 1POP IX 14 DD E1 2POP IY 14 FD E1 2PUSH AF 11 F5 1PUSH BC 11 C5 1PUSH DE 11 D5 1PUSH HL 11 E5 1PUSH IX 15 DD E5 2PUSH IY 15 FD E5 2RES b,(HL) 15 CB 86+8*b 2RES b,(IX+o) 23 DD CB oo 86+8*b 4RES b,(IY+o) 23 FD CB oo 86+8*b 4RES b,r 8 CB 80+8*b+r 2RET 10 C9 1RET C 11/5 D8 1RET M 11/5 F8 1RET NC 11/5 D0 1RET NZ 11/5 C0 1RET P 11/5 F0 1RET PE 11/5 E8 1RET PO 11/5 E0 1RET Z 11/5 C8 1RETI 14 ED 4D 2RETN 14 ED 45 2RL (HL) 15 CB 16 2RL (IX+o) 23 DD CB oo 16 4RL (IY+o) 23 FD CB oo 16 4RL r 8 CB 10+r 2RLA 4 17 1RLC (HL) 15 CB 06 2RLC (IX+o) 23 DD CB oo 06 4RLC (IY+o) 23 FD CB oo 06 4RLC r 8 CB 00+r 2RLCA 4 07 1RLD 18 ED 6F 2RR (HL) 15 CB 1E 2RR (IX+o) 23 DD CB oo 1E 4RR (IY+o) 23 FD CB oo 1E 4RR r 8 CB 18+r 2

Instruction Timing Opcode Size

RRA 4 1F 1RRC (HL) 15 CB 0E 2RRC (IX+o) 23 DD CB oo 0E 4RRC (IY+o) 23 FD CB oo 0E 4RRC r 8 CB 08+r 2RRCA 4 0F 1RRD 18 ED 67 2RST 0 11 C7 1RST 8H 11 CF 1RST 10H 11 D7 1RST 18H 11 DF 1RST 20H 11 E7 1RST 28H 11 EF 1RST 30H 11 F7 1RST 38H 11 FF 1SBC A,(HL) 7 9E 1SBC A,(IX+o) 19 DD 9E oo 3SBC A,(IY+o) 19 FD 9E oo 3SBC A,n 7 DE nn 2SBC A,r 4 98+r 1SBC A,IXp 8 DD 98+p 2SBC A,IYq 8 FD 98+q 2SBC HL,BC 15 ED 42 2SBC HL,DE 15 ED 52 2SBC HL,HL 15 ED 62 2SBC HL,SP 15 ED 72 2SCF 4 37 1SET b,(HL) 15 CB C6+8*b 2SET b,(IX+o) 23 DD CB oo C6+8*b 4SET b,(IY+o) 23 FD CB oo C6+8*b 4SET b,r 8 CB C0+8*b+r 2SLA (HL) 15 CB 26 2SLA (IX+o) 23 DD CB oo 26 4SLA (IY+o) 23 FD CB oo 26 4SLA r 8 CB 20+r 2SRA (HL) 15 CB 2E 2SRA (IX+o) 23 DD CB oo 2E 4SRA (IY+o) 23 FD CB oo 2E 4SRA r 8 CB 28+r 2SRL (HL) 15 CB 3E 2SRL (IX+o) 23 DD CB oo 3E 4SRL (IY+o) 23 FD CB oo 3E 4SRL r 8 CB 38+r 2

Instruction Timing Opcode Size

SUB (HL) 7 96 1SUB (IX+o) 19 DD 96 oo 3SUB (IY+o) 19 FD 96 oo 3SUB n 7 D6 nn 2SUB r 4 90+r 1SUB IXp 8 DD 90+p 2SUB IYq 8 FD 90+q 2XOR (HL) 7 AE 1XOR (IX+o) 19 DD AE oo 3XOR (IY+o) 19 FD AE oo 3XOR n 7 EE nn 2XOR r 4 A8+r 1XOR IXp 8 DD A8+p 2XOR IYq 8 FD A8+q 2

In this overview, the following variables were used:b 3-bit valuen 8-bit value nn 16-bit valueo 8-bit offset (2-complement)r Register. This can be A, B, C, D, E, H, L or (HL). Add the following value to the last byte of the opcode:

Register Register bits value

A 7B 0C 1D 2E 3H 4L 5(HL) 6

p, IXp denotes the high or low part of the IX register, IXh or IXl. Add the following value to the last byte of the opcode:

Register Register bits value

A 7

B 0C 1D 2E 3IXh 4IXl 5

q, IYq denotes the high or low part of the IY register, IYh or IYl. Add the following value to the last byte of the opcode:

Register Register bits value

A 7B 0C 1D 2E 3IYh 4IYl 5