Nirvana 13 UMA Schematics Document -...

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Size Document Number Rev

Date: Sheet of

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13 A00

CoverA3

1 103Tuesday, January 18, 2011

<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CoverA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CoverA3


<Core Design>

2011-01-18

REV : A00

Nirvana 13 UMA Schematics Document

DY :None Installed

10mW: External circuit for 10mW solution installed.

BT: Stand alone BT Module.

GSENSOR_ADI: Stuff for ADI G-Sensor.

VCCSA_PWM: Stuff for VCCSA PWM solution.

VCCSA_LDO: Stuff for VCCSA LDO solution.

P2800A1: Stuff for P2800EA1

Intel PCH

Sandy Bridge

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


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Nirvana 13

Block Diagram

Tuesday, January 04, 2011

<Core Design>

A3

2 103

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Title


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Nirvana 13

Block Diagram


<Core Design>

A3

2 103

A00

Title


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Nirvana 13

Block Diagram


<Core Design>

A3

2 103

A00

Nirvana 13 UMA Block Diagram

(6 layers)

4

25

Project Code: 91.4ID01.001

PCB P/N :10261

Revision : -1

PCB LAYERUMA

L1:TopL2:VCCL3:SignalL4:SignalL5:GNDL6:Bottom

28

55

79

64

63

49

50

51

49

SMBus

56ODD

56HDD

USB2.0 x 4USB 2.0 x 1

HDMI

LVDS(Single Channel)

RGB CRT

28

USB 2.0 x 1

ADC

DACThermal Sensor

FAN Controller

Main:ENEP2800

Main:ENEP2793

SIM

Free Fall Sensor

IDT

92HD87B1

DMIx4

10/100/1000 LOMRealtek

RJ45

CONN

SPI

Flash ROM

4MB

HDMI

Mini-Card

RTL8111E-VB

KBC

Int.

KB

LPC Bus

Intel CPUDDRIII

1066/1333

DDRIII 1066/1333 Channel A Slot 1

Slot 2

Bluetooth V3.0

WWAN

MIC IN

CRT

LCD

Intel

SATA x 2

14 USB 2.0/1.1 ports

High Definition Audio

SATA ports (6)

ACPI 1.1

LPC I/F

CODEC

HDA

1CH SPEAKER

HP

NPCE795PA

ETHERNET (10/100/1000Mb)

NUVOTON

PCIE ports (8)

Fan

Touch

PAD

FDIx4x2

PCIE x 1,USB2.0 x 1

PCIE x 1

Sandy Bridge

DDRIII

1066/1333

DDRIII 1066/1333 Channel B

PCH

Cougar Point

(On Daughter Board)

Finger Print

CAMERA

w/ Digital MIC

USB 2.0 x 1

PCIE x 1USB3.0 Controller

NEC uPD720200F1USB3.0 x 2

USB 2.0 x 1

65

Mini-Card802.11a/b/g

PCIE x 1,USB2.0 x 1

57 57

USB CHARGEUSB2.0 x 1

PI5USB14550

ESATA/USB

Combo

SATA x 1

32RTS5138

Card Reader

74

SD/MMC+/MS/

MS Pro/xD/SDXC

(8 in 1)

17,18,19,20,21,22,23,24,25,26

60

4,5,6,7,8,9,10,11,12,13

29

69 69

27

45

41

INPUTS OUTPUTS

26

VT1316+VT1317

0D75V_S0

1D5V_S3

INPUTSVCC_CORE

OUTPUTS

CPU DC/DC

SYSTEM DC/DCTPS51216

DDR_VREF_S3

OUTPUTS

5V_S5

1D5V_S3

INPUTS

1D5V_S0

OUTPUTS

BQ24745

INPUTS

TI CHARGER

DCBATOUT

Switches

INPUTS

SYSTEM DC/DC

5V_S0

OUTPUTS

26

5V_S5

TPS51311

3D3V_S5

3D3V_S03D3V_S5

1D8V_S0

DCBATOUT

+PBATT+DC_IN_S5

40

1D05V_VTT

3D3V_AUX_S5

TPS51427

DCBATOUT 5V_S5

OUTPUTS

3D3V_S5

TPS51218

OUTPUTS

SYSTEM DC/DC

INPUTS

SYSTEM DC/DC

DCBATOUT

INPUTS

5V_AUX_S5

15V_S5

VCC_GFXCORE

44

5V_S5

OUTPUTS

SYSTEM DC/DC

INPUTS

TPS51461/APL5916

INPUTS0D85V_S0

OUTPUTS

SYSTEM DC/DC

5V_S5

48

VT1316+VT1317

42

36

46

47

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Table of ContentA3

3 103Wednesday, December 22, 2010

<Core Design>

Title


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Nirvana 13 A00

Table of ContentA3


<Core Design>

Title


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Nirvana 13 A00

Table of ContentA3


<Core Design>

PCIE Routing

LANE2

LANE3

LAN (I/O Board)

LANE4

CFG[6:5]

CFG[7]

Processor Strapping

CFG[2]

Disabled - No Physical Display Port attached toEmbedded Display Port.CFG[4]

Pin Name Strap Description Configuration (Default value for each bit is 1 unless specified otherwise)

1:

Huron River Schematic Checklist Rev.1_0

0:

PCI-Express StaticLane Reversal

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

DefaultValue

0

PCI-ExpressPort BifurcationStraps

11 : x16 - Device 1 functions 1 and 2 disabled10 : x8, x8 - Device 1 function 1 enabled ;function 2 disabled01 : Reserved - (Device 1 function 1 disabled ;function 2 enabled)00 : x8, x4, x4 - Device 1 functions 1 and 2enabled

PEG DEFER TRAINING

1

1

1:

0:Enabled - An external Display Port device isconnectd to the Embedded Display Port

11

1:

0:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

SPKR

Name Schematics Notes

HDA_SYNC

Huron River Schematic Checklist Rev.1_0

INIT3_3V# Weak internal pull-up. This signal should not be pulled low. Leave as "No Connect".

GNT3#/GPIO55GNT2#/GPIO53GNT1#/GPIO51

This signal has a weak internal pull-down.On Die PLL VR is supplied by 1.5 V when sampled high, 1.8 V when sampled low.Needs to be pulled High for Huron River platform.

This signal enables the internal Deep Sleep 1.05 V regulators.This signal must be always pulled-up to VccRTC.

PCH Strapping

INTVRMEN

Internal weak Pull-down. Enable when Pull-up.

GPIO15

Reboot option at power-upDefault Mode:No Reboot Mode with TCO Disabled:

GPIO28This signal has a weak internal pull-up.The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled.If not used, 8.2-kΩ to 10-kΩ pull-up to +V3.3A power-rail.

Voltage RailsVOLTAGE DESCRIPTION

ACTIVE IN

POWER PLANE

CPU Core RailGraphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

3D3V_AUX_KBC

3.3V

DSW, Sx ON for supporting Deep Sleep states

S0

S3

All S states

WOL_EN

G3, Sx

5V_S03D3V_S01D8V_S01D5V_S01D05V_VTT0D85V_S00D75V_S0VCC_COREVCC_GFXCORE

5V3.3V1.8V1.5V1.05V0.95 - 0.85V0.75V0.35V to 1.5V0.4 to 1.25V

5V1.5V0.75V

5V_USBX_S31D5V_S3DDR_VREF_S3

BT+DCBATOUT5V_S55V_AUX_S53D3V_S53D3V_AUX_S5

6V-14.1V6V-14.1V5V5V3.3V3.3V

3.3V3D3V_LAN_S5

3.3V

3D3V_AUX_S5

GNT[3:0]# functionality is not available on Mobile.Mobile: Used as GPIO onlyPull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentialityHigh - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentialityThis signal has a weak internal pull-down.

NOTE: A strong pull-up may be needed for GPIO functionality

KBC_SDA1/KBC_SCL1

KBC_SDA2/KBC_SCL2

KBC_SDA2/KBC_SCL2

KBC_SDA2/KBC_SCL2

KBC_SDA2/KBC_SCL2

PCH_SMBDATA/PCH_SMBCLK




Device

I C / SMBus Addresses2

EC SMBus 1BatteryCapacity Board

EC SMBus 2PCHMXMLCDThermal Sensor

PCH SMBusCK505 Clock GeneratorSO-DIMMA (SPD)SO-DIMMB (SPD)Digital Pot

KBC_SDA1/KBC_SCL1

SMBus ADDRESSES

HURON RIVER ORB

Address Hex Bus Ref Des

X

Integrated 1.05 V VRMs is enabled when high. This signal should always be pulled high

DF_TVSWeak internal pull-down. It needs to be connected to PROC_SELECT with a 1K±5% pull-upresistor to PCH VCCPNAND rail and a 4.7K±5% series resistor.

Integrated 1.05 V VRM Enable / Disable

SATA1GP/GPIO19

This Signal has a weak internal pull-up.Note: This field determines the destination of accesses to the BIOS memory range. This strap is used in conjunction with Boot BIOSDestination Selection 1 strap.Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved1 0 PCI1 1 SPI0 0 LPC

HDA_SDO

Signal has a weak internal pull-down.Default: the security measures defined in the Flash Descriptor will be in effect.Pull-up: the Flash Descriptor Security will be overridden.This strap should only be asserted high via external pull-up in manufacturing or debug environments ONLY.

On-Die PLL Voltage Regulator Voltage Select

TLS Confidentiality

DSWVRMEN

Deep S4/S5 Well On-Die Voltage Regulator Enable

On-Die PLL Voltage Regulator

DMI and FDI Tx/Rx Termination Voltage

SATA Table

Pair

SATA

Device

0

5

4

3

2

1

HDD1

ODD

N/A

N/A

N/A

ESATA

Boot BIOS Strap bit 0

LANE1

LANE5

LANE6

LANE7

LANE8 X

X

Display Port Presence strap

USB3.0

X

USB Table

13

X

12

X

Mini Card1 (WLAN)

Fingerprint

X

X

X

10

0

11

Mini Card1(WLAN)

Pair

4

5

2

3

1

Device

6

7

8

9

BLUETOOTH

ESATA / USB COMBO

CARD READER

X

CAMERA

Mini Card2 (WWAN)

X

Mini Card2(WWAN)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DP_COMP

FDI_TXP4FDI_TXP5

DMI_TXN0DMI_TXN1DMI_TXN2DMI_TXN3

DMI_TXP0DMI_TXP1DMI_TXP2DMI_TXP3

DMI_RXN0DMI_RXN1DMI_RXN2DMI_RXN3

DMI_RXP0DMI_RXP1DMI_RXP2DMI_RXP3

FDI_TXP6FDI_TXP7

FDI_TXN0FDI_TXN1

FDI_TXN3FDI_TXN4FDI_TXN5FDI_TXN6FDI_TXN7

FDI_TXN2

FDI_TXP0FDI_TXP1FDI_TXP2FDI_TXP3

PEG_IRCOMP_R

1D05V_VTT

1D05V_VTT

DMI_RXN[3:0](19)

DMI_RXP[3:0](19)

DMI_TXN[3:0](19)

DMI_TXP[3:0](19)

FDI_TXN[7:0](19)

FDI_TXP[7:0](19)

FDI_FSYNC0(19)FDI_FSYNC1(19)

FDI_INT(19)

FDI_LSYNC0(19)FDI_LSYNC1(19)

Title


Date: Sheet of


Nirvana 13 A00

CPU 1/7(PEG/DMI/FDI/eDP)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Signal Routing Guideline:PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

Note:Intel DMI supports both LaneReversal and polarity inversionbut only at PCH side. This isenabled via a soft strap.

Note:Lane reversal does not apply toFDI sideband signals.

Note:Intel FDI supports both LaneReversal and polarity inversionbut only at PCH side. This isenabled via a soft strap.

Signal Routing Guideline:EDP_ICOMPO keep W/S=12/15 mils and routinglength less than 500 mils.EDP_COMPIO keep W/S=4/15 mils and routinglength less than 500 mils.

NOTE.

Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Stuff to disable internal graphics

function for power saving.

SSID = CPU

NOTE.

If PEG is not implemented, the RX&TX pairs can be left as No Connect

NOTE:

Select a Fast FET similar to 2N7002E whose rise/

fall time is less than 6 ns. If HPD on eDP interface is

disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up

resistor on the motherboard.

1 2R401 24D9R2F-L-GPR401 24D9R2F-L-GP

DMI_RX#0B27

DMI_RX#1B25

DMI_RX#2A25

DMI_RX#3B24

DMI_RX0B28

DMI_RX1B26

DMI_RX2A24

DMI_RX3B23

DMI_TX#0G21

DMI_TX#1E22

DMI_TX#2F21

DMI_TX#3D21

DMI_TX0G22

DMI_TX1D22

DMI_TX3C21DMI_TX2F20

FDI0_TX#0A21

FDI0_TX#1H19

FDI0_TX#2E19

FDI0_TX#3F18

FDI1_TX#0B21

FDI1_TX#1C20

FDI1_TX#2D18

FDI1_TX#3E17

FDI0_TX0A22

FDI0_TX1G19

FDI0_TX2E20

FDI0_TX3G18

FDI1_TX0B20

FDI1_TX1C19

FDI1_TX2D19

FDI1_TX3F17

FDI0_FSYNCJ18

FDI1_FSYNCJ17

FDI_INTH20

FDI0_LSYNCJ19

FDI1_LSYNCH17

PEG_ICOMPI J22

PEG_ICOMPO J21

PEG_RCOMPO H22

PEG_RX#0 K33

PEG_RX#1 M35

PEG_RX#2 L34

PEG_RX#3 J35

PEG_RX#4 J32

PEG_RX#5 H34

PEG_RX#6 H31

PEG_RX#7 G33

PEG_RX#8 G30

PEG_RX#9 F35

PEG_RX#10 E34

PEG_RX#11 E32

PEG_RX#12 D33

PEG_RX#13 D31

PEG_RX#14 B33

PEG_RX#15 C32

PEG_RX0 J33

PEG_RX1 L35

PEG_RX2 K34

PEG_RX3 H35

PEG_RX4 H32

PEG_RX5 G34

PEG_RX6 G31

PEG_RX7 F33

PEG_RX8 F30

PEG_RX9 E35

PEG_RX10 E33

PEG_RX11 F32

PEG_RX12 D34

PEG_RX13 E31

PEG_RX14 C33

PEG_RX15 B32

PEG_TX#0 M29

PEG_TX#1 M32

PEG_TX#2 M31

PEG_TX#3 L32

PEG_TX#4 L29

PEG_TX#5 K31

PEG_TX#6 K28

PEG_TX#7 J30

PEG_TX#8 J28

PEG_TX#9 H29

PEG_TX#10 G27

PEG_TX#11 E29

PEG_TX#12 F27

PEG_TX#13 D28

PEG_TX#14 F26

PEG_TX#15 E25

PEG_TX0 M28

PEG_TX1 M33

PEG_TX2 M30

PEG_TX3 L31

PEG_TX4 L28

PEG_TX5 K30

PEG_TX6 K27

PEG_TX7 J29

PEG_TX8 J27

PEG_TX9 H28

PEG_TX10 G28

PEG_TX11 E28

PEG_TX12 F28

PEG_TX13 D27

PEG_TX14 E26

PEG_TX15 D25

EDP_AUXC15

EDP_AUX#D15

EDP_TX0C17

EDP_TX1F16

EDP_TX2C16

EDP_TX3G15

EDP_TX#0C18

EDP_TX#1E16

EDP_TX#2D16

EDP_TX#3F15

EDP_COMPIOA18

EDP_HPDB16EDP_ICOMPOA17

PCI EXPRESS* - GRAPHICS

DMI

Intel(R) FDI

eDP

1 OF 9

SANDY

CPU1A

SANDY

PCI EXPRESS* - GRAPHICS

DMI

Intel(R) FDI

eDP

1 OF 9

SANDY

CPU1A

SANDY

1 2R402 24D9R2F-L-GPR402 24D9R2F-L-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SKTOCC#_R

H_CATERR#

SM_RCOMP_0SM_RCOMP_1SM_RCOMP_2

XDP_TRST#

XDP_TCLKXDP_TDO

XDP_TDIXDP_TMS

XDP_TCLKXDP_TMSXDP_TRST#

XDP_DBRESET#

CLK_DP_P_RCLK_DP_N_R

VDDPWRGOOD

H_CPUPWRGD_R

H_CPUPWRGD_R

H_PROCHOT#

XDP_TDO

XDP_DBRESET#

XDP_TDI

H_PROCHOT#_R

BUF_CPU_RST#

BUF_CPU_RST#BUFO_CPU_RST#

XDP_DBRESET#

1D05V_VTT

1D05V_VTT

1D05V_VTT

3D3V_S0

3D3V_S0

1D05V_VTT

H_PM_SYNC(19)

PM_DRAM_PWRGD(19,37)

H_PECI(22,27)

H_CPUPWRGD(22,36)

H_THERMTRIP#(22,36)

H_PROCHOT#(27,40,42)

CLK_EXP_P (20)CLK_EXP_N (20)H_SNB_IVB#(18)

XDP_DBRESET# (19)

VDDPWRGOOD(37)

SM_DRAMRST# (37)

PLT_RST#(18,27,65,71,82)

PLT_RST#(18,27,65,71,82)

Title


Date: Sheet of


Nirvana 13 A00

CPU 2/7(THERMAL/CLOCK/PM )


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

SSID = CPU

20100622 V1.2

CRB : 47pf

CEKLT:43pf

Connect EC to PROCHOT# through inverting OD buffer.

Disabling Guidelines:If motherboard only supports external graphics:Connect DPLL_REF_SSCLK on Processor to GND through1K +/- 5% resistor.Connect DPLL_REF_SSCLK# on Processor to VCCPthrough 1K +/- 5% resistorpower (~15 mW) may bewasted.

Signal Routing Guideline:SM_RCOMP keep routing length less than 500 mils.

Buffered reset to CPU

20100722 Modify:

Change R516 10K from 1K

20110104 A00:

merge R512,R514 to RN502 1k array resistor.

20110113 A00:

Swap RN502 base on swap report.

1TP502TPAD14-GP TP502TPAD14-GP

12

R51875R2J-1-GP

DY R51875R2J-1-GP

DY

1 2R50310KR2J-3-GP

R50310KR2J-3-GP

12

C501SC220P50V2KX-3GPDY C501SC220P50V2KX-3GPDY

1 2R517 43R2J-GP

DYR517 43R2J-GP

DY

IN B1

IN A2

GND3

OUT Y4

VCC5

U501

74VHC1G09DFT2G-GP

73.01G09.AAH

DY

U501

74VHC1G09DFT2G-GP

73.01G09.AAH

DY

1 2R508 200R2F-L-GPR508 200R2F-L-GP

1 2R5050R2J-2-GPDY

R5050R2J-2-GPDY


1 2R510

1K5R2F-2-GP

R510

1K5R2F-2-GP

SM_RCOMP1A5

SM_RCOMP2A4

SM_DRAMRST#R8

SM_RCOMP0AK1

BCLK#A27

BCLKA28

DPLL_REF_SSCLK#A15

DPLL_REF_SSCLKA16

CATERR#AL33

PECIAN33

PROCHOT#AL32

THERMTRIP#AN32

SM_DRAMPWROKV8

RESET#AR33

PRDY#AP29

PREQ#AP27

TCKAR26

TMSAR27

TRST#AP30

TDIAR28

TDOAP26

DBR#AL35

BPM#0AT28

BPM#1AR29

BPM#2AR30

BPM#3AT30

BPM#4AP32

BPM#5AR31

BPM#6AT31

BPM#7AR32

PM_SYNCAM34

SKTOCC#AN34

SNB_IVB#C26

UNCOREPWRGOODAP33

CLOCKS

MISC

THERMAL

PWR MANAGEMENT

DDR3

MISC

JTAG & BPM

2 OF 9

SANDY

CPU1B

SANDY

CLOCKS

MISC

THERMAL

PWR MANAGEMENT

DDR3

MISC

JTAG & BPM

2 OF 9

SANDY

CPU1B

SANDY

12

R509750R2F-GPR509750R2F-GP

1 2

R501

62R2J-GP

R501

62R2J-GP

1 2

R504

0R0402-PAD

R504

0R0402-PAD

1 2R511 51R2J-2-GPR511 51R2J-2-GP

1234 5

678

RN501

SRN51J-1-GP

RN501

SRN51J-1-GP

1 2 R51610KR2J-3-GPR51610KR2J-3-GP

12 3

4

RN502

SRN1KJ-7-GP

RN502

SRN1KJ-7-GP

12

C502SC47P50V2JN-3GPC502SC47P50V2JN-3GP

12

R5150R2J-2-GPDY R5150R2J-2-GPDY

1 2R5024K99R2F-L-GP

R5024K99R2F-L-GP

1 2R507 25D5R2F-GPR507 25D5R2F-GP1 2R506 140R2F-GPR506 140R2F-GP

12

C503SCD1U10V2KX-5GP

DY C503SCD1U10V2KX-5GP

DY

1 2

R513

56R2J-4-GP

R513

56R2J-4-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11

M_B_DQ15

M_B_DQ13M_B_DQ12

M_B_DQ14

M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19

M_B_DQ23

M_B_DQ21M_B_DQ20

M_B_DQ22

M_B_DQ28

M_B_DQ26

M_B_DQ29

M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30


M_B_DQ39

M_B_DQ37M_B_DQ36

M_B_DQ38

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ46


M_B_DQ55

M_B_DQ53M_B_DQ52

M_B_DQ54

M_B_DQ60

M_B_DQ58

M_B_DQ61

M_B_DQ57

M_B_DQ63

M_B_DQ56

M_B_DQ59

M_B_DQ62

M_B_DQ[63:0]

M_A_DQS4M_A_DQS3

M_A_DQS5M_A_DQS6M_A_DQS7

M_A_DQS2M_A_DQS1M_A_DQS0

M_A_A7

M_A_A12

M_A_A14M_A_A13

M_A_A9

M_A_A15

M_A_A10

M_A_A0

M_A_A6

M_A_A8

M_A_A1M_A_A2M_A_A3M_A_A4M_A_A5

M_A_A11

M_A_DQS#4M_A_DQS#5M_A_DQS#6M_A_DQS#7

M_A_DQS#3M_A_DQS#2M_A_DQS#1M_A_DQS#0

M_A_DQ44

M_A_DQ36

M_A_DQ47

M_A_DQ40M_A_DQ39

M_A_DQ37

M_A_DQ35M_A_DQ34

M_A_DQ59

M_A_DQ54M_A_DQ53

M_A_DQ63

M_A_DQ60M_A_DQ61

M_A_DQ58

M_A_DQ51

M_A_DQ48

M_A_DQ57

M_A_DQ55

M_A_DQ49M_A_DQ50

M_A_DQ62

M_A_DQ52

M_A_DQ56

M_A_DQ[63:0]

M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3

M_A_DQ7

M_A_DQ5M_A_DQ4

M_A_DQ6

M_A_DQ12

M_A_DQ10

M_A_DQ13

M_A_DQ9M_A_DQ8

M_A_DQ11

M_A_DQ15M_A_DQ14

M_A_DQ27

M_A_DQ25

M_A_DQ20M_A_DQ19

M_A_DQ30

M_A_DQ18

M_A_DQ16

M_A_DQ28

M_A_DQ17

M_A_DQ26

M_A_DQ31

M_A_DQ29

M_A_DQ22M_A_DQ23M_A_DQ24

M_A_DQ21

M_A_DQ46

M_A_DQ42

M_A_DQ38

M_A_DQ32

M_A_DQ45

M_A_DQ33

M_A_DQ43

M_A_DQ41

M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7

M_B_DQS#3M_B_DQS#2M_B_DQS#1M_B_DQS#0

M_B_DQS#7M_B_DQS#6M_B_DQS#5M_B_DQS#4

M_B_A5M_B_A6M_B_A7M_B_A8M_B_A9M_B_A10M_B_A11M_B_A12M_B_A13M_B_A14M_B_A15

M_B_A4M_B_A3M_B_A2M_B_A1M_B_A0

M_B_CAS#(15)M_B_RAS#(15)M_B_WE#(15)

M_A_DQS#[7:0] (14)

M_A_A[15:0] (14)

M_A_DQS[7:0] (14)

M_A_DIM0_CKE0 (14)

M_A_DIM0_CKE1 (14)

M_A_DIM0_CS#0 (14)M_A_DIM0_CS#1 (14)

M_A_DIM0_ODT0 (14)M_A_DIM0_ODT1 (14)

M_A_DIM0_CLK_DDR0 (14)M_A_DIM0_CLK_DDR#0 (14)


M_B_BS0(15)M_B_BS1(15)M_B_BS2(15)

M_B_A[15:0] (15)

M_B_DQS[7:0] (15)

M_B_DQS#[7:0] (15)

M_B_DIM0_CKE0 (15)

M_B_DIM0_CKE1 (15)

M_B_DIM0_CS#0 (15)M_B_DIM0_CS#1 (15)

M_B_DIM0_ODT0 (15)M_B_DIM0_ODT1 (15)

M_B_DIM0_CLK_DDR0 (15)M_B_DIM0_CLK_DDR#0 (15)


M_A_DQ[63:0](14)

M_B_DQ[63:0](15)

M_A_BS0(14)M_A_BS1(14)M_A_BS2(14)

M_A_CAS#(14)M_A_RAS#(14)M_A_WE#(14)

Title


Date: Sheet of


Nirvana 13 A00

CPU 3/7(DDR)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CPU 3/7(DDR)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CPU 3/7(DDR)


<Core Design>

SSID = CPU

SA_BS0AE10

SA_BS1AF10

SA_BS2V6

SA_CAS#AE8

SA_RAS#AD9

SA_WE#AF9

SA_CLK0 AB6

SA_CLK1 AA5

SA_CLK#0 AA6

SA_CLK#1 AB5

SA_CKE0 V9

SA_CKE1 V10

SA_CS#0 AK3

SA_CS#1 AL3

SA_ODT0 AH3

SA_ODT1 AG3

SA_DQS0 D4

SA_DQS#0 C4

SA_DQS1 F6

SA_DQS#1 G6

SA_DQS2 K3

SA_DQS#2 J3

SA_DQS3 N6

SA_DQS#3 M6

SA_DQS4 AL5

SA_DQS#4 AL6

SA_DQS5 AM9

SA_DQS#5 AM8

SA_DQS6 AR11

SA_DQS#6 AR12

SA_DQS7 AM14

SA_DQS#7 AM15

SA_MA0 AD10

SA_MA1 W1

SA_MA2 W2

SA_MA3 W7

SA_MA4 V3

SA_MA5 V2

SA_MA6 W3

SA_MA7 W6

SA_MA8 V1

SA_MA9 W5

SA_MA10 AD8

SA_MA11 V4

SA_MA12 W4

SA_MA13 AF8

SA_MA14 V5

SA_MA15 V7

SA_DQ0C5

SA_DQ1D5

SA_DQ2D3

SA_DQ3D2

SA_DQ4D6

SA_DQ5C6

SA_DQ6C2

SA_DQ7C3

SA_DQ8F10

SA_DQ9F8

SA_DQ10G10

SA_DQ11G9

SA_DQ12F9

SA_DQ13F7

SA_DQ14G8

SA_DQ15G7

SA_DQ16K4

SA_DQ17K5

SA_DQ18K1

SA_DQ19J1

SA_DQ20J5

SA_DQ21J4

SA_DQ22J2

SA_DQ23K2

SA_DQ24M8

SA_DQ25N10

SA_DQ26N8

SA_DQ27N7

SA_DQ28M10

SA_DQ29M9

SA_DQ30N9

SA_DQ31M7

SA_DQ32AG6

SA_DQ33AG5

SA_DQ34AK6

SA_DQ35AK5

SA_DQ36AH5

SA_DQ37AH6

SA_DQ38AJ5

SA_DQ39AJ6

SA_DQ40AJ8

SA_DQ41AK8

SA_DQ42AJ9

SA_DQ43AK9

SA_DQ44AH8

SA_DQ45AH9

SA_DQ46AL9

SA_DQ47AL8

SA_DQ48AP11

SA_DQ49AN11

SA_DQ50AL12

SA_DQ51AM12

SA_DQ52AM11

SA_DQ53AL11

SA_DQ54AP12

SA_DQ55AN12

SA_DQ56AJ14

SA_DQ57AH14

SA_DQ58AL15

SA_DQ59AK15

SA_DQ60AL14

SA_DQ61AK14

SA_DQ62AJ15

SA_DQ63AH15

SA_CLK2 AB4

SA_CLK#2 AA4

SA_CLK3 AB3

SA_CLK#3 AA3

SA_CKE2 W9

SA_CKE3 W10

SA_CS#2 AG1

SA_CS#3 AH1

SA_ODT2 AG2

SA_ODT3 AH2DDR SYSTEM MEMORY A

3 OF 9

SANDY

CPU1C

SANDY

DDR SYSTEM MEMORY A

3 OF 9

SANDY

CPU1C

SANDY

SB_BS0AA9

SB_BS1AA7

SB_BS2R6

SB_CAS#AA10

SB_RAS#AB8

SB_WE#AB9

SB_CLK0 AE2

SB_CLK1 AE1

SB_CLK#0 AD2

SB_CLK#1 AD1

SB_CKE0 R9

SB_CKE1 R10

SB_ODT0 AE4

SB_ODT1 AD4

SB_DQS4 AN6

SB_DQS#4 AN5

SB_DQS5 AP8

SB_DQS#5 AP9

SB_DQS6 AK11

SB_DQS#6 AK12

SB_DQS7 AP14

SB_DQS#7 AP15

SB_DQS0 C7

SB_DQS#0 D7

SB_DQS1 G3

SB_DQS#1 F3

SB_DQS2 J6

SB_DQS#2 K6

SB_DQS3 M3

SB_DQS#3 N3

SB_MA0 AA8

SB_MA1 T7

SB_MA2 R7

SB_MA3 T6

SB_MA4 T2

SB_MA5 T4

SB_MA6 T3

SB_MA7 R2

SB_MA8 T5

SB_MA9 R3

SB_MA10 AB7

SB_MA11 R1

SB_MA12 T1

SB_MA13 AB10

SB_MA14 R5

SB_MA15 R4

SB_DQ0C9

SB_DQ1A7

SB_DQ2D10

SB_DQ3C8

SB_DQ4A9

SB_DQ5A8

SB_DQ6D9

SB_DQ7D8

SB_DQ8G4

SB_DQ9F4

SB_DQ10F1

SB_DQ11G1

SB_DQ12G5

SB_DQ13F5

SB_DQ14F2

SB_DQ15G2

SB_DQ16J7

SB_DQ17J8

SB_DQ18K10

SB_DQ19K9

SB_DQ20J9

SB_DQ21J10

SB_DQ22K8

SB_DQ23K7

SB_DQ24M5

SB_DQ25N4

SB_DQ26N2

SB_DQ27N1

SB_DQ28M4

SB_DQ29N5

SB_DQ30M2

SB_DQ31M1

SB_DQ32AM5

SB_DQ33AM6

SB_DQ34AR3

SB_DQ35AP3

SB_DQ36AN3

SB_DQ37AN2

SB_DQ38AN1

SB_DQ39AP2

SB_DQ40AP5

SB_DQ41AN9

SB_DQ42AT5

SB_DQ43AT6

SB_DQ44AP6

SB_DQ45AN8

SB_DQ46AR6

SB_DQ47AR5

SB_DQ48AR9

SB_DQ49AJ11

SB_DQ50AT8

SB_DQ51AT9

SB_DQ52AH11

SB_DQ53AR8

SB_DQ54AJ12

SB_DQ55AH12

SB_DQ56AT11

SB_DQ57AN14

SB_DQ58AR14

SB_DQ59AT14

SB_DQ60AT12

SB_DQ61AN15

SB_DQ62AR15

SB_DQ63AT15

SB_CLK2 AB2

SB_CLK#2 AA2

SB_CKE2 T9

SB_CLK3 AA1

SB_CLK#3 AB1

SB_CKE3 T10

SB_CS#0 AD3

SB_CS#1 AE3

SB_CS#2 AD6

SB_CS#3 AE6

SB_ODT2 AD5

SB_ODT3 AE5

DDR SYSTEM MEMORY B

4 OF 9

SANDY

CPU1D

SANDY

DDR SYSTEM MEMORY B

4 OF 9

SANDY

CPU1D

SANDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_VCCP_SEL

CFG6CFG7

RSVD#AN35RSVD#AM35

CFG7

CFG2

M_VREF_DQ_DIMM0_C

CFG4

CFG2

CFG6

CFG5

CFG5

M_VREF_DQ_DIMM1_C

CFG4

M_VREF_DQ_DIMM1M_VREF_DQ_DIMM0

M_VREF_CA_DIMM0

M_VREF_CA_DIMM1

Title


Date: Sheet of


Nirvana 13 A00

CPU 4/7(RESERVED)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CPU 4/7(RESERVED)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CPU 4/7(RESERVED)


<Core Design>

SSID = CPU

0:Lane Reversed

1: PEG Train immediately following xxRESETB de assertionCFG7

PEG DEFER TRAINING

PEG Static Lane Reversal

1: Normal Operation; Lane # definition matches socket pin map definitionCFG2

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

0: PEG Wait for BIOS for training

B4:VREF_DQ CHA

D1:VREF_DQ CHB

M3 - Processor GeneratedSO-DIMM VREF_DQ

20 mils

CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled

PCIE Port Bifurcation Straps

0: Enabled; An external Display Port device is connected to the Embedded Display Port

Display Port Presence Strap

1: Disabled; No Physical Display Port attached to Embedded Display Port

CFG4

12

R712

1KR2F-3-GP

R712

1KR2F-3-GP

12

R701

1K

R2J-1

-GP

DYR701

1K

R2J-1

-GP

DY

1TP714 TPAD14-GPTP714 TPAD14-GP

12

R711

1KR2F-3-GP

R711

1KR2F-3-GP

12

R7051KR2J-1-GPDYR7051KR2J-1-GPDY

CFG0AK28

CFG1AK29

CFG2AL26

CFG3AL27

CFG4AK26

CFG5AL29

CFG6AL30

CFG7AM31

CFG8AM32

CFG9AM30

CFG10AM28

CFG11AM26

CFG12AN28

CFG13AN31

CFG14AN26

CFG15AM27

CFG16AK31

CFG17AN29

RSVD#AM33 AM33

RSVD#AJ27 AJ27

RSVD#J16 J16

RSVD#AT34 AT34

RSVD#H16 H16

RSVD#G16 G16

RSVD#AR35 AR35

RSVD#AT33 AT33

RSVD#AR34 AR34

RSVD#AT2 AT2

RSVD#AT1 AT1

RSVD#AR1 AR1

RSVD#B34 B34

RSVD#A33 A33

RSVD#A34 A34

RSVD#B35 B35

RSVD#C35 C35

RSVD#AJ32 AJ32

RSVD#AK32 AK32

RSVD#AE7 AE7

RSVD#AK2 AK2

RSVD#L7 L7

RSVD#AG7 AG7

RSVD#J15J15

RSVD#C30C30RSVD#D23D23

RSVD#A31A31

RSVD#B30B30

RSVD#D30D30RSVD#B29B29

RSVD#A30A30RSVD#B31B31

RSVD#C29C29

RSVD#J20J20

RSVD#T8 T8

RSVD#B4B4

RSVD#D1D1

RSVD#F25F25

RSVD#F24F24

RSVD#D24D24

RSVD#G25G25

RSVD#G24G24

RSVD#E23E23

RSVD#W8 W8

RSVD#AT26 AT26

RSVD#B18B18

RSVD#AP35 AP35

RSVD#F23F23

RSVD#AJ26AJ26

RSVD#AJ31AJ31

RSVD#AH31AH31

RSVD#AJ33AJ33

RSVD#AH33AH33

RSVD#AH27 AH27

RSVD#A19A19

RSVD#AN35 AN35

RSVD#AM35 AM35

RESERVED

5 OF 9

SANDY

CPU1E

SANDY

RESERVED

5 OF 9

SANDY

CPU1E

SANDY

1 2R708 0R2J-2-GPDY

R708 0R2J-2-GPDY

12

R704

1K

R2J-1

-GP

DYR704

1K

R2J-1

-GP

DY

1 2R710 0R2J-2-GPDYR710 0R2J-2-GPDY


12

R7021KR2J-1-GPR7021KR2J-1-GP


12

R7033K3R2F-2-GPDY R7033K3R2F-2-GPDY


1 2R709 0R2J-2-GPDY

R709 0R2J-2-GPDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_CPU_SVIDCLKH_CPU_SVIDALRT#

H_CPU_SVIDDAT

VR_SVID_ALERT#

H_CPU_SVIDCLK

H_CPU_SVIDDAT

VCC_CORE

1D05V_VTT

1D05V_VTT

1D05V_VTT

VCC_CORE

VCC_CORE

VCCSENSE (42)VSSSENSE (42)

VCCIO_SENSE (45)

H_CPU_SVIDDAT (42)

VR_SVID_ALERT# (42)

H_CPU_SVIDCLK (42)

VSSIO_SENSE (45)

Title


Date: Sheet of

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13 A00

CPU 5/7(VCC_CORE)


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

CPU 5/7(VCC_CORE)


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

CPU 5/7(VCC_CORE)


<Core Design>

No-stuff sites outside the socket may be removed.

No-stuff sites inside the socket cavity need to remain.

VCC Output Decoupling Recommendation:

4 x 470 uF at Bottom Socket Edge

8 x 22 uF at Top Socket Cavity

8 x 22 uF at Top Socket Edge

8 x 22 uF at Bottom Socket Cavity

VCCIO Output Decoupling Recommendation:

2 x 330 uF (3 x 330 uF for 2012 capable designs)

5 x 22 uF & 5 x 0805 no-stuff at Bottom

7 x 22 uF & 2 x 0805 no-stuff at Top

These resistors need to close to power IC.

SSID = CPU

53A

PROCESSOR CORE POWER

20101231 A00:

Merge R801,R802 to RN801 100 ohm array resistor.

20110113 A00:

Change RN801 to 100 ohm 1% (66.10156.04L).

20110113 A00:

Swap RN801 base on swap report.

12

C8

31

SC

10

U6

D3

V5

KX

-1G

PC

83

1S

C1

0U

6D

3V

5K

X-1

GP

12

C8

07

SC

10

U6

D3

V3

MX

-GP

DY

C8

07

SC

10

U6

D3

V3

MX

-GP

DY

12

C8

29

SC

4D

7U

6D

3V

5K

X-3

GP

C8

29

SC

4D

7U

6D

3V

5K

X-3

GP

12

C8

18

SC

10

U6

D3

V5

KX

-1G

P

DY

C8

18

SC

10

U6

D3

V5

KX

-1G

P

DY

12

C8

44

SC

10

U6

D3

V5

KX

-1G

PC

84

4S

C1

0U

6D

3V

5K

X-1

GP

12

C8

36

SC

10

U6

D3

V5

KX

-1G

PC

83

6S

C1

0U

6D

3V

5K

X-1

GP

12

C8

26

SC

10

U6

D3

V5

KX

-1G

PC

82

6S

C1

0U

6D

3V

5K

X-1

GP

12

C8

40

SC

10

U6

D3

V5

KX

-1G

PC

84

0S

C1

0U

6D

3V

5K

X-1

GP

12

C8

22

SC

22

U6

D3

V5

MX

-2G

PC

82

2S

C2

2U

6D

3V

5M

X-2

GP

12

C8

23

SC

22

U6

D3

V5

MX

-2G

PC

82

3S

C2

2U

6D

3V

5M

X-2

GP

12

C8

24

SC

22

U6

D3

V5

MX

-2G

PC

82

4S

C2

2U

6D

3V

5M

X-2

GP

12

C8

25

SC

22

U6

D3

V5

MX

-2G

PC

82

5S

C2

2U

6D

3V

5M

X-2

GP

12

C8

30

SC

10

U6

D3

V5

KX

-1G

PC

83

0S

C1

0U

6D

3V

5K

X-1

GP

VCC_SENSEAJ35

VSS_SENSEAJ34

VIDALERT#AJ29

VIDSCLKAJ30

VIDSOUTAJ28

VSSIO_SENSEA10

VCCAG35

VCCAG34

VCCAG33

VCCAG32

VCCAG31

VCCAG30

VCCAG29

VCCAG28

VCCAG27

VCCAG26

VCCAF35

VCCAF34

VCCAF33

VCCAF32

VCCAF31

VCCAF30

VCCAF29

VCCAF28

VCCAF27

VCCAF26

VCCAD35

VCCAD34

VCCAD33

VCCAD32

VCCAD31

VCCAD30

VCCAD29

VCCAD28

VCCAD27

VCCAD26

VCCAC35

VCCAC34

VCCAC33

VCCAC32

VCCAC31

VCCAC30

VCCAC29

VCCAC28

VCCAC27

VCCAC26

VCCAA35

VCCAA34

VCCAA33

VCCAA32

VCCAA31

VCCAA30

VCCAA29

VCCAA28

VCCAA27

VCCAA26

VCCY35

VCCY34

VCCY33

VCCY32

VCCY31

VCCY30

VCCY29

VCCY28

VCCY27

VCCY26

VCCV35

VCCV34

VCCV33

VCCV32

VCCV31

VCCV30

VCCV29

VCCV28

VCCV27

VCCV26

VCCU35

VCCU34

VCCU33

VCCU32

VCCU31

VCCU30

VCCU29

VCCU28

VCCU27

VCCU26

VCCR35

VCCR34

VCCR33

VCCR32

VCCR31

VCCR30

VCCR29

VCCR28

VCCR27

VCCR26

VCCP35

VCCP34

VCCP33

VCCP32

VCCP31

VCCP30

VCCP29

VCCP28

VCCP27

VCCP26

VCCIOAH13

VCCIOJ11

VCCIOG12

VCCIOF14

VCCIOF13

VCCIOF12

VCCIOF11

VCCIOE14

VCCIOE12

VCCIOAH10

VCCIOAG10

VCCIOAC10

VCCIOY10

VCCIOU10

VCCIOP10

VCCIOL10

VCCIOJ14

VCCIOJ13

VCCIOJ12

VCCIOH14

VCCIOH12

VCCIOH11

VCCIOG14

VCCIOG13

VCCIOE11

VCCIOC12

VCCIOC11

VCCIOB14

VCCIOB12

VCCIOA14

VCCIOA13

VCCIOA12

VCCIOA11

VCCIOD14

VCCIOD13

VCCIOD12

VCCIOD11

VCCIOC14

VCCIOC13

VCCIO_SENSEB10

VCCIOJ23

POWER

CORE SUPPLY

PEG AND DDR

SENSE LINES

SVID

6 OF 9

SANDY

CPU1F

SANDY

POWER

CORE SUPPLY

PEG AND DDR

SENSE LINES

SVID

6 OF 9

SANDY

CPU1F

SANDY

12

C8

28

SC

22

U6

D3

V5

MX

-2G

PC

82

8S

C2

2U

6D

3V

5M

X-2

GP

1 2R804 130R2F-1-GPR804 130R2F-1-GP

1 2R806 54D9R2F-L1-GPDYR806 54D9R2F-L1-GPDY

12

C8

04

SC

10

U6

D3

V5

KX

-1G

P

DY

C8

04

SC

10

U6

D3

V5

KX

-1G

P

DY

12

C8

39

SC

4D

7U

6D

3V

5K

X-3

GP

C8

39

SC

4D

7U

6D

3V

5K

X-3

GP

12

C8

21

SC

4D

7U

6D

3V

5K

X-3

GP

C8

21

SC

4D

7U

6D

3V

5K

X-3

GP

12

C8

02

SC

10

U6

D3

V5

KX

-1G

P

DY

C8

02

SC

10

U6

D3

V5

KX

-1G

P

DY

12

C8

34

SC

10

U6

D3

V5

KX

-1G

PC

83

4S

C1

0U

6D

3V

5K

X-1

GP

12

C8

27

SC

22

U6

D3

V5

MX

-2G

PC

82

7S

C2

2U

6D

3V

5M

X-2

GP

12

C8

06

SC

10

U6

D3

V3

MX

-GP

DY

C8

06

SC

10

U6

D3

V3

MX

-GP

DY

12 3

4

R1

R2

RN801

SRN100F-1-GP

R1

R2

RN801

SRN100F-1-GP

12

C8

43

SC

4D

7U

6D

3V

5K

X-3

GP

C8

43

SC

4D

7U

6D

3V

5K

X-3

GP

12

C8

09

SC

10

U6

D3

V5

KX

-1G

PC

80

9S

C1

0U

6D

3V

5K

X-1

GP

12

C8

45

SC

10

U6

D3

V5

KX

-1G

PC

84

5S

C1

0U

6D

3V

5K

X-1

GP

1 2R805 75R2J-1-GPR805 75R2J-1-GP

12

C8

08

SC

10

U6

D3

V3

MX

-GP

DY

C8

08

SC

10

U6

D3

V3

MX

-GP

DY

12

C8

11

SC

22

U6

D3

V5

MX

-2G

PC

81

1S

C2

2U

6D

3V

5M

X-2

GP

12

C8

35

SC

10

U6

D3

V5

KX

-1G

PC

83

5S

C1

0U

6D

3V

5K

X-1

GP

12

C8

42

SC

10

U6

D3

V5

KX

-1G

PC

84

2S

C1

0U

6D

3V

5K

X-1

GP

12

C8

20

SC

22

U6

D3

V5

MX

-2G

PC

82

0S

C2

2U

6D

3V

5M

X-2

GP

12

C8

05

SC

10

U6

D3

V3

MX

-GP

DY

C8

05

SC

10

U6

D3

V3

MX

-GP

DY

12

C8

33

SC

10

U6

D3

V5

KX

-1G

PC

83

3S

C1

0U

6D

3V

5K

X-1

GP

12

C8

01

SC

10

U6

D3

V5

KX

-1G

P

DY

C8

01

SC

10

U6

D3

V5

KX

-1G

P

DY

12

C8

10

SC

10

U6

D3

V5

KX

-1G

PC

81

0S

C1

0U

6D

3V

5K

X-1

GP

12

C8

37

SC

22

U6

D3

V5

MX

-2G

PC

83

7S

C2

2U

6D

3V

5M

X-2

GP

12

C8

32

SC

22

U6

D3

V5

MX

-2G

PC

83

2S

C2

2U

6D

3V

5M

X-2

GP

12

C8

41

SC

10

U6

D3

V5

KX

-1G

PC

84

1S

C1

0U

6D

3V

5K

X-1

GP

12

C8

03

SC

10

U6

D3

V5

KX

-1G

PC

80

3S

C1

0U

6D

3V

5K

X-1

GP

12

C8

38

SC

10

U6

D3

V5

KX

-1G

PC

83

8S

C1

0U

6D

3V

5K

X-1

GP

1 2R803 43R2J-GPR803 43R2J-GP

12

C8

15

SC

22

U6

D3

V5

MX

-2G

PC

81

5S

C2

2U

6D

3V

5M

X-2

GP

12

C8

19

SC

22

U6

D3

V5

MX

-2G

PC

81

9S

C2

2U

6D

3V

5M

X-2

GP

12

C8

17

SC

22

U6

D3

V5

MX

-2G

PC

81

7S

C2

2U

6D

3V

5M

X-2

GP

12

C8

16

SC

22

U6

D3

V5

MX

-2G

PC

81

6S

C2

2U

6D

3V

5M

X-2

GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+V_SM_VREF_CNT

H_FC_C22VCCSA_SEL

VCCUSA_SENSE

VSS_AXG_SENSEVCC_AXG_SENSE

1D5V_S0

VCC_GFXCORE

1D8V_S0

0D85V_S0

1D5V_S3

VCC_GFXCOREVCC_AXG_SENSE (42)VSS_AXG_SENSE (42)

VCCSA_SEL (48)

VCCUSA_SENSE (48)

+V_SM_VREF_CNT (37)

H_FC_C22 (48)

Title


Date: Sheet of


Nirvana 13 A00

CPU 6/7(VCC_GFX_CORE)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

PROCESSOR VCCSA: 6A

VDDQ Output Decoupling Recommendation:1 x 330 uF6 x 10 uF

PROCESSOR VDDQ: 10A

VCCSA Output Decoupling Recommendation:1 x 330 uF2 x 10 uF at Bottom Socket Cavity1 x 10 uF at Bottom Socket Edge

Routing Guideline:Power from DDR_VREF_S3 and +V_SM_VREF_CNTshould have 10 mils trace width.

Refer to the latest Huron River Mainstream PDG

(Doc# 436735) for more details on S3 power

reduction implementation.

+V_SM_VREF_CNT should have 10 mil trace width

SSID = CPUVAXG Output Decoupling Recommendation:2 x 470 uF at Bottom Socket Edge2 x 22 uF at Top Socket Cavity4 x 22 uF at Top Socket Edge2 x 22 uF at Bottom Socket Cavity4 x 22 uF at Bottom Socket Edge

VCCPLL Output Decoupling Recommendation:1 x 330 uF2 x 1 uF1 x 10 uF

Disabling Guidelines for External Graphics Designs:Can connect to GND if motherboard only supports externalgraphics and if GFX VR is not stuffed.Can be left floating (Gfx VR keeps VAXG rail from floating)if the VR is stuffed

PROCESSOR VCCPLL: 1.2A

Removed DIS_ONLY Disable Resistor.

R904,R905,R901,R903

PROCESSOR VAXG: 33A

20101231 A00:Merge R906,R907 to RN902 100 ohm array resistor.20110113 A00:Change RN801 to 100 ohm 1% (66.10156.04L).20110113 A00:Swap RN902 base on swap report.

12

C923

SC

10U

6D

3V

5K

X-1

GP

C923

SC

10U

6D

3V

5K

X-1

GP

123 4

RN901SRN1KJ-7-GPRN901SRN1KJ-7-GP

12

C915

SC

10U

6D

3V

5K

X-1

GP

C915

SC

10U

6D

3V

5K

X-1

GP

12 3

4

R1

R2

RN902

SRN100F-1-GP

R1

R2

RN902

SRN100F-1-GP

12

C921

SC

10U

6D

3V

3M

X-G

P

DY

C921

SC

10U

6D

3V

3M

X-G

P

DY

12

C906

SC

4D

7U

6D

3V

5K

X-3

GP

C906

SC

4D

7U

6D

3V

5K

X-3

GP

12

C907

SC

D1U

10V

2K

X-5

GP

DY

C907

SC

D1U

10V

2K

X-5

GP

DY

12

C912

SC

10U

6D

3V

5K

X-1

GP

C912

SC

10U

6D

3V

5K

X-1

GP

12

C919

SC

D1U

10V

2K

X-5

GP

DY

C919

SC

D1U

10V

2K

X-5

GP

DY

12

C913

SC

4D

7U

6D

3V

5K

X-3

GP

C913

SC

4D

7U

6D

3V

5K

X-3

GP

12

C911

SC

10U

6D

3V

3M

X-G

P

DY

C911

SC

10U

6D

3V

3M

X-G

P

DY1

2

C920

SC

10U

6D

3V

3M

X-G

P

DY

C920

SC

10U

6D

3V

3M

X-G

P

DY

12

C905

SC

22U

6D

3V

5M

X-2

GP

C905

SC

22U

6D

3V

5M

X-2

GP

12

C924

SC

1U

10V

2K

X-1

GP

C924

SC

1U

10V

2K

X-1

GP

12

C901

SC

10U

6D

3V

5K

X-1

GP

DY

C901

SC

10U

6D

3V

5K

X-1

GP

DY

12

C918

SC

D1U

10V

2K

X-5

GP

DY

C918

SC

D1U

10V

2K

X-5

GP

DY

12

C916

SC

10U

6D

3V

5K

X-1

GP

C916

SC

10U

6D

3V

5K

X-1

GP

SM_VREF AL1

VSSAXG_SENSE AK34VAXG_SENSE AK35VAXGAT24

VAXGAT23

VAXGAT21

VAXGAT20

VAXGAT18

VAXGAT17

VAXGAR24

VAXGAR23

VAXGAR21

VAXGAR20

VAXGAR18

VAXGAR17

VAXGAP24

VAXGAP23

VAXGAP21

VAXGAP20

VAXGAP18

VAXGAP17

VAXGAN24

VAXGAN23

VAXGAN21

VAXGAN20

VAXGAN18

VAXGAN17

VAXGAM24

VAXGAM23

VAXGAM21

VAXGAM20

VAXGAM18

VAXGAM17

VAXGAL24

VAXGAL23

VAXGAL21

VAXGAL20

VAXGAL18

VAXGAL17

VAXGAK24

VAXGAK23

VAXGAK21

VAXGAK20

VAXGAK18

VAXGAK17

VAXGAJ24

VAXGAJ23

VAXGAJ21

VAXGAJ20

VAXGAJ18

VAXGAJ17

VAXGAH24

VAXGAH23

VAXGAH21

VAXGAH20

VAXGAH18

VAXGAH17

VDDQ U4

VDDQ U1

VDDQ P7

VDDQ P4

VDDQ P1

VDDQ AF7

VDDQ AF4

VDDQ AF1

VDDQ AC7

VDDQ AC4

VDDQ AC1

VDDQ Y7

VDDQ Y4

VDDQ Y1

VDDQ U7

VCCPLLB6

VCCPLLA6

VCCSA M27

VCCSA M26

VCCSA L26

VCCSA J26

VCCSA J25

VCCSA J24

VCCSA H26

VCCSA H25

VCCSA_SENSE H23

VCCSA_VID1 C24

VCCPLLA2

FC_C22 C22

POWER

GRAPHICS

DDR3 -1.5V RAILS

SENSE

LINES

1.8V RAIL

SA RAIL

VREF

MISC

7 OF 9

SANDY

CPU1G

SANDY

POWER

GRAPHICS

DDR3 -1.5V RAILS

SENSE

LINES

1.8V RAIL

SA RAIL

VREF

MISC

7 OF 9

SANDY

CPU1G

SANDY

12

C908

SC

10U

6D

3V

3M

X-G

P

DY

C908

SC

10U

6D

3V

3M

X-G

P

DY

12

C902

SC

4D

7U

6D

3V

5K

X-3

GP

C902

SC

4D

7U

6D

3V

5K

X-3

GP

12

C909

SC

10U

6D

3V

3M

X-G

P

DY

C909

SC

10U

6D

3V

3M

X-G

P

DY

12

C925

SC

D1U

10V

2K

X-5

GP

DY

C925

SC

D1U

10V

2K

X-5

GP

DY

12

C903

SC

4D

7U

6D

3V

5K

X-3

GP

C903

SC

4D

7U

6D

3V

5K

X-3

GP

12

C922

SC

1U

10V

2K

X-1

GP

C922

SC

1U

10V

2K

X-1

GP

12

TC

901

ST

330U

2V

DM

-4-G

P

79.33719.20L2nd = 77.C3371.13L

TC

901

ST

330U

2V

DM

-4-G

P

79.33719.20L2nd = 77.C3371.13L

12

C910

SC

10U

6D

3V

3M

X-G

P

DY

C910

SC

10U

6D

3V

3M

X-G

P

DY

12

C914

SC

10U

6D

3V

5K

X-1

GP

C914

SC

10U

6D

3V

5K

X-1

GP

12

C917

SC

10U

6D

3V

5K

X-1

GP

C917

SC

10U

6D

3V

5K

X-1

GP

12

C904

SC

4D

7U

6D

3V

5K

X-3

GP

C904

SC

4D

7U

6D

3V

5K

X-3

GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

CPU 7/7(VSS)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CPU 7/7(VSS)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CPU 7/7(VSS)


<Core Design>

SSID = CPU

VSST35

VSST34

VSST33

VSST32

VSST31

VSST30

VSST29

VSST28

VSST27

VSST26

VSSP9

VSSP8

VSSP6

VSSP5

VSSP3

VSSP2

VSSN35

VSSN34

VSSN33

VSSN32

VSSN31

VSSN30

VSSN29

VSSN28

VSSN27

VSSN26

VSSM34

VSSL33

VSSL30

VSSL27

VSSL9

VSSL8

VSSL6

VSSL5

VSSL4

VSSL3

VSSL2

VSSL1

VSSK35

VSSK32

VSSK29

VSSK26

VSSJ34

VSSJ31

VSSH33

VSSH30

VSSH27

VSSH24

VSSH21

VSSH18

VSSH15

VSSH13

VSSH10

VSSH9

VSSH8

VSSH7

VSSH6

VSSH5

VSSH4

VSSH3

VSSH2

VSSH1

VSSG35

VSSG32

VSSG29

VSSG26

VSSG23

VSSG20

VSSG17

VSSG11

VSSF34

VSSF31

VSSF29

VSS F22

VSS F19

VSS E30

VSS E27

VSS E24

VSS E21

VSS E18

VSS E15

VSS E13

VSS E10

VSS E9

VSS E8

VSS E7

VSS E6

VSS E5

VSS E4

VSS E3

VSS E2

VSS E1

VSS D35

VSS D32

VSS D29

VSS D26

VSS D20

VSS D17

VSS C34

VSS C31

VSS C28

VSS C27

VSS C25

VSS C23

VSS C10

VSS C1

VSS B22

VSS B19

VSS B17

VSS B15

VSS B13

VSS B11

VSS B9

VSS B8

VSS B7

VSS B5

VSS B3

VSS B2

VSS A35

VSS A32

VSS A29

VSS A26

VSS A23

VSS A20

VSS A3

VSS

9 OF 9

SANDY

CPU1I

SANDY

VSS

9 OF 9

SANDY

CPU1I

SANDY

VSSAT35

VSSAT32

VSSAT29

VSSAT27

VSSAT25

VSSAT22

VSSAT19

VSSAT16

VSSAT13

VSSAT10

VSSAT7

VSSAT4

VSSAT3

VSSAR25

VSSAR22

VSSAR19

VSSAR16

VSSAR13

VSSAR10

VSSAR7

VSSAR4

VSSAR2

VSSAP34

VSSAP31

VSSAP28

VSSAP25

VSSAP22

VSSAP19

VSSAP16

VSSAP13

VSSAP10

VSSAP7

VSSAP4

VSSAP1

VSSAN30

VSSAN27

VSSAN25

VSSAN22

VSSAN19

VSSAN16

VSSAN13

VSSAN10

VSSAN7

VSSAN4

VSSAM29

VSSAM25

VSSAM22

VSSAM19

VSSAM16

VSSAM13

VSSAM10

VSSAM7

VSSAM4

VSSAM3

VSSAM2

VSSAM1

VSSAL34

VSSAL31

VSSAL28

VSSAL25

VSSAL22

VSSAL19

VSSAL16

VSSAL13

VSSAL10

VSSAL7

VSSAL4

VSSAL2

VSSAK33

VSSAK30

VSSAK27

VSSAK25

VSSAK22

VSSAK19

VSSAK16

VSSAK13

VSSAK10

VSSAK7

VSSAK4

VSSAJ25

VSS AJ22

VSS AJ19

VSS AJ16

VSS AJ13

VSS AJ10

VSS AJ7

VSS AJ4

VSS AJ3

VSS AJ2

VSS AJ1

VSS AH35

VSS AH34

VSS AH32

VSS AH30

VSS AH29

VSS AH28

VSS AH26

VSS AH25

VSS AH22

VSS AH19

VSS AH16

VSS AH7

VSS AH4

VSS AG9

VSS AG8

VSS AG4

VSS AF6

VSS AF5

VSS AF3

VSS AF2

VSS AE35

VSS AE34

VSS AE33

VSS AE32

VSS AE31

VSS AE30

VSS AE29

VSS AE28

VSS AE27

VSS AE26

VSS AE9

VSS AD7

VSS AC9

VSS AC8

VSS AC6

VSS AC5

VSS AC3

VSS AC2

VSS AB35

VSS AB34

VSS AB33

VSS AB32

VSS AB31

VSS AB30

VSS AB29

VSS AB28

VSS AB27

VSS AB26

VSS Y9

VSS Y8

VSS Y6

VSS Y5

VSS Y3

VSS Y2

VSS W35

VSS W34

VSS W33

VSS W32

VSS W31

VSS W30

VSS W29

VSS W28

VSS W27

VSS W26

VSS U9

VSS U8

VSS U6

VSS U5

VSS U3

VSS U2

VSS

8 OF 9

SANDY

CPU1H

SANDY

VSS

8 OF 9

SANDY

CPU1H

SANDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


NIRVANA 13 A00

XDPA3


<Core Design>

Title


Date: Sheet of


NIRVANA 13 A00

XDPA3


<Core Design>

Title


Date: Sheet of


NIRVANA 13 A00

XDPA3


<Core Design>

Remove the XDP connector for space saving 6/28

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_A1

M_A_DQS#0



M_A_DQS3

M_A_DQ0

M_A_DQS#5

M_A_A2

SA0_DIM0

SA0_DIM0



M_A_DQS4

M_A_A3

M_A_DQS#6



SA1_DIM0

M_A_DQ1

M_A_A4

M_A_DQS5

M_A_DQS#7



M_A_DQS#1

M_A_A5

M_A_DQ2

SA1_DIM0

M_A_DQS6


M_A_DQS0


M_A_A7M_A_A8M_A_A9M_A_A10M_A_A11

M_A_A6

M_A_DQ3

M_A_DQS#2

M_A_DQS7



M_A_DQS1

M_A_A13M_A_A14M_A_A15

M_A_A12


M_A_DQS#3

M_A_A0


M_A_DQ8

TS#_DIMM0_1

M_A_DQ9M_A_DQ10M_A_DQ11

M_A_DQS2

M_A_DQS#4

M_VREF_DQ_DIMM0

M_VREF_CA_DIMM0

M_VREF_DQ_DIMM0

1D5V_S3

1D5V_S3

3D3V_S0

0D75V_S0

0D75V_S0

DDR_VREF_S3

3D3V_S0

DDR_VREF_S3

M_VREF_CA_DIMM0

DDR3_DRAMRST#(15,37)

M_A_DIM0_ODT0(6)M_A_DIM0_ODT1(6)

M_A_BS2(6)

M_A_BS0(6)M_A_BS1(6)

M_A_DQ[63:0](6)

TS#_DIMM0_1 (15)

PCH_SMBCLK (15,20,65,79,82)PCH_SMBDATA (15,20,65,79,82)

M_A_WE# (6)

M_A_DIM0_CS#0 (6)

M_A_CAS# (6)

M_A_DIM0_CKE0 (6)M_A_DIM0_CKE1 (6)

M_A_DIM0_CS#1 (6)



M_A_RAS# (6)M_A_A[15:0] (6)

M_A_DQS#[7:0] (6)

M_A_DQS[7:0] (6)

Title


Date: Sheet of



Nirvana 13 A00

DDR3-DIMM1 SOCKET1


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

DDR3-DIMM1 SOCKET1


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

DDR3-DIMM1 SOCKET1


<Core Design>

SSID = MEMORY

Note:

If SA0 DIM0 = 0, SA1_DIM0 = 0

SO-DIMMA SPD Address is 0xA0

SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0

SO-DIMMA SPD Address is 0xA2

SO-DIMMA TS Address is 0x32

PART NUMBER

62.10017.F91

62.10017.N61

Height TYPE

9.2mm

Thermal EVENT

H=9.2mm

Place these caps

close to VTT1 and

VTT2.

SODIMM A DECOUPLING

Layout Note:

Place these Caps near

SO-DIMMA.

20101224 A00:

0402 0R pad: R1404 R1405.

20101231 A00:

Merge R1401,R1402 to RN1401 10k ohm array resistor.

20100104 A00:

Change RN1401 to 0R short pad.

12

C1

41

4S

C1

U6

D3

V2

KX

-GP

C1

41

4S

C1

U6

D3

V2

KX

-GP

1 2R140310KR2J-3-GP

R140310KR2J-3-GP

12

C1411

SC

D1

U1

0V

2K

X-5

GP

C1411

SC

D1

U1

0V

2K

X-5

GP

12

C1

42

2S

C1

U6

D3

V2

KX

-GP

DY

C1

42

2S

C1

U6

D3

V2

KX

-GP

DY

1 234

RN0R4P2R-PAD

RN1401

RN0R4P2R-PAD

RN1401

12

C1

42

1S

C1

U6

D3

V2

KX

-GP

C1

42

1S

C1

U6

D3

V2

KX

-GP

12

C1412

SC

2D

2U

10

V3

KX

-1G

P

DY C1412

SC

2D

2U

10

V3

KX

-1G

P

DY

12

C1424

SC

D1

U1

0V

2K

X-5

GP

C1424

SC

D1

U1

0V

2K

X-5

GP

12

C1

40

9S

C1

0U

6D

3V

5K

X-1

GP

DY

C1

40

9S

C1

0U

6D

3V

5K

X-1

GP

DY

12

C1

40

7S

C1

0U

6D

3V

5K

X-1

GP

DY C1

40

7S

C1

0U

6D

3V

5K

X-1

GP

DY

12

R1404

0R0402-PAD

R1404

0R0402-PAD

12

C1402

SC

2D

2U

10

V3

KX

-1G

P

DYC1402

SC

2D

2U

10

V3

KX

-1G

P

DY

12

C1

40

3S

C1

0U

6D

3V

5K

X-1

GP

C1

40

3S

C1

0U

6D

3V

5K

X-1

GP

12

C1

42

0S

C1

U6

D3

V2

KX

-GP

DY

C1

42

0S

C1

U6

D3

V2

KX

-GP

DY

12

C1

41

5S

C1

U6

D3

V2

KX

-GP

C1

41

5S

C1

U6

D3

V2

KX

-GP

12

C1

41

9S

C1

U6

D3

V2

KX

-GP

C1

41

9S

C1

U6

D3

V2

KX

-GP

12

C1

41

7S

C1

U6

D3

V2

KX

-GP

C1

41

7S

C1

U6

D3

V2

KX

-GP

12

C1425S

C2

D2

U1

0V

3K

X-1

GP

DY C1425S

C2

D2

U1

0V

3K

X-1

GP

DY

12

C1

40

4S

C1

0U

6D

3V

5K

X-1

GP

DY C1

40

4S

C1

0U

6D

3V

5K

X-1

GP

DY

12

C1

40

8S

C1

0U

10

V5

ZY

-1G

P

DY

C1

40

8S

C1

0U

10

V5

ZY

-1G

P

DY

12

C1418

SC

10

U6

D3

V5

KX

-1G

P

DY C1418

SC

10

U6

D3

V5

KX

-1G

P

DY

12

C1413

SC

D1

U1

0V

2K

X-5

GP

C1413

SC

D1

U1

0V

2K

X-5

GP

12

C1

40

5S

C1

0U

10

V5

ZY

-1G

P

DY

C1

40

5S

C1

0U

10

V5

ZY

-1G

P

DY

12

C1423

SC

D1

U1

0V

2K

X-5

GP

C1423

SC

D1

U1

0V

2K

X-5

GP

12

TC1401

ST

33

0U

2V

DM

-4-G

P

79.33719.20L2nd = 77.C3371.13L

DYTC1401

ST

33

0U

2V

DM

-4-G

P

79.33719.20L2nd = 77.C3371.13L

DY

12

C1

41

0S

C1

0U

6D

3V

5K

X-1

GP

DY

C1

41

0S

C1

0U

6D

3V

5K

X-1

GP

DY

A098

A197

A296

A395

A492

A591

A690

A786

A889

A985

A10/AP107

A1184

A1283

A13119

A1480

A1578

A16/BA279

BA0109

BA1108

DQ05

DQ17

DQ215

DQ317

DQ44

DQ56

DQ616

DQ718

DQ821

DQ923

DQ1033

DQ1135

DQ1222

DQ1324

DQ1434

DQ1536

DQ1639

DQ1741

DQ1851

DQ1953

DQ2040

DQ2142

DQ2250

DQ2352

DQ2457

DQ2559

DQ2667

DQ2769

DQ2856

DQ2958

DQ3068

DQ3170

DQ32129

DQ33131

DQ34141

DQ35143

DQ36130

DQ37132

DQ38140

DQ39142

DQ40147

DQ41149

DQ42157

DQ43159

DQ44146

DQ45148

DQ46158

DQ47160

DQ48163

DQ49165

DQ50175

DQ51177

DQ52164

DQ53166

DQ54174

DQ55176

DQ56181

DQ57183

DQ58191

DQ59193

DQ60180

DQ61182

DQ62192

DQ63194

DQS0#10

DQS1#27

DQS2#45

DQS3#62

DQS4#135

DQS5#152

DQS6#169

DQS7#186

DQS012

DQS129

DQS247

DQS364

DQS4137

DQS5154

DQS6171

DQS7188

ODT0116

ODT1120

VREF_DQ1

VSS2

NP1NP1

NP2NP2

RAS#110

WE#113

CAS#115

CS0#114

CS1#121

CKE073

CKE174

CK0101

CK0#103

CK1102

CK1#104

DM011

DM128

DM246

DM363

DM4136

DM5153

DM6170

DM7187

SDA200

SCL202

VDDSPD199

SA0197

SA1201

VREF_CA126

VDD18124

NC#177

NC#2122

NC#/TEST125

VDD381

VDD482

VDD587

VDD688

VDD793

VDD894

VDD999

VDD10100

VDD13111

VDD14112

VDD15117

VDD16118

VSS3

VSS8

VSS9

VSS13

VSS14

VSS19

VSS20

VSS25

VSS26

VSS31

VSS32

VSS37

VSS38

VSS43

VSS44

VSS48

VSS49

VSS54

VSS55

VSS60

VSS61

VDD175

VSS65

VSS66

VSS71

VSS72

VDD276

VDD11105

VDD12106

VDD17123

VSS127

VSS128

VSS134

VSS133

VSS138

VSS139

VSS144

VSS145

VSS151

VSS150

VSS155

VSS156

VSS161

VSS162

VSS167

VSS168

VSS173

VSS172

VSS179

VSS178

VSS185

VSS184

VSS189

VSS190

VSS195

VSS196

RESET#30

EVENT#198

VSS205

VSS206

VTT1203

VTT2204

DM1

DDR3-204P-42-GP

62.10017.N61

DM1

DDR3-204P-42-GP

62.10017.N61

12

C1

40

6S

C1

0U

6D

3V

5K

X-1

GP

C1

40

6S

C1

0U

6D

3V

5K

X-1

GP

12

C1401

SC

D1

U1

0V

2K

X-5

GP

C1401

SC

D1

U1

0V

2K

X-5

GP

12

R1405

0R0402-PAD

R1405

0R0402-PAD

12

C1

41

6S

C1

U6

D3

V2

KX

-GP

C1

41

6S

C1

U6

D3

V2

KX

-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_B_A1

M_B_DQ42M_B_DQ41M_B_DQ40

M_B_DQS#0

M_B_DQ43


M_B_DQ15

M_B_DQS3

M_B_DQ0

M_B_A2

M_B_DQS#5

SA0_DIM1

SA1_DIM1


M_B_DQ47


M_B_DQS4

M_B_A3

M_B_DQS#6



SA1_DIM1

M_B_DQ1

M_B_A4

M_B_DQS5

M_B_DQS#7

M_B_DQ53M_B_DQ52

M_B_DQ24

M_B_DQ55M_B_DQ54


M_B_DQS#1

SA0_DIM1

M_B_DQ2

M_B_A5

M_B_DQS6

M_B_DQ57M_B_DQ56

M_B_DQS0

M_B_DQ59M_B_DQ58


M_B_A7M_B_A6

M_B_A11M_B_A10M_B_A9M_B_A8

M_B_DQ3

M_B_DQS#2

M_B_DQS7


M_B_DQ33M_B_DQ32

M_B_DQ35M_B_DQ34

M_B_DQS1

M_B_A12

M_B_A15M_B_A14M_B_A13

M_B_DQ5M_B_DQ4

M_B_DQ7M_B_DQ6

M_B_DQS#3

M_B_A0


M_B_DQ8


M_B_DQS2

M_B_DQS#4

M_VREF_CA_DIMM1M_VREF_DQ_DIMM1

M_VREF_DQ_DIMM1

M_VREF_CA_DIMM1

3D3V_S0

1D5V_S3

3D3V_S0

1D5V_S3

0D75V_S0

DDR_VREF_S3

0D75V_S0

DDR_VREF_S3

DDR3_DRAMRST#(14,37)

M_B_BS0(6)

M_B_BS2(6)

M_B_BS1(6)M_B_DQ[63:0](6)

TS#_DIMM0_1 (14)


M_B_A[15:0] (6)

M_B_DQS[7:0] (6)

M_B_DQS#[7:0] (6)

M_B_DIM0_ODT0(6)M_B_DIM0_ODT1(6)

M_B_WE# (6)

M_B_DIM0_CS#0 (6)

M_B_CAS# (6)

M_B_DIM0_CKE0 (6)M_B_DIM0_CKE1 (6)

M_B_DIM0_CS#1 (6)



M_B_RAS# (6)

Title


Date: Sheet of



Nirvana 13 A00

DDR3-DIMM2 SOCKET2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

DDR3-DIMM2 SOCKET2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

DDR3-DIMM2 SOCKET2


<Core Design>

SSID = MEMORY

PART NUMBER

62.10017.P41

Height TYPE

SODIMM B DECOUPLING

Layout Note:

Place these Caps near

SO-DIMMB.

Note:

SO-DIMMB SPD Address is 0xA4

SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from

the Processor than SO-DIMMA

Place these caps

close to VTT1 and

VTT2.

H=5.2mm

5.2mm

20101224 A00:

0402 0R pad: R1503 R1504.

20100104 A00:

Change R1502 to 0R0402 short pad.

12

R1502

0R0402-PAD

R1502

0R0402-PAD

12

R150110KR2J-3-GPR150110KR2J-3-GP

12

R1503

0R0402-PAD

R1503

0R0402-PAD

12

C1

51

4S

C1

U6

D3

V2

KX

-GP

C1

51

4S

C1

U6

D3

V2

KX

-GP

12

C1516

SC

2D

2U

10

V3

KX

-1G

P

DY C1516

SC

2D

2U

10

V3

KX

-1G

P

DY

12

C1

52

1S

C1

U6

D3

V2

KX

-GP

C1

52

1S

C1

U6

D3

V2

KX

-GP

12

C1502

SC

2D

2U

10

V3

KX

-1G

P

DYC1502

SC

2D

2U

10

V3

KX

-1G

P

DY

12

C1

52

0S

C1

U6

D3

V2

KX

-GP

DY

C1

52

0S

C1

U6

D3

V2

KX

-GP

DY

12

C1

51

9S

C1

U6

D3

V2

KX

-GP

C1

51

9S

C1

U6

D3

V2

KX

-GP

12

C1

50

8S

C1

0U

10

V5

ZY

-1G

P

DY

C1

50

8S

C1

0U

10

V5

ZY

-1G

P

DY

12

C1515

SC

D1

U1

0V

2K

X-5

GP

C1515

SC

D1

U1

0V

2K

X-5

GP

12

C1

50

3S

C1

0U

10

V5

ZY

-1G

P

DY

C1

50

3S

C1

0U

10

V5

ZY

-1G

P

DY

12

C1

51

3S

C1

U6

D3

V2

KX

-GP

C1

51

3S

C1

U6

D3

V2

KX

-GP

12

C1

50

4S

C1

0U

10

V5

ZY

-1G

P

DY

C1

50

4S

C1

0U

10

V5

ZY

-1G

P

DY

12

C1

50

9S

C1

0U

6D

3V

5K

X-1

GP

C1

50

9S

C1

0U

6D

3V

5K

X-1

GP

12

C1

51

2S

C1

U6

D3

V2

KX

-GP

C1

51

2S

C1

U6

D3

V2

KX

-GP

12

C1523

SC

D1

U1

0V

2K

X-5

GP

C1523

SC

D1

U1

0V

2K

X-5

GP

12

C1522

SC

D1

U1

0V

2K

X-5

GP

C1522

SC

D1

U1

0V

2K

X-5

GP

12

C1

51

8S

C1

U6

D3

V2

KX

-GP

DY

C1

51

8S

C1

U6

D3

V2

KX

-GP

DY

12

C1517

SC

D1

U1

0V

2K

X-5

GP

C1517

SC

D1

U1

0V

2K

X-5

GP

12

C1524

SC

2D

2U

10

V3

KX

-1G

P

DY C1524

SC

2D

2U

10

V3

KX

-1G

P

DY

12

R1504

0R0402-PAD

R1504

0R0402-PAD

A098

A197

A296

A395

A492

A591

A690

A786

A889

A985

A10/AP107

A1184

A1283

A13119

A1480

A1578

A16/BA279

BA0109

BA1108

DQ05

DQ17

DQ215

DQ317

DQ44

DQ56

DQ616

DQ718

DQ821

DQ923

DQ1033

DQ1135

DQ1222

DQ1324

DQ1434

DQ1536

DQ1639

DQ1741

DQ1851

DQ1953

DQ2040

DQ2142

DQ2250

DQ2352

DQ2457

DQ2559

DQ2667

DQ2769

DQ2856

DQ2958

DQ3068

DQ3170

DQ32129

DQ33131

DQ34141

DQ35143

DQ36130

DQ37132

DQ38140

DQ39142

DQ40147

DQ41149

DQ42157

DQ43159

DQ44146

DQ45148

DQ46158

DQ47160

DQ48163

DQ49165

DQ50175

DQ51177

DQ52164

DQ53166

DQ54174

DQ55176

DQ56181

DQ57183

DQ58191

DQ59193

DQ60180

DQ61182

DQ62192

DQ63194

DQS0#10

DQS1#27

DQS2#45

DQS3#62

DQS4#135

DQS5#152

DQS6#169

DQS7#186

DQS012

DQS129

DQS247

DQS364

DQS4137

DQS5154

DQS6171

DQS7188

ODT0116

ODT1120

VREF_DQ1

VSS2

NP1NP1

NP2NP2

RAS#110

WE#113

CAS#115

CS0#114

CS1#121

CKE073

CKE174

CK0101

CK0#103

CK1102

CK1#104

DM011

DM128

DM246

DM363

DM4136

DM5153

DM6170

DM7187

SDA200

SCL202

VDDSPD199

SA0197

SA1201

VREF_CA126

VDD18124

NC#177

NC#2122

NC#/TEST125

VDD381

VDD482

VDD587

VDD688

VDD793

VDD894

VDD999

VDD10100

VDD13111

VDD14112

VDD15117

VDD16118

VSS3

VSS8

VSS9

VSS13

VSS14

VSS19

VSS20

VSS25

VSS26

VSS31

VSS32

VSS37

VSS38

VSS43

VSS44

VSS48

VSS49

VSS54

VSS55

VSS60

VSS61

VDD175

VSS65

VSS66

VSS71

VSS72

VDD276

VDD11105

VDD12106

VDD17123

VSS127

VSS128

VSS134

VSS133

VSS138

VSS139

VSS144

VSS145

VSS151

VSS150

VSS155

VSS156

VSS161

VSS162

VSS167

VSS168

VSS173

VSS172

VSS179

VSS178

VSS185

VSS184

VSS189

VSS190

VSS195

VSS196

RESET#30

EVENT#198

VSS205

VSS206

VTT1203

VTT2204

DM2

DDR3-204P-48-GP

62.10017.P41

DM2

DDR3-204P-48-GP

62.10017.P41

12

C1

50

7S

C1

0U

6D

3V

5K

X-1

GP

C1

50

7S

C1

0U

6D

3V

5K

X-1

GP

12

C1

51

1S

CD

1U

10

V2

KX

-5G

PC

15

11

SC

D1

U1

0V

2K

X-5

GP

12

C1

50

5S

C1

0U

6D

3V

5K

X-1

GP

C1

50

5S

C1

0U

6D

3V

5K

X-1

GP

12

C1501

SC

D1

U1

0V

2K

X-5

GP

C1501

SC

D1

U1

0V

2K

X-5

GP

12

C1

51

0S

C1

0U

6D

3V

5K

X-1

GP

DY

C1

51

0S

C1

0U

6D

3V

5K

X-1

GP

DY

12

C1

50

6S

C1

0U

6D

3V

5K

X-1

GP

C1

50

6S

C1

0U

6D

3V

5K

X-1

GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LVDS_VBGLVDS_IBG

DAC_IREF_R

CRT_RED

LVDS_VDD_EN

LVDS_VREFHLVDS_VREFL

L_CTRL_DATAL_CTRL_CLK

LVDS_DDC_CLK_RLVDS_DDC_DATA_R

CRT_BLUE

L_BKLT_EN

CRT_GREEN

PCH_HDMI_DATAPCH_HDMI_CLK

L_CTRL_CLKL_CTRL_DATA

3D3V_S0

CRT_HSYNC(50)CRT_VSYNC(50)

LVDS_DDC_CLK_R(49,97)LVDS_DDC_DATA_R(49,97)

LVDSA_DATA0(49)LVDSA_DATA1(49)LVDSA_DATA2(49)

LVDSA_DATA0#(49)LVDSA_DATA1#(49)LVDSA_DATA2#(49)

LVDSA_CLK#(49)LVDSA_CLK(49)

L_BKLT_CTRL(49)

LVDS_VDD_EN(49)L_BKLT_EN(27)

CRT_BLUE(50)CRT_GREEN(50)CRT_RED(50)

CRT_DDC_CLK(50)CRT_DDC_DATA(50)

HDMI_PCH_DET (51)

PCH_HDMI_CLK (51)PCH_HDMI_DATA (51)

HDMI_DATA0_R (51)HDMI_DATA0_R# (51)

HDMI_CLK_R (51)

HDMI_DATA1_R (51)

HDMI_CLK_R# (51)

HDMI_DATA1_R# (51)HDMI_DATA2_R (51)HDMI_DATA2_R# (51)

Title


Date: Sheet of


Nirvana 13 A00

PCH 1/9(LVDS/CRT/DDI)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

DDI Port B Detect:(SDVO_CTRL_ DATA)

1: Port B detected

0: Port B not detected

L_DDC_DATA(PAGE17):

This signal is on the LVDS interface.

This signal needs to be left NC if eDP is

used for the local flat panel display

Place near PCH

Impedance:90 ohm

Impedance:100 ohm

Close to PCH side

Notes:

1K 0.5% 0402.

20101224 A00:Change RN1704 to 0402 0 ohm pad.

20100104 A00:Merge RN1701,RN1706 to RN1703 2.2k array resistor.

12345 6 7 8

RN1705SRN150F-1-GPRN1705SRN150F-1-GP

L_BKLTCTLP45

L_BKLTENJ47

L_CTRL_CLKT45

L_CTRL_DATAP39

L_DDC_CLKT40

L_DDC_DATAK47

L_VDD_ENM45

LVDSA_CLK#AK39

LVDSA_CLKAK40

LVDSA_DATA#0AN48

LVDSA_DATA#1AM47

LVDSA_DATA#2AK47

LVDSA_DATA#3AJ48

LVDSA_DATA0AN47

LVDSA_DATA1AM49

LVDSA_DATA2AK49

LVDSA_DATA3AJ47

LVDSB_CLK#AF40

LVDSB_CLKAF39

LVDSB_DATA#0AH45

LVDSB_DATA#1AH47

LVDSB_DATA#2AF49

LVDSB_DATA#3AF45

LVDSB_DATA0AH43

DDPB_0N AV42

DDPB_1N AV45

LVD_VREFHAE48

LVD_VREFLAE47

DDPD_2N BF42

DDPD_3N BJ42

DDPB_2N AU48

DDPB_3N AV47

DDPC_0N AY47

DDPC_1N AY43

DDPC_2N BA47

DDPC_3N BB47

DDPD_0N BB43

DDPD_1N BF44

DDPB_0P AV40

DDPB_1P AV46

DDPD_2P BE42

DDPD_3P BG42

DDPB_2P AU47

DDPB_3P AV49

LVDSB_DATA1AH49

LVDSB_DATA2AF47

LVDSB_DATA3AF43

LVD_IBGAF37

LVD_VBGAF36

DDPC_1P AY45

DDPC_0P AY49

DDPC_2P BA48

DDPC_3P BB49

DDPD_0P BB45

DDPD_1P BE44

CRT_BLUEN48

CRT_DDC_CLKT39

CRT_DDC_DATAM40

CRT_GREENP49

CRT_HSYNCM47

CRT_IRTNT42

CRT_REDT49

CRT_VSYNCM49

DAC_IREFT43

SDVO_CTRLCLK P38

SDVO_CTRLDATA M39

DDPC_CTRLCLK P46

DDPC_CTRLDATA P42

DDPD_CTRLCLK M43

DDPD_CTRLDATA M36

DDPB_AUXN AT49

DDPC_AUXN AP47

DDPD_AUXN AT45

DDPB_AUXP AT47

DDPC_AUXP AP49

DDPD_AUXP AT43

DDPB_HPD AT40

DDPC_HPD AT38

DDPD_HPD BH41

SDVO_TVCLKINP AP45SDVO_TVCLKINN AP43

SDVO_STALLP AM40SDVO_STALLN AM42

SDVO_INTP AP40SDVO_INTN AP39

LVDS

Digital Display Interface

CRT

4 OF 10

Cougar

Point

PCH1D

COUGAR-GP-U2-NF

LVDS

Digital Display Interface

CRT

4 OF 10

Cougar

Point

PCH1D

COUGAR-GP-U2-NF

12

R17021KR2D-1-GP

R17021KR2D-1-GP

12

R17012K37R2F-GPR17012K37R2F-GP

12 3

4

RN1702

SRN100KJ-6-GP

RN1702

SRN100KJ-6-GP

1234 5

678

RN1703

SRN2K2J-2-GP

RN1703

SRN2K2J-2-GP


12 3

4

RN

0R4P2R-PAD

RN1704

RN

0R4P2R-PAD

RN1704

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DGPU_PWR_EN#DGPU_HOLD_RST#

INT_PIRQF#INT_PIRQB#

USB_OC#2_3USB_OC#0_1

USB_OC#8_9USB_OC#10_11USB_OC#12_13

USB_OC#6_7

BBS_BIT1

CLK_PCI_LPC_R

INT_PIRQG#INT_PIRQF#

INT_PIRQH#

INT_PIRQE#

CLK_PCI_FB_R

BBS_BIT1

INT_PIRQB#

CLK_PCI_KBC_R

INT_PIRQC#INT_PIRQD#

INT_PIRQA#

DGPU_PWM_SELECT#

PCI_PLTRST#

PCI_GNT3#

DGPU_SELECT#DGPU_PWR_EN#

PCI_PME#


BBS_BIT0

USB_OC#12_13


PCI_PLTRST#

DGPU_HOLD_RST#

NV_ALENV_CLE

PCI_GNT3#

USB_RBIAS

USB_OC#4_5

USB_OC#4_5

INT_PIRQG#

INT_PIRQE#INT_PIRQC#

USB_OC#2_3

INT_PIRQA#

NV_RCOMP

NV_ALE

INT_PIRQD#

NV_CLE

FFS_INT2_R

3D3V_S5

3D3V_S5

3D3V_S0

3D3V_S0

1D8V_S0

3D3V_S0

1D8V_S0

BBS_BIT0 (21)

USB_PP2 (64)USB_PN2 (64)

SATA_ODD_DA#(56)USB30_SMI#(82)

USB_OC#0_1 (61)

CLK_PCI_FB(20)

CLK_PCI_LPC(65,71)

CLK_PCI_KBC(27)

USB_PN12 (49)USB_PP12 (49)

USB_PP5 (32)USB_PN5 (32)

PLT_RST#(5,27,65,71,82)

USB_PN11 (65)USB_PP11 (65)

USB_PN1 (57)USB_PP1 (57)

USB_PN3 (63)USB_PP3 (63)USB_PN4 (82)USB_PP4 (82)

HDD_FALL_INT1(79)

KB_LED_BL_DET(69)

H_SNB_IVB# (5)

FFS_INT2_R (79)

Title


Date: Sheet of


Nirvana 13 A00

PCH 2/9(PCI/USB/NVRAM)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

SSID = PCH

USB Table

13

12

X

Mini Card1 (WLAN)

X

X

X

10

0

11

X

Pair

4

5

2

3

1

Device

6

7

8

9

BLUETOOTH

CARD READER

X

CAMERA

Mini Card2 (WWAN)

SSID = PCH

Fingerprint

X

E-SATA / USB Combo

Danbury Technology:Disabled when Low.Enable when High.

KBC CLK EMI

Reserved 01

11

BOOT BIOS Strap

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 1 Reserved

SPI(Default)

SSID = PCH

0 0 LPC

A16 swap override Strap/Top-BlockSwap Override jumper

PCI_GNT#3 Low = A16 swapoverride/Top-BlockSwap Override enabledHigh = Default USB Ext. port 1 (HS)

External debug port use on Huron river platform

OC[3:0]# for Device 29 (Ports 0-7)

OC[7:4]# for Device 26 (Ports 8-13)

NV_CLESet to Vss when LOW

DMI & FDI Termination Voltage

Set to Vcc when HIGH

20101224 A00:0402 0R pad: R1807.

20101231 A00:Merge R1804,R1806 to RN1804 22 ohm array resistor.20110113 A00:Swap RN1804 base on swap report.

1 2R18021KR2J-1-GPDY R18021KR2J-1-GPDY

12

EC1802

SC

4D

7P

50V

2C

N-1

GPDY

EC1802

SC

4D

7P

50V

2C

N-1

GPDY

12345 6

78910

RN1802

SRN8K2J-2-GP-U

RN1802

SRN8K2J-2-GP-U

1 2R1815 0R0402-PADR1815 0R0402-PAD

12

C1801SC220P50V2KX-3GPDY C1801SC220P50V2KX-3GPDY

1 2R1812 0R0402-PADR1812 0R0402-PAD

1 2

R180522R2J-2-GPR180522R2J-2-GP

12

R1816

100K

R2J-1

-GPDY

R1816

100K

R2J-1

-GPDY

12

R1807

0R0402-PAD

R1807

0R0402-PAD

12 3

4

RN1804

SRN22-3-GP

RN1804

SRN22-3-GP

12

EC1801

SC

4D

7P

50V

2C

N-1

GPDY

EC1801

SC

4D

7P

50V

2C

N-1

GPDY


12

R1814

8K2R2J-3-GP

R1814

8K2R2J-3-GP

RSVD AV5

RSVD AY7

RSVD AV7

RSVD AU3

RSVD BG4

DF_TVS AY1

RSVD AT10

RSVD BC8

RSVD AU2

RSVD AT4

RSVD BB5

RSVD BB3

RSVD BB7

RSVD BE8

RSVD BD4

RSVD BF6

RSVD AT3

RSVD AT1

RSVD AY3

RSVD AT5

RSVD AV3

RSVD AV1

RSVD BB1

RSVD BA3

RSVD AT8

RSVD AV10

RSVD AY5

RSVD BA2

RSVD AT12

RSVD BF3

PIRQA#K40

PIRQB#K38

PIRQC#H38

PIRQD#G38

REQ1#/GPIO50C46

REQ2#/GPIO52C44

REQ3#/GPIO54E40

GNT1#/GPIO51D47

GNT2#/GPIO53E42

GNT3#/GPIO55F46

PIRQE#/GPIO2G42

PIRQF#/GPIO3G40

PIRQG#/GPIO4C42

PIRQH#/GPIO5D44

USBP0N C24

USBP0P A24

USBP1N C25

USBP1P B25

USBP2N C26

USBP2P A26

USBP3N K28

USBP3P H28

USBP4N E28

USBP4P D28

USBP5N C28

USBP5P A28

USBP6N C29

USBP6P B29

USBP7N N28

USBP7P M28

USBP8N L30

USBP8P K30

USBP9N G30

USBP9P E30

USBP10N C30

USBP10P A30

USBP11N L32

USBP11P K32

USBP12N G32

USBP12P E32

USBP13N C32

USBP13P A32

PME#K10

CLKOUT_PCI0H49

CLKOUT_PCI1H43

CLKOUT_PCI2J48

USBRBIAS# C33

USBRBIAS B33

OC0#/GPIO59 A14

OC1#/GPIO40 K20

OC2#/GPIO41 B17

OC3#/GPIO42 C16

OC4#/GPIO43 L16

OC5#/GPIO9 A16

OC6#/GPIO10 D14

OC7#/GPIO14 C14CLKOUT_PCI4H40CLKOUT_PCI3K42

PLTRST#C6

TP1BG26

TP2BJ26

TP3BH25

TP6AH38

TP7AH37

TP8AK43

TP9AK45

TP16Y13

TP17K24

TP18L24

TP19AB46

TP20AB45

TP21B21

TP22M20

TP23AY16

TP25BE28

TP26BC30

TP27BE32

TP28BJ32

TP29BC28

TP30BE30

TP31BF32

TP32BG32

TP33AV26

TP34BB26

TP35AU28

TP36AY30

TP37AU26

TP38AY26

TP39AV28

TP40AW30

TP4BJ16

TP5BG16

TP15AM5TP14AM4TP13AH12TP12H3TP11N30TP10C18

TP24BG46

RSVD

NVRAM

PCI

USB

5 OF 10

Cougar

Point

PCH1E

COUGAR-GP-U2-NF

RSVD

NVRAM

PCI

USB

5 OF 10

Cougar

Point

PCH1E

COUGAR-GP-U2-NF

12

R1808

2K2R2J-2-GP

R1808

2K2R2J-2-GP


1 2R1817 0R0402-PADR1817 0R0402-PAD

1 2

R1818 10KR2J-3-GPR1818 10KR2J-3-GP

1 TP1803 TPAD14-GPTP1803 TPAD14-GP

12


1 2R1813 0R0402-PADR1813 0R0402-PAD

12R1801 4K7R2J-2-GPDYR1801 4K7R2J-2-GPDY

12345 6

78910

RN1801

SRN8K2J-2-GP-U

RN1801

SRN8K2J-2-GP-U



12 3

4RN1803

SRN10KJ-5-GP

RN1803

SRN10KJ-5-GP

1 2

R1809

1KR2J-1-GP

R1809

1KR2J-1-GP

1 2R181122D6R2F-L1-GPR181122D6R2F-L1-GP

1 2R18031KR2J-1-GPDY R18031KR2J-1-GPDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BATLOW#

PM_CLKRUN#

H_PM_SYNC

DSWODVREN

PM_SUS_STAT#

BATLOW#

SUS_CLK

PM_RI#

PM_RSMRST#

PM_SLP_A#

PM_SLP_SUS#

PM_SLP_S5#

PM_SLP_LAN#

DSWODVREN

PM_RSMRST#PCH_DPWROK

PM_RI#

PM_PWRBTN#

SUS_PWR_ACK

RBIAS_CPY

SUSACK#SUS_PWR_ACK

DMI_COMP_R

SYS_RESET#

PWROK

PWROK

SYS_PWROK

MEPWROK

PCH_SUSCLK_KBC

PM_RSMRST#

PM_SLP_LAN#

PM_RSMRST#

AC_PRESENT

PCH_WAKE#

RTC_AUX_S5

3D3V_S5

3D3V_S0

RTC_AUX_S5

1D05V_VTT

3D3V_S0

PM_SLP_S4# (27,46)

PM_SLP_S3# (27,36,37,47)

H_PM_SYNC (5)

PM_CLKRUN# (27)

PCH_WAKE# (27)

PCH_SUSCLK_KBC (27)

DMI_RXP0(4)DMI_RXP1(4)DMI_RXP2(4)DMI_RXP3(4)

PM_PWRBTN#(27)

DMI_TXN0(4)DMI_TXN1(4)DMI_TXN2(4)DMI_TXN3(4)

DMI_TXP0(4)DMI_TXP1(4)DMI_TXP2(4)DMI_TXP3(4)

DMI_RXN0(4)DMI_RXN1(4)DMI_RXN2(4)DMI_RXN3(4)

AC_PRESENT(27)

SUS_PWR_ACK(27)

FDI_FSYNC1 (4)

FDI_LSYNC0 (4)

FDI_INT (4)

FDI_TXN0 (4)

FDI_TXP0 (4)

FDI_TXN6 (4)

FDI_TXP4 (4)

FDI_TXP6 (4)

FDI_TXN4 (4)

FDI_TXP2 (4)

FDI_TXP5 (4)

FDI_TXN2 (4)

FDI_TXN5 (4)

FDI_TXP7 (4)

FDI_TXN7 (4)

FDI_FSYNC0 (4)

FDI_LSYNC1 (4)

FDI_TXN3 (4)

FDI_TXN1 (4)

FDI_TXP3 (4)

FDI_TXP1 (4)

FDI_TXN[7:0] (4)FDI_TXP[7:0] (4)

DMI_RXP[3:0](4)DMI_RXN[3:0](4)

DMI_TXP[3:0](4)DMI_TXN[3:0](4)

RSMRST#_KBC (27)

S0_PWR_GOOD(27,36)

RUNPWROK(45,46,47)

XDP_DBRESET#(5)

SYS_PWROK(36)

PM_DRAM_PWRGD(5,37)

Title


Date: Sheet of


Nirvana 13 A00

PCH 3/9(DM I/FDI/PM)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Signal Routing Guideline:DMI_ZCOMP keep W=4 mils androuting length less than 500mils.DMI_IRCOMP keep W=4 mils androuting length less than 500mils.

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

SSID = PCH

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ‘no connect’

4.SUSWARN# used as SUSPWRDNACK/GPIO30

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

1 2R1925 0R0402-PADR1925 0R0402-PAD

12 R1922 10KR2J-3-GP

DY

R1922 10KR2J-3-GP

DY1

2

EC1901

SC

4D

7P

50V

2C

N-1

GPDY

EC1901

SC

4D

7P

50V

2C

N-1

GPDY

1 2R1902 750R2F-GPR1902 750R2F-GP

1 2 R190510KR2J-3-GPDY R190510KR2J-3-GPDY

1 2R1906 0R0402-PADR1906 0R0402-PAD

12345

678

RN1901

SRN10KJ-6-GP

RN1901

SRN10KJ-6-GP

1 2R1911 10KR2J-3-GPDY R1911 10KR2J-3-GPDY

1 2R19070R2J-2-GPDY

R19070R2J-2-GPDY

1 2R19120R0402-PADR19120R0402-PAD

1 2R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1TP1905TPAD14-GPTP1905TPAD14-GP

1 2R1901 49D9R2F-GPR1901 49D9R2F-GP

12 R190810KR2J-3-GP

R190810KR2J-3-GP

1 2R1903 0R0402-PADR1903 0R0402-PAD

1 2 R1904100KR2J-1-GP

R1904100KR2J-1-GP

12 R1920 10KR2J-3-GP

DY

R1920 10KR2J-3-GP

DY

1 2R1924 0R0402-PADR1924 0R0402-PAD


1 2R1913 0R0402-PADR1913 0R0402-PAD


DMI0RXNBC24

DMI1RXNBE20

DMI2RXNBG18

DMI3RXNBG20

DMI0RXPBE24

DMI1RXPBC20

DMI2RXPBJ18

DMI3RXPBJ20

DMI0TXNAW24

DMI1TXNAW20

DMI2TXNBB18

DMI3TXNAV18

DMI0TXPAY24

DMI1TXPAY20

DMI2TXPAY18

DMI3TXPAU18

DMI_ZCOMPBJ24

DMI_IRCOMPBG25

FDI_RXN0 BJ14

FDI_RXN1 AY14

FDI_RXN2 BE14

FDI_RXN3 BH13

FDI_RXN4 BC12

FDI_RXN5 BJ12

FDI_RXN6 BG10

FDI_RXN7 BG9

FDI_RXP0 BG14

FDI_RXP1 BB14

FDI_RXP2 BF14

FDI_RXP3 BG13

FDI_RXP4 BE12

FDI_RXP5 BG12

FDI_RXP6 BJ10

FDI_RXP7 BH9

FDI_FSYNC0 AV12

FDI_FSYNC1 BC10

FDI_LSYNC0 AV14

FDI_LSYNC1 BB10

FDI_INT AW16

PMSYNCH AP14

SLP_SUS# G16

SLP_S3# F4

SLP_S4# H4

SLP_S5#/GPIO63 D10

SYS_RESET#K3

SYS_PWROKP12

PWRBTN#E20

RI#A10

WAKE# B9

SUS_STAT#/GPIO61 G8

SUSCLK/GPIO62 N14

ACPRESENT/GPIO31H20

BATLOW#/GPIO72E10

PWROKL22

CLKRUN#/GPIO32 N3

SUSWARN#/SUSPWRDNACK/GPIO30K16

RSMRST#C21

DRAMPWROKB13

SLP_LAN#/GPIO29 K14

APWROKL10

DPWROK E22

DMI2RBIASBH21

SLP_A# G10

DSWVRMEN A18

SUSACK#C12

DMI

FDI

System Power Management

3 OF 10

Cougar

Point

PCH1C

COUGAR-GP-U2-NF

DMI

FDI

System Power Management

3 OF 10

Cougar

Point

PCH1C

COUGAR-GP-U2-NF

1 2R1910 0R0402-PADR1910 0R0402-PAD


1 2R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2R1918 330KR2J-L1-GPDYR1918 330KR2J-L1-GPDY

1 2R19230R2J-2-GPDY

R19230R2J-2-GPDY

12

R1921

100KR2J-1-GP

R1921

100KR2J-1-GP

1 2 R192610KR2J-3-GP

DY R192610KR2J-3-GP

DY


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XTAL25_IN

PCIE_CLK_REQ6#

CLK_BUF_EXP_NCLK_BUF_EXP_P

SMB_CLK

CLK_BUF_CKSSCD_P

PCIE_TXP5_CPCIE_TXN5_C

XTAL25_OUT

CLK_PCI_FB

EC_SWI#

PCH_GPIO74

CLK_PCH_SRC0_PCLK_PCH_SRC0_N

CLKOUT_PEG_A_NCLKOUT_PEG_A_P

DGPU_PRSNT#

PEG_B_CLKRQ#

PCIE_CLK_LAN_REQ#

CLK_PCIE_NEW_REQ#

CLK_PCIE_WWAN_REQ#

USB3_PEGB_CLKREQ#

EC_SWI#PCIE_CLK_REQ5#

DRAMRST_CNTRL_PCH

PCIE_CLK_REQ6#

PEG_B_CLKRQ#

CLKOUT_DMI_NCLKOUT_DMI_P

PCIE_CLK_REQ5#

UMA_DIS#

SML1_CLK

PEG_CLKREQ#_R

SML1_DATA

PCH_GPIO74

DRAMRST_CNTRL_PCH

SMB_DATA

XCLK_RCOMP

CLK_BUF_REF14

CL_CLK

CL_DATA

CL_RST#

SMB_DATA



SML1_DATASML1_CLK

CLK_BUF_DOT96_PCLK_BUF_DOT96_N

CLK_BUF_CKSSCD_N

SMB_CLK

PEG_CLKREQ#_R

CLK_PCIE_NEW_REQ#

SMB_CLK


SMB_DATA

CLK_BUF_CPYCLK_NCLK_BUF_CPYCLK_P

CLK_PCIE_WLAN_REQ#PCIE_CLK_RQ2#

ITPXDP_PITPXDP_N

CLK_BUF_EXP_NCLK_BUF_EXP_P

CLK_BUF_DOT96_NCLK_BUF_DOT96_P

CLK_BUF_REF14

CLK_BUF_CKSSCD_NCLK_BUF_CKSSCD_P

CLK_48_USB30

DGPU_PRSNT#

PCIE_CLK_RQ2#



SML0_DATA

SML0_CLK

SML0_DATASML0_CLK

PCIE_TXN3_CPCIE_TXP3_C

XTAL25_OUT

XTAL25_IN

+VCCDIFFCLKN

3D3V_S0

3D3V_S53D3V_S5

3D3V_S0 3D3V_S0

3D3V_S5

3D3V_S0

PCIE_RXN2(82)PCIE_RXP2(82)

PCIE_TXN2(82)PCIE_TXP2(82)



CLK_PCI_FB (18)

PCH_SMBDATA (14,15,65,79,82)

PCH_SMBCLK (14,15,65,79,82)

SML1_DATA (27)

SML1_CLK (27)PCIE_RXN5(82)PCIE_RXP5(82)


DRAMRST_CNTRL_PCH (37)

CLK_PCIE_USB3#(82)CLK_PCIE_USB3(82)

CLK_EXP_N (5)CLK_EXP_P (5)

CLK_PCIE_WWAN(82)

CLK_PCIE_WWAN_REQ#(82)

CLK_PCIE_WWAN#(82)

EC_SWI# (27)

USB3_PEGB_CLKREQ#(82)

UMA_DIS# (22)

CLK_PCH_48M (32,97)

CLK_PCIE_LAN#(82)CLK_PCIE_LAN(82)

CLK_PCIE_WLAN#(65)CLK_PCIE_WLAN(65)

CLK_PCIE_WLAN_REQ#(65)

PCIE_CLK_LAN_REQ#(82)

PCIE_TXN3(82)

PCIE_RXP3(82)PCIE_RXN3(82)

PCIE_TXP3(82)

Title


Date: Sheet of


Nirvana 13 A00

PCH 4/9(PCI-E/SMBUS/CLOCK/CL)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

SSID = PCH

WWAN CLK

– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3– Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2if more than 2 PCI clocks + PCI loopback are routed.

NEW CARD

Dock

Intel GBE LAN

USB3.0 CLK

need very close to PCH

Card Reader

W-WAN

LAN

USB3.0

WLAN

PCIECLKRQ1# and PCIECLKRQ2#

Support S0 power only

PL 10K FOR Integrated CLOCK GEN mode.

For RTS5138

LAN CLK

WLAN CLK

UMA_DISCRETE#

UMA: 1 1

DIS :0 1

SG(PX) : 0 0

ATI(Muxless) : 1 0

20101224 A00:Change RN2010 to 0402 0 ohm pad.

20101224 A00:Change RN2011~RN2014 to 0402 0 ohm pad.

20110112 A00:Change C2007,C2008 to 15pF from 12pF base on vendor's report.

12 3

4

RN2021

SRN10KJ-5-GP

RN2021

SRN10KJ-5-GP

12 3

4

RN

0R4P2R-PAD

RN2012

RN

0R4P2R-PAD

RN2012

1 2C2010 SCD1U10V2KX-5GPC2010 SCD1U10V2KX-5GP

12 3

4

RN

0R4P2R-PAD

RN2013

RN

0R4P2R-PAD

RN2013

1234 5

678

RN2001

SRN10KJ-6-GP

RN2001

SRN10KJ-6-GP

12 3

4

RN2005SRN2K2J-1-GPRN2005SRN2K2J-1-GP

123

4




123

4 RN2003SRN2K2J-1-GPRN2003SRN2K2J-1-GP

12 3

4

RN2020 SRN10KJ-5-GPRN2020 SRN10KJ-5-GP

12

R2011

10K

R2J-3

-GPDY

R2011

10K

R2J-3

-GPDY

12 3

4

RN

0R4P2R-PAD

RN2010

RN

0R4P2R-PAD

RN2010




12

R20061M1R2J-GPR20061M1R2J-GP

41

2 3

X2001

XTAL-25MHZ-155-GP

82.30020.D412nd = 82.30020.G713rd = 82.30020.G61

X2001

XTAL-25MHZ-155-GP

82.30020.D412nd = 82.30020.G713rd = 82.30020.G61


12 3

4

RN2007

SRN2K2J-1-GP

RN2007

SRN2K2J-1-GP

12

R200410KR2J-3-GPR200410KR2J-3-GP

12

C2008

SC15P50V2JN-2-GP

C2008

SC15P50V2JN-2-GP


12

R2010

10K

R2J-3

-GPDY

R2010

10K

R2J-3

-GPDY

1

2

34

5

6

Q2001

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

Q2001

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

1 2R20091KR2J-1-GP

R20091KR2J-1-GP



12


1 2

R2008

10KR2J-3-GP

R2008

10KR2J-3-GP

12

R2013

10K

R2J-3

-GP

R2013

10K

R2J-3

-GP1

2 34

RN2008

SRN10KJ-5-GP

RN2008

SRN10KJ-5-GP

1 2

R2007

90D9R2F-1-GP

R2007

90D9R2F-1-GP



PERN1BG34

PERP1BJ34

PERN2BE34

PERP2BF34

PERN3BG36

PERP3BJ36

PERN4BF36

PERP4BE36

PERN5BG37

PERP5BH37

PERN6BJ38

PERP6BG38

PERN7BG40

PERP7BJ40

PERN8BE38

PERP8BC38

PETN1AV32

PETP1AU32

PETN2BB32

PETP2AY32

PETN3AV34

PETP3AU34

PETN4AY34

PETP4BB34

PETN5AY36

PETP5BB36

PETN6AU36

PETP6AV36

PETN7AY40

PETP7BB40

PETN8AW38

PETP8AY38

CLKOUT_PCIE0NY40

CLKOUT_PCIE0PY39

CLKOUT_PCIE1NAB49

CLKOUT_PCIE1PAB47

CLKOUT_PCIE2NAA48

CLKOUT_PCIE2PAA47

CLKOUT_PCIE3NY37

CLKOUT_PCIE3PY36

CLKOUT_PCIE4NY43

CLKOUT_PCIE4PY45

CLKOUT_PCIE5NV45

CLKOUT_PCIE5PV46

CLKIN_GND1_N BJ30

CLKIN_GND1_P BG30

CLKIN_DMI_N BF18

CLKIN_DMI_P BE18

CLKIN_DOT_96N G24

CLKIN_DOT_96P E24

CLKIN_SATA_N AK7

CLKIN_SATA_P AK5

XTAL25_IN V47

XTAL25_OUT V49

REFCLK14IN K45

CLKIN_PCILOOPBACK H45

CLKOUT_PEG_A_N AB37

CLKOUT_PEG_A_P AB38

PEG_A_CLKRQ#/GPIO47 M10

PCIECLKRQ0#/GPIO73J2

PCIECLKRQ1#/GPIO18M1

PCIECLKRQ2#/GPIO20V10

PCIECLKRQ3#/GPIO25A8

PCIECLKRQ4#/GPIO26L12

PCIECLKRQ5#/GPIO44L14

CLKOUTFLEX0/GPIO64 K43

CLKOUTFLEX1/GPIO65 F47

CLKOUTFLEX2/GPIO66 H47

CLKOUTFLEX3/GPIO67 K49

CLKOUT_DMI_N AV22

CLKOUT_DMI_P AU22

PEG_B_CLKRQ#/GPIO56E6

CLKOUT_PEG_B_PAB40CLKOUT_PEG_B_NAB42

XCLK_RCOMP Y47

CLKOUT_DP_P AM13CLKOUT_DP_N AM12

CLKOUT_PCIE6NV40

CLKOUT_PCIE6PV42

PCIECLKRQ7#/GPIO46K12

CLKOUT_PCIE7NV38

CLKOUT_PCIE7PV37

CLKOUT_ITPXDP_NAK14

CLKOUT_ITPXDP_PAK13

SMBALERT#/GPIO11 E12

SMBCLK H14

SMBDATA C9

SML0ALERT#/GPIO60 A12

SML0CLK C8

SML0DATA G12

SML1ALERT#/PCHHOT#/GPIO74 C13

SML1CLK/GPIO58 E14

SML1DATA/GPIO75 M16

CL_CLK1 M7

CL_DATA1 T11

CL_RST1# P10

PCIECLKRQ6#/GPIO45T13

PCI-E*

CLOCKS

FLEX CLOCKS

SMBUS

Controller

Link

2 OF 10

Cougar

Point

PCH1B

COUGAR-GP-U2-NF

PCI-E*

CLOCKS

FLEX CLOCKS

SMBUS

Controller

Link

2 OF 10

Cougar

Point

PCH1B

COUGAR-GP-U2-NF



12 3

4

RN2019 SRN10KJ-5-GPRN2019 SRN10KJ-5-GP

12 3

4

RN

0R4P2R-PAD

RN2014

RN

0R4P2R-PAD

RN2014


12 3

4

RN

0R4P2R-PAD

RN2011

RN

0R4P2R-PAD

RN2011

12

R2012

10K

R2J-3

-GP

R2012

10K

R2J-3

-GP

12 3

4 RN2006SRN10KJ-5-GPRN2006SRN10KJ-5-GP

1234 5

678

RN2002

SRN10KJ-6-GP

RN2002

SRN10KJ-6-GP


12

C2007

SC15P50V2JN-2-GP

C2007

SC15P50V2JN-2-GP

1 2R201622R2J-2-GPR201622R2J-2-GP

12 3

4

RN2018

SRN10KJ-5-GP

RN2018

SRN10KJ-5-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDA_SYNC

PCH_SPI_CLK

PCH_SPI_SI

PCH_SPI_CS0#

SPI_CS0#_RHDA_CODEC_SYNC

HDA_SYNCHDA_SYNC_R

HDA_CODEC_BITCLK

HDA_SPKR

HDA_SDOUT

PCH_JTAG_TMS

HDA_BITCLK

HDA_RST#

HDA_SYNC

PCH_JTAG_TDI

LPC_AD0LPC_AD1LPC_AD2LPC_AD3

PCH_JTAG_TDO

HDA_SYNC

HDA_RST#

HDA_SDOUT

HDA_BITCLK

RBIAS_SATA3

SATA_COMP

SATA_DET#0

HDA_SDOUT

PCH_JTAG_TCK_BUF

LPC_AD[0..3]

RTC_X2

SM_INTRUDER#

RTC_X2

RTC_X1

SRTC_RST#

PCH_INTVRMEN

BBS_BIT0

RTC_X1

RTC_RST#

SATA3_COMP

HDA_CODEC_SDOUT

SATA_DET#0INT_SERIRQ

CE

RUN_ENABLE

RTC_AUX_S5

RTC_AUX_S5

1D05V_VTT

3D3V_S0

1D05V_VTT

3D3V_S0

+3VS_+1.5VS_HDA_IO

+3VS_+1.5VS_HDA_IO

BBS_BIT0 (18)

HDA_SPKR(29)

INT_SERIRQ (27)

LPC_AD[0..3] (27,65,71)

HDA_SDIN0(29)

SPI_CS0#_R(27,60)

SPI_SO_R(27,60)

SPI_SI_R(27,60)

SPI_CLK_R(27,60)

SATA_LED# (68)

ME_UNLOCK(27)

LPC_FRAME# (27,65,71)

HDA_CODEC_BITCLK(29)HDA_CODEC_RST#(29)

HDA_CODEC_SDOUT(29)HDA_CODEC_SYNC(29)

KB_DET# (69)

SATA_RXN5 (57)SATA_RXP5 (57)SATA_TXN5 (57)SATA_TXP5 (57)



PSW_CLR#(22)FP_DET#(22)

S_GPIO(22)

CE(49)

Title


Date: Sheet of


Nirvana 13 A00

PCH 5/9(SPI/RTC/LPC/SATA/IHDA)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to

sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this

signal on the board. Signal may have leakage paths via powered off devices (Audio

Codec) and hence contend with the external pull-up. A blocking FET is

recommended in such a case to isolate HDA_SYNC from the Audio Codec device

until after the Strap sampling is complete.

PLL ODVR VOLTAGE

HDA_SYNCLow = 1.8V (Default)High = 1.5V

This signal has a weak internal pull down.

On Die PLL VR is supplied by 1.5V when

sampled high, 1.8 V when sampled low.

Needs to be pulled High for Huron River platform.

co-operate with R2310

NO REBOOT STRAP

No Reboot Strap

HDA_SPKRLow = DefaultHigh = No Reboot

ESATA

ODD

HDD1

HDD2

Notes:

ME_UNLOCK (HDA_SDO) connect to EC.

Make sure EC drive this pin "low" all the time.

SSID = PCH

INTVRMEN- Integrated SUS1.05V VRM EnableHigh - Enable internal VRsLow - Enable external VRs

HDA_SDOUTLow = DefaultHigh = Enable

Flash Descriptor Security Overide

20100721 Modify:Remove TP2105 and change PCH_GPIO33 to CE.

20110110 A00:Merge R2115,R2116 to RN2101.

RTCX1A20

RTCX2C20

INTVRMENC17

INTRUDER#K22

HDA_BCLKN34

HDA_SYNCL34

HDA_RST#K34

HDA_SDIN0E34

HDA_SDIN1G34

HDA_SDIN2C34

HDA_SDOA36

SATALED# P3

FWH0/LAD0 C38

FWH1/LAD1 A38

FWH2/LAD2 B37

FWH3/LAD3 C37

LDRQ1#/GPIO23 K36

FWH4/LFRAME# D36

LDRQ0# E36

RTCRST#D20

HDA_SDIN3A34

HDA_DOCK_EN#/GPIO33C36

HDA_DOCK_RST#/GPIO13N32

SRTCRST#G22

SATA0RXN AM3

SATA0RXP AM1

SATA0TXN AP7

SATA0TXP AP5

SATA1RXN AM10

SATA1RXP AM8

SATA1TXN AP11

SATA1TXP AP10

SATA2RXN AD7

SATA2RXP AD5

SATA2TXN AH5

SATA2TXP AH4

SATA3RXN AB8

SATA3RXP AB10

SATA3TXN AF3

SATA3TXP AF1

SATA4RXN Y7

SATA4RXP Y5

SATA4TXN AD3

SATA4TXP AD1

SATA5RXN Y3

SATA5RXP Y1

SATA5TXN AB3

SATA5TXP AB1

SATAICOMPI Y10

SPI_CLKT3

SPI_CS0#Y14

SPI_CS1#T1

SPI_MOSIV4

SPI_MISOU3

SATA0GP/GPIO21 V14

SATA1GP/GPIO19 P1

JTAG_TCKJ3

JTAG_TMSH7

JTAG_TDIK5

JTAG_TDOH1

SERIRQ V5

SPKRT10

SATAICOMPO Y11

SATA3COMPI AB13

SATA3RCOMPO AB12

SATA3RBIAS AH1

RTC

IHDA

SATA

LPC

SPI

JTAG

SATA 6G

1 OF 10

Cougar

Point

PCH1A

COUGAR-GP-U2-NF

RTC

IHDA

SATA

LPC

SPI

JTAG

SATA 6G

1 OF 10

Cougar

Point

PCH1A

COUGAR-GP-U2-NF


1 2R2112 37D4R2F-GPR2112 37D4R2F-GP

G

S

D

Q2101

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

Q2101

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

12

R2117100KR2J-1-GPR2117100KR2J-1-GP

12 3

4

RN2101

SRN20KJ-1-GP

RN2101

SRN20KJ-1-GP

1 2R2114 750R2F-GPR2114 750R2F-GP


1 2

R2105330KR2F-L-GP

R2105330KR2F-L-GP

12

EC2101

SC

4D

7P

50V

2C

N-1

GPDY

EC2101

SC

4D

7P

50V

2C

N-1

GPDY

1 2R2110 33R2J-2-GPR2110 33R2J-2-GP


1 2R2113 49D9R2F-GPR2113 49D9R2F-GP

123

4

RN2104

SRN10KJ-5-GP

RN2104

SRN10KJ-5-GP

1234 5

678

RN2103

SRN10KJ-6-GP

RN2103

SRN10KJ-6-GP

12

EC2103

SC

4D

7P

50V

2C

N-1

GPDY

EC2103

SC

4D

7P

50V

2C

N-1

GPDY

12 3

4

RN2102

SRN33J-5-GP-U

RN2102

SRN33J-5-GP-U

1 2R2101 10MR2J-L-GPR2101 10MR2J-L-GP

1 2R2107 1KR2J-1-GPR2107 1KR2J-1-GP

21

G2101

GAP-OPEN

G2101

GAP-OPEN


1 4

32

X2101

X-32D768KHZ-67-GP

82.30001.A812nd = 82.30001.691

3rd = 82.30001.861

X2101

X-32D768KHZ-67-GP

82.30001.A812nd = 82.30001.691

3rd = 82.30001.861

1 2R2103 1KR2J-1-GPR2103 1KR2J-1-GP

12

C2104SC1U6D3V2KX-GP

C2104SC1U6D3V2KX-GP

1 2R2108 33R2J-2-GPR2108 33R2J-2-GP

12

C2102SC15P50V2JN-2-GPC2102SC15P50V2JN-2-GP

1 2R2109 33R2J-2-GPR2109 33R2J-2-GP

12

EC2102

SC

4D

7P

50V

2C

N-1

GPDY

EC2102

SC

4D

7P

50V

2C

N-1

GPDY


12

R21041M1R2J-GP

R21041M1R2J-GP

12

R2124

33R2J-2-GP

R2124

33R2J-2-GP

12 R212333R2J-2-GP R212333R2J-2-GP12 R212233R2J-2-GP DY R212233R2J-2-GP DY

12

C2103SC1U6D3V2KX-GPC2103SC1U6D3V2KX-GP


12

C2101

SC

15P

50V

2JN

-2-G

PC

2101

SC

15P

50V

2JN

-2-G

P

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TS_VSS

MFG_MODE

PCH_GPIO27

PCH_GPIO16

MFG_MODE

UMA_DIS#

EC_SMI#

3G_EN

H_RCIN#

RTC_DET#PCH_GPIO57

H_A20GATE

DGPU_HPD_INTR#EC_SCI#

S_GPIO GPIO0

ICC_EN#

PLL_ODVR_EN

DMI_OVRVLTG

FDI_OVRVLTG

ICC_EN#

PCH_TEMP_ALERT#

PCH_THERMTRIP_R

INIT3_3V#

FDI_OVRVLTG

DMI_OVRVLTG

H_PECI_R

PLL_ODVR_EN

GSENSOR_DET

3G_EN

EC_SMI#

DGPU_HPD_INTR# VRAM_SIZE1

PSW_CLR#

VRAM_SIZE2

PCH_TEMP_ALERT#

EC_SCI#

DBC_EN

PCH_NCTF_2

PCH_NCTF_4

PCH_NCTF_3

PCH_NCTF_1

SATA_ODD_PRSNT#

PCH_GPIO48

PCH_GPIO15

PCH_GPIO48

PCH_GPIO15

DBC_EN

GSENSOR_DET

PCH_GPIO57

RTC_DET#

3D3V_S0

3D3V_S0

3D3V_S5

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

H_A20GATE (27)

H_CPUPWRGD (5,36)

H_THERMTRIP# (5,36)

H_RCIN# (27)

H_PECI (5,27)

EC_SMI#(27)

SATA_ODD_PRSNT#(56)

EC_SCI#(27)

SATA_ODD_PWRGT (56)

FP_DET#(21)

UMA_DIS# (20)

DBC_EN(49)

3G_EN(82)

S_GPIO(21)

PSW_CLR#(21)

RTC_DET#(60)

Title


Date: Sheet of


Nirvana 13 A00

PCH 6/9(GPIO/CPU)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

PCH 6/9(GPIO/CPU)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

PCH 6/9(GPIO/CPU)


<Core Design>

TS Signal Disable Guideline:

TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4

should not float on the motherboard. They should

be tied to GND directly.

Integrated Clock Enable functionality is achieved

via soft-strap. The default is integrated clock

enable.

GPIO27 has a weak[20K] internal pull up.

To enable on-die PLL Voltage regurator,

should not place external pull down.

Note:For PCH debug with XDP, need to NO STUFF R2218

ICC_EN#

GPIO36(DMI_OVRVLTG)

DMI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated to same voltage(DC Coupling Model DEFAULT)

PLL ON DIE VR ENABLE

NOTE:This signal has a weak internal pull-up 20KENABLED -- HIGH (R2212 UNSTUFFED) DEFAULTDISABLED -- LOW (R2212 STUFFED)

LOW (R2211)- ENABLED

Integrated Clock Chip Enable

HIGH (R2211 DY)- DISABLED [DEFAULT]

Integrated Clock Enable functionality is achieved

via soft-strap. The default is integrated clock

enable.

GPIO37(FDI_OVRVLTG)

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated to same voltage(DC Coupling Model DEFAULT)

SSID = PCH

GPIO8 has a weak[20K] internal pull up.

[VRAM_SIZE1:VRAM_SIZE2]

LL=512M / HL=1G / LH=2G

GSENSOR_ADI GSENSOR_ST R2205 DY 10K

R2206 100K DY

12

R220510KR2J-3-GPGSENSOR_ST

R220510KR2J-3-GPGSENSOR_ST

1 2R22011KR2J-1-GP

R22011KR2J-1-GP

12

R220710KR2J-3-GP

DY

R220710KR2J-3-GP

DY




12

R220910KR2J-3-GP

DY

R220910KR2J-3-GP

DY

1 2R22121KR2J-1-GP

DY R22121KR2J-1-GP

DY

1 2R2213 0R0402-PADR2213 0R0402-PAD

12 3

4RN2203

SRN10KJ-5-GP

RN2203

SRN10KJ-5-GP1 TP2205 TPAD14-GPTP2205 TPAD14-GP

1 2

R2222 10KR2J-3-GPR2222 10KR2J-3-GP

123

4

RN2204

SRN10KJ-5-GP

RN2204

SRN10KJ-5-GP

1 2

R2214 10KR2J-3-GP

DYR2214 10KR2J-3-GP

DY


1 2

R2223 10KR2J-3-GPR2223 10KR2J-3-GP

12

R2206100KR2J-1-GP

GSENSOR_ADI R2206100KR2J-1-GP

GSENSOR_ADI



21

G2201

GA

P-O

PE

N

G2201

GA

P-O

PE

N

1 2R22111KR2J-1-GP

R22111KR2J-1-GP

1234 5

678

RN2201

SRN10KJ-6-GP

RN2201

SRN10KJ-6-GP


1 2

R2202

100KR2J-1-GP

R2202

100KR2J-1-GP

1 2

R2221

10KR2J-3-GP

R2221

10KR2J-3-GP

12

R220810KR2J-3-GPR220810KR2J-3-GP

1 2R2204 390R2J-1-GPR2204 390R2J-1-GP1 2R222010KR2J-3-GPR222010KR2J-3-GP

GPIO27E16

GPIO28P8

GPIO24/MEM_LEDE8

GPIO57D6

LAN_PHY_PWR_CTRL/GPIO12C4

NCTF_VSS#A4A4

NCTF_VSS#A44A44

NCTF_VSS#A45A45

NCTF_VSS#A46A46

NCTF_VSS#A5A5

NCTF_VSS#A6A6

NCTF_VSS#B3B3

NCTF_VSS#B47B47

NCTF_VSS#BD1BD1

NCTF_VSS#BD49BD49

NCTF_VSS#BE1BE1

NCTF_VSS#BE49BE49

TACH2/GPIO6H36

TACH0/GPIO17D40

TACH3/GPIO7E38

SATA3GP/GPIO37M5

SATA5GP/GPIO49V3

SCLOCK/GPIO22T5

SLOAD/GPIO38N2

SDATAOUT0/GPIO39M3

SDATAOUT1/GPIO48V13

PROCPWRGD AY11

RCIN# P5

PECI AU16

THRMTRIP# AY10

GPIO8C10

BMBUSY#/GPIO0T7

GPIO15G2

TACH1/GPIO1A42

SATA2GP/GPIO36V8

INIT3_3V# T14

STP_PCI#/GPIO34K1

GPIO35K4

SATA4GP/GPIO16U2

NCTF_VSS#F49 F49

A20GATE P4

TACH4/GPIO68 C40

TACH6/GPIO70 C41

TACH7/GPIO71 A40

TACH5/GPIO69 B41

NCTF_VSS#BH3 BH3

NCTF_VSS#BH47 BH47

NCTF_VSS#BJ4 BJ4

NCTF_VSS#BJ44 BJ44

NCTF_VSS#BJ45 BJ45

NCTF_VSS#BJ46 BJ46

NCTF_VSS#BJ5 BJ5

NCTF_VSS#BJ6 BJ6

NCTF_VSS#C2 C2

NCTF_VSS#C48 C48

NCTF_VSS#D1 D1

NCTF_VSS#D49 D49

NCTF_VSS#E1 E1

NCTF_VSS#E49 E49

NCTF_VSS#F1 F1

TS_VSS4 AK10

TS_VSS3 AH10

TS_VSS2 AK11

TS_VSS1 AH8

NC_1 P37

NCTF_VSS#BF1BF1

NCTF_VSS#BF49BF49

NCTF_VSS#BG2 BG2

NCTF_VSS#BG48 BG48

CPU/MISC

NCTF

GPIO

6 OF 10

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

D1,D49,E1,E49,F1,F49

Cougar

Point

PCH1F

COUGAR-GP-U2-NF

CPU/MISC

NCTF

GPIO

6 OF 10

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

D1,D49,E1,E49,F1,F49

Cougar

Point

PCH1F

COUGAR-GP-U2-NF

12

R221010KR2J-3-GPR221010KR2J-3-GP

1 2R2218100R2J-2-GP

R2218100R2J-2-GP

1 2R2219 0R0402-PADR2219 0R0402-PAD

1 2R22030R2J-2-GPDY R22030R2J-2-GPDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+1.8VS_VCCTX_LVDS

+1.05VS_VCC_DMI_CCI

+1.05VS_VCC_DMI

+VCCA_DAC_1_2

+1.05VS_VCC_DMI

+3VS_VCCA_LVDS

VCCAPLLEXP

VCCFDIPLL

VCCVRM

1D05V_VTT

1D05V_VTT

1D05V_VTT

1D05V_VTT

3D3V_S0

1D05V_VTT

3D3V_S0

1D05V_VTT

1D8V_S0

3D3V_S5

3D3V_S0

1D8V_S0

1D5V_S0

5V_S5 3D3V_DAC_S0

3D3V_DAC_S0

3D3V_S0

1D5V_S0

3D3V_S0

Title


Date: Sheet of


Nirvana 13 A00

PCH 7/9(POWER1)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

PCH 7/9(POWER1)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

PCH 7/9(POWER1)


<Core Design>

0.001A

0.001A

0.06A

0.266A

2.925A(Total current of VCCIO)

0.266A (Totally VCC3_3 current)

0.159A(Totally current of VCCVRM)

0.042A (Totally current of VCCDMI)

(10uF x1)

(1uFx3)

0.16A

(10uFx1_0603)

(1uF x4)

(0.1uF x1)

1.3A

0.042A

(10uF x1_0603)(0.1uF/0.01uF x1)

(22uF x1)(0.01uF x2)

0.06A

(0.1uFx1)

(1uFx1)

0.02A

0.001A

(1uF x1)

(1uFx1)(10uFx1)

0.02A

0.19A

0.02A

(0.1uFx1)

VCCVRM(Internal PLL and VRMs):

A.1.5V for Mobile

B.1.8 V for Desktop

SSID = PCH

0.19A

0.02A

6A

3.3V CRT LDO

Current Limit=360mA

20101224 A00:0402 0R pad: R2301,R2306,R2307,R2308.

20101228 A00:0402 0R pad: R2301.

12

C2301

SC

10U

6D

3V

5K

X-1

GP

C2301

SC

10U

6D

3V

5K

X-1

GP

12


12

C2303

SC

1U

6D

3V

2K

X-G

PC

2303

SC

1U

6D

3V

2K

X-G

P

1 2

L2301

HCB1608KF-181-GP

2nd = 68.00206.0413rd = 68.00335.081

68.00214.051

DYL2301

HCB1608KF-181-GP

2nd = 68.00206.0413rd = 68.00335.081

68.00214.051

DY

12

R2306

0R0402-PAD

R2306

0R0402-PAD

12

C2311

SC

1U

10V

2K

X-1

GP

C2311

SC

1U

10V

2K

X-1

GP

12

C2322SCD1U10V2KX-5GPC2322SCD1U10V2KX-5GP

12

C2307

SC

1U

6D

3V

2K

X-G

PC

2307

SC

1U

6D

3V

2K

X-G

P

1 2R23050R0805-PADR23050R0805-PAD

12


1 2R23040R0603-PADR23040R0603-PAD

12

R2308

0R0402-PAD

R2308

0R0402-PAD

12

C2312

SC

1U

6D

3V

2K

X-G

P

C2312

SC

1U

6D

3V

2K

X-G

P

12

C2313

SC

D01U

16V

2K

X-3

GP

C2313

SC

D01U

16V

2K

X-3

GP

12

C2316

SC

D01U

16V

2K

X-3

GP

C2316

SC

D01U

16V

2K

X-3

GP

12


12

C2305

SC

10U

6D

3V

5K

X-1

GP

C2305

SC

10U

6D

3V

5K

X-1

GP

12

C2306

SC

1U

6D

3V

2K

X-G

PC

2306

SC

1U

6D

3V

2K

X-G

P

12

C2315

SC

10U

6D

3V

5K

X-1

GP

C2315

SC

10U

6D

3V

5K

X-1

GP

12

C2308

SC

1U

6D

3V

2K

X-G

PC

2308

SC

1U

6D

3V

2K

X-G

P

VCCCOREAA23

VCCCOREAC23

VCCCOREAD21

VCCCOREAD23

VCCCOREAF21

VCCCOREAF23

VCCCOREAG21

VCCCOREAG23

VCCCOREAG24

VCCCOREAG26

VCCCOREAG27

VCCCOREAG29

VCCCOREAJ23

VCCCOREAJ26

VCCCOREAJ27

VccDFTERM AJ17

VccDFTERM AJ16

VCCIOAN21

VCCIOAN26

VCCIOAN27

VCCIOAP21

VCCIOAP26

VCCIOAT24

VCCIOAN16

VCCIOAN17

VCCIOAP23

VCCIOAP24

VCCADAC U48

VCCTX_LVDS AM37

VCCTX_LVDS AM38

VCCALVDS AK36

VCCVRM AT16

VCCVRMAP16

VCCAPLLEXPBJ22

VCCAFDIPLLBG6

VCCIOAN19VCCTX_LVDS AP37

VCCTX_LVDS AP36

VSSADAC U47

VSSALVDS AK37

VCCIOAP17

VCC3_3 V33

VCC3_3 V34

VCC3_3BH29 VccDFTERM AG17

VccDFTERM AG16

VCCDMI AT20

VCCIOAN33

VCCIOAN34

VCCCOREAJ29

VCCCOREAJ31

VCCSPI V1

VCCCLKDMI AB36

VCCDMIAU20

POWER

VCC CORE

DMI

VCCIO

CRT

LVDS

FDI

NAND / SPI

HVCMOS

7 OF 10

Cougar

Point

PCH1G

COUGAR-GP-U2-NF

POWER

VCC CORE

DMI

VCCIO

CRT

LVDS

FDI

NAND / SPI

HVCMOS

7 OF 10

Cougar

Point

PCH1G

COUGAR-GP-U2-NF

VIN1

GND2

EN3 NC#4 4

VOUT 5

U2301

G9091-330T11U-GP

2nd = 74.09198.G7F

74.09091.J3F

3rd = 74.07716.A7F

U2301

G9091-330T11U-GP

2nd = 74.09198.G7F

74.09091.J3F

3rd = 74.07716.A7F


12

C2317

SC

D01U

16V

2K

X-3

GP

C2317

SC

D01U

16V

2K

X-3

GP

12

R2301

0R0402-PAD

R2301

0R0402-PAD

12


12


12

C2302

SC

1U

6D

3V

2K

X-G

PC

2302

SC

1U

6D

3V

2K

X-G

P

12

R2307

0R0402-PAD

R2307

0R0402-PAD


12

C2314

SC

D1U

10V

2K

X-5

GP

C2314

SC

D1U

10V

2K

X-5

GP

12

C2304

SC

1U

6D

3V

2K

X-G

PC

2304

SC

1U

6D

3V

2K

X-G

P

12

C2309

SC

1U

6D

3V

2K

X-G

PC

2309

SC

1U

6D

3V

2K

X-G

P

12

C2318

SC

10U

6D

3V

5K

X-1

GP

C2318

SC

10U

6D

3V

5K

X-1

GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+1.05VS_VCCA_A_DPL

+V1.05S_SSCVCC

+VCCSUS1

+V1.05S_VCCAPLL_SATA3

+V3.3S_VCC_CLKF33

+V1.05S_SSCVCC

+V3.3S_VCC_CLKF33

+1.05VS_VCCA_A_DPL

+VCCRTCEXT

DCPSUSBYP

VCCACLK

+VCCSST

+VCCDIFFCLK

+1.05VS_VCCA_B_DPL

+5VA_PCH_VCC5REFSUS

+VCCAPLL_CPY_PCH

+5VS_PCH_VCC5REF

+VCCPDSW

+VCCDIFFCLK

DCPSUS

+VCCA_USBSUS

1D05V_VTT

3D3V_S5

3D3V_S5

3D3V_S5

3D3V_S0

3D3V_S5

1D05V_VTT

1D05V_VTT

3D3V_S0

1D05V_VTT

3D3V_S0

1D05V_VTT

1D05V_VTT

1D05V_VTT

1D05V_VTT

RTC_AUX_S5

1D05V_VTT

3D3V_S0

1D5V_S01D05V_VTT

1D05V_VTT

+VCCDIFFCLKN

3D3V_S5

1D05V_VTT

3D3V_S5

1D05V_VTT

5V_S0

5V_S5

1D5V_S0

+3VS_+1.5VS_HDA_IO

3D3V_S5

+3VS_+1.5VS_HDA_IO

Title


Date: Sheet of


Nirvana 13 A00

PCH 8/9(POWER2)

24 103Friday, December 24, 2010

<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

PCH 8/9(POWER2)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

PCH 8/9(POWER2)


<Core Design>

0.08A

0.08A

(220uFx1)

(220uFx1)

(1uFx1)

(1uFx1)

(1uFx1)(10uFx1)

(0.1uFx1)

(1uFx3)(22uFx2_0603)

(10uFx1)

0.002A

SSID = PCH

1.01A (Total current of VCCASW)

0.16A (Totally current of VCCVRM

(0.1uFx1)

0.055A

(0.1uFx1)

0.095A

0.001A

6uA

(0.1uFx2)

(1uFx1)

(1uFx1)

(0.1uFx2)

(1uFx1)

(1uFx1)

(4.7uFx1_0603)

(1uFx1)

(10uFx1)

(0.1uFx1)

(1uFx1)

(0.1uFx2)

(1uFx1)

0.01A

(1uFx1)

0.001A

0.001A

0.097A (Totally current of VCCSUS3_3)

(1uFx1)

(0.1uFx1)

(0.1uFx1)

(0.1uFx1)

(0.1uFx1)

(1uFx1)

20101224 A00:0402 0R pad: R2404,R2405.

12

C2433SCD1U10V2KX-5GP


12

C2414SC1U6D3V2KX-GP

C2414SC1U6D3V2KX-GP

12

C2413SC1U6D3V2KX-GPC2413

SC1U6D3V2KX-GP

12

C2401

SC

10U

6D

3V

5K

X-1

GP

C2401

SC

10U

6D

3V

5K

X-1

GP

1 2

L2403

IND-10UH-218-GP

68.10050.10Y2nd = 68.10090.10B

L2403

IND-10UH-218-GP

68.10050.10Y2nd = 68.10090.10B

12


12

C2418

SC

D1U

10V

2K

X-5

GP

C2418

SC

D1U

10V

2K

X-5

GP

12

C2444

SC

10U

6D

3V

3M

X-G

P

DY

C2444

SC

10U

6D

3V

3M

X-G

P

DY

12

C2422

SC

D1U

10V

2K

X-5

GP

C2422

SC

D1U

10V

2K

X-5

GP

12


1 2R24090R0603-PADR24090R0603-PAD

12

C2443

SC

10U

6D

3V

3M

X-G

P

DY

C2443

SC

10U

6D

3V

3M

X-G

P

DY


12



12



12



12


12

C2412SC1U6D3V2KX-GPC2412

SC1U6D3V2KX-GP

12 R2405

0R0402-PAD

R2405

0R0402-PAD


1 2R24030R0603-PADR24030R0603-PAD

12

C2410

SC1U6D3V2KX-GP

C2410

SC1U6D3V2KX-GP

12

C2409

SC1U6D3V2KX-GP

C2409

SC1U6D3V2KX-GP

12



21

D2402

CH751H-40PT-GP83.R0304.A8F2nd = 83.R2004.B8F

D2402



1 2

L2402

IND-10UH-218-GP

68.10050.10Y2nd = 68.10090.10B

L2402

IND-10UH-218-GP

68.10050.10Y2nd = 68.10090.10B

12


12

C2402SC1U10V2KX-1GPC2402SC1U10V2KX-1GP

12

C2434

SC

10U

6D

3V

5K

X-1

GPDY

C2434

SC

10U

6D

3V

5K

X-1

GPDY

1 2R24060R0603-PADR24060R0603-PAD

12

C2421

SC

D1U

10V

2K

X-5

GP

C2421

SC

D1U

10V

2K

X-5

GP

12


12

C2407

SC

1U

6D

3V

2K

X-G

PC

2407

SC

1U

6D

3V

2K

X-G

P

12

C2404S

C10U

6D

3V

5K

X-1

GPDY

C2404S

C10U

6D

3V

5K

X-1

GPDY


1 2

R2411

0R3J-0-U-GP

DYR2411

0R3J-0-U-GP

DY

12

C2428SC1U6D3V2KX-GP

C2428SC1U6D3V2KX-GP

1TP2405TPAD14-GP TP2405TPAD14-GPDCPSUSBYPV12

VCCASWAA19

VCCASWAA21

VCCASWAA24

VCCASWAA27

VCCASWAA29

VCCSUSHDA P32

VCCSUS3_3 P24

VCCIO T26

VCCIO AD17

VCCASWAA31

VCCASWAC26

VCCASWAC27

VCCASWAC29

VCCASWAC31

VCCASWAD29

V5REF P34

VCC3_3 T34

VCCRTCA22

VCCSUS3_3 V24

VCCSUS3_3 V23

VCCSUS3_3 T24

VCCSUS3_3 T23

VCCIO AC16

VCCADPLLBBF47

VCCDIFFCLKNAF33

V5REF_SUS M26

VCCIO AC17

DCPSUST17

VCCSSCAG33

VCCADPLLABD47

VCCVRMY49

VCCACLKAD49

DCPRTCN16

VCCASWAA26

VCCDIFFCLKNAF34

VCCIOAF17

DCPSSTV16

VCCIO AF13

VCCASW T21

VCCASW V21

VCCASW T19

VCC3_3 AA16

VCC3_3 W16

VCCSUS3_3 N20

VCCSUS3_3 N22

VCCSUS3_3 P20

VCCSUS3_3 P22

VCCIO N26

VCCIO P26

VCCIO P28

VCCIO T27

V_PROC_IOBJ8

VCCIO T29

VCCDIFFCLKNAG34

VCCASWAD31

VCCASWW21

VCCASWW23

VCCASWW24

VCCASWW26

VCCASWW29

VCCASWW31

VCCASWW33

VCCIO AF14

VCCVRM AF11

VCCIO AH13

VCCIO AH14

VCC3_3 AJ2

VCCAPLLSATA AK1

DCPSUSAL24

VCCIOAL29

DCPSUS AN23

VCCSUS3_3 AN24

VCCAPLLDMI2BH23

DCPSUSV19

VCCDSW3_3T16

VCC3_3T38

POWER

SATA

USB

Clock and Miscellaneous

HDA

CPU

RTC

PCI/GPIO/LPC

MISC

10 OF 10

Cougar

Point

PCH1J

COUGAR-GP-U2-NF

POWER

SATA

USB

Clock and Miscellaneous

HDA

CPU

RTC

PCI/GPIO/LPC

MISC

10 OF 10

Cougar

Point

PCH1J

COUGAR-GP-U2-NF

12


12

C2437SC1U10V2KX-1GPDYC2437SC1U10V2KX-1GPDY

12

C2417SC4D7U6D3V3KX-GP


1 2

R2408

10R2J-2-GP

R2408

10R2J-2-GP

1 2

R2407

10R2J-2-GP

R2407

10R2J-2-GP

12

C2435SC1U6D3V2KX-GP

C2435SC1U6D3V2KX-GP

12 R2404

0R0402-PAD

R2404

0R0402-PAD

1 2

L2401

IND-10UH-218-GP

68.10050.10Y2nd = 68.10090.10B

L2401

IND-10UH-218-GP

68.10050.10Y2nd = 68.10090.10B

12

C2432SC1U6D3V2KX-GP

C2432SC1U6D3V2KX-GP

12

C2403

SC

10U

6D

3V

5K

X-1

GP

C2403

SC

10U

6D

3V

5K

X-1

GP


12

C2406

SC

1U

6D

3V

2K

X-G

PC

2406

SC

1U

6D

3V

2K

X-G

P

21

D2401


D2401


12

C2408

SC

1U

6D

3V

2K

X-G

PC

2408

SC

1U

6D

3V

2K

X-G

P

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

PCH 9/9(VSS)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

PCH 9/9(VSS)


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

PCH 9/9(VSS)


<Core Design>

SSID = PCHSSID = PCH

VSSAA17

VSSAA2

VSSAA3

VSSAA34

VSSAB11

VSSAB14

VSSAB39

VSSAB4

VSSAB43

VSSAB5

VSSAB7

VSSAC19

VSSAC2

VSSAC21

VSSAC24

VSSAC33

VSSAC34

VSSAC48

VSSAD10

VSSAD11

VSSAD12

VSSAD13

VSSAD19

VSSAD24

VSSAD26

VSSAD27

VSSAD33

VSSAD34

VSSAD36

VSSAD37

VSSAD39

VSSAD4

VSSAD40

VSSAD42

VSSAD43

VSSAD45

VSSAD46

VSSAF10

VSSAF12

VSSAD16

VSSAF16

VSSAF19

VSSAF24

VSSAF26

VSSAF27

VSSAF29

VSSAF31

VSSAF38

VSSAF4

VSSAF42

VSSAF46

VSSAF7

VSSAF8

VSSAG19

VSSAG2

VSSAG31

VSSAG48

VSSAH11

VSSAH3

VSSAH36

VSSAH39

VSSAH40

VSSAH42

VSSAH46

VSSAH7

VSSAJ19

VSSAJ33

VSSAJ34

VSSAK12

VSSAK3

VSS AK38

VSS AK4

VSS AK42

VSS AK46

VSS AK8

VSS AL16

VSS AL17

VSS AL19

VSS AL2

VSS AL21

VSS AL23

VSS AL26

VSS AL27

VSS AL31

VSS AL48

VSS AM11

VSS AM14

VSS AM36

VSS AM39

VSS AM45

VSS AM46

VSS AM7

VSS AN2

VSS AN29

VSS AN3

VSS AN31

VSS AP12

VSS AP19

VSS AP28

VSS AP30

VSS AP32

VSS AP38

VSS AP42

VSS AP46

VSS AP8

VSS AR2

VSS AR48

VSS AT11

VSS AT13

VSS AT18

VSS AT22

VSS AT26

VSS AT28

VSS AT30

VSS AT32

VSS AT42

VSS AT46

VSS AT7

VSS AU24

VSS AU30

VSS AV16

VSS AV20

VSS AV24

VSS AV30

VSS AV38

VSS AV4

VSS AV43

VSS AV8

VSS AW14

VSS AW18

VSS AW2

VSS AW22

VSS AW26

VSS AW28

VSS AW32

VSS AW34

VSS AW36

VSS AW40

VSS AW48

VSS AV11

VSS AY12

VSS AY22

VSS AY28

VSSAD8

VSSAE3

VSSAD14

VSS AP4

VSSH5

VSSAF5

VSSAD38

VSSAA33

VSSAJ21

VSSAJ24

VSSAE2

VSS AT34

VSS AT39

VSS AM43

VSS AL34VSS AL33

8 OF 10

Cougar

Point

PCH1H

COUGAR-GP-U2-NF

8 OF 10

Cougar

Point

PCH1H

COUGAR-GP-U2-NF

VSSAY4

VSSAY42

VSSAY46

VSSAY8

VSSB11

VSSB15

VSSB19

VSSB23

VSSB27

VSSB31

VSSB35

VSSB39

VSSB7

VSSBB12

VSSBB16

VSSBB20

VSSBB22

VSSBB24

VSSBB28

VSSBB30

VSSBB38

VSSBB4

VSSBB46

VSSBC14

VSSBC18

VSSBC2

VSSBC22

VSSBC26

VSSBC32

VSSBC34

VSSBC36

VSSBC40

VSSBC42

VSSBC48

VSSBD46

VSSBD5

VSSBE22

VSSBE26

VSSBE40

VSSBF10

VSSBF12

VSSBF16

VSSBF20

VSSBF22

VSSBF24

VSSBF26

VSSBF28

VSSBD3

VSSBF30

VSSBF38

VSSBF40

VSSBF8

VSSBG17

VSSBG21

VSSBG33

VSSBG44

VSSBG8

VSSBH11

VSSBH15

VSSBH17

VSSBH19

VSSBH27

VSSBH31

VSSBH33

VSSBH35

VSSBH39

VSSBH43

VSSBH7

VSSD3

VSSD12

VSSD16

VSSD18

VSSD22

VSSD24

VSSD26

VSSD30

VSSD32

VSS K7

VSS L18

VSS L2

VSS L20

VSS L26

VSS L28

VSS L36

VSS L48

VSS M12

VSS P16

VSS M18

VSS M22

VSS M24

VSS M30

VSS M32

VSS M34

VSS M38

VSS M4

VSS M42

VSS M46

VSS M8

VSS N18

VSS P30

VSS P11

VSS P18

VSS T33

VSS P40

VSS P43

VSS P47

VSS P7

VSS R2

VSS R48

VSS T12

VSS T31

VSS T37

VSS T4

VSS W34

VSS T46

VSS T47

VSS T8

VSS V11

VSS V17

VSS V26

VSS V27

VSS V29

VSS V31

VSS V36

VSS V39

VSS V43

VSS V7

VSS W17

VSS W19

VSSD34

VSSD38

VSSD42

VSSD8

VSSE18

VSSE26

VSSG18

VSSG20

VSSG26

VSSG28

VSSG36

VSSG48

VSSH12

VSSH18

VSS W2

VSS W27

VSS W48

VSS Y12

VSS Y38

VSS Y4

VSS Y42

VSS Y46

VSS Y8

VSS BG29

VSS N24

VSS AJ3

VSS N47

VSSH22

VSSH24

VSSH26

VSSH30

VSSH32

VSSH34

VSSF3

VSS K39

VSS K46

VSS H46

VSS K18

VSS K26

VSS AD47

VSS B43

VSS BE10

VSS BG41

VSS G14

VSS H16

VSS T36

VSS BG22

VSS BG24

VSS C22

VSS AP13

VSSF45

VSSH10

VSS M14

VSS AP3

VSS AP1

VSS BE16

VSS BC16

VSS BG28

VSS BJ28

9 OF 10

Cougar

Point

PCH1I

COUGAR-GP-U2-NF

9 OF 10

Cougar

Point

PCH1I

COUGAR-GP-U2-NF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EC_ENABLE#_1

FAN_TACH1

E51_RxD

BAT_SCLBAT_SDA

BLUETOOTH_EN

AC_IN#_KBCBAT_IN#

S5_ENABLEECRST#

EC_ENABLE#_1

PANEL_BLEN

PSL_IN1

PROCHOT_EC

ECSMI#_KBC

ECRST#

EC_SPI_DO_C

EC_SPI_CLK_C

KCOL0

KCOL9KCOL10KCOL11KCOL12KCOL13KCOL14KCOL15KCOL16

KROW0KROW1

KCOL1

KROW2

KCOL2

KROW3

KCOL3KCOL4

KROW4KROW5

KCOL5KCOL6

KROW6KROW7

KCOL7KCOL8

KBC_VCORF

PANEL_BLEN

KBC_ON#_R

EC_GPIO72

KBC_ON#

ECSCI#_KBC

ECSWI#_KBC

LPC_AD0LPC_AD1LPC_AD2LPC_AD3

PSL_IN2

AC_IN#_KBC

MEDIA_BTN1#

EC

_A

GN

D

VBAT

H_PROCHOT#_EC

PROCHOT_EC

3D3V_AUX_KBC_VCC

EC_GPIO72

EC_SPI_DI_C

PSL_OUT

PSL_IN2

PLT_RST#_EC

PCB_VER_AD

MODEL_ID_DET

EC_SPI_CS#_C

MEDIA_BTN2#

KBC_ON#

PSL_OUT

EC_GPIO72

AC_IN#_KBC

KBC_ON#_R

AC_OK

KBC_ON#_RKBC_ON#

PSL_IN1

EC_GPIO72

PSL_IN1

EC_SPI_DI_C

USB_DET#

MEDIA_BTN1#

KBC_ON#_R

MEDIA_BTN3#

MEDIA_BTN2#

MEDIA_BTN1#

PCIE_WAKE#

INSTANT_ON#

KBC_ON#_R

USB_DET#

USBDET_CON#

ECSMI#_KBC

EC_SMI# ECSMI#_KBC

USB_DET#

ECSWI#_KBC

ECSCI#_KBC

ECSWI#_KBC

ECSCI#_KBC

CPU_THRM

SYS_THRM

PECI

ECRST#

EC_VTT

MODEL_ID_DET

DATA_RECOVERY#

KBC_ON#_R

MEDIA_BTN2#

PCB_VER_AD

EC_ENABLE#_1

USB_PWR_EN#AC_PRESENTE51_TxD

S5_ENABLE

KBC_ON#_GATE

AD_IA_HW2

USB3_PWR_ON

3D3V_S03D3V_AUX_KBC

3D3V_AUX_S5

EC_AGND

3D3V_AUX_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_KBCRTC_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_KBC

3D3V_S0

3D3V_AUX_KBC

EC_AGND

3D3V_AUX_KBC

EC_AGND

EC_AGND

EC_AGND

1D05V_VTT

3D3V_AUX_KBC

EC_AGND

IMVP_PWRGD(36,42)

MEDIA_BTN3#(82)

PCH_WAKE# (19)

SPI_CLK_R (21,60)

SPI_SI_R (21,60)

BAT_IN#(39)

SPI_SO_R (21,60)

AD_IA(40)

SPI_CS0#_R (21,60)

TPCLK (69)TPDATA (69)

USB_PWR_EN#(61)

PM_SLP_S4#(19,46)RSMRST#_KBC(19)

BLON_OUT (49)

SUS_PWR_ACK(19)

PLT_RST# (5,18,65,71,82)

PURE_HW_SHUTDOWN#(28,36)

ME_UNLOCK(21)

KCOL[0..16] (69)

KROW[0..7] (69)

H_A20GATE (22)

LID_CLOSE#(70)

BAT_SDA (39,40)BAT_SCL (39,40)

WIFI_RF_EN(65)

PM_CLKRUN# (19)

LPC_FRAME# (21,65,71)

INT_SERIRQ (21)

LPC_AD[0..3] (21,65,71)

S5_ENABLE(36)

AC_PRESENT(19)

BLUETOOTH_EN(63,65)

CLK_PCI_KBC (18)

SML1_DATA (20)SML1_CLK (20)

HDMI_IN# (51)

H_RCIN# (22)

H_PROCHOT# (5,40,42)

FAN1_DAC(28)

CPU_THRM(28)

SYS_THRM(28)

S0_PWR_GOOD(19,36)

L_BKLT_EN(17)

PSID_EC(38)

USBCHARGER_CB0(57)

PM_LAN_ENABLE (82)

LCD_TST(49)

BATT_WHITE_LED#(68)

CAP_LED(69)

RCID(38)

LCD_TST_EN (49)

TP_LOCK_LED#(68)

KBC_PWRBTN#(68)

AC_IN# (40)

AC_OK(40)

FAN_TACH1(28)

INSTANT_ON#(82)

USBDET_CON#(57)

EC_SMI#(22)

EC_SCI#(22)

EC_SWI#(20)

EC_SCI#(22)

EC_SWI#(20)

AD_IA_HW(40)

PCIE_WAKE#(82)PM_SLP_S3#(19,36,37,47)

KBC_BEEP(29)

AMP_MUTE#(29)PCH_SUSCLK_KBC(19)

PWRLED#(68)

H_PECI(5,22)

E51_RxD(65)E51_TxD(65)

PM_PWRBTN#(19)

CHG_AMBER_LED#(68)

FAN_TACH1(28)

KB_BL_CTRL(69)MEDIA_LED1#(82)

MEDIA_LED2#(82)MEDIA_LED3#(82)

DATA_RECOVERY#(82)

AD_IA_HW2 (40)

USB3_PWR_ON(62,82)

Title


Date: Sheet of



Nirvana 13 A00

KBC Nuvoton NPCE785PA2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00



<Core Design>

Title


Date: Sheet of



Nirvana 13 A00



<Core Design>

EC GPIO standard PH/PL

<------PCH / eDP

<------ BATTERY / CHARGER

SSID = KBC

NOTE:

Connect GND and AGND planes via either

0R resistor or one point layout connection.

EC_GPIO47 High Active

NOTE:

Locate resistors R2719 and R2722 close

to the NPCE791L.

<------ TP

ROSA Multi GPIO setting

PSL SOLUTION

PSL_IN1

PSL_OUT

10mW SOLUTION

VBACKUP

MEDIA BUTTON CONTROL

NOTES:

The NPCE795P GPIO/PWM outputs that are connected

to LEDs have high drive buffers (20mA) and can be

connected directly to the LEDs.

NOTES:

Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.

Notes:

The total SPI interface signal between EC and PCH

can’t not exceed 6500mil. The mismatch between

SPI signal must be within 500mil

143.0K100.0K 1.358VReserved

174.0KReserved 100.0K

Reserved

64.9K

Reserved 1.65V

76.8

100.0K

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0KX00

X01

3.0V

2.75V100.0K

100.0K

10.0K

Reserved

100.0K

100.0K

20.0K

2.0V

1.87V

1.204V

Reserved 100.0K 215.0K 1.048V

MODEL_ID_DET(GPIO07)

143.0K100.0K 1.358V

174.0K100.0K

47.0K(64.47025.6DL)

1.65V

64.9K(64.64925.6DL)

76.8K

100.0K

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0KDQ15_UMA 3.0V

2.75V100.0K

2.48V100.0K

100.0K

100.0K

100.0K

100.0K

10.0K(64.10025.6DL)

2.24V

20.0K(64.20025.6DL)

2.0V

33.0K

1.87V

1.204V

DQ15_Ventura 100.0K 215.0K 1.048V

DQ15_ATI

Reserved

DQ15_NVIDIA

Reserved

DN15_UMA

DN15_ATI

DN13_UMA

DN13_ATI

Need very close to EC

20101224 A00 Modify:

Change R2724 to 47K from 33K.

20101224 A00:

0402 0R pad: R2737,R2735.

20101224 A00:

0402 0R pad: R2758,R2759.

20101224 A00:

0402 0R pad: R2760.

47.0K

X02

A00

2.48V

100.0K 2.24V

100.0K 33.0K

20101228 A00:

VGA_THRM change to USB_PWR_EN.

20101229 A00:

Rename USB_PWR_EN to USB3_PWR_ON.

20101228 A00:

Change R2756,R2763,R2766 to 0R short pad.

12

C2

71

0S

CD

1U

10

V2

KX

-5G

PC

27

10

SC

D1

U1

0V

2K

X-5

GP

VREF104

GPIO90/AD097

GPIO91/AD198

GPIO92/AD299

GPIO93/AD3100

GPIO94/DA0101

GPIO95/DA1105

GPIO96/DA2106

GPIO279

GPIO3/AD695

GPIO4/AD596

GPIO5/AD4108

PSL_IN2#_GPIO693

GPIO7/AD794

GPIO16114

GPIO246

GPIO30109

GPIO34/CIRRXL14

GPIO4180

GPIO42/TCK17

GPIO43/TMS20

GPIO44/TDI21

GPIO46/CIRRXM/TRST#23

GPIO5126

PSL_IN1_GPIO7073

PSL_OUT_GPIO7174

VBKUP75

GPIO7582

GPO76/SHBM83

GPIO7784

GPIO8191

GPO82/IOX_LDSH/TEST#110

GPIO84/IOX_SCLK/XORTR#112

GPIO97107

GPIO3615

VCORF44

GN

D18

GN

D45

GN

D78

GN

D89

GN

D116

GN

D5

AG

ND

103

GPIO11/CLKRUN#8

LAD31

LAD2128

LAD1127

LAD0126

LFRAME#3

LCLK2

LRESET#7

SERIRQ125

GPIO85/GA20121

KBRST#/GPIO86122

ECSCI#/GPIO5429

GPIO65/SMI#9

GPIO10/LPCPD#124

GPIO67/PWUREQ#123

GPIO37/PSCLK172

GPIO26/PSCLK210

GPIO35/PSDAT171

GPIO27/PSDAT211

GPIO50/PSCLK3/TDO25

GPIO52/PSDAT3/RDY#27

GPIO17/SCL170

GPIO73/SCL267

GPIO23/SCL3119

GPIO22/SDA169

GPIO74/SDA268

GPIO31/SDA3120

GPIO47/SCL424

GPIO53/SDA428

F_SDI/F_SDIO186

F_SDIO/F_SDIO087

F_SCK92

F_CS0#90

VC

C19

VC

C46

VC

C76

VC

C88

VC

C115

AV

CC

102

VD

D4

1 OF 2U2701A

NPCE795PA0DX-GP-U

1 OF 2U2701A

NPCE795PA0DX-GP-U

1

2

3

D2706

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

D2706

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

1 2

C2711

SC220P50V2KX-3GP

DYC2711

SC220P50V2KX-3GP

DY

123

4

RN2703

SRN100KJ-6-GP

RN2703

SRN100KJ-6-GP

1

2

3

D2704

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

DY

D2704

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

DY

123

4

RN2701

SRN4K7J-8-GP

RN2701

SRN4K7J-8-GP

12

R2705

10KR2J-3-GP

R2705

10KR2J-3-GP

12


DYC2713SCD1U10V2KX-5GP

DY

1 2R2709 10KR2J-3-GP

DYR2709 10KR2J-3-GP

DY

12

C2715

SC

1U

6D

3V

2K

X-G

PDY

C2715

SC

1U

6D

3V

2K

X-G

PDYG

S

D

Q2702

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

Q2702

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

1

2

3

D2703

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

10mW

D2703

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

10mW

1 2R2770 100KR2J-1-GPR2770 100KR2J-1-GP

1 2R2768

0R2J-2-GP

DYR2768

0R2J-2-GP

DY

1

2

3

D2707

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

D2707

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

1 2R27670R2J-2-GP

DYR2767

0R2J-2-GP

DY

1 2

R2704

330KR2J-L1-GP

R2704

330KR2J-L1-GP

12

C2718

SC

D1

U1

0V

2K

X-5

GP

DYC2718

SC

D1

U1

0V

2K

X-5

GP

DY

1AFTP2701AFTP2701

12

R2739100KR2F-L1-GPR2739100KR2F-L1-GP

1 2R2772 100KR2J-1-GPR2772 100KR2J-1-GP

12

C2

70

4S

CD

1U

10

V2

KX

-5G

PC

27

04

SC

D1

U1

0V

2K

X-5

GP

G

S

D

Q2705

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

DY

Q2705

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

DY

1AFTP2703AFTP2703

12 R27590R0402-PAD

R27590R0402-PAD

12

C2

70

7S

CD

1U

10

V2

KX

-5G

PC

27

07

SC

D1

U1

0V

2K

X-5

GP

1 2R2720 0R0402-PADR2720 0R0402-PAD

12

C2

70

6S

CD

1U

10

V2

KX

-5G

PC

27

06

SC

D1

U1

0V

2K

X-5

GP

1 2R2721 43R2J-GPR2721 43R2J-GP

1 2R2776 100KR2J-1-GPR2776 100KR2J-1-GP

1 2R27660R0402-PADR27660R0402-PAD

12

R2710143KR2F-GPR2710143KR2F-GP


12

C2719 SCD1U10V2KX-5GP

DYC2719 SCD1U10V2KX-5GP

DY

12

R2732

10

0K

R2

J-1

-GP

R2732

10

0K

R2

J-1

-GP

12

C2712SC1U10V3ZY-6GPC2712SC1U10V3ZY-6GP

C

B

E

Q2701

MMBT3906-4-GP

2nd = 84.03906.F1184.T3906.A11

Q2701

MMBT3906-4-GP

2nd = 84.03906.F1184.T3906.A11

12

R2773100KR2J-1-GPR2773100KR2J-1-GP

1

2

3

D2702

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

D2702

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

1 2

C2722

SCD1U10V2KX-5GP

C2722

SCD1U10V2KX-5GP

12

C2716

SC

D1

U1

6V

2K

X-3

GP

C2716

SC

D1

U1

6V

2K

X-3

GP

12

C2717SCD1U10V2KX-5GP DYC2717SCD1U10V2KX-5GP DY

12 R27600R0402-PAD

R27600R0402-PAD

1 2R2708 10KR2J-3-GP

DYR2708 10KR2J-3-GP

DY

12

C2

70

5S

CD

1U

10

V2

KX

-5G

P

DY

C2

70

5S

CD

1U

10

V2

KX

-5G

P

DY

12



12

C2

70

8S

CD

1U

10

V2

KX

-5G

PC

27

08

SC

D1

U1

0V

2K

X-5

GP

1 2R2761 0R0402-PADR2761 0R0402-PAD

1

2

3

D2708

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

D2708

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

1 2R2711 0R0402-PADR2711 0R0402-PAD

12

R272447KR2F-GPR272447KR2F-GP

12 R2737 0R0402-PADR2737 0R0402-PAD

12 R27350R0402-PAD

R27350R0402-PAD

12

C2

70

9S

C2

D2

U1

0V

3K

X-1

GP

C2

70

9S

C2

D2

U1

0V

3K

X-1

GP

12

C2703SC2D2U10V3KX-1GPDY C2703SC2D2U10V3KX-1GPDY

12

R2726100KR2F-L1-GPR2726100KR2F-L1-GP

1 2R27340R2J-2-GPDY

R27340R2J-2-GPDY

1 2R2774 100KR2J-1-GPR2774 100KR2J-1-GP

1 2R2775 100KR2J-1-GPR2775 100KR2J-1-GP

12 33R2J-2-GPR2736 33R2J-2-GPR2736S

D

G G

D

Q2703

DMP2130L-7-GP

2ND = 84.03413.A31

84.02130.031

G

D

Q2703

DMP2130L-7-GP

2ND = 84.03413.A31

84.02130.031

12

C2701

SC

2D

2U

10

V3

KX

-1G

P

C2701

SC

2D

2U

10

V3

KX

-1G

P

1AFTP2702AFTP2702

12 R2722 33R2J-2-GPR2722 33R2J-2-GP

12

C2721 SCD1U10V2KX-5GP

DYC2721 SCD1U10V2KX-5GP

DY

12 R27580R0402-PAD

R27580R0402-PAD

GPIO56/TA131

GPIO20/TA2117

GPIO14/TB163

GPIO01/TB264

GPIO15/A_PWM32

GPIO21/B_PWM118

GPIO13/C_PWM62

GPIO32/D_PWM65

GPIO66/G_PWM81

GPIO33/H_PWM66

GPIO45/E_PWM22

GPIO40/F_PWM16

VCC_POR#85

GPIO83/SOUT_CR/TRIST#111

GPIO87/CIRRXM/SIN_CR113

GPIO00/EXTCLK77

GPIO55/CLKOUT/IOX_DIN_DIO30

PECI13

VTT12

KBSOUT0/JENK#53

KBSOUT1/TCK52

KBSOUT2/TMS51

KBSOUT3/TDI50

KBSOUT4/JEN0#49

KBSOUT5/TDO48

KBSOUT6/RDY#47

KBSOUT743

KBSOUT842

KBSOUT9/SDP_VIS#41

KBSOUT10/P80_CLK40

KBSOUT11/P80_DAT39

KBSOUT12/GPIO6438

KBSOUT13/GPIO6337

KBSOUT14/GPIO6236

KBSOUT15/GPIO61/XOR_OUT35

GPIO60/KBSOUT1634

GPIO57/KBSOUT1733

KBSIN054

KBSIN155

KBSIN256

KBSIN357

KBSIN458

KBSIN559

KBSIN660

KBSIN761

2 OF 2U2701B

NPCE795PA0DX-GP-U

2 OF 2U2701B

NPCE795PA0DX-GP-U

1 2

R2756

0R0402-PAD

R2756

0R0402-PAD

1 2R2712 10KR2J-3-GPR2712 10KR2J-3-GP

1 2R27020R0603-PADR27020R0603-PAD

G

S

D

Q2706

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

Q2706

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

1 2R2733 0R0402-PADR2733 0R0402-PAD

1 2

R2763

0R0402-PAD

R2763

0R0402-PAD

12 33R2J-2-GPR2719 33R2J-2-GPR2719

12345

678

RN2705

SRN10KJ-6-GP

RN2705

SRN10KJ-6-GP

1

2

3

D2701

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

DY

D2701

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

DY

123

4

RN2706

SRN10KJ-5-GP

RN2706

SRN10KJ-5-GP

1

2

3

D2705

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

DY

D2705

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

DY

12

R2769100KR2J-1-GPDY R2769100KR2J-1-GPDY

G

S

D

Q2704

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

10mW

Q2704

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

10mW

12

R2771

2D2R3-1-U-GP

R2771

2D2R3-1-U-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FAN_VCCFAN_VCC

P2800_DXP

THERM_SYS_SHDN#_OTZ ADJP2800_DXN

ADJ

FAN_TACH1_C

FAN_VCC

FON#

FAN_VCC

FAN_TACH1_C

U2805_5U2805_1

U2805_4

U2805_3THERM_SYS_SHDN#

THERM_SYS_SHDN#_OTZ

THERM_SYS_SHDN#

3D3V_S0

5V_S0

3D3V_S0

5V_S0

3D3V_S0

3D3V_DAC_S0

3D3V_DAC_S0

3D3V_DAC_S0

PURE_HW_SHUTDOWN#(27,36)

CPU_THRM (27)SYS_THRM (27)

FAN_TACH1(27)

FAN1_DAC(27)

Title


Date: Sheet of


Nirvana 13 A00

THERMAL P2800 / Fan controlA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

87.1 Degree

Layout notice :Both DXN and DXP routing 10 miltrace width and 10 mil spacing.

*Layout* 15 mil

1.H/W T8 Shutdown2.System Sensor, Put on palm rest

0629 Modify

Thermal sensor P2800SSID = Thermal

For linear FAN

Fan controller

*Layout* 10 mil

Hysterisis is 10°C for HYST = VCC, 2°C for HYST = GND.

RSET = 0.0012T 2 — 0.9308T + 96.147

T=87 ; RSET=24.25ohm

20101224 A00 Modify:If stuff P2800EA1 then must stuff R2803,R2804C2805 but if stuff P28003B0 should be un-stuff.

20101228 A00 Modify:Un-stuff U2805 G709T1UF related circuitand R2812 then stuff R2805 at X-Build.

1AFTP2801AFTP2801

FON#1

VIN2

VO3

VSET4

GND 8

GND 7

GND 6

GND 5

U2802

G991P11U-GP

74.00991.0312nd = 74.02793.A31

3rd = 74.05606.A71

U2802

G991P11U-GP

74.00991.0312nd = 74.02793.A31

3rd = 74.05606.A71

12

R2803107KR2F-GPP2800A1R2803107KR2F-GPP2800A1

12

C2811

SC

D1U

10V

2K

X-5

GPDY

C2811

SC

D1U

10V

2K

X-5

GPDY

12

R2810

0R2J-2-GPDYR2810

0R2J-2-GPDY

1AFTP2802AFTP2802

12

R2809100KR2J-1-GPR2809100KR2J-1-GP

1 2

R280624K3R2F-1-GP

DY

R280624K3R2F-1-GP

DY

12

R2808NTC-100K-8-GP

DY

R2808NTC-100K-8-GP

DY

12

C2808

SC

D1U

16V

2K

X-3

GP DY

C2808

SC

D1U

16V

2K

X-3

GP DY

VCC5

DXP6

DXN7

OTZ8GND 2

ADJ 1

TDL 3TDR 4

U2801

P2800EA1-GP

74.02800.A71

U2801

P2800EA1-GP

74.02800.A71

12

C2805

SC

D1U

10V

2K

X-5

GP

P2800A1C2805

SC

D1U

10V

2K

X-5

GP

P2800A1

12

R2801

150R2F-1-GP

DYR2801

150R2F-1-GP

DY

12

C2810

SC

2200P

50V

2K

X-2

GP

DY

C2810

SC

2200P

50V

2K

X-2

GP

DY

12

R2804226KR2F-GP

P2800A1

R2804226KR2F-GP

P2800A1

12

C2809

SC

4D

7U

6D

3V

3K

X-G

P

C2809

SC

4D

7U

6D

3V

3K

X-G

P

G

S

D

Q2802

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

Q2802

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

1 2

R2802 0R2J-2-GP

DYR2802 0R2J-2-GP

DY

SET1

GND2

OUT#3 HYST 4

VCC 5

U2805

G709T1UF-GP

74.00709.A7F

DY

U2805

G709T1UF-GP

74.00709.A7F

DY

12

C2817

SCD1U10V2KX-5GPDY

C2817

SCD1U10V2KX-5GPDY

12

C2803

SC

4D

7U

6D

3V

3K

X-G

P

C2803

SC

4D

7U

6D

3V

3K

X-G

P

3

1

2

Q2801

PM

BS

3904-1

-GP

84.03904.L062nd = 84.03904.P11

3rd = 84.03904.T11

Q2801

PM

BS

3904-1

-GP

84.03904.L062nd = 84.03904.P11

3rd = 84.03904.T11

21

D2802

CH551H-30PT-GP

2ND = 83.R5003.H8H3rd = 83.5R003.08F

83.R5003.C8F

D2802

CH551H-30PT-GP

2ND = 83.R5003.H8H3rd = 83.5R003.08F

83.R5003.C8F

12


1 2R2812 0R2J-2-GP

DYR2812 0R2J-2-GP

DY

1 2

R2805

0R2J-2-GP

R2805

0R2J-2-GP

12

C2807SC2200P50V2KX-2GPC2807SC2200P50V2KX-2GP

12

C2802

SC

D1U

10V

2K

X-5

GP

C2802

SC

D1U

10V

2K

X-5

GP

12

C2804

SC

D1U

10V

2K

X-5

GP

C2804

SC

D1U

10V

2K

X-5

GP

1

23

4

5

FAN1

ACES-CON3-11-GP

20.F0772.003

2nd = 20.F1841.003

FAN1

ACES-CON3-11-GP

20.F0772.003

2nd = 20.F1841.003

12

R2811

0R2J-2-GPDY

R2811

0R2J-2-GPDY

1 2R2807 0R0402-PADR2807 0R0402-PAD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AUD_DMIC_IN0 AUD_V_B

AU

D_S

EN

SE

_B

HDA_CODEC_SDIN0

AUD_DVDDCORE

HDA_CODEC_BITCLK

HDA_CODEC_BITCLK

PUMP_CAPN

AUD_SENSE_A

PUMP_CAPP

AMP_MUTE#

KBC_BEEP_R

SB_SPKR_R

AUD_V_B

AUD_SENSE_B

AUD_VREG

AUD_SPK_L+AUD_SPK_L-

AUD_EXT_MIC_RAUD_EXT_MIC_L

AUD_VREFOUT_B

PC

H_A

Z_C

OD

EC

_S

DO

UT

1

HDA_CODEC_SDOUT

AUD_VREFFLT

AMP_MUTE#

HDA_CODEC_SYNCHDA_CODEC_RST#

HDA_CODEC_SDOUT

AUD_CAP2

HDA_CODEC_BITCLK_1

AU

D_S

EN

SE

_A

AU

D_C

AP

2

AUD_DMIC_CLK

AUD_PC_BEEP

AU

D_V

RE

FO

UT

_B

AUD_PC_BEEP

AU

D_V

RE

G

AU

D_P

C_B

EE

P

AU

D_V

RE

FF

LT

AUD_VREFOUT_B

AUD_HP1_JACK_RAUD_HP1_JACK_L

3D3V_S0

+AVDD

+AVDD

5V_S0

3D3V_S0

5V_S0 +PVDD

+AVDD

+AVDD

+AVDD

+PVDD

AUD_DMIC_CLK(49,97)AUD_DMIC_IN0(49,97)

HDA_CODEC_SYNC(21)HDA_CODEC_RST#(21)

HDA_SDIN0(21)HDA_CODEC_BITCLK(21)HDA_CODEC_SDOUT(21)

AUD_HP1_JD# (58)

EXT_MIC_JD# (58)

AUD_SPK_L+ (58)AUD_SPK_L- (58)

AMP_MUTE#(27)

HDA_SPKR (21)

KBC_BEEP (27)

MIC_IN_L (58)MIC_IN_R (58)

MIC_IN_L(58)MIC_IN_R(58)

AUD_HP1_JACK_L2 (58)AUD_HP1_JACK_R2 (58)

Title


Date: Sheet of


Nirvana 13 A00

Audio Codec 92HD87B1

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00


A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00


A3


<Core Design>

Close to codec

Close to Pin14

From PCH

From EC

SSID = AUDIO

Close to Pin13

Azalia I/F EMI

Close to codec

AUD_PC_BEEP

Trace width>15 mils

Close to codec

Put C2921 and C2922 close to codec

12

G2901

DUMMY-C2

G2901

DUMMY-C2

DVDD_LV1

DMIC_CLK/GPIO_12

DMIC_0/GPIO_23

SDATA_OUT4

BITCLK5

SDATA_IN6

DVDD7

SYNC8

RESET#9

PCBEEP10

SE

NS

E_A

11

SE

NS

E_B

12

PO

RT

F_L

13

PO

RT

F_R

14

PO

RT

C_L

15

PO

RT

C_R

16

VR

EF

FIL

T17

CA

P2

18

VR

EF

OU

T_A

19

VR

EF

OU

T_C

20

AVDD1 21PORTA_L 22PORTA_R 23

AVSS2 24PORTB_L 25PORTB_R 26

AVSS2 27V- 28

CAP- 29CAP+ 30

VR

EG

/+2_5V

31

AV

DD

232

PV

DD

33

PO

RT

D_+

L34

PO

RT

D_-L

35

PV

SS

36

PO

RT

D_-R

37

PO

RT

D_+

R38

PV

DD

39

EA

PD

40

TH

ER

MA

L_P

AD

41

U2901

92HD87B1A5NDGXTBX8-GP

71.92H87.A03

U2901

92HD87B1A5NDGXTBX8-GP

71.92H87.A03

1 2

R2910470KR2J-2-GP

R2910470KR2J-2-GP

1 2

R2907

47R2J-2-GP

DYR2907

47R2J-2-GP

DY

12

C2918

SC

10U

6D

3V

5M

X-3

GP

C2918

SC

10U

6D

3V

5M

X-3

GP

12

C2907SC4D7P50V2CN-1GPDY C2907SC4D7P50V2CN-1GPDY

12

R291247R2J-2-GPDYR291247R2J-2-GPDY

12

C2908

SC

D1U

10V

2K

X-5

GP

C2908

SC

D1U

10V

2K

X-5

GP

12

R2919

39K2R2F-L-GP

R2919

39K2R2F-L-GP

12

C2916

SC

1U

6D

3V

2K

X-G

PC

2916

SC

1U

6D

3V

2K

X-G

P

12

C2902

SC

D1U

10V

2K

X-5

GP

C2902

SC

D1U

10V

2K

X-5

GP

1 2

R2913

20KR2F-L-GP

R2913

20KR2F-L-GP

1 2R29030R0603-PADR29030R0603-PAD

12

C2901SC10U6D3V5MX-3GPC2901SC10U6D3V5MX-3GP

1 2R2905 60D4R2F-GPR2905 60D4R2F-GP

12

C2905

SC

D1U

10V

2K

X-5

GP

C2905

SC

D1U

10V

2K

X-5

GP

1 2R29020R0603-PADR29020R0603-PAD

12

C2919SC1000P50V3JN-GP-UC2919SC1000P50V3JN-GP-U

12

C2915

SC

10U

6D

3V

5M

X-3

GP

C2915

SC

10U

6D

3V

5M

X-3

GP

12C2912 SCD1U10V2KX-5GPC2912 SCD1U10V2KX-5GP

12

C2920SCD1U10V2KX-5GPDY C2920SCD1U10V2KX-5GPDY

12

C2910

SC

10U

6D

3V

5M

X-3

GP

C2910

SC

10U

6D

3V

5M

X-3

GP

12C2913 SCD1U10V2KX-5GPC2913 SCD1U10V2KX-5GP

123 4

RN2901SRN4K7J-8-GP

RN2901SRN4K7J-8-GP

12

C2909

SC

1U

10V

2K

X-1

GP

C2909

SC

1U

10V

2K

X-1

GP

12C2921 SC1U10V3KX-3GPC2921 SC1U10V3KX-3GP

12

C2903

SC

1U

6D

3V

2K

X-G

PC

2903

SC

1U

6D

3V

2K

X-G

P

12

R290810KR2J-3-GPR290810KR2J-3-GP

12


1 2

R2909120KR2J-L-GP

R2909120KR2J-L-GP

12

C2917

SC

4D

7U

6D

3V

3K

X-G

PC

2917

SC

4D

7U

6D

3V

3K

X-G

P

12C2922 SC1U10V3KX-3GPC2922 SC1U10V3KX-3GP

1 2R29040R0603-PADR29040R0603-PAD

12

C2906

SC

1U

10V

2K

X-1

GP

C2906

SC

1U

10V

2K

X-1

GP

1 233R2J-2-GP

R290133R2J-2-GP

R2901

12


1 2R2906 60D4R2F-GPR2906 60D4R2F-GP

12

C2914

SC2D2U10V3KX-1GP

C2914

SC2D2U10V3KX-1GP

12

C2904

SC

D1U

10V

2K

X-5

GP

C2904

SC

D1U

10V

2K

X-5

GP

12

R291820KR2F-L-GPR291820KR2F-L-GP

12

C2923SC1U10V2KX-1GP

C2923SC1U10V2KX-1GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB_PP5_R

USB_PN5_R

SP11

SP3SP4SP5

USB_PN5_R

RREF

USB_PP5_R

V18

XD_CD#

SP7SP8SP9

SP1

SP10

SP12

SP2

SP13SP14XD_D7

SP63D3V_CARD_S0

3D3V_S0

3D3V_CARD_S0

USB_PN5(18)

USB_PP5(18)

SP11 (74)

SP3 (74)SP4 (74)SP5 (74)

CLK_PCH_48M(20,97)

XD_CD# (74)

SP7 (74)SP8 (74)SP9 (74)

SP1 (74)

SP10 (74)

SP12 (74)

SP2 (74)

SP13 (74)SP14 (74)XD_D7 (74)

SP6 (74)

Title


Date: Sheet of


Nirvana 13 A00

Card Reader RTS5138

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Card Reader RTS5138

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Card Reader RTS5138

A3


<Core Design>

The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout

with differential characteristic impedance (Zdiff) is 90Ω± 10%

Close to chip

3D3V_CARD_S0

PCH GPIO67(48M) confirm with SW

MAX 0.4A

SSID = SDIO

48MHz clock input trace of characteristic impedance (Zo) must be 50 ±15%.

The maximum range of the PMOS output current

1. xD-Picture Card: 250mA

2. SD/MMC Card: 250mA

3. MS/MSPRO/Duo-HG: 250mA

POWER TRACE

1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum).

2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum).

3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum).

Keep the trace routing lengths as short as possible.

4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum).

5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace.

6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.

7.It is recommended that use of ferrites bead on power trace.

8.Via size: Pad>=32 mils, Finished hole>=16 mils.

20101227 A00:Change R3210,R3211 to 0R 0402 pad.20100104 A00:Remove TR3201.

12


DY C3204SC4D7U6D3V3KX-GP

DY

1 2R3211

0R0402-PAD

R3211

0R0402-PAD

12


1 2R32016K2R2F-GP

R32016K2R2F-GP

12

C3207SC4D7U6D3V5KX-3GPC3207SC4D7U6D3V5KX-3GP

CLK

_IN

24

RREF1

DM2

DP3

3V3_IN4

CARD_3V35

V186

XD

_C

D#

7

SP

18

SP

29

SP

310

SP

411

SP

512

SP6 13SP7 14SP8 15SP9 16

GPIO0 17SP10 18S

P11

19

SP

12

20

SP

13

21

SP

14

22

XD

_D

723

GND25

U3201

RTS5138-GR-GP

71.05138.003

U3201

RTS5138-GR-GP

71.05138.003

1 2R3210

0R0402-PAD

R3210

0R0402-PAD

1 2

C3201

SC100P50V2JN-3GP

DYC3201

SC100P50V2JN-3GP

DY

12



12

C3206

SCD1U10V2KX-4GP

C3206

SCD1U10V2KX-4GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.5V_RUN_ENABLE

PS_S3CNTRL

5V_RUN_ENABLE

3.3V_RUN_ENABLE

H_PWRGD_R

PS_S3CNTRL

SYS_PWROK

3D3V_S5 3D3V_S0

3D3V_AUX_S5

1D5V_S3 1D5V_S0

RUN_ENABLE

15V_S5

5V_S5 5V_S0

1D05V_VTT

PS_S3CNTRL (37)

PM_SLP_S3#(19,27,37,47)

S5_ENABLE (27)

PURE_HW_SHUTDOWN# (27,28)

H_THERMTRIP# (5,22)

H_CPUPWRGD(5,22)

3V_5V_EN(41)S0_PWR_GOOD(19,27)

SYS_PWROK (19)

IMVP_PWRGD(27,42)

Title


Date: Sheet of



Nirvana 13 A00

Power Plane EnableA2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00



<Core Design>

Title


Date: Sheet of



Nirvana 13 A00



<Core Design>

+1.5V_RUN_CPU Comsumption

Peak current 10A

+1.5V_RUN for Mini-Card Comsumption

Peak current 1A

1D5V_S0

MAX Current ? mA

Design Current ? mA

1

+3.3V_RUN Comsumption

Peak current 8.14A

+5V_RUN Comsumption

Peak current 7.73A

+5V_RUN

+3.3V_RUN

Run Power

SSID = Reset.Suspend

G

GD

D

S

S

AO4468 MAX 9ARds(on) = 18.5mOhm

AO4468 MAX 11.6ARds(on) = 18.5mOhm

0621 Modify:

Change R3603 to 1K from 2K 0402.

TPCA8062-H-GP MAX 28A

Rds(on) = 4.1~5.4m OHM

Total= 11.39A

20100723 Default stuff R3622 PH Resistor to fix Annie demo board SLP_S3 abnormal issue from Annie team updated.

Power Sequence

SSID = Reset.Suspend

20101224 A00:

0402 0R pad: R3614.

1 2 3456

Q3602

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

Q3602

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

12

R3604100KR2J-1-GPR3604100KR2J-1-GP

1 2R3606100KR2J-1-GP

R3606100KR2J-1-GP

12

R3

60

22

00

KR

2J-

L1

-GP

DY

R3

60

22

00

KR

2J-

L1

-GP

DY

12



12

C3603SC10U10V5ZY-1GPC3603SC10U10V5ZY-1GP

G

S

D

Q3603

2N7002K-2-GP

Q3603

2N7002K-2-GP

1 2R36011KR2J-1-GPDY

R36011KR2J-1-GPDY

1 2R360710KR2J-3-GP

R360710KR2J-3-GP

12



DY

12 R36140R0402-PAD

R36140R0402-PAD

1 2R363010KR2J-3-GP

R363010KR2J-3-GP

12

C3609SC10U6D3V5KX-1GPC3609SC10U6D3V5KX-1GP

C

B

E

Q3601

CHT2222APT-GP

DYQ3601

CHT2222APT-GP

DY

12

R3622

56R2J-4-GP

R3622

56R2J-4-GP

12


12


1 2R360510KR2J-3-GP

R360510KR2J-3-GP

12



DY

12345

678 S

S

S

GD

D

DD

U3601

AO4468-GP84.04468.037

2nd = 84.08882.037

SS

S

GD

D

DD

U3601

AO4468-GP84.04468.037

2nd = 84.08882.037

12345

678 S

S

S

GD

D

DD

U3602

AO4468-GP84.04468.037

2nd = 84.08882.037

SS

S

GD

D

DD

U3602

AO4468-GP84.04468.037

2nd = 84.08882.037

1

2

3

D3601

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

D3601

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

1 2R3603 1KR2J-1-GPR3603 1KR2J-1-GP

12


12345

678 S

S

S

GD

D

DD

U3606

TPCA8062-H-GP

84.08062.037

2nd = 84.00460.037

3rd = 84.00312.037

SS

S

GD

D

DD

U3606

TPCA8062-H-GP

84.08062.037

2nd = 84.00460.037

3rd = 84.00312.037

1

2

3

D3602

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

D3602

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PS_S3CNTRL

Q3702_D

Q3701_D

0D75V_EN

SM_DRAMRST#_D

DRAMRST_CNTRL_PCH

0D75V_ENVDDPWRGOOD_R

VDDPWRGOOD_R

Q3707_D

PS_S3CNTRL

+V_SM_VREF

1D5V_S00D75V_S0

1D5V_S3

RUN_ENABLE

1D5V_S03D3V_S0

3D3V_S0

M_VREF_DQ_DIMM0

PS_S3CNTRL(36)

0D75V_EN (46)

PS_S3CNTRL(36)

1.05VTT_PWRGD (45,48)

PM_SLP_S3#(19,27,36,47)

DDR3_DRAMRST# (14,15)

DRAMRST_CNTRL_PCH (20)

SM_DRAMRST#(5)

+V_SM_VREF_CNT (9)

PM_DRAM_PWRGD(5,19)

VDDPWRGOOD (5)

PM_DRAM_PWRGD(5,19)

Title


Date: Sheet of


Nirvana 13 A00

S3 Power ReductionA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Close to CPU

S3 Power Reduction Circuit SM_DRAMPWROK

Close to CPU

S3 Power Reduction Circuit Processor VREF_DQ Implementation 2

5 S3 Power Reduction

S3 Power Reduction Circuit

SM_DRAMRST#

Close to DIMM


Close to CPU


SM_DRAMPWROK must have a maximum of 15ns rise or fall time

over VDDQ * 0.55± 200mV and the edge must be monotonic

CEKLT V1.0: PCH to 1K,CUP to 200R

20101224 A00:0402 0R pad: R3710.

1 2R3708 0R0402-PADR3708 0R0402-PAD

1

2

34

5

U3701

TC7SZ08FU-2-GP

73.7SZ08.EAH2ND = 73.01G08.L043rd = 73.7SZ08.DAH

U3701

TC7SZ08FU-2-GP

73.7SZ08.EAH2ND = 73.01G08.L043rd = 73.7SZ08.DAH

1 2R3716 22R2J-2-GP

DYR3716 22R2J-2-GP

DY G

S

D

Q3703

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

Q3703

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

1 2

R3717

0R2J-2-GPDY

R3717

0R2J-2-GPDY

1 2R37181KR2J-1-GP

R37181KR2J-1-GP

G S

D

Q3702

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031DY

Q3702

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031DY

1 2R37090R2J-2-GPDY R37090R2J-2-GPDY

12

R37061KR2J-1-GPR37061KR2J-1-GP

G S

D

Q3701

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

Q3701

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

1 2

R3719

910R2F-GP

R3719

910R2F-GP

12

R370322R2J-2-GPR370322R2J-2-GP

12

R3705

100KR2J-1-GP

R3705

100KR2J-1-GP

12

R372139R2J-L-GPDY

R372139R2J-L-GPDY

12

R3702200R2F-L-GPDY

R3702200R2F-L-GPDY

12

R3713

200R2F-L-GP

R3713

200R2F-L-GP

G

S

D

Q3704

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

Q3704

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

1 2

R37070R2J-2-GP

DY

R37070R2J-2-GP

DY

12

C3703

SCD047U16V2KX-1-GP

C3703

SCD047U16V2KX-1-GP

12


G

S

D

Q3708

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

Q3708

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

12

C3705SCD1U10V2KX-5GPDYC3705SCD1U10V2KX-5GPDY

12

R3704220R2J-L2-GPDYR3704220R2J-L2-GPDY

12

R3710

0R0402-PAD

R3710

0R0402-PAD

12

R3720750R2F-GPR3720750R2F-GP

G S

D

Q3707

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

DY Q3707

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

DY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+DC_INPS_ID_R

PSID_DISABLE#_R

PU

3801_G

PS_ID

PQ3802_1

PS_ID_R PS_ID_1

+DC_IN

3D3V_S5

+DC_IN AD+

3D3V_S5

5V_S5

PSID_EC (27)

RCID(27)

PS_ID_R(82)

Title


Date: Sheet of


Nirvana 13 A00

DCIN JackA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

DCIN JackA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

DCIN JackA3


<Core Design>

Place close to BTB connector

280mils or Copper Shape

This cap should be usedonly as last resort forEMI suppression.

Id=-12AQg=-25nCRdson=10~38mohm

1 2

PR3804

0R0402-PAD

PR3804

0R0402-PAD

3

1

2

PQ3802

PMBS3904-1-GP 84.03904.L062nd = 84.03904.P113rd = 84.03904.T11

PQ3802

PMBS3904-1-GP 84.03904.L062nd = 84.03904.P113rd = 84.03904.T11

G

S

D

PQ3803

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

DY

PQ3803

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

DY

12

PR3812100KR2J-1-GP

DY

PR3812100KR2J-1-GP

DY

1AFTP3803AFTP3803

12

PR38062K2R2J-2-GPPR38062K2R2J-2-GP

12

PC3801SCD1U50V3KX-GPDY PC3801SCD1U50V3KX-GPDY

12

PR3803100KR2J-1-GP

PR3803100KR2J-1-GP

1 2

PR3808

33R2J-2-GP

DYPR3808

33R2J-2-GP

DY

12

PC

3805

SC

D01U

50V

2K

X-1

GP

PC

3805

SC

D01U

50V

2K

X-1

GP

1AFTP3802AFTP3802

12

PR380115KR2J-1-GP

PR380115KR2J-1-GP

1234 5

678S

S

S

G D

D

DD

PU3801

AO4407A-GP

SS

S

G D

D

DD

PU3801

AO4407A-GP

KA

PD3801

1SMB22AT3G-GP-U

83.22R03.03G

2ND = 83.P6SBM.AAG

PD3801

1SMB22AT3G-GP-U

83.22R03.03G

2ND = 83.P6SBM.AAG

12

PC

3802

SC

D01U

50V

2K

X-1

GP

DY

PC

3802

SC

D01U

50V

2K

X-1

GP

DY

1 2

PR3807

33R2J-2-GP

PR3807

33R2J-2-GP

12

PC

3803

SC

D01U

50V

2K

X-1

GP

DY

PC

3803

SC

D01U

50V

2K

X-1

GP

DY

G

SDD

PQ3801FDV301N-NL-GP

D

PQ3801FDV301N-NL-GP

12

PR380210KR2J-3-GPPR380210KR2J-3-GP

12

PC

3806

SC

10U

25V

6K

X-1

GP

PC

3806

SC

10U

25V

6K

X-1

GP

12

PR381147KR3J-L-GPPR381147KR3J-L-GP

12

PC

3804

SC

1U

25V

5K

X-1

GP

PC

3804

SC

1U

25V

5K

X-1

GP 1

2

PR

3810

240K

R3-G

PP

R3810

240K

R3-G

P

12

3

PD3803

BAV99-5-GP-U

83.00099.T112nd = 83.00099.K11

3rd = 83.BAV99.D11

PD3803

BAV99-5-GP-U

83.00099.T112nd = 83.00099.K11

3rd = 83.BAV99.D11

1AFTP3801AFTP3801

21

PD3804

B240A-13-GPDYPD3804

B240A-13-GPDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BA

T_S

CL

PBAT_SMBDAT1PBAT_SMBCLK1

PBAT_PRES1#

BAT_ALERT

BT+

PBAT_PRES1#

PBAT_SMBCLK1PBAT_SMBDAT1

BA

T_S

DA

BA

T_IN

#

BT+

3D3V_AUX_KBC

BATT_SENSE(40)

BAT_SDA(27,40)BAT_SCL(27,40)

BAT_IN#(27)

Title


Date: Sheet of


Nirvana 13 A00

BATT CONNA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

BATT CONNA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

BATT CONNA3


<Core Design>


Placement: Close to Batt Connector

For actual location, need to be swap all pin

Batt Connecter

20101224 A00:Rename PRN3901 to PN3901.

1AFTP3904AFTP3904

1AFTP3901AFTP3901

1AFTP3903AFTP3903

1 2

3

D3901

BAV99-5-GP-U

83.00099.T112nd = 83.00099.K113rd = 83.BAV99.D11

D3901

BAV99-5-GP-U

83.00099.T112nd = 83.00099.K113rd = 83.BAV99.D11

KA

PD

3902

1S

MA

18A

T3G

-GP

DY

PD

3902

1S

MA

18A

T3G

-GP

DY

1AFTP3902AFTP3902

1 2

3

D3903

BAV99-5-GP-U

83.00099.T112nd = 83.00099.K113rd = 83.BAV99.D11

D3903

BAV99-5-GP-U

83.00099.T112nd = 83.00099.K113rd = 83.BAV99.D11

12

C3902SCD1U50V3KX-GP

C3902SCD1U50V3KX-GP

12

EC3901

SC

10P

50V

2JN

-4G

P

DY

EC3901

SC

10P

50V

2JN

-4G

P

DY

1

23456789

10

11

BATT1

TCN-CON9-3-GP

20.81327.009

BATT1

TCN-CON9-3-GP

20.81327.009

1AFTP3905AFTP3905

12

G3901

GAP-CLOSE-PWR-3-GP

G3901

GAP-CLOSE-PWR-3-GP

12

C3901SC2200P50V2KX-2GPC3901SC2200P50V2KX-2GP

12

EC3902

SC

10P

50V

2JN

-4G

P

DY

EC3902

SC

10P

50V

2JN

-4G

P

DY

1 2

3

D3902

BAV99-5-GP-U

83.00099.T112nd = 83.00099.K113rd = 83.BAV99.D11

D3902

BAV99-5-GP-U

83.00099.T112nd = 83.00099.K113rd = 83.BAV99.D11

1234 5

678

PN3901

SRN33J-7-GP

PN3901

SRN33J-7-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_CHG_BST1

PWR_CHG_UGATE

PWR_CHG_DCIN

PWR_CHG_FBO

PWR_CHG_SDA

PWR_CHG_EAO

PWR_CHG_ACOK

PWR_DCBATOUT_CHG

PWR_CHG_LX1

AC_OKPWR_CHG_SCL

DC_IN_D

PWR_CHG_CSON

PWR_CHG_CSOP_1

PWR_CHG_ACOK

PWR_CHG_ICOUT

PWR_CHG_REF

PWR_CHG_VICM

AD+_G_2

PR

45

33

_0

2

PW

R_

CH

G_

FB

O1

PWR_CHG_VFB

AC_OK

PWR_CHG_CSSN

PWR_CHG_CE

PWR_CHG_CSOP

PWR_CHG_CSSP

PR

45

24

_0

3

PWR_CHG_EAI

PR4526_01

PWR_CHG_ACIN

PG

40

09

_1

AD

+_

G_

1

PWR_CHG_PHASE

PQ4003_D

ICR

EF

PQ4003_G

PWR_CHG_LGATE

PWR_CHG_VDDPPWR_CHG_BOOT

ICREF

PQ4004_D

PQ4004_G

BT+

CHG_AGND

CHG_AGND

CHG_AGND

BT+_R

CHG_AGND

CHG_AGND

3D3V_AUX_KBC

CHG_AGND

CHG_AGND

DCBATOUT

PWR_DCBATOUT_CHG

AD+_TO_SYS BT+

CHG_AGND

CHG_AGND

CHG_AGND

AD+

AD+

PWR_CHG_REF

AD+

CHG_AGND

PWR_CHG_REF

CHG_AGND

CHG_AGND

CHG_AGND

3D3V_AUX_S5

CHG_AGND

H_PROCHOT#(5,27,42)

AD_IA(27)

AC_IN#(27)

BAT_SCL(27,39)

BAT_SDA(27,39)

BATT_SENSE (39)

AC_OK (27)

AD_IA_HW(27)

AD_IA_HW2(27)

Title


Date: Sheet of



Nirvana 13 A00

CHARGER BQ24745


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

CHARGER BQ24745


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

CHARGER BQ24745


<Core Design>

SSID = Charger

PU4004

Id=12A

Qg=3.8nC

Rdson=24~30mohmCharger Current=1.4~3.6A

PU4005

Id=16A

Qg=7.3nC

Rdson=13.5~16.5mohm

This Resistor

must be 1%

tolerance.

Id=-12A

Qg=-25nC

Rdson=10~38mohm

Id=-12A

Qg=-25nC

Rdson=10~38mohm

PL4001

Id=7.5A

DCR=23mohm(Max)

Size=10*10


400mils or Copper Shape280mils or Copper Shape


20101222 A00

Power/Brian: Change PR4034 to 0 ohm pad.

Stuff PQ4003.

20101222 A00


Stuff PQ4004.

Change PR4037 to 76.8k ohm from 49.9k ohm.

20101222 A00


20101222 A00

Power/Brian: Change PR4047 to 174k ohm from 121k ohm.

Change PR4035 to 300k from 49.9k.

Change PR4031 to 150k from 0 ohm.

12

PR404010KR2J-3-GPDYPR404010KR2J-3-GPDY

1 2PR40170R0603-PADPR40170R0603-PAD

12345 6 7 8

SSSGD D D D

PU

40

05

SIS

41

2D

N-T

1-G

E3

-GP

84.00412.037

SSSGD D D D

PU

40

05

SIS

41

2D

N-T

1-G

E3

-GP

84.00412.037

1234 5

678S

S

S

G D

D

DD

PU4003

AO4407A-GP

84.04407.F372nd = 84.P1403.B37

SS

S

G D

D

DD

PU4003

AO4407A-GP

84.04407.F372nd = 84.P1403.B37

12

PC4029

SC

1U

6D

3V

2K

X-G

P

PC4029

SC

1U

6D

3V

2K

X-G

P

12

PC

40

07

SC

10

U2

5V

6K

X-1

GP

PC

40

07

SC

10

U2

5V

6K

X-1

GP

1 2PR40200R0402-PADPR40200R0402-PAD

12

PR

40

04

10

KR

2J-

3-G

PP

R4

00

41

0K

R2

J-3

-GP

12

PR403776K8R2F-GPPR403776K8R2F-GP

12

PC4013SC3300P50V3KX-1GPDYPC4013SC3300P50V3KX-1GPDY

G S

D

PQ40042N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

PQ40042N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

12

PR40080R0402-PADPR40080R0402-PAD

12

PG

40

10

GA

P-C

LO

SE

-PW

R-3

-GP

PG

40

10

GA

P-C

LO

SE

-PW

R-3

-GP

12

PG4002GAP-CLOSE-PWR-3-GP

PG4002GAP-CLOSE-PWR-3-GP

12

PC4001SCD1U10V2KX-5GPPC4001SCD1U10V2KX-5GP

1 2

PC4005

SCD1U50V3KX-GP

PC4005

SCD1U50V3KX-GP

12

PC

40

09

SC

D1

U5

0V

3K

X-G

PP

C4

00

9S

CD

1U

50

V3

KX

-GP

12

PC4026

SC

D1

U5

0V

3K

X-G

P

DYPC4026

SC

D1

U5

0V

3K

X-G

P

DY

12

PR40267K5R2F-1-GPPR40267K5R2F-1-GP

12

PC

40

06

SC

1U

6D

3V

2K

X-G

P

DY PC

40

06

SC

1U

6D

3V

2K

X-G

P

DY

12

PR

40

30

1K

8R

6J-

GP

DY

PR

40

30

1K

8R

6J-

GP

DY

12

PR

40

25

8K

45

R2

F-2

-GP

DYPR

40

25

8K

45

R2

F-2

-GP

DY

12

PC4030

SC

D1

U1

0V

2K

X-5

GP

DYPC4030

SC

D1

U1

0V

2K

X-5

GP

DY

12

PR

40

03

10

0K

R2

J-1

-GP

PR

40

03

10

0K

R2

J-1

-GP

12

PC

40

24

SC

22

0P

50

V2

JN-3

GP

PC

40

24

SC

22

0P

50

V2

JN-3

GP

G S

D

PQ40032N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

PQ40032N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

12

PR

40

05

10

KR

2F

-2-G

PP

R4

00

51

0K

R2

F-2

-GP

1 2PR40270R0402-PADPR40270R0402-PAD

12

PG

40

05

GA

P-C

LO

SE

-PW

R-3

-GP

PG

40

05

GA

P-C

LO

SE

-PW

R-3

-GP

12

PG

40

06

GA

P-C

LO

SE

-PW

R-3

-GP

PG

40

06

GA

P-C

LO

SE

-PW

R-3

-GP

12

PC

40

20

SC

D1

U5

0V

3K

X-G

PP

C4

02

0S

CD

1U

50

V3

KX

-GP

12

PR

40

09

31

6K

R3

F-2

-GP

PR

40

09

31

6K

R3

F-2

-GP

12

EC

40

01

SC

22

00

P5

0V

2K

X-2

GP

DY EC

40

01

SC

22

00

P5

0V

2K

X-2

GP

DY

12

EC

40

02

SC

D1

U2

5V

2Z

Y-1

GP

DY EC

40

02

SC

D1

U2

5V

2Z

Y-1

GP

DY

1 2PC4002SCD1U50V3KX-GPPC4002SCD1U50V3KX-GP

12

PC

40

10

SC

D0

1U

50

V2

KX

-1G

PP

C4

01

0S

CD

01

U5

0V

2K

X-1

GP

12

PR

40

13

33

R3

J-2

-GP

DYPR

40

13

33

R3

J-2

-GP

DY

12

PC

40

31

SC

D1

U5

0V

3K

X-G

P

DY

PC

40

31

SC

D1

U5

0V

3K

X-G

P

DY

12

PG

40

09

GA

P-C

LO

SE

-PW

R-3

-GP

PG

40

09

GA

P-C

LO

SE

-PW

R-3

-GP

12

PR

40

16

10

KR

2F

-2-G

PP

R4

01

61

0K

R2

F-2

-GP

12

PC4033SCD1U10V2KX-5GP DY

PC4033SCD1U10V2KX-5GP DY

1 2

PR403320R5F-1GP

PR403320R5F-1GP

1 2

PR4001

20KR2J-L2-GP

PR4001

20KR2J-L2-GP

12345 6 7 8

SSSGD D D D

PU

40

04

SIS

41

2D

N-T

1-G

E3

-GP

SSSGD D D D

PU

40

04

SIS

41

2D

N-T

1-G

E3

-GP

K A

PD4001

SD103AWS-1-GP

83.1R504.A8F2nd = 83.1R504.B8F

PD4001

SD103AWS-1-GP

83.1R504.A8F2nd = 83.1R504.B8F

12

PC

40

16

SC

10

U2

5V

6K

X-1

GP

PC

40

16

SC

10

U2

5V

6K

X-1

GP

12

PR4047174KR2F-GPPR4047174KR2F-GP

CE7

VDDSMB11

DCIN22

PGND19

SCL10

SDA9

ACIN2

NC#1414

VICM8

ACOK13

GND12

FBO6

EAI5

EAO4

CSSP28

CSSN27

VREF3

BOOT25

VDDP21

UGATE24

PHASE23

LGATE20

ICR

EF

1

CSON17

NC#1616

VFB15

ICOUT26

CSOP18

GN

D29

PU4001

BQ24745RHDR-GP

PU4001

BQ24745RHDR-GP

1

2

3 4

5

6

PQ4001

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

PQ4001

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

12345

678 S

S

S

GD

D

DD

PU4002

AO4407A-GP

2nd = 84.P1403.B3784.04407.F37

SS

S

GD

D

DD

PU4002

AO4407A-GP

2nd = 84.P1403.B3784.04407.F37

1 2PR4034

0R0402-PAD

PR4034

0R0402-PAD

1 2PR40230R0402-PADPR40230R0402-PAD

1 2

PL4001

IND-5D6UH-48-GP-U1

PL4001

IND-5D6UH-48-GP-U1

1 2PR40290R0402-PADPR40290R0402-PAD

1 2PR4032

0R0402-PAD

PR4032

0R0402-PAD

12

PG

40

04

GA

P-C

LO

SE

-PW

R-3

-GP

PG

40

04

GA

P-C

LO

SE

-PW

R-3

-GP

1 2PR40120R0402-PADPR40120R0402-PAD

12

PR40100R0402-PADPR40100R0402-PAD

1 2PC4025

SC56P50V2JN-2GP

PC4025

SC56P50V2JN-2GP

12

PR40240R0402-PADPR40240R0402-PAD

12

PC4022SC2200P50V2KX-2GP


12 P

C4

03

2S

CD

1U

25

V2

ZY

-1G

P

DY

PC

40

32

SC

D1

U2

5V

2Z

Y-1

GP

DY

1 2PC4014SC220P50V2JN-3GP

DYPC4014SC220P50V2JN-3GP

DY

12

PC

40

18

SC

10

U2

5V

6K

X-1

GP

PC

40

18

SC

10

U2

5V

6K

X-1

GP

12

PR4031150KR2F-L-GPPR4031150KR2F-L-GP

1 2

PC4003SCD47U50V5KX-1GP


12

PR40070R2J-2-GP

DYPR40070R2J-2-GP

DY

12

PG

40

01

GA

P-C

LO

SE

-PW

R-3

-GP

PG

40

01

GA

P-C

LO

SE

-PW

R-3

-GP

12

PR40214K7R2J-2-GPPR40214K7R2J-2-GP

12

PC

40

08

SC

10

U2

5V

6K

X-1

GP

PC

40

08

SC

10

U2

5V

6K

X-1

GP

12PG4007 GAP-CLOSE-PWR-3-GPPG4007 GAP-CLOSE-PWR-3-GP

1 2PR40280R0402-PADPR40280R0402-PAD

1 2

PC4021SC150P50V2JN-3GPPC4021SC150P50V2JN-3GP


12

PC

40

17

SC

10

U2

5V

6K

X-1

GP

PC

40

17

SC

10

U2

5V

6K

X-1

GP

12

PC

40

34

SC

10

U2

5V

6K

X-1

GP

PC

40

34

SC

10

U2

5V

6K

X-1

GP

1 2

PR4002

D01R2512F-4-GP

PR4002

D01R2512F-4-GP

12


DYPC4028

SCD01U50V2KX-1GP

DY

12

PC

40

04

SC

D1

U5

0V

3K

X-G

PP

C4

00

4S

CD

1U

50

V3

KX

-GP

12

PR4035300KR2F-L-GPPR4035300KR2F-L-GP

12

PC

40

19

SC

D1

U5

0V

3K

X-G

PP

C4

01

9S

CD

1U

50

V3

KX

-GP

12

PG4003

GAP-CLOSE-PWR-3-GP

PG4003

GAP-CLOSE-PWR-3-GP

1 2PR4036

0R0402-PAD

PR4036

0R0402-PAD

1 2

PR4019

D01R2512F-4-GP

PR4019

D01R2512F-4-GP

GS

D

PQ4002

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

PQ4002

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

12

PR4006470KR2J-2-GP

PR4006470KR2J-2-GP

12

PC4027

SC

D0

1U

50

V2

KX

-1G

P

DYPC4027

SC

D0

1U

50

V2

KX

-1G

P

DY

12

PC

40

15

SC

10

U2

5V

6K

X-1

GP

PC

40

15

SC

10

U2

5V

6K

X-1

GP


12

PR

40

14

49

K9

R2

F-L

-GP

PR

40

14

49

K9

R2

F-L

-GP

12

PC4023SCD1U50V3KX-GPPC4023SCD1U50V3KX-GP

12PG4008 GAP-CLOSE-PWR-3-GPPG4008 GAP-CLOSE-PWR-3-GP

1 2PR40180R0603-PADPR40180R0603-PAD

1 2

PR4022200KR2F-L-GP

PR4022200KR2F-L-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_5V3D3V_EN

15V_C_1

PWR_5V_SNUB

PWR_3D3V_VOUT2

3V/5V_POK

15V_C

PW

R_

5V

_V

OU

T1

PW

R_

5V

3D

3V

_T

ON

SE

L

PWR_5V_LL1

PWR_5V_TRIP13V/5V_POKPWR_5V3D3V_EN

PWR_3D3V_SNUB

PWR_3D3V_DVRH2

PWR_5V3D3V_REFIN2

PG

41

21

_2

PWR_3D3V_LL2

PWR_3D3V_TRIP2

PWR_5V3D3V_EN

PWR_5V3D3V_SKIPSEL

PWR_5V__DRVL1

PR4119_2

5V_C_2

10V_C

5V_C_1

3V/5V_POK

PW

R_

5V

3D

3V

_V

IN

PWR_5V_DRVH1

PWR_5V__VBST1_1 PWR_5V__VBST1 PWR_3D3V_VBST2 PWR_3D3V_VBST2_1

PWR_3D3V_DRVL2

PWR_5V3D3_AGND

5V_PWR

5V_PWR

PWR_5V3D3_AGND

3D3V_PWR

PWR_5V3D3_AGND

PWR_5V3D3_AGND

5V_S5

5V_AUX_S5

PWR_5V3D3_AGNDPWR_5V3D3_AGND

PWR_DCBATOUT_5V3D3V

5V_AUX_S5

+5V_VCC1

DCBATOUT

3D3V_S5

PWR_DCBATOUT_5V3D3V

PWR_5V3D3_AGND

15V_S5

+5V_VCC1PWR_5V3D3V_VREF3

+5V_VCC1PWR_DCBATOUT_5V3D3VDCBATOUT

PWR_5V3D3V_VREF2

15V_PWR

PWR_5V3D3_AGND

3D3V_S5

3D3V_AUX_S55V_AUX_S5

DCBATOUT

3V_5V_EN (36)

Title


Date: Sheet of



Nirvana 13 A00

TPS51427_5V/3D3VA2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

TPS51427_5V/3D3VA2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

TPS51427_5V/3D3VA2


<Core Design>0.5A= 20mils

1A= 40mils

0.375A= 15mils

V_REFIN2=VREF2*PR4109/(PR4109+PR4105)

Vout(3.3V)=V_REFIN2*(1+R1/R2)

TONSEL GND VREF2 or Float V5FILT

Ch1 400 kHz 400 kHz 200 kHz

Ch2 500 kHz 300 kHz 300 kHz

Connect VFB1to GND for fixe 5V opteration

SKIPSEL GND FLOAT/VREF2 V5IN

Mode Auto Skip OOA. PWM Only

Connect REFIN2 to V5FILT for fixed 3.3V operation

Vout(5V)=VFB1*(1+R1/R2)

Design Current = 7.4A

11.6A<OCP< 13.7A

Design Current = 16A

25.1A<OCP< 29.3A

CLOSE TO PIN 10

CLOSE TO PIN 30

20101224 A00:

Rename PTC4101~PTC4103 to PT4101~PT4103.

20101230 A00:

Change PR4119 to 0R short pad.

20101230 A00:

Change PR4114 to 0R short pad.

20101230 A00:

Change PR4116 to 0R0603 short pad.

20101230 A00:

Change PR4106 to 0R0603 short pad.

20101230 A00:

Change PR4103,PR4104 to 0R0805 short pad.

20110110 A00:

Change PG4110,PG4112,PG4114~PG4119,PG4122,PG4126,PG4129,PG4131,PG4133,PG4135~PG4138,PG4140,PG4142 to ZZ.CLOSE.001.

20110110 A00:

Change PG4102~PG4109,PG4111,PG4113 to ZZ.CLOSE.001.

20110110 A00:

Change PG4118,PG4120,PG4123,PG4101,PG4127,PG4130,PG4132,PG4134 to ZZ.CLOSE.001.

20110110 A00:

Change PG4143 to ZZ.CLOSE.001.

20110110 A00:

Change PG4139,PG4141 to ZZ.CLOSE.001.

20110110 A00:

Add PT4104 47uF.

20110112 A00:

Change PT4104 to 100uF.

20110118 A00:

Remove PU4101,PU4106 and add PT4105 100uF at PWR_DCBATOUT_5V3D3V.

12

PR41122D2R6J-3-GP

DY PR41122D2R6J-3-GP

DY

12

PC4104SCD1U25V3KX-GP


1 2

PG4129 GAP-CLOSE-PWR-3-GPPG4129 GAP-CLOSE-PWR-3-GP

1

2

3

PD4103

BAT54SW-2-GP

PD4103

BAT54SW-2-GP

12

PG4123

GAP-CLOSE-PWR-3-GP

PG4123

GAP-CLOSE-PWR-3-GP

1 2

PC4103

SC1U25V3KX-1-GP

PC4103

SC1U25V3KX-1-GP

12

PC

41

07

SC

10

U2

5V

6K

X-1

GP

PC

41

07

SC

10

U2

5V

6K

X-1

GP

12


12

PR41070R2J-2-GP

DY

PR41070R2J-2-GP

DY

1 2PR4125200KR2J-L1-GPPR4125200KR2J-L1-GP

12

PT

41

01

ST

22

0U

6D

3V

DM

-20

GP

PT

41

01

ST

22

0U

6D

3V

DM

-20

GP

12

PR

41

13

2D

2R

6J-

3-G

P

DY

PR

41

13

2D

2R

6J-

3-G

P

DY

12

PC

41

15

SC

10

U2

5V

6K

X-1

GP

PC

41

15

SC

10

U2

5V

6K

X-1

GP

12

PC4128SCD1U25V2ZY-1GP


12

PR4118

0R2J-2-GPDY PR4118

0R2J-2-GPDY

12

PR

41

05

0R

2J-

2-G

P

DY

PR

41

05

0R

2J-

2-G

P

DY

12

PG4132

GAP-CLOSE-PWR-3-GP

PG4132

GAP-CLOSE-PWR-3-GP

1 2


1 2PC4106SC1U25V3KX-1-GP

PC4106SC1U25V3KX-1-GP

1 2


1 2


12



1 2PR4108 0R2J-2-GPDYPR4108 0R2J-2-GPDY

12

PC

41

10

SC

1K

P5

0V

2K

X-1

GP

PC

41

10

SC

1K

P5

0V

2K

X-1

GP

1 2PC4125SCD1U25V2ZY-1GPPC4125SCD1U25V2ZY-1GP

12

PC

41

08

SC

10

U2

5V

6K

X-1

GP

PC

41

08

SC

10

U2

5V

6K

X-1

GP

12

PG4127

GAP-CLOSE-PWR-3-GP

PG4127

GAP-CLOSE-PWR-3-GP

VIN1

GND2

EN3

NC#44

VOUT5

PU4105

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

3rd = 74.07716.A7F

PU4105

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

3rd = 74.07716.A7F

1 2


12

PG4118

GAP-CLOSE-PWR-3-GP

PG4118

GAP-CLOSE-PWR-3-GP

1 2PR4110

0R2J-2-GP

DYPR4110

0R2J-2-GP

DY

1

2

3

PD4102

BAT54SW-2-GP

PD4102

BAT54SW-2-GP

12345 6 7 8

SSSGD D D D

PU4104AON7410-GP

84.07410.A37

SSSGD D D D

PU4104AON7410-GP

84.07410.A37

12

PG4113GAP-CLOSE-PWR-3-GP PG4113GAP-CLOSE-PWR-3-GP

12 PC4118

SC680P50V2KX-2GP

DYPC4118SC680P50V2KX-2GP

DY

12


12

PC

41

16

SC

10

U2

5V

6K

X-1

GP

PC

41

16

SC

10

U2

5V

6K

X-1

GP

12

PT

41

02

ST

22

0U

6D

3V

DM

-20

GP

PT

41

02

ST

22

0U

6D

3V

DM

-20

GP

1 2


12 P

C4

13

2S

C1

U1

0V

3K

X-3

GP

PC

41

32

SC

1U

10

V3

KX

-3G

P

12

PR412739KR2J-GPPR412739KR2J-GP

12


12345 6 7 8

SSSGD D D D

PU4107AON7702-GP

84.07702.037

SSSGD D D D

PU4107AON7702-GP

84.07702.037

1 2


1 2


12

PR

41

04

0R

08

05

-PA

DP

R4

10

40

R0

80

5-P

AD

12

PT4105SE100U25VM-L1-GP

79.1

0712.L

02

2n

d =

79.1

0712.6

JL


79.1

0712.L

02

2n

d =

79.1

0712.6

JL

1 2


1 2


12

PR

41

06

0R

06

03

-PA

DP

R4

10

60

R0

60

3-P

AD

1 2


1 2


1 2 3 45678

S S S

DDDD

G

PU

41

08

SIR

46

0D

P-T

1-G

E3

-GP

S S S

DDDD

G

PU

41

08

SIR

46

0D

P-T

1-G

E3

-GP

1 2

PL4102

IND-1D5UH-34-GP

68.1R510.10J

PL4102

IND-1D5UH-34-GP

68.1R510.10J

12


1 2PR412424D9R3F-GPPR412424D9R3F-GP

1 2


1 2


1 2PR4102 10R3J-3-GPPR4102 10R3J-3-GP

12

PC

41

21

SC

D1

U2

5V

3K

X-G

PP

C4

12

1S

CD

1U

25

V3

KX

-GP

1 2PC4127SCD1U25V2ZY-1GPPC4127SCD1U25V2ZY-1GP

12

PG4120

GAP-CLOSE-PWR-3-GP

PG4120

GAP-CLOSE-PWR-3-GP

12

PC

41

12

SC

1K

P5

0V

2K

X-1

GP

PC

41

12

SC

1K

P5

0V

2K

X-1

GP

1 2 3 45678

S S S GDDDD

PU

41

02

SIR

17

2D

P-T

1-G

E3

-GP

84.00172.037

S S S GDDDD

PU

41

02

SIR

17

2D

P-T

1-G

E3

-GP

84.00172.037

12

PC

41

20

SC

68

0P

50

V2

KX

-2G

P

DYPC

41

20

SC

68

0P

50

V2

KX

-2G

P

DY

12

PG4134

GAP-CLOSE-PWR-3-GP

PG4134

GAP-CLOSE-PWR-3-GP

1 2


12

PC

41

09

SC

D1

U5

0V

3K

X-G

PP

C4

10

9S

CD

1U

50

V3

KX

-GP

1 2


VR

EF

21

TO

NS

EL

2V

5F

ILT

3E

N_LD

O4

VR

EF

35

VIN

6LD

O7

LD

OR

EF

IN8

VSW9

VOUT110

VFB111

TRIP112

PGOOD113

EN114

DRVH115

LL116

VB

ST

117

DR

VL1

18

V5D

RV

19

NC

#20

20

GN

D21

PG

ND

22

DR

VL2

23

VB

ST

224

LL225

DVRH226

EN227

PGOOD228

SKIPSEL29

VOUT230

TRIP231

REFIN232

GND33

PU4103

TPS51427RHBR-GP

PU4103

TPS51427RHBR-GP

12PC4117

SCD1U25V3KX-GPPC4117

SCD1U25V3KX-GP

12

PC

41

19

SC

D1

U1

0V

2K

X-4

GP

PC

41

19

SC

D1

U1

0V

2K

X-4

GP

1

2

3

PD4101

BAT54-7-F-GP

PD4101

BAT54-7-F-GP

12

PC

41

24

SC

D1

U1

0V

2K

X-4

GP

PC

41

24

SC

D1

U1

0V

2K

X-4

GP

12

PG4125

GA

P-C

LO

SE

-PW

R-3

-GP

PG4125

GA

P-C

LO

SE

-PW

R-3

-GP

12

PG4121

GA

P-C

LO

SE

-PW

R-3

-GP

PG4121

GA

P-C

LO

SE

-PW

R-3

-GP

12

PR

41

03

0R

08

05

-PA

DP

R4

10

30

R0

80

5-P

AD

12

PG4130

GAP-CLOSE-PWR-3-GP

PG4130

GAP-CLOSE-PWR-3-GP

1 2


12

PT

41

03

ST

22

0U

6D

3V

DM

-20

GP

77.22271.27L

PT

41

03

ST

22

0U

6D

3V

DM

-20

GP

77.22271.27L

12

PC

41

11

SC

D1

U5

0V

3K

X-G

PP

C4

11

1S

CD

1U

50

V3

KX

-GP

1 2


12

PC

41

29

SC

10

U2

5V

6K

X-1

GP

PC

41

29

SC

10

U2

5V

6K

X-1

GP

12

PC

41

05

SC

1U

25

V3

KX

-1-G

PP

C4

10

5S

C1

U2

5V

3K

X-1

-GP

12

PR4122200KR2J-L1-GP

PR4122200KR2J-L1-GP

12

PR4123100KR2J-1-GPPR4123100KR2J-1-GP

12

PR41170R2J-2-GPDYPR41170R2J-2-GPDY

12

PG4101

GAP-CLOSE-PWR-3-GP

PG4101

GAP-CLOSE-PWR-3-GP

12



12


1 2PR4120 2KR2J-1-GPPR4120 2KR2J-1-GP

12

PR

41

09

0R

2J-

2-G

P

DY

PR

41

09

0R

2J-

2-G

P

DY

1 2


1 2

PR4116

0R0603-PAD

PR4116

0R0603-PAD

12

PC4102SC4D7U10V5KX-1GP

PC4102SC4D7U10V5KX-1GP

1 2


12

PC4101SC1U25V3KX-1-GPPC4101

SC1U25V3KX-1-GP

12


12

PC

41

13

SC

D1

U5

0V

3K

X-G

PP

C4

11

3S

CD

1U

50

V3

KX

-GP

12

PR4114

0R0402-PAD

PR4114

0R0402-PAD

1 2


1 2

PR4115

2D2R3-1-U-GP

PR4115

2D2R3-1-U-GP

12P

C4

13

1S

C1

U1

0V

3K

X-3

GP

PC

41

31

SC

1U

10

V3

KX

-3G

P

12


79.10712.L022nd = 79.10712.6JL


79.10712.L022nd = 79.10712.6JL

12


12

PC

41

14

SC

10

U2

5V

6K

X-1

GP

PC

41

14

SC

10

U2

5V

6K

X-1

GP

1 2


1 2


12

PR41190R0402-PAD

PR41190R0402-PAD

1 2

PL4101

IND-2D2UH-46-GP-U

68.2R210.20B

PL4101

IND-2D2UH-46-GP-U

68.2R210.20B

12


1 2PR4111

200KR2F-L-GPPR4111

200KR2F-L-GP

1 2PR4101 187KR2F-GPPR4101 187KR2F-GP

1 2


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PQ4202_DPWR_VCORE_IDES1_P

PQ4203_G

PQ4201_G

PQ4201_D

PWR_VCORE_DB1

PWR_VCORE_R_SEL0

PWR_VCORE_IDES1_N

PWR_VCORE_TEMP_SENSE1

PWR_VCORE_VDD3

PWR_VCORE_R_SEL6

PWR_VCORE_R_SEL1

PWR_VCORE_VDD3

PWR_VCORE_IMON1

TEMP_SENSE_GFX_R

PWR_VCORE_SENSE2+PWR_VCORE_SENSE2-PWR_VCORE_SENSE1+

PWR_VCORE_SPHASE_1

PWR_VCORE_VDD5

PWR_VCORE_R_SEL4

TEMP_SENSE_GFX

PWR_VCORE_DCMDRP1

PWR_VCORE_IDES1_P

PWR_VCORE_DCMDRP2

H_PROCHOT#

DB1_GFX

PWR_VCORE_DCMDRP2

PWR_VCORE_IMON2

PWR_VCORE_R_REF2

PWR_VCORE_TEMP_SENSE1_R

PWR_VCORE_DCMDRP1

PWR_VCORE_SPHASE_0

PWR_VCORE_VR2_DELAY

PWR_VCORE_R_SEL3

PWR_VCORE_R_OSC

PWR_VCORE_SENSE1-

PWR_VCORE_R_SEL5

PWR_VCORE_R_REF1

PWR_VCORE_R_SEL2

H_PROCHOT#

5V_S5

5V_S5

GND_1316

GND_1316

GND_1316

GND_1316

1D05V_PWR

GND_1316

GND_1316

5V_S5

1D05V_PWR

3D3V_S01D05V_VTT

1D05V_PWR

GND_1316

GND_1316

3D3V_PWR

D85V_PWRGD (48)

PWR_VCORE_DB1 (43)

VSS_AXG_SENSE (9)VCCSENSE (8)VSSSENSE (8)

IMVP_PWRGD (27,36)IDES_P_GFX(44)

VCC_AXG_SENSE (9)

DB2_GFX(44)

H_PROCHOT# (5,27,40)

SPHASE_GFX (44)

H_CPU_SVIDDAT (8)H_CPU_SVIDCLK (8)

VR_SVID_ALERT# (8)

D85V_PWRGD (48)

DB0_GFX(44)

IDES_N_GFX(44)

DB1_GFX(44)

PWR_VCORE_DB0(43)PWR_VCORE_DB1(43)PWR_VCORE_DB2(43)

PWR_VCORE_IDES1_P(43)

PWR_VCORE_SPHASE_1 (43)PWR_VCORE_SPHASE_0 (43)

PWR_VCORE_IDES1_N(43)

Title


Date: Sheet of


Nirvana 13 A00

VT1316+1317_CPU_CORE(1/3)A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

VT1316+1317_CPU_CORE(1/3)A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

VT1316+1317_CPU_CORE(1/3)A3


<Core Design>

20101012

20101012

NTCG104QH224HT

SSID = CPU.Regulator

NTCG104QH224HT

20101223 A00:Power/Brian:Change PU4201 to 74.01316.F33.

20101227 A00:Change PR4217~PR4220,PR4254 to 0R 0402 pad.

20101231 A00:Change PR4209,PR4212 to PN4201 10k array resistor.20110113 A00:Swap RN4201 base on swap report.

12


G

DS

PQ4203

AO7401-GP

DY

PQ4203

AO7401-GP

DY

G

DS

PQ4202

DMN601K-7-GP DY

PQ4202

DMN601K-7-GP DY

1 2PR4224 100KR2F-L1-GPPR4224 100KR2F-L1-GP

1 2PR4220 0R0402-PADPR4220 0R0402-PAD

12

PR4256NTC-220K-2-GPPR4256NTC-220K-2-GP

12

PR4215

100R2F-L1-GP-UDYPR4215

100R2F-L1-GP-UDY

12

PC

4218

SC

D047U

25V

2K

X-G

P

PC

4218

SC

D047U

25V

2K

X-G

P

12

PC4228SC2200P50V2KX-2GPPC4228SC2200P50V2KX-2GP

12

PC

4214

SC

D022U

16V

2K

X-3

GP

PC

4214

SC

D022U

16V

2K

X-3

GP

1 2PG4203GAP-CLOSE-PWRPG4203GAP-CLOSE-PWR

1 2PR423532K4R2F-1-GP PR423532K4R2F-1-GP

12

PR42216K98R2-GPPR42216K98R2-GP

12

PR42051R2F-GPPR42051R2F-GP

12

PR42041R2F-GPPR42041R2F-GP

12

PC

4213

SC

D1U

25V

3K

X-G

P

PC

4213

SC

D1U

25V

3K

X-G

P

1 234

PN4201SRN10KJ-5-GPPN4201SRN10KJ-5-GP

ALERT# 7

DB1037

DB1136

DB1235

DB2033

DB2132

DB2231

GND 3GND 11GND 49

IDES1_N24

IDES1_P23

IDES2_N27

IDES2_P28

R_OSC41

R_REF122

R_REF226

R_SEL02

R_SEL11

R_SEL248

R_SEL347

R_SEL446

VR2_READY 9VR1_READY 8

VR_TT# 10VR_ENABLE 6

VDIO 4

VDD512

VDD343

VDD342

VCLK 5

TEMP_SENSE1 29

SPHASE2 34SPHASE1_2 38SPHASE1_1 39SPHASE1_0 40

SENSE2+ 16SENSE2- 15SENSE1+ 13SENSE1- 14

NC#17 17

NC#20 20

TEMP_SENSE2 30

R_SEL545

R_SEL644

IMON121

IMON225

DCMDRP1 18

DCMDRP2 19

PU4201

VT1316MAFQX-041-GP

74.01316.F33

PU4201

VT1316MAFQX-041-GP

74.01316.F33

1 2PR422644K2R2D-GP PR422644K2R2D-GP

12

PC

4231

SC

D022U

16V

2K

X-3

GP

PC

4231

SC

D022U

16V

2K

X-3

GP

12PR

4238

43K

2R

2F

-L-G

PP

R4238

43K

2R

2F

-L-G

P

12

PR4240

0R2J-2-GP

DY

PR4240

0R2J-2-GP

DY

12

PR4216

100R2F-L1-GP-UDYPR4216

100R2F-L1-GP-UDY

1 2PR4217 0R0402-PADPR4217 0R0402-PAD

1 2

PR4233

5K76R2F-2-GP

PR4233

5K76R2F-2-GP

12

PC4428

SC4700P50V2KX-1GPDY

PC4428

SC4700P50V2KX-1GPDY

1 2PR42013K74R2F-GP PR42013K74R2F-GP

12

PR42505K11R2F-L1-GPPR42505K11R2F-L1-GP

1 2PR4219 0R0402-PADPR4219 0R0402-PAD

1 2PR42540R0402-PADPR42540R0402-PAD

1 2PR423123K7R2F-GP PR423123K7R2F-GP

1 2PR423739K2R2F-L-GP PR423739K2R2F-L-GP

12

PR4251

1KR2F-3-GPDY

PR4251

1KR2F-3-GPDY

12

PR42491K54R2F-GPPR42491K54R2F-GP

12

PR4239NTC-220K-2-GPPR4239NTC-220K-2-GP

12


12

PR4207100R2F-L1-GP-UDYPR4207100R2F-L1-GP-UDY

12

PC

4219

SC

D047U

25V

2K

X-G

P

PC

4219

SC

D047U

25V

2K

X-G

P

1 2PR423627K4R2F-GP PR423627K4R2F-GP

12

PR424348K7R3F-1-GPPR424348K7R3F-1-GP

1 2PR4223 100KR2F-L1-GPPR4223 100KR2F-L1-GP

12

PR

4208

54D

9R

2F

-L1-G

PP

R4208

54D

9R

2F

-L1-G

P

1 2PR423439K2R2F-L-GP PR423439K2R2F-L-GP

12

PC

4201

SC

D1U

25V

3K

X-G

P

PC

4201

SC

D1U

25V

3K

X-G

P1 2

PR423239K2R2F-L-GP PR423239K2R2F-L-GP

1 2PR4225130KR2F-GP PR4225130KR2F-GP

12

PR42228K87R2F-2-GPPR42228K87R2F-2-GP

G

DS

PQ4201

DMN601K-7-GP

DY

PQ4201

DMN601K-7-GP

DY

12

PR

4210

130R

2F

-1-G

PP

R4210

130R

2F

-1-G

P

1 2PR4218 0R0402-PADPR4218 0R0402-PAD

12


12

PR4253

1KR2F-3-GPDYPR4253

1KR2F-3-GPDY

12

PR425561K9R2F-GP

PR425561K9R2F-GP

12

PC4211SC220P50V2JN-3GP

DY PC4211SC220P50V2JN-3GP

DY

1 2PR422944K2R2D-GP PR422944K2R2D-GP

12


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_VCORE_VX0

PWR_VCORE1_IDES_P_1

PWR_VCORE1_IDES_N

PWR_VCORE_IDES1_N_2

PWR_VCORE_IDES0_P_1

PWR_VCORE0_IDES_P_1

PWR_VCORE_IDES1_N_1

PU

4202_A

VD

D

PWR_VCORE_IDES1_N

PWR_VCORE_IDES1_P

PWR_VCORE0_IDES_PPWR_VCORE0_IDES_N

PWR_VCORE1_IDES_P

PU

4203_A

VD

D

PWR_VCORE_VX1

PWR_VCORE_IDES1_P_1

GND_1317S_2

VCC_CORE

5V_S5

5V_S5

5V_S5

5V_S5

GND_1317S_1



PWR_VCORE_SPHASE_0(42)

PWR_VCORE_IDES1_N(42)

PWR_VCORE_IDES1_P(42)

PWR_VCORE_SPHASE_1(42)

Title


Date: Sheet of


Nirvana 13 A00

VT1316+1317_CPU_CORE(2/3)A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

VT1316+1317_CPU_CORE(2/3)A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

VT1316+1317_CPU_CORE(2/3)A3


<Core Design>

20101231 A00:Power/Brian: change PL4201 to 68.2415N.101 from 68.10110.10G.

12

PC

4225

SC

1U

10V

2K

X-1

GP

PC

4225

SC

1U

10V

2K

X-1

GP

1 2

PR4203

11K3R2F-2-GP

PR4203

11K3R2F-2-GP

12

PC

4221

SC

10U

6D

3V

3M

X-G

PP

C4221

SC

10U

6D

3V

3M

X-G

P

12


12

PC

4207

SC

D1U

25V

3K

X-G

PP

C4207

SC

D1U

25V

3K

X-G

P

12

PR42413K09R2F-1-GP

PR42413K09R2F-1-GP

12



1 2

PG4202

GAP-CLOSE-PWR

PG4202

GAP-CLOSE-PWR

1 2PC4202 SC1KP50V2KX-1GPPC4202 SC1KP50V2KX-1GP

DB1A1

AG

ND

A2

AVDDA3

IDES_PA4IDES_NA5

DB0A6

DB2B1

AG

ND

B2

AGNDB3

AGNDB4

AGNDB5

SPHASEB6

GN

DC

1

GN

DC

2

GN

DC

3

VD

DH

C4

VD

DH

C5

VD

DH

C6

VX#D1 D1

VX#D2 D2

VX#D3 D3

VX#D4 D4

VX#D5 D5

VX#D6 D6

GN

DE

1G

ND

E2

GN

DE

3

VD

DH

E4

VD

DH

E5

VD

DH

E6

VX#F1 F1VX#F2 F2VX#F3 F3VX#F4 F4VX#F5 F5VX#F6 F6

GN

DG

1G

ND

G2

GN

DG

3

VD

DH

G4

VD

DH

G5

VD

DH

G6

VX#H1 H1

VX#H2 H2

VX#H3 H3

VX#H4 H4

VX#H5 H5

VX#H6 H6

GN

DJ1

GN

DJ2

GN

DJ3

VD

DH

J4

VD

DH

J5

VD

DH

J6

PU4202

VT1317SFCX-001-GP

74.01317.B3Z

PU4202

VT1317SFCX-001-GP

74.01317.B3Z

1 2PC4216 SC1KP50V2KX-1GPPC4216 SC1KP50V2KX-1GP

12

PC

4206

SC

1U

10V

2K

X-1

GP

PC

4206

SC

1U

10V

2K

X-1

GP

1 2

PR4211

10R2J-2-GP

PR4211

10R2J-2-GP

1 2

PR4230

6K19R2F-GP

PR4230

6K19R2F-GP

1 2

PR4202

6K19R2F-GP

PR4202

6K19R2F-GP

1 2

PR4227

11K3R2F-2-GP

PR4227

11K3R2F-2-GP

1 2PC4227SC1KP50V2KX-1GP

PC4227SC1KP50V2KX-1GP

12

PC

4222

SC

10U

6D

3V

3M

X-G

PP

C4222

SC

10U

6D

3V

3M

X-G

P

12

PR42063K09R2F-1-GP

PR42063K09R2F-1-GP

12

PC

4209

SC

10U

6D

3V

3M

X-G

PP

C4209

SC

10U

6D

3V

3M

X-G

P1

2

PC

4223

SC

10U

6D

3V

3M

X-G

PP

C4223

SC

10U

6D

3V

3M

X-G

P

12

PC

4220

SC

10U

6D

3V

3M

X-G

PP

C4220

SC

10U

6D

3V

3M

X-G

P

12



12

PC

4204

SC

10U

6D

3V

3M

X-G

PP

C4204

SC

10U

6D

3V

3M

X-G

P

12

PC

4226

SC

D1U

25V

3K

X-G

PP

C4226

SC

D1U

25V

3K

X-G

P

DB1A1A

GN

DA

2

AVDDA3

IDES_PA4IDES_NA5

DB0A6

DB2B1A

GN

DB

2

AGNDB3

AGNDB4

AGNDB5

SPHASEB6

GN

DC

1

GN

DC

2

GN

DC

3

VD

DH

C4

VD

DH

C5

VD

DH

C6

VX#D1 D1

VX#D2 D2

VX#D3 D3

VX#D4 D4

VX#D5 D5

VX#D6 D6G

ND

E1

GN

DE

2G

ND

E3

VD

DH

E4

VD

DH

E5

VD

DH

E6


GN

DG

1G

ND

G2

GN

DG

3

VD

DH

G4

VD

DH

G5

VD

DH

G6

VX#H1 H1

VX#H2 H2

VX#H3 H3

VX#H4 H4

VX#H5 H5

VX#H6 H6

GN

DJ1

GN

DJ2

GN

DJ3

VD

DH

J4

VD

DH

J5

VD

DH

J6

PU4203

VT1317SFCX-001-GP

74.01317.B3Z

PU4203

VT1317SFCX-001-GP

74.01317.B3Z

12


12

PC

4208

SC

10U

6D

3V

3M

X-G

PP

C4208

SC

10U

6D

3V

3M

X-G

P

1 2

PR4242

10R2J-2-GP

PR4242

10R2J-2-GP

1 2PG4201

GAP-CLOSE-PWR

PG4201

GAP-CLOSE-PWR

1 2

PC4212

SC1KP50V2KX-1GP

PC4212

SC1KP50V2KX-1GP

12

PC

4205

SC

10U

6D

3V

3M

X-G

PP

C4205

SC

10U

6D

3V

3M

X-G

P

1 2

PR4214

11K3R2F-2-GP

PR4214

11K3R2F-2-GP

1 2

PR4247

6K19R2F-GP

PR4247

6K19R2F-GP

12

PC

4210

SC

1U

10V

2K

X-1

GP

PC

4210

SC

1U

10V

2K

X-1

GP

12

PC

4224

SC

1U

10V

2K

X-1

GP

PC

4224

SC

1U

10V

2K

X-1

GP

43

12

PL4201

IND-240NH-GP

68.2415N.101

PL4201

IND-240NH-GP

68.2415N.101

1 2

PR4213

6K19R2F-GP

PR4213

6K19R2F-GP

1 2

PR4248

11K3R2F-2-GP

PR4248

11K3R2F-2-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IDES_N_GFX_1

IDES_P_GFX_1

PWR_AXG_IDES_P

PWR_AXG_IDES_P_1

PW

R_A

XG

_A

VD

D

PWR_AXG_VXPWR_AXG_IDES_N

5V_S5

GND_1317S_3

VCC_GFXCORE

5V_S5

SPHASE_GFX(42)

IDES_N_GFX(42)

IDES_P_GFX(42)

DB0_GFX(42)DB1_GFX(42)DB2_GFX(42)

Title


Date: Sheet of


Nirvana 13 A00

VT1316+1317_AXG_CORE(3/3)A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

VT1316+1317_AXG_CORE(3/3)A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

VT1316+1317_AXG_CORE(3/3)A3


<Core Design>

0.12UH~0.15UH0.12UH~0.15UH0.12UH~0.15UH0.12UH~0.15UH20101012

20101012




12

PC

4404

SC

22U

6D

3V

5M

X-2

GP

PC

4404

SC

22U

6D

3V

5M

X-2

GP

12

PC

4412

SC

22U

6D

3V

5M

X-2

GP

PC

4412

SC

22U

6D

3V

5M

X-2

GP

12



12

PC

4415

SC

10U

6D

3V

3M

X-G

PP

C4415

SC

10U

6D

3V

3M

X-G

P

12

PC

4425

SC

22U

6D

3V

5M

X-2

GP

PC

4425

SC

22U

6D

3V

5M

X-2

GP

12

PC

4420

SC

1U

10V

2K

X-1

GP

PC

4420

SC

1U

10V

2K

X-1

GP

12

PC

4409

SC

22U

6D

3V

5M

X-2

GP

PC

4409

SC

22U

6D

3V

5M

X-2

GP

12

PC

4423

SC

22U

6D

3V

5M

X-2

GP

PC

4423

SC

22U

6D

3V

5M

X-2

GP

12

PC

4405

SC

22U

6D

3V

5M

X-2

GP

PC

4405

SC

22U

6D

3V

5M

X-2

GP

12

PC4414

SC4700P50V2KX-1GP

PC4414

SC4700P50V2KX-1GP


12

PC

4416

SC

10U

6D

3V

3M

X-G

PP

C4416

SC

10U

6D

3V

3M

X-G

P

12

PC

4410

SC

22U

6D

3V

5M

X-2

GP

PC

4410

SC

22U

6D

3V

5M

X-2

GP

12

PR440110R2J-2-GPPR440110R2J-2-GP

12

PC

4402

SC

22U

6D

3V

5M

X-2

GP

DY

PC

4402

SC

22U

6D

3V

5M

X-2

GP

DY

1 2PC4413

SC2700P50V2KX-1-GP

PC4413

SC2700P50V2KX-1-GP

12

PC

4419

SC

1U

10V

2K

X-1

GP

PC

4419

SC

1U

10V

2K

X-1

GP

1 2PC4422

SC2700P50V2KX-1-GP

PC4422

SC2700P50V2KX-1-GP

12

PR

4404

3K

09R

2F

-1-G

PP

R4404

3K

09R

2F

-1-G

P

1 2

PR4406

3K24R2F-GP

PR4406

3K24R2F-GP

12

PC

4408

SC

22U

6D

3V

5M

X-2

GP

PC

4408

SC

22U

6D

3V

5M

X-2

GP

12

PC

4403

SC

22U

6D

3V

5M

X-2

GP

DY

PC

4403

SC

22U

6D

3V

5M

X-2

GP

DY

1 2

PR4402

3K24R2F-GP

PR4402

3K24R2F-GP

1 2

PL4401

IND-D1UH-26-GP

68.R1010.10T

PL4401

IND-D1UH-26-GP

68.R1010.10T

12

PC

4407

SC

22U

6D

3V

5M

X-2

GP

PC

4407

SC

22U

6D

3V

5M

X-2

GP

12

PC

4411

SC

22U

6D

3V

5M

X-2

GP

PC

4411

SC

22U

6D

3V

5M

X-2

GP

12

PC

4424

SC

22U

6D

3V

5M

X-2

GP

PC

4424

SC

22U

6D

3V

5M

X-2

GP

DB1A1

AG

ND

A2

AVDDA3

IDES_PA4IDES_NA5

DB0A6

DB2B1

AG

ND

B2

AGNDB3

AGNDB4

AGNDB5

SPHASEB6

GN

DC

1

GN

DC

2

GN

DC

3

VD

DH

C4

VD

DH

C5

VD

DH

C6

VX#D1 D1

VX#D2 D2

VX#D3 D3

VX#D4 D4

VX#D5 D5

VX#D6 D6

GN

DE

1G

ND

E2

GN

DE

3

VD

DH

E4

VD

DH

E5

VD

DH

E6


GN

DG

1G

ND

G2

GN

DG

3

VD

DH

G4

VD

DH

G5

VD

DH

G6

VX#H1 H1

VX#H2 H2

VX#H3 H3

VX#H4 H4

VX#H5 H5

VX#H6 H6

GN

DJ1

GN

DJ2

GN

DJ3

VD

DH

J4

VD

DH

J5

VD

DH

J6

PU4401

VT1317SFCX-001-GP

74.01317.B3Z

PU4401

VT1317SFCX-001-GP

74.01317.B3Z

12

PC

4418

SC

10U

6D

3V

3M

X-G

PP

C4418

SC

10U

6D

3V

3M

X-G

P

1 2

PR4405

11KR2F-L-GP

PR4405

11KR2F-L-GP 12

PC

4401

SC

22U

6D

3V

5M

X-2

GP

PC

4401

SC

22U

6D

3V

5M

X-2

GP

12

PC

4406

SC

22U

6D

3V

5M

X-2

GP

PC

4406

SC

22U

6D

3V

5M

X-2

GP

1 2

PR4403

11KR2F-L-GP

PR4403

11KR2F-L-GP

12

PC

4421

SC

D1U

25V

3K

X-G

PP

C4421

SC

D1U

25V

3K

X-G

P

12

PC

4426

SC

22U

6D

3V

5M

X-2

GP

PC

4426

SC

22U

6D

3V

5M

X-2

GP

12

PC

4417

SC

10U

6D

3V

3M

X-G

PP

C4417

SC

10U

6D

3V

3M

X-G

P

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VTT_SENSE_L

VSS_SENSE_L

PWR_1D05V_VFB

PWR_1D05V_CCMPWR_1D05V_DRVL

PWR_1D05V_VBST_RPWR_1D05V_DRVHPWR_1D05V_VBST

PWR_1D05V_SWPWR_1D05V_VFBPWR_1D05V_EN

PWR_1D05V_TRIP

PW

R_1D

05V

_S

NU

B

VSS_SENSE_L

VTT_SENSE_L

1D05V_PWR

PWR_1D05V_DCBATOUT

DCBATOUT PWR_1D05V_DCBATOUT

1D05V_VTT1D05V_PWR

3D3V_S0

5V_S5

VCCIO_SENSE (8)

VSSIO_SENSE (8)

RUNPWROK(19,46,47)

1.05VTT_PWRGD(37,48)

Title


Date: Sheet of


Nirvana 13 A00

TPS51218_1D05V_VTTA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Id=14.3AQg=9.2~14nCRdson=11~14mohm

Id=26.5AQg=40.6~61nC,Rdson=2.6~3.2mohm

TPS51218 for 1D05V_VTT

Vout=0.704V*(R1+R2)/R2

Design Current = 9.9A 15.6A<OCP< 18.3A

Mag. 0.56uH 10*10*4DCR=1.6~1.8mohmIdc=25A, Isat=40A

20101224 A00:Rename PTC4502,PTC4509 to PT4502~PT4509.

20101224 A00 Modify:Change PR4514 to 0ohm short pad from 0402and un-stuff PC4523 at X-Build stage.

12

PC4532SC1000P50V3JN-GP-UDY PC4532SC1000P50V3JN-GP-UDY

1 2PR45150R0402-PADPR45150R0402-PAD

12

PC4506

SC

4D

7U

25V

5K

X-G

P

PC4506

SC

4D

7U

25V

5K

X-G

P

1 2

PG4518 GAP-CLOSE-PWRPG4518 GAP-CLOSE-PWR

1 2


1 2


12

PC4530SC560P50V-GP

DY PC4530SC560P50V-GP

DY

12

PC4526

SC

4D

7U

25V

5K

X-G

P

PC4526

SC

4D

7U

25V

5K

X-G

P

1 2


12

PR45239K76R2F-1-GP

PR45239K76R2F-1-GP

12

PR45222D2R5F-2-GPDYPR45222D2R5F-2-GPDY

1 2


1 2

PR4501

75KR2F-GP

PR4501

75KR2F-GP

12


12

PC4523

SC

1K

P50V

2K

X-1

GP

DYPC4523

SC

1K

P50V

2K

X-1

GP

DY

12

PT4502

ST

330U

2V

DM

-4-G

P

79.33719.20L2nd = 77.C3371.13L

PT4502

ST

330U

2V

DM

-4-G

P

79.33719.20L2nd = 77.C3371.13L

DRVL 6V5IN 7SW 8

DRVH 9VBST 10GND 11PGOOD1

TRIP2

EN3

VFB4

CCM5

PU4503

TPS51218DSCR-GP-U1

PU4503

TPS51218DSCR-GP-U1

1 2


1 2


12

PR4519

10KR2J-3-GP

PR4519

10KR2J-3-GP

12345 6 7 8

SSS

D D D D

G

PU4504

SIR460DP-T1-GE3-GP

84.00460.037

SSS

D D D D

G

PU4504

SIR460DP-T1-GE3-GP

84.00460.037

12

PC4531

SC

D1U

25V

3K

X-G

P

PC4531

SC

D1U

25V

3K

X-G

P

1 2


1 2


1 2


12

PR4517100R2F-L1-GP-U

PR4517100R2F-L1-GP-U

12345 6 7 8

SSSGD D D DPU4502

SIR172DP-T1-GE3-GP

84.00172.037

SSSGD D D DPU4502

SIR172DP-T1-GE3-GP

84.00172.037

1 2PR4514 0R0402-PADPR4514 0R0402-PAD

12

PR4516100R2F-L1-GP-UPR4516100R2F-L1-GP-U

1 2


1 2PR45100R0402-PADPR45100R0402-PAD

1 2


12

PC4529

SC

4D

7U

25V

5K

X-G

P

PC4529

SC

4D

7U

25V

5K

X-G

P

1 2


12

PT4509

SC

D1U

25V

3K

X-G

P

DYPT4509

SC

D1U

25V

3K

X-G

P

DY

1 2


12

PC4528

SC

D1U

10V

2K

X-4

GP

PC4528

SC

D1U

10V

2K

X-4

GP

1 2PR45182D2R3-1-U-GP

PR45182D2R3-1-U-GP

1 2


12

PR4520470KR2F-GPPR4520470KR2F-GP 1

2

PC4527

SC

1U

10V

2K

X-1

GP

PC4527

SC

1U

10V

2K

X-1

GP

12

PR451320KR2F-L-GP

PR451320KR2F-L-GP

1 2

PL4502

IND-D56UH-27-GP

PL4502

IND-D56UH-27-GP

1 2


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_1D5V_VDDQS

PWR_1D5V_SW

PWR_1D5V_EN

PWR_1D5V_VTTREF

TPS51216_PHS_SET

PWR_1D5V_EN

PWR_1D5V_TRIP

PR

4601_1

PWR_1D5V_MODE

TPS51216_DRVL

PW

R_1D

5V

_V

DD

QS

PWR_1D5V_VTTREF

0D75V_EN

PWR_1D5V_VREF

PWR_1D5V_VBST

PWR_1D5V_DRVH

PWR_1D5V_REFIN

PR

4605_2

1D5V_PWR

+PWR_SRC_1D5V

+PWR_SRC_1D5V

+0D75V_DDR_P 0D75V_S0

DCBATOUT

+0D75V_DDR_P

5V_S5

3D3V_S0

1D5V_PWR 1D5V_S3

1D5V_PWR

DDR_VREF_S3

RUNPWROK(19,45,47)

PM_SLP_S4#(19,27)

0D75V_EN(37)

Title


Date: Sheet of


Nirvana 13 A00

TPS51116_+1.5V_SUSA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

68k ohm

47k ohm 400kHz

Design Current = 14.45A 22.71A<OCP< 26.84A

PR5003

200k ohm

300kHz

300kHz

400kHzTracking Discharge

Non-tracking Discharge

Frequency Discharge Mode

State S3 S5 VDDR VTTREF VTT

S0

S3

S4/S5

Hi Hi

HiLo

Lo Lo

On

On

On

On

On

Off Off Off

Off(Hi-Z)

SSID = PWR.Plane.Regulator_1p5v0p75v

MODE

100k ohm

20101224 A00:Rename PTC4601,PTC4602 to PT601~PT4602.

20101224 A00 Modify:Change PR4607 to short pad at X-Build.

20101230 A00:Follow the standard schematics: remove PR4615,PR4616.

12

PC

4620

SC

4D

7U

6D

3V

5K

X-3

GP

PC

4620

SC

4D

7U

6D

3V

5K

X-3

GP

12

PC

4603

SC

D1U

25V

3K

X-G

PP

C4603

SC

D1U

25V

3K

X-G

P



1 2

PR4605

2D2R3J-2-GP

PR4605

2D2R3J-2-GP

12

PC4606SCD1U10V2KX-5GPDYPC4606SCD1U10V2KX-5GPDY

12

PC

4621

SC

D1U

10V

2K

X-4

GP

PC

4621

SC

D1U

10V

2K

X-4

GP

12

PC

4613

SC

D1U

50V

3K

X-G

PP

C4613

SC

D1U

50V

3K

X-G

P



1 2





12PC

4615

SC

D1U

10V

2K

X-4

GP

PC

4615

SC

D1U

10V

2K

X-4

GP


12

PR

4606

240R

2F

-1-G

PP

R4606

240R

2F

-1-G

P

12

PC

4614

SC

4D

7U

25V

5K

X-G

PP

C4614

SC

4D

7U

25V

5K

X-G

P

12PC

4617

SC

10U

6D

3V

5M

X-3

GP

DY

PC

4617

SC

10U

6D

3V

5M

X-3

GP

DY

12

PG4605

GAP-CLOSE-PWR

PG4605

GAP-CLOSE-PWR


12

PR

4608

200K

R2F

-L-G

P

PR

4608

200K

R2F

-L-G

P

12

PT4602

SE

220U

2V

DM

-8G

P

PT4602

SE

220U

2V

DM

-8G

P

12

PC

4612

SC

10U

25V

6K

X-1

GP

PC

4612

SC

10U

25V

6K

X-1

GP


12

PR460310KR2F-2-GPPR460310KR2F-2-GP



1 2

PG4601

GAP-CLOSE-PWR

PG4601

GAP-CLOSE-PWR

12

PG4603

GAP-CLOSE-PWR

PG4603

GAP-CLOSE-PWR

1 2

PG4602

GAP-CLOSE-PWR

PG4602

GAP-CLOSE-PWR


VTT 3

VREF6

VTTS 1

V5IN 12

VTTIN 2

PGND 10

PGOOD20

VDDQS 9

MODE19

VTTGND 4

VBST 15

DRVH 14

SW 13

DRVL 11

GND7

GND21

EN/PSV16

VTTEN17

REFIN8

TRIP18

VTTREF5

PU4601

TPS51216RUKR-GP

74.51216.073

PU4601

TPS51216RUKR-GP

74.51216.073

12

PT4601SE

220U

2V

DM

-8G

P

PT4601SE

220U

2V

DM

-8G

P

1 2PR46070R0402-PADPR46070R0402-PAD


12

PG

4607

GA

P-C

LO

SE

-PW

R-3

-GP

PG

4607

GA

P-C

LO

SE

-PW

R-3

-GP

12345 6 7 8

SSS

D D D D

G

PU4603

SIR

460D

P-T

1-G

E3-G

P

SSS

D D D D

G

PU4603

SIR

460D

P-T

1-G

E3-G

P


12

PC

4604

SC

1U

10V

3K

X-3

GP

PC

4604

SC

1U

10V

3K

X-3

GP

12

PR46122D2R5F-2-GPDY PR46122D2R5F-2-GPDY

12

PG4604

GAP-CLOSE-PWR

PG4604

GAP-CLOSE-PWR1

2

PR

4601

47K

R2F

-GP

PR

4601

47K

R2F

-GP


12

PR

4602

82K

R2F

-1-G

PP

R4602

82K

R2F

-1-G

P

12PC

4616

SC

10U

6D

3V

5M

X-3

GP

PC

4616

SC

10U

6D

3V

5M

X-3

GP


12345 6 7 8

SSSGD D D D PU4602

SIR172DP-T1-GE3-GP

84.00172.037

SSSGD D D D PU4602

SIR172DP-T1-GE3-GP

84.00172.037


12

PC

4609

SC

10U

25V

6K

X-1

GP

PC

4609

SC

10U

25V

6K

X-1

GP

12

PG4606

GAP-CLOSE-PWR

PG4606

GAP-CLOSE-PWR

12

PC4622SC330P50V2KX-3GPDY PC4622SC330P50V2KX-3GPDY

1 2PR46110R0603-PAD

PR46110R0603-PAD

1 2

PL4601

IND-D68UH-51-GP-U

PL4601

IND-D68UH-51-GP-U

12

PC

4611

SC

10U

25V

6K

X-1

GP

PC

4611

SC

10U

25V

6K

X-1

GP

12

PC

4602

SC

D01U

16V

2K

X-3

GP

PC

4602

SC

D01U

16V

2K

X-3

GP

12

PC4610SCD22U6D3V2KX-1GPPC4610SCD22U6D3V2KX-1GP

12

PR4604

20KR2J-L2-GP

PR4604

20KR2J-L2-GP

12

PC

4601

SC

1U

10V

3K

X-3

GP

PC

4601

SC

1U

10V

3K

X-3

GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_1D8V_FB

PWR_1D8V_FB_1

PWR_1D8V_VBST PWR_1D8V_VBST_1

PWR_1D8V_SW

PW

R_1D

8V

_F

B_2

PWR_1D8V_FB

PWR_1D8V_COMP

PWR_1D8V_PS

1D8V_EN

3D3V_S5

PWR_1D8V_VIN

3D3V_S5

3D3V_S0

PWR_1D8V_RUN 1D8V_S0

RUNPWROK(19,45,46)PM_SLP_S3#(19,27,36,37)

Title


Date: Sheet of


Nirvana 13 A00

TPS51311_ +1.8V_RUNA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

TPS51311_ +1.8V_RUNA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

TPS51311_ +1.8V_RUNA3


<Core Design>

SSID = PWR.Plane.Regulator_1p8v

0.5A= 20mils1.5A= 60mils1A= 40mils

12

PC

4719

SC

10U

6D

3V

5M

X-3

GP

PC

4719

SC

10U

6D

3V

5M

X-3

GP

1 2PR4715 10KR2J-3-GPPR4715 10KR2J-3-GP

12



12

PC4715SC10U6D3V5MX-3GPPC4715SC10U6D3V5MX-3GP

12

PR471757K6R2F-GP

DY PR471757K6R2F-GP

DY

1 2PG4702

GAP-CLOSE-PWRPG4702

GAP-CLOSE-PWR

1 2PG4701

GAP-CLOSE-PWRPG4701

GAP-CLOSE-PWR

12



1 2

PG4706

GAP-CLOSE-PWR

PG4706

GAP-CLOSE-PWR

12

PR471840D2R2F-GPPR471840D2R2F-GP

12

PR471610KR2F-2-GPPR471610KR2F-2-GP

12

PR

4702

20K

R2F

-L-G

PP

R4702

20K

R2F

-L-G

P

1 2PR4707 20KR2J-L2-GPPR4707 20KR2J-L2-GP

12

PC

4720

SC

22U

6D

3V

5M

X-2

GP

DY

PC

4720

SC

22U

6D

3V

5M

X-2

GP

DY

1 2PR47060R0603-PADPR47060R0603-PAD

1 2PC4718 SC2200P50V2KX-2GPPC4718 SC2200P50V2KX-2GP

12

PC4703SC1U6D3V2KX-GPPC4703SC1U6D3V2KX-GP

12



1 2

PR4705

5K9R2F-GP

PR4705

5K9R2F-GP

12



1 2

PG4704

GAP-CLOSE-PWR

PG4704

GAP-CLOSE-PWR

1 2

PL4701IND-2D2UH-46-GP-U

68.2R210.20B

PL4701IND-2D2UH-46-GP-U

68.2R210.20B

12

PC4721SC10U6D3V5MX-3GPPC4721SC10U6D3V5MX-3GP

1 2

PG4705

GAP-CLOSE-PWR

PG4705

GAP-CLOSE-PWR

1 2

PC4702 SC100P50V2JN-3GPPC4702 SC100P50V2JN-3GP

VBST 4

VIN 13

SW#5 5

MODE8

PGOOD3

AGND11

RES2

FB10

COMP9

VDD12

EN1 SW#6 6

SW#7 7

VIN 14

PGND 15

PGND 16PGND17

PU4701

TPS51311RGTR-GP

74.51311.073

PU4701

TPS51311RGTR-GP

74.51311.073

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_VCCSA_SLEW

PWR_VCCSA_BST_R

PW

R_

VC

CS

A_

SN

UB

PWR_VCCSA_BST

PWR_VCCSA_V5DRV

PWR_VCCSA_EN

PWR_VCCSA_VOUT

PWR_VCCSA_SW

PW

R_

VC

CS

A_

CO

MP

_1

PW

R_

VC

CS

A_

CO

MP

PW

R_

VC

CS

A_

PG

OO

D

PWR_VCCSA_VID0

PWR_VCCSA_VID1

PW

R_

VC

CS

A_

VR

EF

PWR_VCCSA_FB

PQ

48

01

_D

PQ4801_G

PQ4801_5

5V_S5

5V_S5

0D85V_S0

0D85V_S0

3D3V_S0

3D3V_S0

0D85V_S0

5V_S5

1D05V_VTT

3D3V_S0

1.05VTT_PWRGD (37,45)

D85V_PWRGD (42)

H_FC_C22 (9)

VCCSA_SEL (9)

VCCUSA_SENSE (9)

D85V_PWRGD(42)

1.05VTT_PWRGD(37,45)

VCCSA_SEL (9)

Title


Date: Sheet of



Nirvana 13 A00

TPS51461_VCCSA

A2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

TPS51461_VCCSA

A2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

TPS51461_VCCSA

A2


<Core Design>

Design Current = 4.2A

6.6A<OCP< 7.8A

TPS51461 for VCCSA

VID0 VCCSA

0.675V

0.725VL

L

VID1

H

0.8VL

H

L

H

H

0.9V

Iomax=6A

OCP>9A

VCCSA=0.85V

SB modify 2K2 for no run code

APL5916 for VCCSA

Vout=0.8*(1+R1/R2)

H

VCCSA_SEL VCCSA_PWR

L

0.8V

0.9V

R1

R2

20101224 A00:

Rename PTC4801 to PT4801.

1 2PR48121KR2F-3-GP

DYPR48121KR2F-3-GP

DY

1 2PR48070R0603-PAD

VCCSA_PWM

PR48070R0603-PAD

VCCSA_PWM

12

PC4813

SC

4D

7U

25

V5

KX

-GP

VCCSA_PWMPC4813

SC

4D

7U

25

V5

KX

-GP

VCCSA_PWM

1 2

PR4811

100R2F-L1-GP-UVCCSA_PWM

PR4811

100R2F-L1-GP-UVCCSA_PWM

1 2PR48080R0402-PAD

VCCSA_PWM

PR48080R0402-PAD

VCCSA_PWM

12

PR48024K99R2F-L-GPVCCSA_PWMPR48024K99R2F-L-GPVCCSA_PWM

12

PC4803

SC

D1

U2

5V

3K

X-G

P

VCCSA_PWMPC4803

SC

D1

U2

5V

3K

X-G

P

VCCSA_PWM

12

PT4801ST100U6D3VBM-7GP

DYPT4801ST100U6D3VBM-7GP

DY

12

PC4816SC

2D

2U

10

V3

KX

-1G

P

VCCSA_PWM

PC4816SC

2D

2U

10

V3

KX

-1G

P

VCCSA_PWM

GN

D1

FB2

VOUT3

VOUT4

VIN5

VC

NT

L6

POK7

EN8

VIN9

U4802APL5916KAI-TRL-GP

74.05916.031

VCCSA_LDO

U4802APL5916KAI-TRL-GP

74.05916.031

VCCSA_LDO

12

PC4819

SC

4D

7U

25

V5

KX

-GP

VCCSA_PWMPC4819

SC

4D

7U

25

V5

KX

-GP

VCCSA_PWM

1 2 3456

PQ4801

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

DYPQ4801

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

DY

1 2PR48040R0402-PAD

VCCSA_PWMPR48040R0402-PAD

VCCSA_PWM

12

PC

48

11

SC

22

U6

D3

V5

MX

-2G

P

VC

CS

A_P

WM

PC

48

11

SC

22

U6

D3

V5

MX

-2G

P

VC

CS

A_P

WM

12

PC4818SC560P50V-GPDYPC4818SC560P50V-GPDY

12

PC4817SC3300P50V3KX-1GPVCCSA_PWMPC4817SC3300P50V3KX-1GPVCCSA_PWM

12

PC

48

10

SC

22

U6

D3

V5

MX

-2G

P

VC

CS

A_P

WM

PC

48

10

SC

22

U6

D3

V5

MX

-2G

P

VC

CS

A_P

WM

12

PC4822

SC10U6D3V5MX-3GP

VCCSA_LDOPC4822

SC10U6D3V5MX-3GP

VCCSA_LDO

12

PC4814SC

1U

10

V2

KX

-1G

P

VCCSA_PWM PC4814SC

1U

10

V2

KX

-1G

P

VCCSA_PWM

12

PC4824

SC

10

U6

D3

V5

MX

-3G

P

VCCSA_LDOPC4824

SC

10

U6

D3

V5

MX

-3G

P

VCCSA_LDO

12

PC4825SC1U6D3V2KX-GP

VCCSA_LDOPC4825SC1U6D3V2KX-GP

VCCSA_LDO

12

PR48061R2F-GP VCCSA_PWMPR48061R2F-GP VCCSA_PWM

12

PR481810KR2F-2-GP DY

PR481810KR2F-2-GP DY

1 2PR48100R0402-PAD

VCCSA_PWM

PR48100R0402-PAD

VCCSA_PWM

12

PC

48

01

SC

22

U6

D3

V5

MX

-2G

P

VC

CS

A_P

WM

PC

48

01

SC

22

U6

D3

V5

MX

-2G

P

VC

CS

A_P

WM

12

PC4812

SC

D1

U2

5V

3K

X-G

P

DYPC4812

SC

D1

U2

5V

3K

X-G

P

DY1

2

PR48094K7R2J-2-GP

VCCSA_PWM PR48094K7R2J-2-GP

VCCSA_PWM

12


DY PC4826SCD1U10V2KX-4GP

DY

12

PR481410KR2F-2-GP

VCCSA_LDOPR481410KR2F-2-GP

VCCSA_LDO

12

PR4816160KR2F-GP DYPR4816160KR2F-GP DY

12

PC

48

08

SC

22

U6

D3

V5

MX

-2G

P

DY

PC

48

08

SC

22

U6

D3

V5

MX

-2G

P

DY

12

PC

48

09

SC

22

U6

D3

V5

MX

-2G

P

DY

PC

48

09

SC

22

U6

D3

V5

MX

-2G

P

DY

12

PC

48

07

SC

22

U6

D3

V5

MX

-2G

P

VC

CS

A_P

WM

PC

48

07

SC

22

U6

D3

V5

MX

-2G

P

VC

CS

A_P

WM

1 2PR48050R0402-PAD VCCSA_PWMPR48050R0402-PAD VCCSA_PWM

12

PC4827

SC

10

U6

D3

V5

MX

-3G

P

VCCSA_LDO

PC4827

SC

10

U6

D3

V5

MX

-3G

P

VCCSA_LDO

12

R48072K2R2J-2-GP

VCCSA_LDOR48072K2R2J-2-GP

VCCSA_LDO

12

PC4820

SC

10

0P

50

V2

JN-3

GP

VCCSA_LDOPC4820

SC

10

0P

50

V2

JN-3

GP

VCCSA_LDO

12

PC4802

SCD22U10V2KX-1GP

VCCSA_PWM PC4802

SCD22U10V2KX-1GP

VCCSA_PWM

12

PC4806

SCD01U50V2KX-1GP

VCCSA_PWM PC4806

SCD01U50V2KX-1GP

VCCSA_PWM

12

PR481580K6R2F-GP

VCCSA_LDO

PR481580K6R2F-GP

VCCSA_LDO

1 2

PR4813

10KR2J-3-GP

DY

PR4813

10KR2J-3-GP

DY

1 2


VCCSA_PWM


VCCSA_PWM

12

PR48032D2R5F-2-GPDYPR48032D2R5F-2-GPDY

12


DY


DY

GN

D1

VR

EF

2

CO

MP

3

SLE

W4

VO

UT

5

MO

DE

6

SW#77

SW#88

SW#99

SW#1010

SW#1111

BST12

EN

13

VID

014

VID

115

PG

OO

D16

V5F

ILT

17

V5D

RV

18

PGND19

PGND20

PGND21

VIN22

VIN23

VIN24

GND25

U4801

TPS51461RGER-GP

74.51461.043

VCCSA_PWM

U4801

TPS51461RGER-GP

74.51461.043

VCCSA_PWM

12

PC4821

SC

10

U6

D3

V5

MX

-3G

P

VCCSA_LDO

PC4821

SC

10

U6

D3

V5

MX

-3G

P

VCCSA_LDO

1 2

PL4801

IND-D47UH-22-GP

68.R4710.10M

VCCSA_PWM

PL4801

IND-D47UH-22-GP

68.R4710.10M

VCCSA_PWM

12


DYPC4823

SC1U6D3V2KX-GP

DY

1 2PR48010R0402-PADVCCSA_PWMPR48010R0402-PADVCCSA_PWM

12

PC4815

SC

4D

7U

25

V5

KX

-GP

VCCSA_PWMPC4815

SC

4D

7U

25

V5

KX

-GP

VCCSA_PWM

ENVDDLCDVDD_EN


DBC_EN_C

LCD_TST_C

BLON_OUT_C_1

USB_CAMERA#USB_CAMERA

LVDSA_CLK

LCD_TST_CLCD_BRIGHTNESS

LVDSA_CLK#

BLON_OUT_CLCD_TST_C

LCD_BRIGHTNESS

LVDS_VDD_EN

BLON_OUT_C

LVDSA_CLK#_RLVDSA_CLK_R

LVDSA_DATA2_RLVDSA_DATA2#_R









LVDSA_CLK#_RLVDSA_CLK_R

CE_C

CE_CDBC_EN_C

BLON_OUT_C_1

3D3V_S0

3D3V_CAMERA_S0

3D3V_S0LCDVDD

3D3V_S0

DCBATOUT_LCD DCBATOUT

3D3V_CAMERA_S03D3V_S0

DCBATOUT_LCD

LCDVDD

LCD_TST_EN(27)

LVDS_VDD_EN(17)

LCD_TST (27)BLON_OUT (27)

L_BKLT_CTRL (17)

LVDS_DDC_DATA_R (17,97)LVDS_DDC_CLK_R (17,97)

AUD_DMIC_CLK (29,97)AUD_DMIC_IN0 (29,97)

USB_PP12 (18)USB_PN12 (18)

LVDSA_CLK# (17)LVDSA_CLK (17)

LVDSA_DATA1# (17)LVDSA_DATA1 (17)

LVDSA_DATA2# (17)LVDSA_DATA2 (17)

LVDSA_DATA0 (17)LVDSA_DATA0# (17)

CE (21)DBC_EN (22)

Title


Date: Sheet of


Nirvana 13 A00

LCD/Inverter ConnectorA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

SSID = VIDEOSSID = VIDEO

Camera Power

For EMI requestClose to LVDS connector

LVDS CONNECTOR

LCD POWER for ROSA

CAMERA and DIGITAL MIC PIN DEFINE!

20101227 A00:Change R4908,R4909,R4903,R4910,R4913~R4916R4917,R4918 to 0R 0402 pad.20110111 A00:Change R4908,R4909,R4903,R4910,R4913~R4916R4917,R4918 to 0R 0402 reisstors.

20100104 A00:Remove TR4902.

20110107 A00:Change F4902 to 0603 0 ohm.

12

C4904

SC

1K

P50V

2K

X-1

GP

C4904

SC

1K

P50V

2K

X-1

GP

12

C4907

SC

1U

10V

3K

X-3

GP

C4907

SC

1U

10V

3K

X-3

GP

1 2R4910 0R2J-2-GPR4910 0R2J-2-GP

EN1

GND2

OUT3 IN#4 4

IN#5 5

U4901

G5285T11U-GP

74.05285.07F2nd = 74.09724.09F

U4901

G5285T11U-GP

74.05285.07F2nd = 74.09724.09F

12

EC4903SCD1U10V2KX-5GP DYEC4903SCD1U10V2KX-5GP DY

1 2R4907100KR2J-1-GPDY

R4907100KR2J-1-GPDY

12


12

R4951100KR2J-1-GP

R4951100KR2J-1-GP

12

C4905

SC

D1U

50V

3K

X-G

P

C4905

SC

D1U

50V

3K

X-G

P

1 2R4919100KR2J-1-GPR4919100KR2J-1-GP

1 2

R4904

0R0402-PAD

R4904

0R0402-PAD

12

R4905

49K

9R

2F

-L-G

PR

4905

49K

9R

2F

-L-G

P

1 2R49090R2J-2-GP R49090R2J-2-GP

1 2EC4911 SC10P50V2JN-4GPDYEC4911 SC10P50V2JN-4GPDY



12 3

4RN4901

SRN100J-3-GP

RN4901

SRN100J-3-GP


12 R490133R2J-2-GP

R490133R2J-2-GP

12

C4902

SC1U6D3V2KX-GP

C4902

SC1U6D3V2KX-GP

1 2R4915 0R2J-2-GPR4915 0R2J-2-GP


1 2R4917 0R2J-2-GPR4917 0R2J-2-GP

12

R4912

10KR2J-3-GPDYR4912

10KR2J-3-GPDY

1

2

3

D4901

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

D4901

BAT54CPT-GP

2ND = 83.00054.Q8183.R2003.E81

1 2R4913 0R2J-2-GPR4913 0R2J-2-GP

12

C4901

SC

D1U

10V

2K

X-5

GP

C4901

SC

D1U

10V

2K

X-5

GP


12

EC4901

SC

33P

50V

2JN

-3G

PDY

EC4901

SC

33P

50V

2JN

-3G

PDY

12

EC4902

SC

33P

50V

2JN

-3G

P

DYEC4902

SC

33P

50V

2JN

-3G

P

DY

12 R490233R2J-2-GPR490233R2J-2-GP

1 2R4903 0R2J-2-GPR4903 0R2J-2-GP

12

EC4904

SC

5D

6P

50V

2C

N-1

GP DY

EC4904

SC

5D

6P

50V

2C

N-1

GP DY

12

C4908

SC

D1U

10V

2K

X-5

GP

DYC

4908

SC

D1U

10V

2K

X-5

GP

DY

12 R491133R2J-2-GP

R491133R2J-2-GP

1 2R49080R2J-2-GP R49080R2J-2-GP

1 234

RN9403SRN2K2J-1-GP

RN9403SRN2K2J-1-GP

1

23456789101112131415161718192021222324252627282930

31

32

NP1

NP2

LCD1

PS-CON30-GP

20.F1816.030

LCD1

PS-CON30-GP

20.F1816.030

12

R4906

10KR2J-3-GP

DY

R4906

10KR2J-3-GP

DY

12

EC4905

SC

5D

6P

50V

2C

N-1

GP DY

EC4905

SC

5D

6P

50V

2C

N-1

GP DY

1 2R4916 0R2J-2-GPR4916 0R2J-2-GP

1 2

F4902

0R3J-0-U-GP

F4902

0R3J-0-U-GP

1 2R4918 0R2J-2-GPR4918 0R2J-2-GP

K A

PD4901

SD103AWS-1-GP

83.1R504.A8F2nd = 83.1R504.B8F

PD4901

SD103AWS-1-GP

83.1R504.A8F2nd = 83.1R504.B8F

12F4901

POLYSW-1D1A24V-GP-U

69.50007.A31

2nd = 69.50007.A41

F4901

POLYSW-1D1A24V-GP-U

69.50007.A31

2nd = 69.50007.A41

1 2R4914 0R2J-2-GPR4914 0R2J-2-GP


1 TP4903TPAD14-GPTP4903TPAD14-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CRT_R

CRT_G

CRT_B

CRT_VSYNC_CONCRT_HSYNC_CON

CRT_DDCCLK_CON

CRT_VSYNC_CON

CRT_DDCDATA_CON

CRT_HSYNC_CON

CRT_VSYNC

CRT_GREEN

CRT_BLUE

CR

T_B

CR

T_R

CR

T_G

CRT_DDCDATA_CONCRT_DDC_DATA

CRT_DDC_CLK

CRT_DDCCLK_CON

CRT_RED

CRT_HSYNC

CRT_R

CRT_G

CRT_B

CRT_DDCCLK_CON

CRT_VSYNC_CON

CRT_DDCDATA_CON

CRT_HSYNC_CON

3D3V_S0

5V_CRT_S0

3D3V_S0

3D3V_S0

5V_CRT_S0_R

5V_S0 5V_CRT_S0 5V_CRT_S0_R

CRT_GREEN(17)

CRT_BLUE(17)

CRT_RED(17)

CRT_HSYNC(17)CRT_VSYNC(17)

CRT_DDC_CLK(17)

CRT_DDC_DATA(17)

Title


Date: Sheet of


Nirvana 13 A00

CRT ConnectorA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CRT ConnectorA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CRT ConnectorA3


<Core Design>

CRT Hsync & Vsync level shift

CRT DDCDATA & DDCCLK level shift

Place closer500mA

20101231 A00:Change R5004,R5005 to RN5001 33 ohm array resistor.

12

R5003

150R

2F

-1-G

PR

5003

150R

2F

-1-G

P

1 2

3

D5002

BAV99PT-GP-U

DY

D5002

BAV99PT-GP-U

DY

1 2

L5002

FCM1608CF-220T05-GP

L5002

FCM1608CF-220T05-GP

1

2

34

5

6

Q5001

2N7002KDW-GP

84.2N702.A3F2nd = 84.DM601.03F

Q5001

2N7002KDW-GP

84.2N702.A3F2nd = 84.DM601.03F

12

C5004

SC

10P

50V

2JN

-4G

PC

5004

SC

10P

50V

2JN

-4G

P

12

C5010

SC

18P

50V

2JN

-1-G

P

DY

C5010

SC

18P

50V

2JN

-1-G

P

DY

123 4


12

C5006

SC

10P

50V

2JN

-4G

PC

5006

SC

10P

50V

2JN

-4G

P

12

C5008

SC

100P

50V

2JN

-3G

P

DY

C5008

SC

100P

50V

2JN

-3G

P

DY

1 2

3

D5004

BAV99PT-GP-U

DY

D5004

BAV99PT-GP-U

DY

12 3

4

RN5001

SRN33J-5-GP-U

RN5001

SRN33J-5-GP-U

12



12

R5001

150R

2F

-1-G

PR

5001

150R

2F

-1-G

P

123 4

RN5007SRN2K2J-1-GP

RN5007SRN2K2J-1-GP

1 2

F5001

FUSE-1D1A6V-4GP-U

69.50007.6912nd = 69.50007.771

F5001

FUSE-1D1A6V-4GP-U

69.50007.6912nd = 69.50007.771

12

C5003

SC

10P

50V

2JN

-4G

P

DY

C5003

SC

10P

50V

2JN

-4G

P

DY

12

C5001

SC

10P

50V

2JN

-4G

P

DY

C5001

SC

10P

50V

2JN

-4G

P

DY

1 2

L5003

FCM1608CF-220T05-GP

L5003

FCM1608CF-220T05-GP

12

C5005

SC

10P

50V

2JN

-4G

PC

5005

SC

10P

50V

2JN

-4G

P12

C5002

SC

10P

50V

2JN

-4G

P

DY

C5002

SC

10P

50V

2JN

-4G

P

DY

1 2

L5001

FCM1608CF-220T05-GP

L5001

FCM1608CF-220T05-GP

1 2

R5006

0R3J-0-U-GP

DYR5006

0R3J-0-U-GP

DY

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

CRT1

D-SUB-15-81-GP

CRT1

D-SUB-15-81-GP

21

D5001

CH551H-30PT-GP2ND = 83.R5003.H8H

3rd = 83.5R003.08F

83.R5003.C8F

D5001

CH551H-30PT-GP2ND = 83.R5003.H8H

3rd = 83.5R003.08F

83.R5003.C8F

12

C5009

SC

18P

50V

2JN

-1-G

P

DY

C5009

SC

18P

50V

2JN

-1-G

P

DY

12

C5011

SC

100P

50V

2JN

-3G

P

DY

C5011

SC

100P

50V

2JN

-3G

P

DY

12

R5002

150R

2F

-1-G

PR

5002

150R

2F

-1-G

P

1 2

3

D5003

BAV99PT-GP-U

DY

D5003

BAV99PT-GP-U

DY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDMI_HPD_E

HDMI_HPD_B

HP

D_H

DM

I_C

ON

HDMI_DATA2_R_C

HDMI_DATA2_R_C#HDMI_DATA1_R_C

HDMI_DATA1_R_C#HDMI_DATA0_R_C

HDMI_DATA0_R_C#HDMI_CLK_R_C

HDMI_CLK_R_C#

DDC_CLK_HDMIDDC_DATA_HDMI

PCH_HDMI_DATA

DDC_DATA_HDMI

DDC_CLK_HDMIPCH_HDMI_CLK

HDMI_DATA0_R_CHDMI_DATA0_R_C#

HDMI_PLL_GND

HDMI_DATA2_R_CHDMI_DATA2_R_C#

HDMI_DATA1_R_C

HDMI_PLL_GND

PCH_HDMI_DATAPCH_HDMI_CLK

HDMI_DATA1_R_C#

HDMI_CLK_R_CHDMI_CLK_R_C#

HDMI_OE#

HPD_HDMI_CON

HDMI_CLK_R#_1HDMI_CLK_R_1

HDMI_DATA0_R#_1HDMI_DATA0_R_1



3D3V_S0

5V_CRT_S0_R

3D3V_S0

5V_S0

5V_CRT_S0_R

3D3V_S0

HDMI_PCH_DET (17)

HDMI_CLK_R#(17)HDMI_CLK_R(17)

HDMI_DATA0_R#(17)HDMI_DATA0_R(17)

PCH_HDMI_DATA(17)PCH_HDMI_CLK(17)



HDMI_IN# (27)

Title


Date: Sheet of


Nirvana 13 A00

HDMI Level Shifter/ConnectorA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Removed HDMI_IN# CIRCUIT

connect to KBC GPIO.SSID = VIDEO HDMI Level Shifter & CONNECTOR HDMI CONN

suggestion to stuff 680-ohm for UMA.

Routing Guidelines:

CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm).

The total delay on CTRLDATA should be longer than CTRLCLK.

Removed LEVEL SHIFTER base on DELL feedback spec.

(No support 220MHZ deep color mode, so can be removed

HDMI LEVEL SHIFTER circuit.

Already PH on PCH side.(RN1706)

Close to HDMI Connector

20100723 Swap RN5106 and RN5107 base in the swap report.

20101224 A00:Change RN5117 to 0402 0 ohm pad.20110111 A00:Change RN5117 to 0 ohm resistor.20110118 A00:Remove RN5117 for PCH_HDMI_CLK and PCH_HDMI_DATA.

20110111 A00:Change R5101~R5108 to 0 ohm array resistors RN5102~RN5105.

3

1

2

Q5102

PMBS3904-1-GP 84.03904.L062nd = 84.03904.P113rd = 84.03904.T11

Q5102

PMBS3904-1-GP 84.03904.L062nd = 84.03904.P113rd = 84.03904.T11

12 3

4

RN5102 SRN0J-6-GPRN5102 SRN0J-6-GP

1 2 R51270R2J-2-GP

DY R51270R2J-2-GP

DY

1 2 3 45678

RN5106

SRN680J-GP

RN5106

SRN680J-GP

12



12 3

4


12

R511210KR2J-3-GPR511210KR2J-3-GP



1 2R5111 150KR2J-L1-GPR5111 150KR2J-L1-GP

12

R5123

0R2J-2-GPDYR5123

0R2J-2-GPDY

1 2R5125 0R0402-PADR5125 0R0402-PAD


1 2 3 45678

RN5107

SRN680J-GP

RN5107

SRN680J-GP

20

21

22

23

1

2345678910111213141516171819

HDMI1

SKT-HDMI23-GP

22.10296.341

HDMI1

SKT-HDMI23-GP

22.10296.341

12


G S

D

Q5103

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

Q5103

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

G S

D

Q5101

2N7002K-2-GP84.2N702.J31

2ND = 84.2N702.031DY

Q5101

2N7002K-2-GP84.2N702.J31

2ND = 84.2N702.031DY

12 3

4


12

R5110

200KR2J-L1-GP DYR5110

200KR2J-L1-GP DY

1 234



1

2

34

5

6

Q5104

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

Q5104

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F



12 3

4


12

R510920KR2J-L2-GPDYR510920KR2J-L2-GPDY


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

LVDS_SwitchA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

LVDS_SwitchA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

LVDS_SwitchA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ITPA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ITPA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ITPA3


<Core Design>

ITP ConnectorCPU

TCK(PIN AC5)

FBO(PIN 11)

TCK(PIN 5)

ITP Connector

H_CPURST# use pull-up Resistor closeITP connector 500 mil ( max ),others place near CPU side.

SSID = User.Interface

SATA_ODD_PWRGTSATA_ODD_DA#

ODD_PWR_5V

SATA_ODD_DA#_C

SATA_ODD_PWRGT SATA_ODD_DA#

OD

D_P

WR

GT

#

SATA_ODD_DA#_C

SATA_RX4-_CSATA_RX4+_C

SATA_TXN4_CSATA_TXP4_C

HDD1_22

HDD1_20

SATA_RXN0_C

SATA_TXN0_CSATA_TXP0_C

SATA_RXP0_C

SATA_RXN0_C

SATA_TXP0_C

SATA_RXP0_C

HDD1_21

SATA_TXN0_C

FFS_INT2

ODD_PWR_5V

3D3V_S0

5V_S0

5V_S0

3D3V_S0 5V_S0

3D3V_S0

5V_S0

3D3V_S0

5V_S0

SATA_ODD_PRSNT# (22)

SATA_ODD_PWRGT(22)

SATA_ODD_DA# (18)

SATA_TXP4 (21)

SATA_RXN4 (21)

SATA_TXN4 (21)

SATA_RXP4 (21)

SATA_RXN0(21)

SATA_TXN0(21)SATA_TXP0(21)

SATA_RXP0(21)

FFS_INT2(79)

Title


Date: Sheet of


Nirvana 13 A00

HDD/ODDA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

HDD/ODDA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

HDD/ODDA3


<Core Design>

SUPPORT ZERO SATA ODD

ODD Connector

SATA Zero Power ODD

Current limit

Active High

typ =>2A

When the drive is powered on, the FET to the MD/DA pin drive is OFF.

When the drive is powered off, the FET to the MD/DA pin is ON

SATA_RX- and SATA_RX+ TraceLength match within 20 mil

Mars:

Exchange ODD and ESATA differential pair each other.

SATA HDD ConnectorSSID = SATA

12



123

4RN5601

SRN10KJ-5-GP

RN5601

SRN10KJ-5-GP

12

R5605100KR2J-1-GPR5605100KR2J-1-GP

12

C5604

SC

10U

6D

3V

5K

X-1

GP

DYC5604

SC

10U

6D

3V

5K

X-1

GP

DY

1 2C5615 SCD01U16V2KX-3GPC5615 SCD01U16V2KX-3GP1 2C5616 SCD01U16V2KX-3GPC5616 SCD01U16V2KX-3GP


GND1IN#22IN#33EN/EN#4 OC# 5

OUT#6 6

OUT#7 7

OUT#8 8

U5601G547F1P81U-GP

2ND = 74.02191.07974.00547.C79

U5601G547F1P81U-GP

2ND = 74.02191.07974.00547.C79

12

C5605

SC

10U

10V

5Z

Y-1

GP

C5605

SC

10U

10V

5Z

Y-1

GP

12

C5609SC10U6D3V5KX-1GPC5609SC10U6D3V5KX-1GP1 2C5611 SCD01U16V2KX-3GPC5611 SCD01U16V2KX-3GP


12

C5606

SC

D1U

10V

2K

X-5

GP

C5606

SC

D1U

10V

2K

X-5

GP


1AFTP5601AFTP5601


12 R56020R2J-2-GP DY R56020R2J-2-GP DY

S1

S2S3S4S5S6S7

8

9

P1

P3P4P5P6

P2

ODD1

SKT-SATA7P+6P-50-GP

62.10065.6512nd = 62.10065.221

ODD1

SKT-SATA7P+6P-50-GP

62.10065.6512nd = 62.10065.221

1

3

5

7

9

11

13

15

17

2

4

6

8

10

12

14

16

18

20

2221

19HDD1

MLX-CONN18A-S1GP

20.K0229.018

HDD1

MLX-CONN18A-S1GP

20.K0229.01812 C5613SCD01U16V2KX-3GP C5613SCD01U16V2KX-3GP12 C5614SCD01U16V2KX-3GP C5614SCD01U16V2KX-3GP

1 2 3456

Q56012N7002KDW-GP

84.2N702.A3F2nd = 84.DM601.03F

Q56012N7002KDW-GP

84.2N702.A3F2nd = 84.DM601.03F


12

C5601

SC

D1U

10V

2K

X-5

GP

DYC5601

SC

D1U

10V

2K

X-5

GP

DY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB_PP1_CUSB_PN1_C5V_USB1_S3

SATA_TXN5_C

SATA_RXP5_CSATA_RXN5_C

USB_PN1_C

SATA_TXP5_C

USB_PP1_C

ESATA1_D1

CBUSB_PP1_RUSB_PN1_R

USB_PN1_CUSB_PN1_R

USB_PP1_R USB_PP1_C

5V_USB1_S3

5V_S5

SATA_TXN5(21)

SATA_RXP5(21)

USBDET_CON# (27)

SATA_RXN5(21)

SATA_TXP5(21)

USBCHARGER_CB0 (27)USB_PP1 (18)

USB_PN1 (18)

Title


Date: Sheet of


Nirvana 13 A00A3


<Core Design>

USB/ESATATitle


Date: Sheet of


Nirvana 13 A00A3


<Core Design>

USB/ESATATitle


Date: Sheet of


Nirvana 13 A00A3


<Core Design>

USB/ESATA

SSID = ESATA

close to ESATA1

ESATA CONN

S0 S1

0 0

0

0

1

1

Auto

1

1

D+/- connects to Y+/-

Switch Control Bit:

CB=0 (AM):auto detection charger identification active.

CB=1 (PM):connect DP/DM to TDP/TDM.

USB CHARGER

20100104 A00:Remove R5718,R5719

1 2

R57220R0402-PAD

R57220R0402-PAD

S01

D+2

D-3

GND4

A+5

A- 6VDD 7

Y- 8Y+ 9S1 10

GND 11

U5702

PI5USB14550AZEE-GP

73.5USB1.003

U5702

PI5USB14550AZEE-GP

73.5USB1.003

1AFTP5703 AFTE14P-GPAFTP5703 AFTE14P-GP

1 2R5721 0R0402-PADR5721 0R0402-PAD



1 2EC5701 SC5P50V2CN-2GP

DYEC5701 SC5P50V2CN-2GP

DY

VBUS1

D-2D+3

GND 4

GND 5A+6

A-7

GND 8

B-9B+10 GND 11

GND 14

GND 15

GND 16

GND 17

DT1 12

DT2 13

ESATA1

SKT-ESATA-USB-11P-6-GP-U

22.10321.W11

2nd = 22.10339.261

ESATA1

SKT-ESATA-USB-11P-6-GP-U

22.10321.W11

2nd = 22.10339.261



1

34

2TR5701

WCM2012F2S-GP-U2

69.10084.081TR5701

WCM2012F2S-GP-U2

69.10084.081



12

C5701

SC

D1U

10V

2K

X-4

GP

C5701

SC

D1U

10V

2K

X-4

GP

1

AFTP5714AFTE14P-GPAFTP5714AFTE14P-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AUD_SPK_L+_CAUD_SPK_L-_C

MIC_IN_R_C

MIC_IN_L_C

AUD_HP1_JACK_R1

AUD_HP1_JACK_L1

AUD_HP1_JD#

EXT_MIC_JD#

MIC_IN_R_C

MIC_IN_L_CMIC_IN_L

AUD_SPK_L+_C

AUD_SPK_L-_C

MIC_IN_R

AUD_HP1_JD#

AUD_HP1_JACK_R1

AUD_HP1_JACK_L1

AUD_HP1_JACK_R2_RAUD_HP1_JACK_R2

AUD_HP1_JACK_L2 AUD_HP1_JACK_L2_R

MIC_IN_L(29)

MIC_IN_R(29)

EXT_MIC_JD#(29)

AUD_SPK_L-(29)

AUD_SPK_L+(29)

AUD_HP1_JD#(29)

AUD_HP1_JACK_R2(29)

AUD_HP1_JACK_L2(29)

Title


Date: Sheet of


Nirvana 13 A00

Audio JackA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Audio JackA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Audio JackA3


<Core Design>

600ohm 100MHz200mA 0.5ohm DC

Speaker

Connector

SSID = AUDIO

MIC IN

40 mils

LINE OUT

20101224 A00:0402 0R pad: R5805,R5806.20101224 A00:

Change R5803,R5804 to 0603 0 ohm pad.

20101224 A00:Rename LINEOUT1 to LOUT1.

12

EC5801

MLV

G0402220N

V05B

P-G

P-U

DYEC5801

MLV

G0402220N

V05B

P-G

P-U

DY

1

AFTP5810AFTP5810

12 EC

5804

SC

D01U

16V

2K

X-3

GP

EC

5804

SC

D01U

16V

2K

X-3

GP

1 2R58050R0402-PAD R58050R0402-PAD

1

2

3

4

56

78

MICIN1

PHONE-JK383-GP-U

22.10133.K31

MICIN1

PHONE-JK383-GP-U

22.10133.K31

1 2

L5802

BLM18BD601SN1D-GP

L5802

BLM18BD601SN1D-GP

1AFTP5802AFTP5802

1AFTP5807AFTP5807

12

EC5806SC1KP50V2KX-1GPEC5806SC1KP50V2KX-1GP

1

2

3

4

56

78

LOUT1

PHONE-JK383-GP-U

22.10133.K31

LOUT1

PHONE-JK383-GP-U

22.10133.K31

1AFTP5811AFTP5811

12

EC5807

SC

100P

50V

2JN

-3G

P

DY

EC5807

SC

100P

50V

2JN

-3G

P

DY

1 2R5801 BLM18BD601SN1D-GPR5801 BLM18BD601SN1D-GP

1 2R5804 0R0603-PADR5804 0R0603-PAD

1AFTP5809AFTP5809

1 2R58060R0402-PAD R58060R0402-PAD

12

EC5802

MLV

G0402220N

V05B

P-G

P-U

DYEC5802

MLV

G0402220N

V05B

P-G

P-U

DY

1AFTP5801AFTP5801

12

EC5805SC1KP50V2KX-1GP

EC5805SC1KP50V2KX-1GP

12

EC5808

SC

100P

50V

2JN

-3G

P

DY

EC5808

SC

100P

50V

2JN

-3G

P

DY

1AFTP5803AFTP5803

1 2

L5801

BLM18BD601SN1D-GP

L5801

BLM18BD601SN1D-GP

1

2

3

4

SPK1

JST-CON2-33-GP

21.D0300.102

SPK1

JST-CON2-33-GP

21.D0300.102

1AFTP5804AFTP5804

12EC

5803

SC

D01U

16V

2K

X-3

GP

EC

5803

SC

D01U

16V

2K

X-3

GP

1AFTP5808AFTP5808

1 2R5803 0R0603-PADR5803 0R0603-PAD

1AFTP5806AFTP5806

1 2R5802 BLM18BD601SN1D-GPR5802 BLM18BD601SN1D-GP

1AFTP5805AFTP5805

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


A00

ReservedA3


<Core Design>

Nirvana 13

Title


Date: Sheet of


A00

ReservedA3


<Core Design>

Nirvana 13

Title


Date: Sheet of


A00

ReservedA3


<Core Design>

Nirvana 13

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RTC_PWR

+RTC_VCC

SPI_SOSPI_WP#

SPI_HOLD_0#

RTC_PWR

RTC_AUX_S5

3D3V_AUX_S5

+RTC_VCC

3D3V_S5

3D3V_S5

3D3V_S5

SPI_CLK_R (21,27)SPI_SO_R(21,27)

SPI_SI_R (21,27)

SPI_CS0#_R(21,27)

RTC_DET# (22)

Title


Date: Sheet of


Nirvana 13 A00

Flash/RTCA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Flash/RTCA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Flash/RTCA3


<Core Design>Width=20mils

SSID = RBATT

SSID = Flash.ROM

SPI FLASH ROM (4M byte) for PCH

72.25Q32.A01

72.25320.C01

72.25P32.C01

WINDBOND

MXIC

NUMONYX

W25Q32BVSSIG

MX25L3206EM2I-12G

M25PX32-VMW6F

Priority Wistron P/N Manufacturer Vendor P/N

1

2

3

Notes:

The total SPI interface signal between EC and PCH

can’t not exceed 6500mil. The mismatch between

SPI signal must be within 500mil

CS#1

DO2

WP#3

VSS4 DI 5CLK 6

HOLD# 7VCC 8

U6001

W25Q32BVSSIG-1-GP

2nd = 72.25320.C01

3rd = 72.25P32.C01

72.25Q32.A01

U6001

W25Q32BVSSIG-1-GP

2nd = 72.25320.C01

3rd = 72.25P32.C01

72.25Q32.A01

12

C6001

SC

10U

6D

3V

5K

X-1

GP

DY

C6001

SC

10U

6D

3V

5K

X-1

GP

DY

12

R600310MR2J-L-GPR600310MR2J-L-GP

G

S

D

Q6002

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

Q6002

2N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

12

EC6001

SC

4D

7P

50V

2C

N-1

GP

DY EC6001

SC

4D

7P

50V

2C

N-1

GP

DY

1 2R6001 33R2J-2-GPR6001 33R2J-2-GP

1 2 3 45678

RN6001

SRN4K7J-10-GP

RN6001

SRN4K7J-10-GP


12

C6003SC1U6D3V2KX-GP

C6003SC1U6D3V2KX-GP

PWR1

GND2

NP1NP1

NP2NP2

RTC1

BAT-060003HA002M213ZL-GP

62.70014.001

RTC1

BAT-060003HA002M213ZL-GP

62.70014.001

2

1

3

Q6001

CH715FPT-GP

2nd = 83.00040.E8183.R0304.B81

Q6001

CH715FPT-GP

2nd = 83.00040.E8183.R0304.B81

12

EC6002SC4D7P50V2CN-1GP

DYEC6002SC4D7P50V2CN-1GP

DY

12

C6002

SC

D1U

10V

2K

X-5

GP

C6002

SC

D1U

10V

2K

X-5

GP

1 2R60021KR2J-1-GPR60021KR2J-1-GP


12

EC6003

SC

4D

7P

50V

2C

N-1

GP

DYEC6003

SC

4D

7P

50V

2C

N-1

GP

DY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

5V_USB1_S35V_S5

USB_OC#0_1 (18)

USB_PWR_EN#(27)

Title


Date: Sheet of


Nirvana 13 A00

USB2.0 Power SW


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

USB2.0 Power SW


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

USB2.0 Power SW


<Core Design>

USB POWER SW

Main G547F2P81U-GP P/N:74.00547.A79at least 80 mil

at least 80 mil

SSID = USB

Support 2A

Close to ESATA Combo connector

12

C6103SC

D1U

10V

2K

X-5

GP

C6103SC

D1U

10V

2K

X-5

GP

12

TC6101ST100U6D3VAM-3-GP

80.10715.B1L2nd = 77.C1071.20L

TC6101ST100U6D3VAM-3-GP

80.10715.B1L2nd = 77.C1071.20L

12

C6102SC1U10V2KX-1GP

C6102SC1U10V2KX-1GP

12

C6101SC

D1U

10V

2K

X-5

GP

C6101SC

D1U

10V

2K

X-5

GP

GND1

IN#22

IN#33

EN/EN#4

OUT#8 8

OUT#7 7

OUT#6 6

OC# 5

U6101

G547F2P81U-GP

74.00547.A792nd = 74.00547.079

U6101

G547F2P81U-GP

74.00547.A792nd = 74.00547.079

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB3_PWR_ON

5V_S5

3D3V_S5

1V_USB30

1V_USB30_LDO_FB (82)

USB3_PWR_ON(27,82)

Title


Date: Sheet of


Nirvana 13 A00

USB 3.0 PortA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

USB 3.0 PortA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

USB 3.0 PortA3


<Core Design>

1V_USB30 LDO

0.6A Vo = 0.8 * ( 1 + ( RT / RB ) )

RT (R6202) RB (R6203)

2.37k ohm (64.23715.6DL) 7.5k ohm (64.75015.6DL)NEC

USB3.0 Host

TI 11.8k ohm (64.11825.6DL) 30.9k ohm (64.30925.6DL)

VOUT

1.1V

1.05V

RT

RB

20101227 A00:Change R6205 to 0R 0402 pad.20101228 A00:VGA_THRM change to USB_PWR_EN.20101229 A00:Remove R6205,R6201 and rename USB3_PWR_ON from USB_PWR_EN.

12

R6202

2K37R2F-GPDYR6202

2K37R2F-GPDY12

C6203SC1U10V2KX-1GP

C6203SC1U10V2KX-1GP

12

C6201

SC

10U

10V

5Z

Y-1

GP

C6201

SC

10U

10V

5Z

Y-1

GP

12

R6203

7K5R2F-1-GPDYR6203

7K5R2F-1-GPDYPOK1

VEN2

VIN3

VPP4

NC#5 5VO 6

ADJ 7GND 8GND 9

U6201

G9661-25ADJF11U-GP

74.09661.07D

2nd = 74.09025.03D

U6201

G9661-25ADJF11U-GP

74.09661.07D

2nd = 74.09025.03D

12

C6202

SC

10U

10V

5Z

Y-1

GP

C6202

SC

10U

10V

5Z

Y-1

GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BLUETOOTH_GPIO5

BDC_ON

BT_LED

BLUETOOTH_DET#

WLAN_ACT

BLUETOOTH_EN

BLUETOOTH_GPIO3

BT_ACT3D3V_S0

WLAN_ACTBLUETOOTH_EN

USB_PP3USB_PN3

USB_PP3

BT_ACT

USB_PN3

BT_ACT

WLAN_ACTBLUETOOTH_EN

WLAN_WWAN_LED#

BT_LED

3D3V_S0

USB_PP3(18)USB_PN3(18)

BLUETOOTH_EN(27,65)WLAN_ACT(65)

BT_ACT(65)

WLAN_WWAN_LED# (68)

Title


Date: Sheet of


Nirvana 13 A00

BluetoothA4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

BluetoothA4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

BluetoothA4


<Core Design>


Bluetooth Module

12

C6301

SC2D2U6D3V3KX-GPBT

C6301

SC2D2U6D3V3KX-GPBT1AFTP6307AFTP6307

12

EC6301

SC

220P

50V

2K

X-3

GP

DY

EC6301

SC

220P

50V

2K

X-3

GP

DY

15NP12

468101214NP216

1

3579

1113

BT1

ACES-CONN14D-GP

20.F1500.014

BT

BT1

ACES-CONN14D-GP

20.F1500.014

BT

1AFTP6308AFTP6308

12

R6301

100K

R2J-1

-GP

DY

R6301

100K

R2J-1

-GP

DY

1AFTP6301AFTP6301

1AFTP6302AFTP6302

1AFTP6311AFTP6311

1AFTP6309AFTP6309

1AFTP6313AFTP6313

1AFTP6304AFTP6304

1 2

R6303

0R2J-2-GP

DYR6303

0R2J-2-GP

DY

12

R630210K

R2J-3

-GPBT

R630210K

R2J-3

-GPBT

1 AFTP6306AFTP6306

1AFTP6312AFTP6312

1AFTP6310AFTP6310

1AFTP6305AFTP6305

G

S

D

Q6301

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

BT

Q6301

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

BT

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Biometric_USBPP

Biometric_USBPN

Biometric_USBPPBiometric_USBPN3D3V_S0

Biometric_USBPNBiometric_USBPP

3D3V_S0

USB_PP2(18)

USB_PN2(18)

Title


Date: Sheet of


Nirvana 13 A00

Finger Printer Conn

A4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Finger Printer Conn

A4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Finger Printer Conn

A4


<Core Design>

20101227 A00:

Change R6403,R6404 to 0R 0402 pad.

20100104 A00:

Remove TR6401.

1 2R6403

0R0402-PAD

R6403

0R0402-PAD

1AFTP40AFTP40

1AFTP43AFTP43

12


1 2R6404

0R0402-PAD

R6404

0R0402-PAD

1AFTP44AFTP44

1

23456

7

8

FP1

ACES-CON6-7GP

20.K0256.006

FP1

ACES-CON6-7GP

20.K0256.006

1AFTP42AFTP42

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LPC_FRAME#_C

USB_P11-USB_P11+

LPC_AD3_CLPC_AD2_CLPC_AD1_C

WPAN_LED#

LPC_AD0_C

E51_RXD_RE51_TXD_R

WLAN_ACT

WPAN_LED#_R

+5V_MINI_DEBUG

USB_P11-

USB_P11+

3D3V_S0

5V_S5

1D5V_S03D3V_S0

3D3V_S0 1D5V_S0

5V_S5

CLK_PCI_LPC(18,71)

WPAN_LED#(68)


PCIE_RXP4 (20)PCIE_RXN4 (20)

LPC_FRAME#(21,27,71)LPC_AD3(21,27,71)

WLAN_ACT(63)

LPC_AD2(21,27,71)LPC_AD1(21,27,71)

WIFI_RF_EN(27)

BT_ACT(63)

CLK_PCIE_WLAN# (20)CLK_PCIE_WLAN (20)

PCIE_TXN4 (20)PCIE_TXP4 (20)

PLT_RST# (5,18,27,71,82)

LPC_AD0(21,27,71)

E51_RXD(27)E51_TXD(27)

CLK_PCIE_WLAN_REQ# (20)

BLUETOOTH_EN(27,63)

WLAN_LED#(68)

USB_PN11 (18)

USB_PP11 (18)

Title


Date: Sheet of


Nirvana 13 A00

MINICARD(WLAN)/ITP CONNA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

SSID = Wireless

Mini Card Connector(802.11a/b/g/n)

20101227 A00:Change R6511 to 0R 0402 pad.

20101230 A00:Change R4606,R4605 to 0R short pad.20100104 A00:Remove TR6501.

20101227 A00:Change R6510 to 0R 0603 pad.

1 2R6508 0R2J-2-GPDYR6508 0R2J-2-GPDY

3.3V2

1.5V6

+3.3VAUX24

+1.5V28

+1.5V48

+3.3V52

GND 4

GND 9

GND 15

GND 18

GND 21

GND 26

GND 27

GND 29

GND 34

GND 35

GND 40

GND 50

GND 53

GND 54

RESERVED#33

RESERVED#55

RESERVED#88

RESERVED#1010

RESERVED#1212

RESERVED#1414

RESERVED#1616

RESERVED#1717

RESERVED#1919

RESERVED#2020

RESERVED#3737

RESERVED#3939

RESERVED#4141

RESERVED#4343

RESERVED#4545

RESERVED#4747

RESERVED#4949

RESERVED#5151

REFCLK+ 13

REFCLK- 11

PERN0 23

PERP0 25

PETN0 31

PETP0 33

USB_D- 36

USB_D+ 38

WAKE# 1

CLKREQ# 7

PERST# 22

SMB_CLK 30

SMB_DATA 32

LED_WWAN#42

LED_WLAN#44

LED_WPAN#46

NP

1N

P1

NP

2N

P2

WLAN1

SKT-MINI52P-42-GP-U1

62.10043.831

WLAN1

SKT-MINI52P-42-GP-U1

62.10043.831

1 2R6503 0R3J-0-U-GPDYR6503 0R3J-0-U-GPDY

1 2R6505 0R2J-2-GPDYR6505 0R2J-2-GPDY

1 2R6509 0R2J-2-GPDYR6509 0R2J-2-GPDY

1 2R6406

0R0402-PAD

R6406

0R0402-PAD

12

C6501

SC

D1U

16V

2K

X-3

GP

C6501

SC

D1U

16V

2K

X-3

GP

12

C6508

SC

220P

50V

2K

X-3

GPDY C6508

SC

220P

50V

2K

X-3

GPDY

12

C6503

SC

10U

6D

3V

5K

X-1

GP

C6503

SC

10U

6D

3V

5K

X-1

GP

1 2R6502

0R2J-2-GPDY R65020R2J-2-GPDY

1 2R6507 0R2J-2-GPDYR6507 0R2J-2-GPDY1 2R6506 0R2J-2-GPDYR6506 0R2J-2-GPDY

1 2R6511 0R0402-PADR6511 0R0402-PAD

1 2R6510 0R0603-PADR6510 0R0603-PAD

12

C6502

SC

D1U

16V

2K

X-3

GP

C6502

SC

D1U

16V

2K

X-3

GP

1 2

R65010R2J-2-GPDY R65010R2J-2-GPDY

12

C6504

SC

D1U

16V

2K

X-3

GP

C6504

SC

D1U

16V

2K

X-3

GP

12

C6507

SC

D1U

16V

2K

X-3

GP

C6507

SC

D1U

16V

2K

X-3

GP

12

C6506

SC

D1U

16V

2K

X-3

GP

C6506

SC

D1U

16V

2K

X-3

GP

12

C6505

SC

10U

6D

3V

5K

X-1

GP

C6505

SC

10U

6D

3V

5K

X-1

GP

1 2R6405

0R0402-PAD

R6405

0R0402-PAD

1 2R6504 0R2J-2-GPDYR6504 0R2J-2-GPDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA4


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

WLAN_LEDLED_WLAN_OUT_R#WLAN_WWAN_LED#

WLAN_WWAN_LED#

SATA_LEDBAT_WHITEBAT_AMBER

PWR_LED_B

LED_WLAN_OUT_B

POWER_SW_LED_B

SATA_LED#_CSATA_LED

PWRLED#_C

SATA_LED_R

WHITE_LED_BAT#

WHITE_LED_BAT#

SATA_LED#_C

WHITE_LED_BAT

PWR_LED_BLED_PWRPWRLED#_C

BAT_WHITE

BAT_AMBERAMBER_LED_BATAMBER_LED_BAT#

AMBER_LED_BAT#

Q6804_BTP_LOCK_LED_R TP_LOCK_LED_A

POWER_SW_LED_B

KBC_PWRBTN#_C

PWR_LED_BSATA_LEDBAT_WHITEBAT_AMBERLED_WLAN_OUT_B

KBC_PWRBTN#_CPOWER_SW_LED_B

LED_WLAN_OUT_B

5V_S0

3D3V_S0

5V_S0

5V_AUX_S5

5V_AUX_S5

5V_S5

5V_S0

WLAN_LED#(65)

WWAN_LED#(82)

WPAN_LED#(65)

WLAN_WWAN_LED#(63)

PWRLED#(27)

SATA_LED#(21)

BATT_WHITE_LED#(27)CHG_AMBER_LED#(27)

KBC_PWRBTN#(27)

TP_LOCK_LED#(27)

Title


Date: Sheet of



Nirvana 13 A00

LED Bord/Power ButtonA2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00



<Core Design>

Title


Date: Sheet of



Nirvana 13 A00



<Core Design>

LED BD Connector

WLAN LED (White)

SATA HDD LED(White)

Battery LED2(Amber)

Battery LED1(White)

Power button LED(White)

SSID = User.InterfacePower LED(White)

TPLOCK LED

Need change to LOW actived from KBC GPIO

20101224 A00:

Rename PWRBTN1 to PWRBT1.

20110103 A00:

Change R6801 to 1k.

20110103 A00:

Change R6804,R6806,R6808,R6810 to 620 ohm 5%.

20100106 A00:

Change R6804,R6806,R6808,R6810 to 1k ohm 5%.

12

EC

68

07

SC

D1

U1

0V

2K

X-5

GP

EC

68

07

SC

D1

U1

0V

2K

X-5

GP

1 2R6803 100R2J-2-GPR6803 100R2J-2-GP

1 2R68061KR2J-1-GPR68061KR2J-1-GP

EB

C

R1

R2

Q6804

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

R1

R2

Q6804

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

12 E

C6

80

4S

C2

20

P5

0V

2K

X-3

GP

DY

EC

68

04

SC

22

0P

50

V2

KX

-3G

P

DY

12 E

C6

60

4S

C2

20

P5

0V

2K

X-3

GP

DY

EC

66

04

SC

22

0P

50

V2

KX

-3G

P

DY

1 2R68101KR2J-1-GPR68101KR2J-1-GP

A KLED1

LED-Y-57-GP

83.01921.P70

LED1

LED-Y-57-GP

83.01921.P70

1AFTP6805AFTP6805

1AFTP6806AFTP6806

1

2

3

D6801

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

D6801

BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

1

234

5

6

PWRBT1

ACES-CON4-10-GP-U

20.K0320.004

PWRBT1

ACES-CON4-10-GP-U

20.K0320.004

1AFTP6804AFTP6804

1

2

3

U6801

BAT54A-5-GP

83.BAT54.U81

U6801

BAT54A-5-GP

83.BAT54.U81

EB

C

R1

R2

Q6802

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

R1

R2

Q6802

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

1AFTP6803AFTP68031AFTP6802AFTP6802

12

EC6803SC220P50V2KX-3GPDY EC6803SC220P50V2KX-3GPDY

EB

C

R1

R2

Q6805

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

R1

R2

Q6805

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

12

EC6801

SC220P50V2KX-3GPDYEC6801

SC220P50V2KX-3GPDY

1 2

R6802

15KR2J-1-GP

R6802

15KR2J-1-GP

1 2R68041KR2J-1-GPR68041KR2J-1-GP

1 2R6809 390R2J-1-GPR6809 390R2J-1-GP

EB

C

R1

R2

Q6801

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

R1

R2

Q6801

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

1234 5

678

RN6801

SRN15KJ-2-GP

RN6801

SRN15KJ-2-GP

1 2R68081KR2J-1-GPR68081KR2J-1-GP 1AFTP6807AFTP6807

EB

C

R1

R2

Q6803

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

R1

R2

Q6803

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

12

EC6802SC220P50V2KX-3GPDY EC6802SC220P50V2KX-3GPDY

1 2R680715KR2J-1-GP

R680715KR2J-1-GP

1

23456

7

8

LEDBD1

ACES-CON6-13-GP

20.K0320.006

LEDBD1

ACES-CON6-13-GP

20.K0320.006

1 2

R6813

390R2J-1-GP

R6813

390R2J-1-GP

EB

C

R1

R2

Q6812

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

R1

R2

Q6812

PDTA143ET-GP

84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

1AFTP6801AFTP6801

1 2R68011KR2J-1-GP

R68011KR2J-1-GP

12

EC

68

06

SC

D1

U1

0V

2K

X-5

GP

EC

68

06

SC

D1

U1

0V

2K

X-5

GP

12 E

C6

80

5S

C2

20

P5

0V

2K

X-3

GP

DY

EC

68

05

SC

22

0P

50

V2

KX

-3G

P

DY

12

R6805

100KR2J-1-GPDYR6805

100KR2J-1-GPDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

KCOL13

KCOL4

KROW7

KCOL10

KCOL3

KROW5

KCOL12

KCOL5

KCOL11

KCOL8

KROW2

KCOL0

KROW0

KCOL9

KCOL6

KROW4

KCOL2

KROW3

KCOL15

KCOL14

KCOL7

KROW6CAP_LED_RCAP_LED_Q

CAP_LED_1

KCOL1

KROW1

KCOL16

TPDATA

5V_S0TPCLK

KB

_B

L_C

TR

L#

+5V_KB_BL

KB_BL_CTRL#

KB_LED_DET_C

KB_LED_BL_DET

CAP_LED_R

CAP_LED_R5V_S5

5V_S0

5V_S0

+5V_KB_BL5V_S0

CAP_LED_R

KROW[0..7] (27)

KCOL[0..16] (27)

KB_DET# (21)CAP_LED(27)

TPCLK(27)TPDATA(27)

KB_LED_BL_DET(18)

KB_BL_CTRL(27)

Title


Date: Sheet of


Nirvana 13 A00

Key Board/Touch Pad/Media BoardA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

TouchPad LOCKED

Internal KeyBoard Connector CAP LED CONTROLSSID = KBC

TouchPad Connector

KB Backlight Connector

CAP_LED:(X01 Low actived)

Connect to KB driving internal LED directly.(MAX 25mA)

20101227 A00:Change R6902 to 0R 0402 pad.

20110103 A00:Change R6906 to 620 ohm 5%.20110106 A00:Change R6906 to 1k ohm 5%.

1AFTP6925AFTP6925

1AFTP6915AFTP6915

EB

C

R1

R2

Q6902

PDTA143ET-GP84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

R1

R2

Q6902

PDTA143ET-GP84.00143.M112nd = 84.02143.0113rd = 84.00143.N11

1

23456789101112131415161718192021222324252627282930

31

32

KB1

JAE-CON30-7-GP

20.K0565.030

KB1

JAE-CON30-7-GP

20.K0565.030

1AFTP6918AFTP6918

1AFTP6912AFTP6912

1AFTP6921AFTP6921

1AFTP76AFTP76

12

C6902SC33P50V2JN-3GP

DYC6902SC33P50V2JN-3GP

DY1

234

5

6

TPAD1

PTWO-CON4-9-GP-U1

20.K0382.004

TPAD1

PTWO-CON4-9-GP-U1

20.K0382.004

1AFTP74AFTP74

1 2

R6905

15KR2J-1-GP

R6905

15KR2J-1-GP

12


1AFTP6927AFTP6927

1 2R69061KR2J-1-GP

R69061KR2J-1-GP

1AFTP77AFTP77

12


1AFTP75AFTP75

1AFTP6923AFTP6923

1AFTP6933AFTP6933

1 AFTP72AFTP72

1AFTP6926AFTP6926

1AFTP6916AFTP6916

1

2346

5KBLIT1

ACES-CON4-34-GP

20.K0589.0042nd = 20.K0613.004

KBLIT1

ACES-CON4-34-GP

20.K0589.0042nd = 20.K0613.004

1AFTP6919AFTP6919

1AFTP79AFTP79

1AFTP6922AFTP6922

1AFTP6936AFTP6936

1AFTP6911AFTP6911

12

R6901100KR2J-1-GPR6901100KR2J-1-GP

1AFTP71AFTP71

1AFTP6914AFTP6914

1 AFTP6901AFTP6901

1AFTP6928AFTP6928

1AFTP6931AFTP6931

12

C6903SC33P50V2JN-3GP

DY C6903SC33P50V2JN-3GP

DY

1 2R6907 100R2J-2-GPDYR6907 100R2J-2-GPDY

1AFTP6924AFTP6924

1AFTP6934AFTP6934

12

R6903

100K

R2J-1

-GP

R6903

100K

R2J-1

-GP

123 4

RN6901SRN10KJ-5-GP

RN6901SRN10KJ-5-GP

1AFTP78AFTP78

1AFTP6917AFTP6917

1AFTP6920AFTP6920

1 2

R6904

51KR2J-1-GP

R6904

51KR2J-1-GP

1AFTP6930AFTP6930

G

DS

Q6901P8503BMG-GP

84.P8503.0312nd = 84.03404.C31

Q6901P8503BMG-GP

84.P8503.0312nd = 84.03404.C31

1AFTP73AFTP73

1 2

R6902

0R0402-PAD

R6902

0R0402-PAD

1AFTP6935AFTP6935

12

C6906SC

D1U

10V

2K

X-5

GP

C6906SC

D1U

10V

2K

X-5

GP

1AFTP6929AFTP6929

1AFTP6913AFTP6913

1AFTP6932AFTP6932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LID_CLOSE#_1

3D3V_S5LID_CLOSE#_1

LID_CLOSE#

3D3V_S5

3D3V_S5

LID_CLOSE#(27)

Title


Date: Sheet of


Nirvana 13 A00

Hall SensorA4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Hall SensorA4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Hall SensorA4


<Core Design>

20101224 A00:

Rename HALLSW1 to LID1.

20101227 A00:

Change R7002 to 0R 0402 pad.


12

C7001SCD047U16V2KX-1-GPDY C7001SCD047U16V2KX-1-GPDY

12



1AFTP82AFTE14P-GP

AFTP82AFTE14P-GP


1 2

R7002

0R0402-PAD

R7002

0R0402-PAD

12

R7001100KR2J-1-GPDY R7001100KR2J-1-GPDY

VCC1

VOUT2

GND3

LID1

TCS20DPR-GP

74.TCS20.03B

74.09132.A7B

LID1

TCS20DPR-GP

74.TCS20.03B

74.09132.A7B

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3D3V_S0

PLT_RST#(5,18,27,65,82)

LPC_AD1(21,27,65)LPC_AD0(21,27,65)

LPC_FRAME#(21,27,65)

CLK_PCI_LPC(18,65)

LPC_AD3(21,27,65)LPC_AD2(21,27,65)

Title


Date: Sheet of


Nirvana 13 A00

Dubug CONN

A4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Dubug CONN

A4


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Dubug CONN

A4


<Core Design>

20101229 A00 Modify:

DB1 change to ZZ.00PAD.Y41(solder mask type)

and keep un-stuff at X-Build stage.

111

23456789

1012

DB1

PAD-10P-177042-GP

DY

ZZ.00PAD.Y41PCB Footprint = PAD-10P-177042

DB1

PAD-10P-177042-GP

DY

ZZ.00PAD.Y41PCB Footprint = PAD-10P-177042

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SP

9_1

SP

10_1

XD

_D

7_1

SP2SP4SP9SP12 SP5SP14 SP6 SP1SP13 SP7SP10XD_D7 SP8SP11XD_CD#

SP

7_1

SP

8_1

SP

3_1

SP

4_1

SP

1_1

SP

2_1

SP3

XD

_C

D#_1

SP

5_1

SP

6_1

SP

13_1

SP

14_1

SP

11_1

SP

12_1

3D3V_CARD_S0

3D3V_CARD_S0

SP10(32)

SP7(32)

SP12(32)

SP2 (32)

SP1(32)

SP3 (32)SP4 (32)SP5 (32)SP6 (32)

SP5(32)

SP7 (32)

SP14(32)

SP12(32)

SP3(32)

SP8(32)

SP9(32)

SP8 (32)

SP1(32)

SP6(32)SP8(32)

XD_CD# (32)

SP9(32)

SP5(32)

SP9 (32)

SP11(32)

SP10 (32)SP11 (32)SP12 (32)

SP13(32)

SP13 (32)SP14 (32)

SP1 (32)

XD_D7 (32)

SP4(32)

SP2(32)

Title


Date: Sheet of


Nirvana 13 A00

CARD Reader CONNA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CARD Reader CONNA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

CARD Reader CONNA3


<Core Design>

For EMI Reserved

SSID = SDIO

Close to CARD1

SD/XD/MS/MMC+ Card Reader1

2 EC

7402

SC

220P

50V

2K

X-3

GP

DY

EC

7402

SC

220P

50V

2K

X-3

GP

DY

12

R7409

47R

2J-2

-GP

DY R7409

47R

2J-2

-GP

DY

12 EC

7407

SC

220P

50V

2K

X-3

GP

DY

EC

7407

SC

220P

50V

2K

X-3

GP

DY

12

R7414

47R

2J-2

-GP

DY R7414

47R

2J-2

-GP

DY

12 EC

7411

SC

220P

50V

2K

X-3

GP

DY

EC

7411

SC

220P

50V

2K

X-3

GP

DY

12

R7404

47R

2J-2

-GP

DY R7404

47R

2J-2

-GP

DY

12 EC

7416

SC

220P

50V

2K

X-3

GP

DYE

C7416

SC

220P

50V

2K

X-3

GP

DY

12 EC

7412

SC

220P

50V

2K

X-3

GP

DY

EC

7412

SC

220P

50V

2K

X-3

GP

DY

12

R7407

47R

2J-2

-GP

DY R7407

47R

2J-2

-GP

DY

12

R7406

47R

2J-2

-GP

DY R7406

47R

2J-2

-GP

DY

12 EC

7409

SC

220P

50V

2K

X-3

GP

DY

EC

7409

SC

220P

50V

2K

X-3

GP

DY

12

R7403

47R

2J-2

-GP

DY R7403

47R

2J-2

-GP

DY

12 EC

7410

SC

220P

50V

2K

X-3

GP

DY

EC

7410

SC

220P

50V

2K

X-3

GP

DY

12

C7401

SC

D1U

10V

2K

X-5

GP

DY C7401

SC

D1U

10V

2K

X-5

GP

DY

12

C7405

SC

10U

6D

3V

5M

X-3

GP

C7405

SC

10U

6D

3V

5M

X-3

GP

SD_CDP1

SD_WPP2

SD_DAT1P3

MMC_DATA7P5

MS_GND P6

SD_GND P7

MMC_DATA6P8

MS_BSP9

SD_CLKP10

MS_DATA1P11

SD_VCCP13

MS_DATA2P14

SD_GND P15

MS_INSP16

MMC_DATA5P17

MS_DATA3P18

SD_CMDP19

MS_SCLKP20

MMC_DATA4P21

MS_VCCP22

SD_DATA3P23

MS_GND P24

SD_DAT2P25

SD_WP_COM/SDIO_GND P26

SD_CD_COM/SDIO_GND P27

XD_CD 1

XD_R/B 2

XD_RE 3

XD_CE 4

XD_CLE 5

XD_ALE 6

XD_WE 7

XD_WP_IN 8

XD_GND 9

XD_D0 10

XD_D1 11

XD_D2 12

XD_D3 13

XD_D4 14

XD_D5 15

XD_D6 16

XD_D7 17

XD_VCC18

XD_GND 19

SD_DAT0P4

MS_DATA0P12

NP1 NP1

NP2 NP2

CARD1

CARD-PUSH-46P-1-GP-U

20.I0129.001

2nd = 20.I0135.001

CARD1

CARD-PUSH-46P-1-GP-U

20.I0129.001

2nd = 20.I0135.0011

2

R7412

47R

2J-2

-GP

DY R7412

47R

2J-2

-GP

DY

12 EC

7415

SC

220P

50V

2K

X-3

GP

DY

EC

7415

SC

220P

50V

2K

X-3

GP

DY

12

R7405

47R

2J-2

-GP

DY R7405

47R

2J-2

-GP

DY

12 EC

7405

SC

220P

50V

2K

X-3

GP

DY

EC

7405

SC

220P

50V

2K

X-3

GP

DY

12 EC

7404

SC

220P

50V

2K

X-3

GP

DY

EC

7404

SC

220P

50V

2K

X-3

GP

DY

12

R7402

47R

2J-2

-GP

DY R7402

47R

2J-2

-GP

DY

12

R7411

47R

2J-2

-GP

DY R7411

47R

2J-2

-GP

DY

12

R7416

47R

2J-2

-GP

DY R7416

47R

2J-2

-GP

DY

12

R7417

47R

2J-2

-GP

DY R7417

47R

2J-2

-GP

DY

12 EC

7406

SC

220P

50V

2K

X-3

GP

DY

EC

7406

SC

220P

50V

2K

X-3

GP

DY

12 EC

7413

SC

220P

50V

2K

X-3

GP

DY

EC

7413

SC

220P

50V

2K

X-3

GP

DY

12

C7404

SC

2D

2U

6D

3V

3K

X-G

PC

7404

SC

2D

2U

6D

3V

3K

X-G

P

12 EC

7408

SC

220P

50V

2K

X-3

GP

DY

EC

7408

SC

220P

50V

2K

X-3

GP

DY

12

R7408

47R

2J-2

-GP

DY R7408

47R

2J-2

-GP

DY

12 EC

7417

SC

220P

50V

2K

X-3

GP

DY

EC

7417

SC

220P

50V

2K

X-3

GP

DY

12 EC

7414

SC

220P

50V

2K

X-3

GP

DY

EC

7414

SC

220P

50V

2K

X-3

GP

DY

12

C7402

SC

D1U

10V

2K

X-5

GP

DY C7402

SC

D1U

10V

2K

X-5

GP

DY

12

R7415

47R

2J-2

-GP

DY R7415

47R

2J-2

-GP

DY

12

R7410

47R

2J-2

-GP

DY R7410

47R

2J-2

-GP

DY

12

C7403

SC

D01U

16V

2K

X-3

GP

C7403

SC

D01U

16V

2K

X-3

GP

12

R7413

47R

2J-2

-GP

DY R7413

47R

2J-2

-GP

DY

12 EC

7403

SC

220P

50V

2K

X-3

GP

DY

EC

7403

SC

220P

50V

2K

X-3

GP

DY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FFS_INT2_R

FALL_INT2

HDD_FALL_SDO

HDD_FALL_INT1PCH_SMBCLK

PCH_SMBDATA

5V_S03D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

FFS_INT2 (56)

FFS_INT2_R (18)

PCH_SMBDATA(14,15,20,65,82)

HDD_FALL_INT1 (18)

PCH_SMBCLK(14,15,20,65,82)

Title


Date: Sheet of


Nirvana 13 A00

Free Fall SensorA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Free Fall SensorA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Free Fall SensorA3


<Core Design>

Note

(1) Keep all signals are the same trace width. (included VDD, GND).

(2) No VIA under IC bottom.


Free Fall SensorNote

- no via, trace, under the sensor (keep out area around 2mm)

- stay away from the screw hole or metal shield soldering joints

- design PCB pad based on our sensor LGA pad size (add 0.1mm)

- solder stencil opening to 90% of the PCB pad size

- mount the sensor near the center of mass of the NB as possible as you can

09/0422

(#1) Just pull +3.3V_RUN ~ Ref. Rothschild

(#2) FAE/ DY is ok, chip internal pull-up resistors

(#3) From spec, Slave ADdress(SAD) is 001110xb

Pull HIGH SAD is 0011101b

Pull GND SAD is 0011100b

For ADI G-sensor : R7901 is required.

For ST G-sensor : R7901 need DY1 2

R7901

100KR2J-1-GP

GSENSOR_ADIR7901

100KR2J-1-GP

GSENSOR_ADI

12

R790610KR2J-3-GP

DYR790610KR2J-3-GP

DY

12


12

R7903100KR2J-1-GPR7903100KR2J-1-GP

SCL/SPC14

SDA/SDI/SDO13

SDO12

CS7

RESERVED#33

VD

D6

VD

D_IO

1

INT1 8

INT2 9

GND 2

GND 4

GND 5

GND 10RESERVED#1111

U7901

DE351DLTR8-GP

2nd = 74.00345.0BZ

74.00351.0B3

U7901

DE351DLTR8-GP

2nd = 74.00345.0BZ

74.00351.0B3

1234 5 6

Q7901

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

Q7901

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

12


12

C7902

SCD1U10V2KX-4GP

C7902

SCD1U10V2KX-4GP

12

C7901SC10U6D3V5MX-3GP DY

C7901SC10U6D3V5MX-3GP DY

1 2 R79050R2J-2-GPDY R79050R2J-2-GPDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MEDIA_LED2#

MEDIA1_2MEDIA1_3

MEDIA1_1

MEDIA_LED1#

MEDIA_LED3#

MEDIA1_2MEDIA1_1

MEDIA_BTN3#DATA_RECOVERY#INSTANT_ON#MEDIA1_3

MEDIA1_2MEDIA1_1

MEDIA1_35V_S5

DATA_RECOVERY#INSTANT_ON#

MEDIA_BTN3#

USB3_PWR_ON

5V_S5

5V_S5

1V_USB30

5V_S5

1D5V_S0

3D3V_S0

3D3V_S5

+DC_IN

5V_S5 5V_S5

PCIE_CLK_LAN_REQ#(20)

DATA_RECOVERY# (27)

MEDIA_LED1# (27)

MEDIA_LED2# (27)MEDIA_LED3# (27)INSTANT_ON# (27)

MEDIA_BTN3# (27)

WWAN_LED#(68)

CLK_PCIE_LAN# (20)CLK_PCIE_LAN (20)

CLK_PCIE_WWAN# (20)CLK_PCIE_WWAN (20)

PCH_SMBCLK(14,15,20,65,79)PCH_SMBDATA(14,15,20,65,79)

USB30_SMI#(18)

PLT_RST# (5,18,27,65,71)PM_LAN_ENABLE (27)

PCIE_WAKE# (27)

PCIE_TXP2(20)

3G_EN(22)CLK_PCIE_WWAN_REQ#(20)

PCIE_TXN2(20)


PCIE_TXN3(20)


USB_PP4(18)USB_PN4(18)

PCIE_TXP3(20)

CLK_PCIE_USB3#(20)CLK_PCIE_USB3(20)

PCIE_RXN5 (20)PCIE_RXP5 (20)

PCIE_TXN5 (20)PCIE_TXP5 (20)

USB3_PEGB_CLKREQ# (20)

PS_ID_R(38)

1V_USB30_LDO_FB(62)

USB3_PWR_ON(27,62)

Title


Date: Sheet of


Nirvana 13 A00

IO Board ConnectorA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Media Button Board Connector

Low active

IO Board CONN 80 pin

1D05V_VTT FOR USB3.0 POWER at least ?A

1D5V_S0 FOR USB3.0 POWER at least ?A

USB3.0 PCIE

USB3.0 PCIE

at least 160 mil

LAN CLK

WWAN CLK

WWAN SMBUS

LAN PCIE

LAN PCIE

WWAN PCIE

WWAN PCIE

USB3.0 CLK

WWAN USB

3D3V_S5 FOR LAN POWER at least over 3pin amount.

5V_USB FOR USB3.0 POWER at least 4A

20101224 A00:Change R8210 to 0402 0 ohm pad.20101228 A00:VGA_THRM change to USB_PWR_EN.20101229 A00:Remove R2809 and R8210. Connect USB3_PWR_ON from KBC to IOBD1.61.

20110103 A00:Change R8201~R8203 to 1k.20110104 A00:Merge R8201~R8203 to RN8201 1k array resistor.20110113 A00:Swap RN8201 base on swap report.

1AFTP8204AFTP8204

1AFTP8205AFTP8205

12

EC

8201

SC

D1U

10V

2K

X-5

GP

EC

8201

SC

D1U

10V

2K

X-5

GP

12

EC

8207

SC

D1U

10V

2K

X-5

GP

EC

8207

SC

D1U

10V

2K

X-5

GP

1

2345678910111213141516171819202122232425262728293031323334353637383940

80

797877767574737271706968676665646362616059585756555453525150494847464544434241

NP1

NP2NP3

NP4

IOBD1

ACES-CONN80C-GP-U

20.F1432.080

IOBD1

ACES-CONN80C-GP-U

20.F1432.080

1234 5

678

RN8201

SRN1KJ-4-GP

RN8201

SRN1KJ-4-GP

12

EC

8204

SC

D1U

10V

2K

X-5

GP

EC

8204

SC

D1U

10V

2K

X-5

GP

12345

678

RN8209

SRN10KJ-6-GP

DY

RN8209

SRN10KJ-6-GP

DY

1AFTP8203AFTP8203

12

EC

8206

SC

D1U

10V

2K

X-5

GP

EC

8206

SC

D1U

10V

2K

X-5

GP

1AFTP8206AFTP8206

1

2345678

9

10

MEDIA1

ACES-CON8-19-GP

20.K0320.008

MEDIA1

ACES-CON8-19-GP

20.K0320.0081AFTP8207AFTP8207

12

EC

8208

SC

D1U

10V

2K

X-5

GP

EC

8208

SC

D1U

10V

2K

X-5

GP

1AFTP8201AFTP8201

12

EC

8203

SC

D1U

10V

2K

X-5

GP

EC

8203

SC

D1U

10V

2K

X-5

GP

12

EC

8202

SC

D1U

10V

2K

X-5

GP

EC

8202

SC

D1U

10V

2K

X-5

GP

1AFTP8202AFTP8202

12

EC

8205

SC

D1U

10V

2K

X-5

GP

EC

8205

SC

D1U

10V

2K

X-5

GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A388 103Wednesday, December 22, 2010

<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Reverved

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reverved

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reverved

A3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved

A3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Reserved


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Reserved


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

ReservedA3


<Core Design>

(Blanking)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK_PCH_48M


AU

D_D

MIC

_IN

01

AUD_DMIC_IN0

AU

D_D

MIC

_C

LK

1

AUD_DMIC_CLK

5V_S5

5V_S5 5V_S0

1D5V_S3 5V_S5

1D05V_VTT

5V_S0 3D3V_S0

5V_S0

5V_S5 DCBATOUT

5V_S0 3D3V_S0

3D3V_S0 5V_S0

3D3V_S01D05V_VTT

5V_S5 +DC_IN

1D05V_VTT 3D3V_S0

1D05V_VTT

3D3V_S0 5V_S5

3D3V_S0 5V_S0

5V_S05V_S5

1D05V_VTT 3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S0

1D05V_VTT

5V_S0

5V_S0 3D3V_S0

CLK_PCH_48M(20,32)AUD_DMIC_CLK(29,49)AUD_DMIC_IN0(29,49)LVDS_DDC_DATA_R(17,49)LVDS_DDC_CLK_R(17,49)

Title


Date: Sheet of


Nirvana 13 A00

UNUSED PARTS/EMI CapacitorsA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

RF RequestEMI Request

12EC

9721

SC

D1U

10V

2K

X-5

GP

DY

EC

9721

SC

D1U

10V

2K

X-5

GP

DY

12EC

9735

SC

D1U

10V

2K

X-5

GP

DY

EC

9735

SC

D1U

10V

2K

X-5

GP

DY

1

H5HOLE256R115-GP

ZZ.00PAD.D11

H5HOLE256R115-GP

ZZ.00PAD.D11

1

H8HOLE256R115-GPH8HOLE256R115-GP

12EC

9728

SC

D1U

10V

2K

X-5

GP

DY

EC

9728

SC

D1U

10V

2K

X-5

GP

DY

1

SPR6

SP

RIN

G-2

4-G

P-U DY

SPR6

SP

RIN

G-2

4-G

P-U DY

1

SPR7SPRING-57-GP

34.4

2T

14.0

02

DY

SPR7SPRING-57-GP

34.4

2T

14.0

02

DY

12EC

9737

SC

D1U

10V

2K

X-5

GP

DY

EC

9737

SC

D1U

10V

2K

X-5

GP

DY

12EC

9730

SC

D1U

10V

2K

X-5

GP

DY

EC

9730

SC

D1U

10V

2K

X-5

GP

DY

1

H16HT85B85X925R29-S-GPH16HT85B85X925R29-S-GP

1

H17HOLE276R158-GP

ZZ

.00P

AD

.U61

H17HOLE276R158-GP

ZZ

.00P

AD

.U61

1

SPR4SPRING-24-GP-U

34.45T31.001

DY

SPR4SPRING-24-GP-U

34.45T31.001

DY

12

EC9739 SCD1U10V2KX-5GP

DYEC9739 SCD1U10V2KX-5GP

DY

12



DY

12



DY

1

H11HOLE197R166-1-GP

ZZ.00PAD.V71

H11HOLE197R166-1-GP

ZZ.00PAD.V71

1

H7HOLE256R115-GP

ZZ.00PAD.D11

H7HOLE256R115-GP

ZZ.00PAD.D11

12EC

9732

SC

D1U

10V

2K

X-5

GP

DY

EC

9732

SC

D1U

10V

2K

X-5

GP

DY

12



DY

12EC

9719

SC

D1U

10V

2K

X-5

GP

DY

EC

9719

SC

D1U

10V

2K

X-5

GP

DY

1

SPR3

SP

RIN

G-2

4-G

P-U DY

SPR3

SP

RIN

G-2

4-G

P-U DY

1

H3 STF276R160H209-1-GP

34.4ID01.001

H3 STF276R160H209-1-GP

34.4ID01.0011

H13HOLE197R166-1-GP

ZZ.00PAD.V71

H13HOLE197R166-1-GP

ZZ.00PAD.V71

12

R9702

47R

2J-2

-GP

DYR9702

47R

2J-2

-GP

DY

12EC

9725

SC

D1U

10V

2K

X-5

GP

DY

EC

9725

SC

D1U

10V

2K

X-5

GP

DY

12EC

9720

SC

D1U

10V

2K

X-5

GP

DY

EC

9720

SC

D1U

10V

2K

X-5

GP

DY

12EC

9729

SC

D1U

10V

2K

X-5

GP

DY

EC

9729

SC

D1U

10V

2K

X-5

GP

DY

1

SPR1SPRING-51-GP

34.4F822.002DY

SPR1SPRING-51-GP

34.4F822.002DY

12EC

9731

SC

D1U

10V

2K

X-5

GP

DY

EC

9731

SC

D1U

10V

2K

X-5

GP

DY

12



DY

12



DY

1

H15HOLE335R115-GP

ZZ.00PAD.D01

H15HOLE335R115-GP

ZZ.00PAD.D01

1

H2HOLE335R115-GP

ZZ.00PAD.D01

H2HOLE335R115-GP

ZZ.00PAD.D01

12EC

9724

SC

D1U

10V

2K

X-5

GP

DY

EC

9724

SC

D1U

10V

2K

X-5

GP

DY

1

H14

HT85BE85R29-U-5-GP

ZZ.00PAD.D41

H14

HT85BE85R29-U-5-GP

ZZ.00PAD.D41

12



DY

12EC

9736

SC

D1U

10V

2K

X-5

GP

DY

EC

9736

SC

D1U

10V

2K

X-5

GP

DY

12



DY

12



DY

12



DY

1

H10HT85BE85R29-U-5-GPH10HT85BE85R29-U-5-GP

1

H1HT85B85X925R29-S-GPH1HT85B85X925R29-S-GP

12



DY

1

H6

HT85BE85R29-U-5-GP

ZZ.00PAD.D41

H6

HT85BE85R29-U-5-GP

ZZ.00PAD.D41

12EC

9726

SC

D1U

10V

2K

X-5

GP

DY

EC

9726

SC

D1U

10V

2K

X-5

GP

DY

12



DY

12



DY

12EC

9723

SC

D1U

10V

2K

X-5

GP

DY

EC

9723

SC

D1U

10V

2K

X-5

GP

DY

12



DY

1

H12HOLE197R166-1-GP

ZZ.00PAD.V71

H12HOLE197R166-1-GP

ZZ.00PAD.V71

12

R9701

47R

2J-2

-GP

DYR9701

47R

2J-2

-GP

DY

1

SPR8SPRING-51-GP

34.4F822.002

DY

SPR8SPRING-51-GP

34.4F822.002

DY

12EC

9722

SC

D1U

10V

2K

X-5

GP

DY

EC

9722

SC

D1U

10V

2K

X-5

GP

DY

1

SPR2

SP

RIN

G-2

4-G

P-U DY

SPR2

SP

RIN

G-2

4-G

P-U DY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of



Nirvana 13 A00

Power SequenceA1


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

Power SequenceA1


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00

Power SequenceA1


<Core Design>

8209A_EN/DEM_VGA(Discrete only)

Robson XT Power-Up/Down Sequence

DGPU_PWR_EN#(Discrete only)

PCH GPIO54 output

3D3V_VGA_S0(Discrete only)

3D3V_VGA_S0 above VT357 VIH

3D3V_S0

VGA_CORE(Discrete only)

1V_VGA_S0(Discrete only)

RT9035 PGOOD9035_PGOOD_1V(Discrete only)


Td <20ms

Tb

For power-down, reversing the ramp-up sequence is recommended.

>0ms

V5REF_Sus must be powered up before

VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power

down after VccSus3_3, or before

VccSus3_3 within 0.7 V.

>9ms

Sense the power button status

>5ms

PCH to KBC GPIO00PCH_SUSCLK_KBC

KBC GPIO43 to PCHPM_RSMRST#(EC Delay 40ms) T6

T8

T7

<90ms

KBC GPO84 to PCH>5ms

>10ms

AC_PRESENTNot floating. 0ms<

3D3V_AUX_KBC

>16ms

Platform to KBC PSL_IN2AC KBC_PWRBTN#

PM_PWRBTN#

T9This signal has an internal

pull-up resistor and has an

internal 16 ms de-bounce on the

input.

Sense the power button status

KBC GPIO20 to PCH

Press Power button

AC

T3

Enable by PM_SLP_S4#

KBC GPIO23 to LAN>30us

3D3V_AUX_KBC

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

T11

DCBATOUT

PM_PWRBTN#AC

T10

T12

PCH to KBC GPIO01

PCH to KBC GPIO44

S5_ENABLE

KBC GPIO43 to PCH

1D8V_S0

3D3V_S0

1D5V_S0

5V_S0

DDR_VREF_S3(0.75V)

1D5V_S3

+5V_RUN & +3.3V_RUN need meet 0.7V difference

+5VS_PCH_VCC5REF

(AC mode) (DC mode)

T13

V5REF must be powered up before

Vcc3_3, or after Vcc3_3 within 0.7 V.

Also, V5REF must power down after

Vcc3_3, or before Vcc3_3 within 0.7 V.

T17

T23

0D85V_S0

TPS51461RGER PGOODD85V_PWRGD

T24

CPU SVID BUS

0D85V_S0

VCC_CORE

VCC_GFXCORE

50us< <2000usT25

IMVP_PWRGD

T26ISL95831 PGOOD to system

<5ms

DMI

<200us

PCH to all system

T36PLT_RST#

PCH to CPU

<100msT35

H_CPUPWRGD

T28

1ms<

KBC GPIO77 to PCHPWROK

>0us

PCH to CPU

T321D8V_S0

T4

<650ms5ms<

EC_ENABLE#_1(GPIO31) keep low

This signal represents the Power

Good for all the non-CORE and

non-graphics power rails.

ALL_SYS_PWRGD=D85V_PWRGD>99msT27

T5

T29D85V_PWRGD

<650ms2ms<

T7

T16

PCH to KBC GPIO00PCH_SUSCLK_KBC

T8

>0msTa

Tc >0ms

Huron River Platform Power Sequence

S5_ENABLE

5V_S5


DGPU_PWROK(Discrete only)

VT357 PGOOD

3D3V_S5

T3

3D3V_AUX_S5

KBC GPIO34 control power on by 3V_5V_EN

KBC_PWRBTN#

PM_PWRBTN#

T15

T14

T9

KBC GPIO20 to PCH

T4

VT357FCX PGOOD

DCBATOUT

RTC_RST#

1D05V_VTT

T2

+RTC_VCC

T22

T21

T1

RUNPWROK

1.05VTT_PWRGD

T20

+RTC_VCC

RTC_RST#

T18

0D75V_S0

T1

T19

>10ms

+5V_ALW & +3.3V_ALW need meet 0.7V difference

>9ms

T5+5VA_PCH_VCC5REFSUS

CLK_EXP_P

+5V_ALW & +3.3V_ALW need meet 0.7V difference

T6

Within logic high level and disable if

it is less than the logic low level.

+5VA_PCH_VCC5REFSUS

V5REF_Sus must be powered up before

VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power

down after VccSus3_3, or before

VccSus3_3 within 0.7 V.

T30

PM_RSMRST#

Press Power button

T2

3D3V_AUX_S5

Platform to KBC PSL_IN2

red word: KBC GPIO

KBC GPIO34 control power on by 3V_5V_EN

PCH_RSMRST#DC

>16ms

SetVID ACK

VDDPWRGOOD

red word: KBC GPIO

SYS_PWROK

>1ms

>2msT31

>1ms+60usT34

T10

T33 >0ms

Enable by PM_SLP_S4#

PM_SLP_S4#

PM_SLP_S3#

KBC GPIO23 to LAN>30us

PM_LAN_ENABLE

T11

PCH to KBC GPIO44

PCH to KBC GPIO01

T12

DDR_VREF_S3(0.75V)

1D8V_S0

3D3V_S0

1D5V_S0

5V_S0

+5V_RUN & +3.3V_RUN need meet 0.7V difference

1D5V_S3

+5VS_PCH_VCC5REF

T17

T13

V5REF must be powered up before

Vcc3_3, or after Vcc3_3 within 0.7 V.

Also, V5REF must power down after

Vcc3_3, or before Vcc3_3 within 0.7 V.

0D85V_S0

T23

TPS51461RGER PGOODD85V_PWRGD

T24

CPU SVID BUS

0D85V_S0

VCC_CORE

50us< <2000usT25

VCC_GFXCORE

ISL95831 PGOOD to systemIMVP_PWRGD

<5ms

T26

DMI

<200us

PCH to all system

T36PLT_RST#

T35

H_CPUPWRGD

>0usT28

1ms<

PCH to CPU

<100ms

KBC GPIO77 to PCHPWROK

T321D8V_S0

PCH to CPU

T27

<650ms5ms<

D85V_PWRGD

This signal represents the Power

Good for all the non-CORE and

non-graphics power rails.

ALL_SYS_PWRGD=D85V_PWRGD>99ms

<650ms2ms< T29

T16

1D05V_VTT

1D8V_S0 & 1D5V_S3 power ready

VT357FCX PGOOD

T15

T14

T22

T21

T20RUNPWROK

1.05VTT_PWRGD

T19

T18

0D75V_S0

CLK_EXP_P

T30

ACKSetVID

VDDPWRGOOD

SYS_PWROK

>1ms

>2msT31

T33>1ms+60usT34

>0ms

1D8V_S0 & 1D5V_S3 power ready

3D3V_S5

5V_S5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


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Nirvana 13 A00

Power Up Sequence Diagram

A2


<Core Design>

Title


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Nirvana 13 A00


A2


<Core Design>

Title


Date: Sheet of



Nirvana 13 A00


A2


<Core Design>

OUTPUT

PGOOD1.05VTT_PWRGD

1D05_VTT

DRAMPWRGD

PROCPWRGD

7

Cougar Point

PCH

-4

GPIO70AC_IN#

9

PLT_RST#

Page46

Page47

Page45

Page48

Page42 & 43 & 44

12

2

SYS_PWROK

10

0D75V_ENVDDPWRGOOD

H_CPUPWRGD_R

3V_5V_EN

3D3V_AUX_KBC

S0_PWR_GOOD

IMVP_PWRGD

-3-3.1

-3.1 -3.1 -3.1

BJT

BUF_CPU_RST#

SVID

SVID 8

RSTIN#

SM_DRAMPWROK

UNCOREPWRGOOD

Sandy Bridge

CPU

AND GATE

A

BY

DCBATOUT5V_S5

8

11

IMVP_PWRGD

H_CPUPWRGD

SWITCH

Adapter in

PWR_CHG_ACOK

AD+

DCBATOUT

+RTC_VCC

Page40

VIN

ENC

Page41

DC/DC

RTC battery

-8

APWROK

SYS_PWROK

PWROK

TPS51218DSCR

VOUT

PWRBTN#

RSMRST#

VR_ON

SVID

3D3V_AUX_S5

RTC_AUX_S5

-7

3

DC

Battery

Page39

BT+

PLTRST#

PM_RSMRST#

PM_PWRBTN#

-6

-5

ACOK

5V_AUX_S5

3D3V_S0

SWITCHPage37

5V_S0

REF

VTT0D75V_S0

PGDRUNPWROK

VCC_CORE

VCC_GFXCORE

PGOOD

PM_SLP_S3#

PGDRUNPWROK

TPS53311RGTR

VOUT

5

VIN 1D8V_S0

5

S0_PWR_GOOD

S5_ENABLE

3

KBC_PWRBTN#

VR

PM_SLP_S4#

4

DDR_VREF_S3

RUNPWROK

5

5a

Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

V5IN VIN

5V_S5 DCBATOUT

RT8208BGQW

VOUTVIN

1.05VTT_PWRGDEN

DCBATOUT

0D85_S0

PGOODD85V_PWRGD

5a

PM_SLP_S3#

PM_SLP_S4#GPIO44

GPIO01

GPIO77

SWITCHPage37

1D5V_S0

VDDP

5V_S5

Power Up Sequence: -8 ~ 13

PM_DRAM_PWRGD

OUTPUT

ISL95831HRTZ

IMVP_VR_ON

SVID

VIN

1D5V_S3

TPS51116RGER

VOUTVDDP VIN

6

-6.1-5

-2

6

AND GATE

A

BY

10

SYS_PWROK

S5_ENABLE

13

DCBATOUT

AC

Page38

Charger

BQ24745

Page40

(3V/5V)

RT8223MGQW3D3V_AUX_S5

3D3V_S5

5V_S5

VREG5

VREG3

PWR_5V3D3V_ENC

Page27

GPIO20

GPIO43

GPIO6

KBC NPCE795P

GPIO34

LL1

LL2

-3.2

PUMP15V_S5

-3.3

PGOOD3V_5V_POK

-1

Power Button

1

-2.1

SLP_S4# SLP_S3#

PM_SLP_S4#EN

EN

PM_SLP_S3#

SWITCH

Page37

D85V_PWRGD

EN

VDD

5V_S5 3D3V_S5

4

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Power Block DiagramA3


<Core Design>

Title


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Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Charger

BQ24745

+PBATT

Adapter

Battery

TPS51427

5V_AUX_S5

Regulator LDO Switch

5V_S53D3V_AUX_S5

TPCA8062

5V_S0

G547F2P81

5V_USB1_S3

3D3V_S5

VT1317VT1317

VCC_CORE

TPS51218

DCBATOUT

VCC_GFXCORE

TPS51216

0D75V_S0DDR_VREF_S3

1D5V_S0

1D5V_S3

Power Shape

AO4407A

TPS51311

1D8V_S0

POLYSW DCBATOUT_LCD

TPS51461

0D85V_S0

1D05V_VTT

AO3403

3D3V_LAN_S5

AO4468

3D3V_S0

RTS5138

3D3V_CARD_S0

G5285T11

LCDVDD

TPCA8062

15V_S5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of



Nirvana 13 A00

SMBUS Block DiagramA2


<Core Design>

Title


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Nirvana 13 A00



<Core Design>

Title


Date: Sheet of



Nirvana 13 A00



<Core Design>

+3.3V_RUN_VGA‧

TPDATA

TPCLK

+5V_RUN‧‧‧ TouchPad Conn.TPDATA

TPCLKPSCLK1

PSDAT1

VGA

LCD CONN

PCH SMBus Block Diagram

PCH

SMBCLK

SMBDATA

GPIO74/SDA2

GPIO73/SCL2

KBC

CLK_SMB

ThermalSCL

SDA

+3.3V_RUN‧SRN2K2J-1-GP

+3.3V_ALW‧‧‧ SRN2K2J-1-GP

+3.3V_RUN

2N7002SPT

‧ ‧‧DAT_SMB

KBC_SCL1

KBC_SDA1

DDC1DATA

DDC1CLK

Minicard

WLAN

SMB_DATA

SMB_CLK

SCL1

SDA1

BAT_SCL

BAT_SDA

SMBus address:D2

SMBus Address:A0

SMBus Address:A4

DIMM 1SCL

SDA

+KBC_PWR‧DIMM 2SCL

SDASMBus address:16

PCH_SMB_CLK

PCH_SMB_DATA

PCH_SMBCLK

PCH_SMBDATA

PBAT_SMBCLK1

PBAT_SMBDAT1

KBC SMBus Block Diagram

Battery Conn.PCH_SMBCLK

PCH_SMBDATA

Clock

GeneratorSCLK

SDATA

PCH_SMBCLK

PCH_SMBDATA

BQ24745SCL

SDA

TPDATA

TPCLK

+3.3V_RUN

2N7002DW-1-GP

‧THERM_SCL

THERM_SDA

SMBus address:7A

PCH_SMBDATA

PCH_SMBCLK

‧‧SMBus address:12

+3.3V_RUN‧‧‧

2N7002DW-1-GP

‧‧+3.3V_RUN

SRN2K2J-1-GP

CRT CONNCRT_DDCCLK_CON

CRT_DDCDATA_CON

PCH_CRT_DDCCLK

PCH_CRT_DDCDATA

DDC2CLK

DDC2DATA

SRN10KJ-5-GP

SRN4K7J-8-GP

SRN4K7J-8-GP

SRN2K2J-1-GP

NPCE781BA0DX

SRN100J-3-GP

SRN2K2J-1-GP

GPU_HDMI_CLK

GPU_HDMI_DATA

+3.3V_RUN_VGA‧HDMI CONNIFPC_AUX_I2C_SDA#

IFPC_AUX_I2CW_SCL

XDP

SML0CLK

SML0DATA

SML0_CLK

SML0_DATA

+3.3V_ALW‧SRN2K2J-1-GP

Minicard

W-WAN

SMB_DATA

SMB_CLK

PCH_SMBDATA

PCH_SMBCLK

‧‧‧‧

VGA_CRT_DDCDATA

VGA_CRT_DDCCLK

UMA

LDDC_CLK_PCH

LDDC_DATA_PCH

SRN0J-6-GP

L_DDC_DATA

L_DDC_CLK

CRT_DDC_DATA

CRT_DDC_CLK

SDVO_CTRLDATA

SDVO_CTRLCLK

+5V_RUN‧SRN2K2J-1-GP

PCH_HDMI_DATA

PCH_HDMI_CLK Level

Shift

PCH_HDMI_CLK

PCH_HDMI_DATA

DIS

‧+3.3V_RUN

SRN2K2J-1-GP

SRN0J-6-GP

UMA

UMA

UMA

UMA

UMA

SRN0J-6-GP

DIS

UMA

‧+3.3V_RUN

SRN2K2J-1-GP

DIS

+3.3V_RUN

SRN2K2J-8-GP

+3.3V_ALW‧

TSCBTD3305CPWR

+5V_RUN

+5V_RUN‧SRN2K2J-1-GP

KBC_SCL1

KBC_SDA1 To KBCSML1DATA

SML1CLK

2N7002DW-1-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Thermal/Audio Block DiagramA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

Title


Date: Sheet of


Nirvana 13 A00



<Core Design>

OTZ2N7002

THERM_SYS_SHDN#

S IMVP_PWRGD

PURE_HW_SHUTDOWN#

VR

3V/5VENPGOD

T8

FAN CONTROL

PAGE28

VIN VSET

GPIO94

5V

VOUT

FAN VIN

TACH

GPIO56

FA

N_T

AC

H1

P2793

Digital

MIC

Put under CPU(T8 HW shutdown)

P2800_DXP

P2800_DXN

DMIC_CLK/GPIO1

DMIC0/GPIO2

D

G

FA

N1_D

AC

MMBT3904-3-GP

Place near CPU

PWM CORE

Audio Block Diagram

Codec

92HD79B1HP

OUT

MIC

IN

SPEAKER

HP0_PORT_A_L

HP0_PORT_A_R

VREFOUT_A_OR_F

TDR

TDLKBC

NPCE795P

GPIO5

GPIO92

SYS_THRM

CPU_THRM

GPIO4

PAGE28

PAGE27

HP1_PORT_B_L

HP1_PORT_B_R

Analog

MIC

PORTC_L

SPKR_PORT_D_L+

PORTC_R

VREFOUT_C

SPKR_PORT_D_L-

Thermal Block Diagram

UMA

ThermalP2800

DXP

DXN

MMBT3904-3-GP

SC2200P50V2KX-2GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Change HistoryA3

103 103Thursday, January 06, 2011

<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Change HistoryA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Change HistoryA3


<Core Design>

Date Page Change ItemVersion Function

A00 20101222 40 Power Power/Brian: Change PR4047 to 174k ohm from 121k ohm. Change PR4035 to 300k from 49.9k. Change PR4031 to 150k from 0 ohm. Change PR4034 to 0 ohm pad. Stuff PQ4003. Change PR4036 to 0 ohm pad. Stuff PQ4004.

Change PR4037 to 76.8k ohm from 49.9k ohm. Change PR4032 to 0 ohm pad.

Power/Brian: Change PU4201 to 74.01316.F33.Power4220101222A00

Change all of 0ohm to short pad at X-build stage:

0402: R1404 R1405 R1503 R1504 R5010~R5012 R1807 R2301 R2306 R2307 R2308 R2404 R2405 R2735 R2737 R2758 R2759 R2760 R3614 R3710

0603: R5803 R5804 R8507

Parallel resistor: RN1704 RN2010 RN2011 RN2012 RN2013 RN2014 RN2016

RN5117,RN5112,RN5113,RN5114,RN5115

EE20101224A00

Rename PRN3901 to PN3901. Rename PTC4101~PTC4103 to PT4101~PT4103. Rename PTC4502,PTC4509 to PT4502~PT4509. Rename PTC4601,PTC4602 to PT601~PT4602. Rename PTC4801 to PT4801. Rename LINEOUT1 to LOUT1. Rename PWRBTN1 to PWRBT1.

Rename HALLSW1 to LID1.

EE20101224A00

Change R2724 to 47K from 33K.EE2720101224A00

EE If stuff P2800EA1 then must stuff R2803,R2804 C2805 but if stuff P28003B0 should be un-stuff.2820101224A00

Power Change PR4514,PR4607 to 0ohm short pad from 0402 and un-stuff PC4523 at X-Build stage.45,4620101224A00

EEA00 20101224 28 If stuff P2800EA1 then must stuff R2803,R2804 C2805 but if stuff P28003B0 should be un-stuff.

Change R3210,R3211;PR4217~PR4220,PR4254;R4908,R4909,R4903,R4910,R4913~R4916, R4917,R4918;R6205;R6403,R6404;R6511;R6902;R7002 to 0R 0402 pad.EE32,42,49

62,64,65

69,70

20101227A00

0402 0R pad: R2301.EE2320101228A00

20101228 27,62,82 EE VGA_THRM change to USB_PWR_EN.A00

20101228 27 EE Change R2756,R2763,R2766 to 0R short pad.A00

Un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 at X-Build.EE2820101228A00

DB1 change to ZZ.00PAD.Y41(solder mask type) and keep un-stuff at X-Build stage.EE7120101229A00

20101229 27,62,82 EE Rename USB_PWR_EN to USB3_PWR_ON. Remove R6205,R620. Remove R2809 and R8210. Connect USB3_PWR_ON from KBC to IOBD1.61.A00

41,46,6520101230 Change PR4119 to 0R short pad. Change PR4114 to 0R short pad. Follow the standard schematics: remove PR4615,PR4616. Change R6406,R6405 to 0R short pad. Change PR4116 to 0R0603 short pad. Change PR4106 to 0R0603 short pad.

Change R6510 to 0R 0603 pad. Change PR4103,PR4104 to 0R0805 short pad.

EEA00

Power/Brian: change PL4201 to 68.2415N.101 from 68.10110.10G.4320101231 PowerA00

Change PR4209,PR4212 to PN4201 10k array resistor. Change R5004,R5005 to RN5001 33 ohm array resistor. Merge R1804,R1806 to RN1804 22 ohm array resistor. Merge R1401,R1402 to RN1401 10k ohm array resistor.

Merge R906,R907 to RN902 100 ohm array resistor. Merge R801,R802 to RN801 100 ohm array resistor.

EE42,50,18

14,9,8

20101231A00

Change R6801,R8201~R8203 to 1k.EE68,8220110103A00

Change R6801,R8201~R8203 to 1k.EE68,8220110103A00

merge R512,R514 to RN502 1k array resistor.EE520110104A00

Swap VCC_CORE to RN801.4 and VCCSENSE to RN801.1.EE820110104A00

Swap VCC_GFXCORE to RN902.1 and VCC_AXG_SENSE to RN902.4.EE920110104A00

A00 20110104 14 EE Change RN1401 to 0R short pad.

A00 20110104 15 EE Change R1502 to 0R0402 short pad.

A00 20110104 17 EE Merge RN1701,RN1706 to RN1703 2.2k array resistor.

Remove TR3201,TR4902,R5718,R5719,TR6401EE32,49,57

64

20110104A00

Change R6804,R6806,R6808,R6810,R6906 to 620 ohm 5%.EE68,6920110104A00

20110104 Merge R8201~R8203 to RN8201 1k array resistor.EE82A00

Change R6804,R6806,R6808,R6810,R6906 to 1k ohm 5%.EE68,6920110107A00

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Nirvana 13 A00

Change HistoryA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Change HistoryA3


<Core Design>

Title


Date: Sheet of


Nirvana 13 A00

Change HistoryA3


<Core Design>

Date Page Change ItemVersion Function

Change F4902 to 0603 0 ohm.EE4920110107A00

Merge R2115,R2116 to RN2101.EE2120110110A00

Change PG4110,PG4112,PG4114~PG4119,PG4122,PG4126,PG4129,PG4131,PG4133,PG4135~PG4138,PG4140,PG4142,PG4102~PG4109,PG4111,PG4113,PG4118,PG4120,PG4123,PG4101,PG4127,PG4130,PG4132,PG4134, PG4139,PG4141 to ZZ.CLOSE.001.Power4120110110A00

Add PT4104 47uF.Power4120110110A00

Change R4908,R4909,R4903,R4910,R4913~R4916 R4917,R4918 to 0R 0402 reisstors. Change R5101~R5108 to 0 ohm array resistors RN5102~RN5105. Change RN5117 to 0 ohm resistor.EE49,5120110111A00

Change C2007,C2008 to 15pF from 12pF base on vendor's report.EE2020110112A00

Change PT4104 to 100uF.EE4120110112A00

Change RN801,RN902 to 100 ohm 1% (66.10156.04L).A00 20110113 8,9 EE

Swap RN502,RN801,RN902,RN1703,RN1804,RN2101,RN4201,RN8201 base on swap report.EE5,8,9

17,18,21

42,82

20110113A00

Remove RN5117 for PCH_HDMI_CLK and PCH_HDMI_DATA.EE5120110118A00

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