Nios

Designing with Nios II Designing with Nios II and SOPC Builderand SOPC Builder

Copyright © 2005 Altera Corporation

AgendaAgenda

Nios II® Hardware DevelopmentNios II Software DevelopmentNios II Software DevelopmentNios II Software DebugRTL SimulationRTL SimulationAvalon Switch Fabric

C stom Peripherals− Custom PeripheralsCustom InstructionsM lti M t d Di t M A (DMA)Multi-Masters and Direct Memory Access (DMA)Configuring the Development Board

Copyright © 2005 Altera Corporation2

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Nios II Hardware Nios II Hardware DevelopmentDevelopment


What is Nios II?What is Nios II?Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor− Developed Internally By Altera- Nios II Plus All Peripherals Written In HDL− Harvard Architecture− Royalty-Free- Can Be Targeted For All Altera FPGAs- Synthesis Using Quartus II Integrated Synthesis

witc

h Fa

bric UART

GPIO

TimerOn-Chip

Nios IICPUDebug C

ache

Aval

on S

w Timer

SPI

SDRAMController

On ChipROM

On-ChipRAM

FPGA


FPGA

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Problem: Reduce Cost, Complexity & PowerProblem: Reduce Cost, Complexity & Power

FlashI/O

SDRAM

CPU

I/O

DSP

I/O

I/O FPGA

I/O I/O I/O

GI/O FPGACPU DSP

FPGA

Solution: Replace External Devices with Programmable Logic


with Programmable Logic

Problem: Reduce Cost, Complexity & PowerProblem: Reduce Cost, Complexity & PowerSystem On A Programmable Chip (SOPC)System On A Programmable Chip (SOPC)

FlashFPGA

SDRAM

FPGA

Solution: Replace External Devices with Programmable Logic

CPU is a Critical Control Function Required for System Level Integration


with Programmable LogicRequired for System-Level Integration

FPGA Hardware Design Flow with Quartus II and SOPC BuilderFPGA Hardware Design Flow with Quartus II and SOPC Builderwith Quartus II and SOPC Builderwith Quartus II and SOPC Builder

•• Create FPGA project in Quartus IICreate FPGA project in Quartus II

•• Build embedded subBuild embedded sub--system in SOPC Buildersystem in SOPC Builder

•• Integrate subIntegrate sub--system in Quartus IIsystem in Quartus II .sof / .pof file.sof / .pof file


•• Compile and generate a programming fileCompile and generate a programming file

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Development Kits, Stratix & Cyclone EditionDevelopment Kits, Stratix & Cyclone Edition

Power Connector

Download /JTAG Debug ConnectorSerial RS-232

Connectors

10/100 Ethernet MAC/PHY &

8 MB Flash

MAC/PHY & RJ-45 Connector

Expansion Prototype Connectors

CPU Reset

16 MB SDRAM

(40 I/O pins each)

Configuration Controller

1MB SRAM


g(MAX 7128AE)Compact Flash

(Connector Mounted on Back)Buttons LEDs 7 Segment

Configuration Control

Standard Design Block DiagramStandard Design Block Diagram16MB Compact

FLASH8MB

FLASH1MB

SRAMEthernet MAC/PHY

32MB SDRAM

Nios II Processor C t

32-BitNios II

Processor

Address (32)

Read

Write

Data In (32)

Avalo

Tri-StateBridge

evel

Shi

fterSDRAM

ControllerTri-StateBridge

Compact Flash PIOs

UARTProcessorROM

(with Monitor)

( )

Data Out (32)

IRQ

on Switch Fa

LeGeneral Purpose

Timer

Periodic Timer

UART

Reconfig PIO

Q

IRQ #(6)

abric Button PIO7-SegmentLED PIOLCD PIOLED PIO

Expansion 4


On-Chip Off-Chip 8 LEDsExpansion

Header J12

2 Digit Display

4 Momentary

buttons

Nios II System ArchitectureNios II System ArchitectureUART nInstr.

D t

AddressDecoder

AvalonMaster/SlaveP t

UART 0

Nios IICPU

On-ChipDebug Core

Timer n

SPI n

DataInterrupt

Controller

PortInterfaces

Timer 0

SPI 0

CPU

g SPI n

GPIO n

Wait StateGeneration

D t i

GPIO 0

Off-ChipSoftware Trace

Memory DMA n

Data inMultiplexer

Master

DMA 0

MemoryInterface

DynamicBus Sizing

Arbitration MemoryInterface

User-Defined


User-DefinedInterface

Avalon Switch Fabric

Bus SizingInterface

Nios II Block DiagramNios II Block Diagram

Programl k

resetInstruction

Nios II Processor Core

ProgramController

&Address

Generation Instruction

Cache

clock

Hardware-Assisted

Debug ModuleJTAG interfaceto Software Debugger

MasterPortGeneral

PurposeRegistersr0 to r31

irq[31..0]Control

Registerstl0 t tl4

InterruptController

ExceptionController

irq[31..0] ctl0 to ctl4

A ith ti

Controller

C stomData

Cache

DataMasterPort

ArithmeticLogic Unit

Custom Instruction

Logic

Cache Custom

I/O Signals


Nios II Processor ArchitectureNios II Processor Architecture

Classic Pipelined RISC Machine32 G l P R i t− 32 General Purpose Registers

− 3 Instruction Formats − 32-Bit Instructions32 Bit Instructions− 32-Bit Data Path− Flat Register File− Separate Instruction and Data Cache (configurable sizes)− Branch Prediction− 32 Prioritized Interrupts− 32 Prioritized Interrupts− Custom Instructions− JTAG-Based Hardware Debug Unit


Nios II VersionsNios II VersionsNios II Processor Comes In Three ISA Compatible Versions

− FAST: Optimized for Speed

− STANDARD: Balanced for Speed and Size

S f

Size

− ECONOMY: Optimized for Size

Software− Code is Binary Compatible

No Changes Required When CPU is Changed


Binary Compatibility / Flexible PerformanceBinary Compatibility / Flexible PerformanceNios II /f

FastNios II /sStandard

Nios II /eEconomy

Pipeline 6 Stage 5 Stage None

H/W Multiplier & Barrel Shifter 1 Cycle 3 Cycle Emulated

In Software

Branch Prediction Dynamic Static None

Instruction Cache Configurable Configurable NoneInstruction Cache Configurable Configurable None

Data Cache Configurable None None

L i ULogic Usage (Logic Elements) 1400 - 1800 1200 – 1400 600 – 700

CustomInstructions Up to 256


Instructions

Hardware Multiplier AccelerationHardware Multiplier AccelerationNios II Economy version - No Multiply Hardware− Uses GNUPro Math Library to Implement Multiplier

Nios II Standard - Full Hardware MultiplierNios II Standard - Full Hardware Multiplier− 32 x 32 32 in 3 Clock Cycles if DSP block present, else uses software

only multiplier

Nios II Fast Full Hardware MultiplierNios II Fast - Full Hardware Multiplier− 32 x 32 32 in 1 Clock Cycles if DSP block present, else uses software

only multiplier

AccelerationHardware

Clock Cycles(32 x 32 32)

None 250

StandardMUL in Stratix

3

Fast


FastMUL in Stratix

1

LicensingLicensingNios II Delivered As Encrypted Megacore− Licensed Via Feature Line In Existing Quartus II License File

C i t t With G l Alt M D li M h i− Consistent With General Altera Megacore Delivery Mechanism− Enables Detection Of Nios II In Customer Designs (Talkback)

No Nios II Feature Line (OpenCore Plus Mode)− System Runs If Tethered To Host PC− System Times Out If Disconnected from PC After ~ 1 hr

Nios II Feature Line (Active Subscriber)( )− Subscription and New Dev Kit Customers Obtain Licenses From

www.altera.com− Nios II CPU RTL Remains Encrypted

SNios II Source License− Available Upon Request On Case-By-Case Basis− Included With Purchase Of Nios II ASIC License


Requirements for Nios II DesignsRequirements for Nios II Designs

Quartus II 4.0 SP1 or higher N t Q t II 4 2 il blNote: Quartus II now 4.2 available − Required for Nios II 1.1

No spaces in Quartus II project pathnameNios II license or a programming cable p g gtethered to PC to run the OpenCore Plus version of Nios II


Nios II: Hard NumbersNios II: Hard NumbersNios II/f Nios II/s Nios II/e

Stratix II 200 DMIPS @ 175MHz 90 DMIPS @ 175MHz 28 DMIPS @ 190MHzStratix II1180 LEs1 of 8 DSP4K Icache, 2K DcacheStratix 2S10-C5

800 LEs

4K Icache, No DcacheStratix 2S10-C5

400 LEs

No Icache, No DcacheStratix 2S10-C5Stratix 2S10 C5 Stratix 2S10 C5 Stratix 2S10 C5

Stratix 150 DMIPS @ 135MHz1800 LEs1 of 8 DSP4K I h 2K D h

67 DMIPS @ 135MHz1200 LEs

4K I h N D h


N I h N D h4K Icache, 2K DcacheStratix 1S10-C5

4K Icache, No DcacheStratix 1S10-C5

No Icache, No DcacheStratix 1S10-C5

Cyclone 100 DMIPS @ 125MHz1800 LEs



4K Icache, 1K DcacheCyclone 1C4-C6

2K Icache, No DcacheCyclone 1C4-C6

No Icache, No DcacheCyclone 1C4-C6


* FMax Numbers Based Reference Design Running From On-Chip Memory (Nios II/f ≅1.15 DMIPS / MHz)

SOPC BuilderSOPC Builder – System Contents Page

Altera, Partner & UserAltera, Partner & User Cores− Processors− Memory Interfaces− Peripherals− Bridges− Hardware Accelerators

Over 60 Cores Available

Today− Import User Logic

(ie. custom peripherals)Web-Based IP Deployment

y


Clock-Domain CrossingClock-Domain Crossing New in4.2

Auto-Insertion of Clock-Domain Crossing Logic FIFO Wh P t d R d A S t d− FIFO Where Posted-Reads Are Supported

− Simple Metastability-Hardening Otherwise

Unlimited Number of Clock Domains− Added, Named & Managed Through GUI


Nios II CPU Configured in SOPC BuilderNios II CPU Configured in SOPC BuilderHardware designer selects which Nios II version to use when creating system


Selecting JTAG Debug CoreSelecting JTAG Debug CoreConfiguration is chosen when hardware designer selects appropriate Nios II processor core


SOPC BuilderSOPC Builder – More “cpu” Settings Page


SOPC Builder – System Generation PageSOPC Builder – System Generation Page


SOPC Builder Produces a .PTF FileSOPC Builder Produces a .PTF File

Text file that records SOPC Builder editsDescribes Nios II SystemDescribes Nios II SystemUsed by software development tools


Integrate SOPC Builder O/P in Quartus IIIntegrate SOPC Builder O/P in Quartus IIIntegrate SOPC Builder block symbol to Quartus II schematic (as shown below) and compile designO i t ti t t d l i t HDL d i d ilOr, instantiate top module into your HDL design and compile


New Peripherals for Nios II New Peripherals for Nios II Memory Interfaces− EPCS Serial Flash

System ID Peripheral− Used to Ensure Hardware/

Controller− On-Chip

RAM, ROM

Software Version Synchronization− Simple 2 read-only register

peripheral containing hardware ID − Off-Chip

SRAMCFI Flash

tags.Register 1 contains random number

LCD Display

Register 2 contains time and date when system was generated in SOPC Builder

Can be checked at runtime to− Can be checked at runtime to ensure that the software to be downloaded matches the hardware image


hardware image

New Peripherals for Nios II New Peripherals for Nios II

JTAG UART− Single JTAG

Compact Flash Interface− Mass Storage SupportSingle JTAG

Connection For:Device ConfigurationFl h P i

gTrue IDE ModeCompact Flash Mode

− Software SupportsFlash ProgrammingCode Download DebugT t STDIO ( i ti )

ppLow-Level APIMicroC/OS-II File System Support

Target STDIO (printing) µCLinux File System Support

Supported through


Supported through www.niosforum.com

Project DirectoriesProject DirectoriesHardware− HDL Source & Netlist− db - Quartus project

database

SoftwareSoftware− Application source code− Library files

Simulation− Testbench− Automatically generatedAutomatically generated

test memory and vectors


Exercise 1A Basic Nios II DesignExercise 1A Basic Nios II Designgg

35 mins35 mins


Nios II Software Nios II Software DevelopmentDevelopment


Nios II System Design FlowNios II System Design FlowProcessor Library Custom Instructions

IP M d l

Configure ProcessorSOPC Builder GUI

Connect Blocks

Peripheral Library Select & Configure Peripherals, IP

IP Modules

Software DevelopmentHardware DevelopmentNios II IDENios II IDE

C Header files

Custom Library

Peripheral DriversGenerate

HDL Source Files

Testbench

E t blH d

Compiler, Linker, Debugger

Synthesis &Fitter

JTAG

ExecutableCode

HardwareConfiguration

File Verification& Debug

User Code

Libraries

RTOS

User Design

Other IP Blocks

Quartus II

On-ChipDebugAltera

FPGA

JTAG,Serial, orEthernet


GNU ToolsQuartus II

Software TraceHard Breakpoints

SignalTap® II

FPGA

Nios II Software Design ProcessNios II Software Design Process

Deliverables Required to Start Deliverables Required to Start Software Development:Software Development:

Software DevelopmentNios II IDENios II IDE

•• .ptf file from SOPC Builder.ptf file from SOPC Builder(defines hardware for the Nios II IDE)(defines hardware for the Nios II IDE)

•• f ( f) fil f Q t IIf ( f) fil f Q t II E t bl

C Header files

Custom Library

Peripheral Drivers

•• .sof (or .pof) file from Quartus II.sof (or .pof) file from Quartus II(used to program the FPGA on the board)(used to program the FPGA on the board)

ExecutableCode Compiler,

Linker, Debugger

User Code

Libraries

RTOS

That’s ALL you need to start That’s ALL you need to start to run with the Nios II IDEto run with the Nios II IDE


GNU Tools

Nios II IDE (Integrated Development Environment)*Nios II IDE (Integrated Development Environment)*

Leading Edge Software Development ToolTarget Connections− Hardware (JTAG)− Instruction Set Simulator− ModelSim®-Altera Software

Advanced Hardware Debug FeaturesDebug Features− Software and Hardware

Break Points, Data Triggers, Trace

Flash Memory Programming Support


* Based on Eclipse Project

Opening the Nios II IDEOpening the Nios II IDELaunch the Nios II IDE from Launch the Nios II IDE from the SOPC Builder or from the SOPC Builder or from the Windows Start menuthe Windows Start menu


Nios II IDENios II IDE

List of Open File Viewer Window

Projectsdo

(for C code, C++, and assembly*)

Terminal window


•Note: C++ files must have extension .cppIn-line assembly code offset by asm();

Nios II IDE C/C++ Projects/NavigatorNios II IDE C/C++ Projects/Navigator

Lists all open

List all open and

projects

Displays

closed projects

p ysource files associated with project

Allows you to drag and drop new files into existing projects


Creating a C/C++ ApplicationCreating a C/C++ ApplicationFile > New > Project


Creating a C/C++ ApplicationCreating a C/C++ Application

Link to a System LibrarySelect a pre existing library- Select a pre-existing library

- Or create a new library


This Creates Two Software Projects- Application and System Library ProjectThis Creates Two Software Projects- Application and System Library Project- Application and System Library Project- Application and System Library Project

Application Project- contains application source code

System Library Project- contains system y

header file, etc.

Drivers Directory- contains all device drivers – DO NOT DELETE !


Application and System Library ProjectsApplication and System Library Projects

Application Projects build executablesSystem Library Projects contain interface to theSystem Library Projects contain interface to the hardware

Nios II device drivers (Hardware Abstraction− Nios II device drivers (Hardware Abstraction Layer)

− Optional RTOS (MicroC/OS-II)p ( )− Optional software components (Lightweight

TCP/IP stack, Read Only Zip File System)


Other New Project OptionsOther New Project OptionsSystem Library− Only creates system library project− Build C applications upon this later

Advanced C/C++ Project− Disable automatic tool features like

makefile and linker script generation− User defines own instead

Managed Library Projectg y j− Facilitates software library

development− Enables you to associate pre-

compiled code into an Application Project

− Tool writes makefile for included files


Importing Projects into the IDEImporting Projects into the IDE


Project Properties Project Properties Both Application and System Library have Properties pages


System Library OptionsSystem Library OptionsSelect RTOSSpecify stdio devicesPartition the memory map


Software CompilationSoftware Compilation

To compile a software application, highlight your project and select Build Project from the Projects menuand select Build Project from the Projects menu


Directory Structure After CompilationDirectory Structure After Compilation

Application Project System Library Project


Nios II Host Platform SupportNios II Host Platform Support

Windows XPLi H t S t (R dH t 7 3 8 0Linux Host Support (RedHat 7.3, 8.0, Enterprise 3)− Nios II GNU Toolchain (Compiler, Binary Utilities)− Nios II Instruction Set Simulator− Nios II Debugger− Nios II IDE− USB Blaster Linux driver


Hardware Abstraction LayerHardware Abstraction LayerA lightweight runtime environment for Nios II software− Provides a level of abstraction between application code and

low level hardware

HAL libraries are generated by Nios II IDEA HAL contains:A HAL contains:− device drivers− initialization software− file system− stdio, stderr


Hardware Abstraction LayerHardware Abstraction LayerProvides generic device models for classes of peripherals common in embedded systems− eg. timers, I/O peripherals, etc.

Gives a consistent POSIX-like API, regardless of underlying hardwareunderlying hardwareMake programming as familiar as possible to software engineers who may not be familiar with the specific peripheral architectures

ANSI C (through the Newlib library)UNIX style interface (i.e. POSIX like)UNIX style interface (i.e. POSIX like)Altera extensions where standards don’t exist or were inappropriate (watch for the alt_* extension)


Hardware Abstraction LayerHardware Abstraction LayerKey features of the HAL− Uses standard interfaces where appropriate− Close integration with the Newlib ANSI C library

http://sources.redhat.com/newlib/− Device drivers automatically configured to match the PTF− Device drivers automatically configured to match the PTF− Drivers initialised before main()− Scalable (i.e. packs down small)

C f− Clear distinction between system and application software


Nios II HAL: Runtime LibraryNios II HAL: Runtime Library

The HAL ‘UNIX Style’ Functions are the glue between the C library and the device driversy

_exit()close()closedir()

open()opendirread()

HAL API

C Standard LibraryC Standard Library

User Program

D i D i D i

fstat()getpid()gettimeofday()ioctl()isatty()

readdir()rewinddir()sbrk()settimeofday()stat()

HAL API

Nios II Processor System Hardware

DeviceDriver

DeviceDriver

DeviceDriver…

isatty()kill()lseek()

stat()usleep()wait()write()


HAL File SystemHAL File System/

/dev /mnt

/dev/jtag_uart0 /dev/lcd0 /mnt/rozipfs

/mnt/rozipfs/myfile1p y

/mnt/rozips/myfile21• Device names match those set in SOPC builder.

C l d t di t i• Can only access nodes, not directories.• All paths must be absolute (no current directory)


Familiar File/Device AccessFamiliar File/Device Access

ANSI C:fp = fopen (“/dev/lcd0”, “w”); fprintf (fp, “%s”, msg);

UNIX Style:fd = open (“/dev/lcd0”, O_WRONLY); write (fd, msg, strlen(msg));

N lib l CNewlib also supports C++ streams:ofstream ofp(“/dev/lcd0”, ios::out); ofp << msg;

Existing code (outside the Nios world) usesExisting code (outside the Nios world) uses these interfaces. Porting is now much easiereasier.Use of existing standards means there’s nothing new to learn


nothing new to learn.

HAL System Header FileHAL System Header FileSOPCSOPC Builder System ContentsBuilder System Contents

system.hsystem.h


System Library SettingsSystem Library Settings

system.hsystem.hContains macro definitions for system parameters, including peripheral configuration, for instance: − Hardware configuration of the peripheral− Base address− IRQ priority (if any)p y ( y)− Symbolic name for peripheral

Does not include: static information, function prototypes or device structures (unlike the oldprototypes, or device structures (unlike the old excalibur.h)Located in the syslib project directoryRarely necessary to include it explicitly in your application code, which improves rebuild time


system.h - examplesystem.h - exampleDefines system settings and peripheral configurations:− Replaces excalibur.h (from Nios)

.

.

./*

/** system configuration**/

/* button_pio configuration**/

#define ALT_SYSTEM_NAME "std_1s10ES"#define ALT_CPU_NAME "cpu"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT DEVICE FAMILY "STRATIX"

#define BUTTON_PIO_NAME "/dev/button_pio"#define BUTTON_PIO_TYPE "altera_avalon_pio"#define BUTTON_PIO_BASE 0x00920830#define BUTTON_PIO_IRQ 2#define BUTTON PIO HAS TRI 0

#define ALT_DEVICE_FAMILY STRATIX#define ALTERA_NIOS_DEV_BOARD_STRATIX_1S10_ES#define ALT_STDIN "/dev/jtag_uart"#define ALT_STDOUT "/dev/jtag_uart"#define ALT_STDERR "/dev/jtag_uart"

#define BUTTON_PIO_HAS_TRI 0#define BUTTON_PIO_HAS_OUT 0#define BUTTON_PIO_HAS_IN 1#define BUTTON_PIO_CAPTURE 1#define BUTTON_PIO_EDGE_TYPE "ANY"

#define ALT_CPU_FREQ 50000000#define ALT_CPP_CONSTRUCTORS#define ALT_IRQ_BASE NULL

.


#define BUTTON_PIO_IRQ_TYPE "EDGE"#define BUTTON_PIO_FREQ 50000000

.

.

HAL ReferencesHAL ReferencesEach HAL project references library routines and drivers for the components included in your Nios II system


Reading/Writing Hardware in NiosReading/Writing Hardware in Nios

Nios Classic used volatile pointers to access hardware e gaccess hardware e.g.− volatile *my_led_pointer = (int *) LED_BASE;

Volatiles will no longer provide access to hardware registers in Nios II− They are still used to tell the compiler not to

optimize code− No longer disable cache access


Reading/Writing Hardware in Nios IIReading/Writing Hardware in Nios II

Instead use I/O macros to access hardware− I/O macros bypass the cache for hardware accessesI/O macros bypass the cache for hardware accesses− They set bit 31 of address bus high (ie. control bit)

IORD(BASE REGNUM)− IORD(BASE, REGNUM)Reads value at register REGNUM offset from base dd BASE

REGNUM = 0REGNUM = 0REGNUM = 1REGNUM = 1REGNUM 2REGNUM 2

BASEBASE

address BASE

− IOWR(BASE,REGNUM,DATA)

REGNUM = 2REGNUM = 2REGNUM = 3REGNUM = 3REGNUM = 4REGNUM = 4

BASE+2BASE+2

BASE+4BASE+4IOWR(BASE,REGNUM,DATA)Writes DATA to register REGNUM offset from base address BASE


address BASE

Header Files for Nios II PeripheralsHeader Files for Nios II Peripherals

Each Nios II peripheral has specific read/write macros for each registermacros for each register− Example: UART (altera_avalon_uart_regs.h)

#define IORD_ALTERA_AVALON_UART_RXDATA(base) IORD(base, 0)

#define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) IOWR(base, 0, data)

#define IORD_ALTERA_AVALON_UART_TXDATA(base) IORD(base, 1)

#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) IOWR(base, 1, data)

#define IORD_ALTERA_AVALON_UART_STATUS(base) IORD(base, 2)

#define IOWR_ALTERA_AVALON_UART_STATUS(base, data) IOWR(base, 2, data)


Data CacheData Cache

Memory space is mirrored (e.g. 2GB addressable space)addressable space)− Upper half is uncacheable

L h lf i h bl− Lower half is cacheableAll data variables are cached by default− This can cause memory coherency issues if

you are using a DMA controller in your design.


Data CacheData Cache

To bypass the cache and maintain coherency…Flush before any DMA transfers using− Flush before any DMA transfers using alt_dcache_flush()

− Allocate uncacheable regions on the heap− Allocate uncacheable regions on the heap using alt_uncached_malloc()

− Remap an existing area of memory usingRemap an existing area of memory using alt_remap_uncached()

− Use ldio or stio instructions in assemblyUse ldio or stio instructions in assembly


InterruptsInterrupts

HAL API for ISRs - Functionslt i i t ()− alt_irq_register()

Associates interrupt with your ISR function.

− alt irq disable all()alt_irq_disable_all()Disables all IRQs

− alt_irq_enable_all()Enables all IRQs

− alt_irq_interruptible()Used in ISR function body Allows ISR to be interrupted byUsed in ISR function body. Allows ISR to be interrupted by higher priority IRQs.

− alt_irq_non_interruptible()U d t k ISR i t tibl (d f lt b h i )


Used to make ISRs uninterruptible (default behavior).

HAL API for ISRs - Useful InfoHAL API for ISRs - Useful Info

Write your ISRsample_isr ( void* context, alt_u32 id);

(Follow prototype) id == irq number (0 to 31)context == void pointer to data produced by or consumed by ISR.

Register your ISR

alt_irq_register ( alt_u32 id, void* context,

void (*irq_handler) (void*, alt_u32));

Sample Usage:Using alt_irq_register()

Sa p e Usagealt_irq_register ( 3, &some_data, sample_isr);


HAL API for ISRs - Useful InfoHAL API for ISRs - Useful InfoCreating interruptible code blocks in ISR− Use alt_irq_interruptible() & alt_irq_non_interruptible()

Do not use standard C library or RTOS software functions inside ISR that may pend for any reason− Eg. printf()

Keep it simple….− Use ISR to trigger execution of slow processing tasks outside of

interrupt contextp− Do NOT perform these tasks within ISR

References:References:− Exception Handling Chapter in “Nios II Software Developer’s

Handbook”


Nios II OS / RTOS SupportNios II OS / RTOS SupportProduct Provider Source

CodeStandards TCP/IP

StackFile

SystemOther

* MicroC/OS-II Micrium Yes RTCA/DO-178B Opt. Opt. GUIFlash

* Lightweight IPTCP/IP Stack

Open Source Yes Sockets APIIP, ICMP, UDP, TCP

µC/OS-II Support

** Nucleus Plus ATI/Mentor Yes OSEKµITRON

Opt. Opt. GUI, SNMPRMON, SPAN

µCLinux Open Source Yes Incl. Many, Extensive µ p(GPL)

y,inc. FAT and

JFFS2

drivers and middlewear,

inc USB, IPSec, etc.

KROS KROSTechnologies

Yes POSIX Opt. Opt.

<continued on next slide>


* Included in Nios II Development Kits** Evaluation Version Included in Nios II Development Kits

<continued on next slide>

Nios II OS / RTOS Support (cont)Nios II OS / RTOS Support (cont)Product Provider Source

CodeStandards TCP/IP

StackFile

SystemOther

NORTi MiSPO Yes µITRON Opt. Opt. PPP, SNMP, HTTP

PrKERNELv4 eSOL Yes µITRON Opt. Opt. USB, MailHTTP

Th dX E L i Y O t O t USBThreadX Express Logic Yes Opt. Opt. USB

eCos Open Source (GPL with excpetion)

Yes POSIZ, uITRON, EL/IX

Incl. FAT, JFFS2,

ROMFS

Extensive drivers and middlewareexcpetion) ROMFS,

RAMFSmiddleware, inc. USB, IPSec, etc.



Nios II MicroC/OS-II Nios II MicroC/OS-II Single-seat developers license included for free with Nios II kitsLicensing fee req’d when you productize your systemFull source code includedPreemptive operating systemSmall footprintp− Code Size (min 5KB, max 20KB)− Data Space (min 1KB, max 5KB)

Supports Semaphores, and Mailboxes for task synchronization


Nios II MicroC/OS-II Nios II MicroC/OS-II


Lightweight IP for MicroC/OS-IILightweight IP for MicroC/OS-IIPlugs is being replaced with the Lightweight IP TCP/IP stack in Nios IIg gOpen source TCP/IP Stack− Supports TCP, UDP, IP, DHCP and ARP− Optimised for size (Very simple web server < 500k)Optimised for size (Very simple web server 500k)− LWIP supports IPv4 and IPv6, but we support IPv4 ONLY− Based on version 0.6.3

Integrated into Nios II IDEgUsed in conjunction with uC/OS-IISockets API availableFree Licensing− Modified BSD License, must keep the copyright notice and display it in the

product documentation


LWIP - InstantiationLWIP - Instantiation

Available as a Software Component


LWIP – ConfigurationLWIP – Configuration


Nios to Nios II ConversionNios to Nios II Conversion

Hardware Must be PortedAdd Ni II d ti i− Add Nios II processor and connections in SOPC Builder

Software can be Used in Legacy SDK Mode or Ported to HALMode or Ported to HAL

See AN350 for full details



Legacy Software SupportMi i l if C d Ch R i d− Minimal if any Code Changes Required

− No Access to Nios II IDEO l t d f St d d d E− Only supported for Standard and Economy coresN i h l (CFI fl h id t ) t− New peripherals (CFI flash, sysid, etc…) not supportedNew software components (uC/OSII LWIP)− New software components (uC/OSII, LWIP) not supported



Full Port from Nios to Nios IIR i C d h− Requires C code changes

− No GERMS supportP id HAL C/OSII LWIP− Provides access HAL, uC/OSII, LWIP



Porting Process:Replace header files− Replace header files

Example: system.h for excalibur.h

− Change API calls from SDK to HAL syntax g yExample: nr_delay() is replaced with usleep()

− Replace data types (int, char, etc..) with Nios II data types (alt u32 alt u8 etc )types (alt_u32, alt_u8, etc…)

− Replace hardware access pointers with macrosExample: my pio->data = 1 is replaced with p y_p pIOWR_ALTERA_AVALON_PIO_DATA(PIO_BASE,1)

− Take into account that *volatile pointers no longer prevent data from being cached


prevent data from being cached

Software Run & DebugSoftware Run & DebugSoftware Run & DebugSoftware Run & Debug


Software Run and DebugSoftware Run and Debug

Nios II RunNi II IDE JTAG D bNios II IDE JTAG DebuggerNios II ISSNios II ConsoleThird Party toolsThird Party tools


Running Code On A TargetRunning Code On A TargetNios II IDE can be used to download code to target board


Running Code On A TargetRunning Code On A TargetDownload messages, stdout and stdin appear in console window


Nios II IDE Run OptionsNios II IDE Run Options

Nios II IDE > Run > Run…


System ID Peripheral RevisitedSystem ID Peripheral RevisitedWhen downloading code to a target, Nios II IDE computes expected System ID peripheral values from PTF filey− If computed ID values do not match System ID variables stored on

the target board then an error is flagged− Generally, to fix this you should recompile your hardwareGenerally, to fix this you should recompile your hardware


Nios II IDE JTAG DebuggerNios II IDE JTAG Debugger

Requirements− Must have JTAGMust have JTAG

Debug Core enabled in CPU


Nios II IDE Debug PerspectiveNios II IDE Debug Perspective

Basic Debug• Run Controls

• Stack View

DoubleDouble click toclick to

• Active Debug Sessions

DoubleDouble--click to click to add breakpointsadd breakpoints

• Variables

• Registers

Memory View


• Signals

Nios II IDE DebuggerNios II IDE Debugger

Step ReturnStep ReturnStep ReturnStep ReturnStep OverStep OverStep IntoStep IntoStep with FiltersStep with Filters

DisconnectDisconnectsco ectsco ectTerminateTerminateSuspendSuspend

RRResumeResume

Run last ConfigurationRun last ConfigurationD b l t C fi tiD b l t C fi ti


Debug last ConfigurationDebug last Configuration

Nios II IDE DebuggerNios II IDE Debugger

Standard debug windowswindows− memory− registersg− Variables− breakpoints− expressions− signals


Nios II IDE – Multi-Processor LaunchNios II IDE – Multi-Processor LaunchMechanism to Quickly Launch Multiple Debuggers and Connect Them to Multiple Nios II Processors− Run > Debug… > Nios II Multiprocessor Collection


Accelerates Debug Cycle for Multi-Processor Systems

Nios II IDE: DebuggerNios II IDE: DebuggerDebug each CPU by selecting it’s program thread


Nios II Instruction Set SimulatorNios II Instruction Set Simulator

Instruction Set Simulators are software models of an Instruction Set Architecturemodels of an Instruction Set Architecture− Generally used to debug code if a target board

is unavailableis unavailable.− Provides limited models of a few hardware

peripheralsperipherals.TimerUARTUMemory (flash, SDRAM, on-chip, etc…)


Nios II Instruction Set SimulatorNios II Instruction Set Simulator

Launch an ISS Debug session from the Run MenuRun Menu


Nios II Instruction Set SimulatorNios II Instruction Set SimulatorTargets .elf file to ISS and opens debugger− Application can then be debugged as normal


Customizing Views in the IDE GUICustomizing Views in the IDE GUI

You can turn windows on or off in either the Run or Debug PerspectiveRun or Debug Perspective


Nios II SDK ShellNios II SDK ShellSDK shell is still provided with Nios IIUsed to support legacy SDK flow (eg n2b n2c) asUsed to support legacy SDK flow (eg.. n2b, n2c) as well as other general commandsCan launch terminal to interface to JTAG UART’s− nios2-terminal

And compile code− nios2-elf-gcc


Nios II / FS2 ConsoleNios II / FS2 Console

Command line debugger


Nios II Console LaunchNios II Console Launch

FS2 Console Launches then minimizes


Nios II ConsoleNios II ConsoleAllows for hardware breakpoints and trace data− 2 HWBP’s and 16 Frames of On-

Chip Trace Included

Displays C Source, A bl Mi dAssembly, Mixed


Nios II Debug SolutionsNios II Debug SolutionsProduct Provider Description Features

* Nios II IDE Altera IDE / Debugger JTAG Target Connection, H/W gg g ,Breakpoints, Data Triggers, On-Chip Trace, FS2 Trace Probe

** code|lab ATI Mentor IDE / Debugger JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace , FS2 Trace Probe

Watchpoint Sophia Systems

Debugger Supports FS2 ISA-Nios/T

ISA-Nios/T First Silicon Solution (FS2)

JTAG Trace Probe

External Trace Capture, Timestamp, Complex Data Triggers



Upgrades from FS2Upgrades from FS2(see www.fs2.com for details)

Feature Nios II IDE FS2 S/W Upgrade

FS2 H/W UpgradeUpgrade Upgrade

Hardware Execution Breakpoints

2 4 4

Data Triggers 2 4 4

Trace (PC) On-Chip16 Frames

On-Chip128 Frames

Off-Chip128K Frames16 Frames 128 Frames 128K Frames

Trace (Load / Store) No Yes Yes

Trace (Timestamp) No No YesTarget Connection Altera

USB/B BlasterAltera

USB/B BlasterFS2 Black Box(USB, Ethernet)

Cost Included See FS2 See FS2


FS2 System Analyzer UpgradeFS2 System Analyzer UpgradeISA-Nios II System Analyzer− 10-pin JTAG Target Connection

Unlimited Software Breakpoints− Unlimited Software Breakpoints− 2 Hardware Breakpoints (upgradable to 4)− Supports On-Chip Trace (upgrades available for

deeper trace)

ISA-Nios II/T System Analyzer− 38-pin Mictor Connection− Blackbox probeBlackbox probe− Supports 128k frames Off-Chip Trace

in addition to Unlimited On-Chip Trace


Lab 2Software FlowLab 2Software Flow

45 mins45 mins


RTL SimulationRTL Simulation


RTL SimulationRTL Simulation

Nios II SOPC Builder Automatically Creates Simulation Models Plus:Simulation Models Plus:− ModelSim Project− Testbench− Simulation Scripts


Set Simulation Option

Simulation TestBenchSimulation TestBenchSDRAMDev board

SRAMDev board

FLASH Compact FLASHEthernet MAC/PHY

Nios II Processor C t

32-BitNios II

Processor

Address (32)

Read

Write

Data In (32)

Avalon S

Tri-StateBridge

SDRAMController

Tri-StateBridge

Compact Flash PIOs

ProcessorOn Chip

ROM)

( )

Data Out (32)

IRQ

Switch Fabric U

ser D

evic

eOn Chip RAM

Custom Instruction

UART

IRQ #(6)

c

User Defined Interface

User Defined

Peripheral

I l d d


Clock Reset User Device User Peripheral

Included

Not Included

User Additions to Nios II TestBenchUser Additions to Nios II TestBench

SOPC Builder creates testbench embedded intestbench embedded in top level file eg NiosII.v

Sections within this fileSections within this file are reserved to add user files and code

These sections are preserved if the SOPC builder is used to re-builder is used to re-generate the Nios II system


Running an RTL SimulationRunning an RTL SimulationModify Nios II IDE System Library For Simulation:− Specify Program Memoryp y g y− Set Up As Simulation Only


Running an RTL SimulationRunning an RTL Simulation

Checking the “ModelSim only, no hardware support” button:

L h i iti li d− Leaves caches uninitialized− Does not initialize the .bss section

As a result simulation speeds are increased

You can still simulate with this button unchecked but simulation time will be much longer


Running an RTL SimulationRunning an RTL SimulationLaunch ModelSim from Nios II IDE:− Highlight Software Project In C/C++ Projects panelHighlight Software Project In C/C Projects panel− Right click− Run As Nios II ModelSim


Running an RTL SimulationRunning an RTL Simulation


Simulation ScriptsSimulation ScriptsWhen ModelSim is started from the Nios II IDE a set-up script is run automatically which creates aliases for simulation scriptssimulation scriptsThe set up script can also be run independently as follows:− do setup sim dodo setup_sim.do

Simulation Scripts− s↵ Compiles HDL source code and loads design− c↵ Rebuilds memory contents based on software code

Includes changes since Nios II generation

O W i d ith “ f l” i l− w↵ Opens Wave window with “useful” signals− l↵ Opens List window with “useful” signals

h↵ Displays help message describing scripts


− h↵ Displays help message describing scripts

Memory Device Simulation ModelsMemory Device Simulation Models

Applies To The Following Nios II Memories− On Chip Memory (ROM or RAM)On Chip Memory (ROM or RAM)− SRAM− Flash Memory and now SDRAMy

Include SDRAM Model for Simulation


for Simulation

Memory Device Simulation ModelsMemory Device Simulation Models

You can no longer initialize memories in the SOPC BuilderSOPC Builder.− Memory init file are created by the Nios II IDE.

− ext_ram will be initialized for simulation with the ext_ram.dat file

− You must compile your software in the Nios II IDE to generate this file

− Onchip memories are initialized with <component_name>.hex

− Onchip memory init files can be created by an editor or by the Nios II IDE


UART SimulationUART SimulationText is transmitted to UART during simulationCreates and saves txt file containing UART tx tstream

Creates window to input t t t i l ti titext at simulation run time


Note: ModelSim Options are mutually exclusive

UART SimulationUART SimulationInput is interactive or predefinedOutput is shown and saved independently forOutput is shown and saved independently for multiple UARTs


JTAG_UART Simulation JTAG_UART Simulation New

Text is transmitted to the new JTAG_UART peripheral during simulationCreates and saves txt fileCreates and saves txt file containing UART tx streamCreates window to input text at simulation run time


Note: ModelSim Options are mutually exclusive

Wave WindowWave WindowAdds UART and CPU signals by default


SignalTap™ II Logic AnalyzerSignalTap™ II Logic AnalyzerUp to 200 MHzMulti-Analyzer Supporty pp1,024 Channels128K Samples10 T i L l10 Trigger LevelsNo Probes!Can be usedCan be used simultaneously with the Nios II IDE debugger and the FS2 console!

Capture the state of internal nodesI t t f ll t d

the FS2 console!


In-system, at full system speeds

SignalTap™ II Logic AnalyzerSignalTap™ II Logic Analyzer


Lab 3RTL SimulationLab 3RTL SimulationRTL SimulationRTL Simulation

30 mins30 mins


Avalon Switch FabricAvalon Switch Fabric


Avalon Switch FabricAvalon Switch FabricProprietary interconnect specification used with Nios II

Principal design goals− Low resource utilization for

bus logicg− Simplicity− Synchronous operation

32-BitNios II

Switch PIO

LED PIO

Address (32)

Read

Write

Ava

Nios II Processor

Transfer Types− Slave Transfers− Master Transfers

Nios IIProcessor LED PIO

7-SegmentLED PIO

Data In (32)

Data Out (32)

alon Switch Master Transfers

− Streaming Transfers− Latency-Aware Transfers− Burst Transfers

PIO-32

User-ROM UART Ti

IRQ

IRQ #(6)

Fabric


Burst Transfers Defined Interface

ROM(with Monitor) UART Timer

Avalon Switch FabricAvalon Switch FabricCustom-Generated for Peripherals− Contingencies are on a Per-Peripheral Basisg p− System is Not Burdened by Bus Complexity

SOPC Builder Automatically Generates− Arbitration− Address Decoding

Data Path Multiplexing− Data Path Multiplexing− Bus Sizing− Wait-State Generation− Interrupts


Avalon Master PortsAvalon Master Ports

Initiate Transfers with Avalon Switch FabricTransfer TypesTransfer Types− Fundamental Read − Fundamental Write

All Avalon Masters Must Honor a waitrequest signalTransfer Properties− Latency

Streaming− Streaming− Burst


Avalon Slave PortsAvalon Slave Ports

Respond to Transfer Requests from Avalon Switch FabricSwitch FabricTransfer Types− Fundamental Read − Fundamental Write

Transfer Properties− Wait States− Latency− Streamingg− Burst


Slave Read TransferSlave Read Transfer

0 Setup Cyclesy0 Wait Cycles

A C D EBclk

address,be_n address, be_n

A C D EB

readn

chipselect

readdata readdata


Slave Read Transfer with Wait StatesSlave Read Transfer with Wait States

1 Setup Cycle1 Wait Cycle1 Wait Cycle

A B C D E F G Hclk

address,be_n

chipselect

address, be_n

A B C D E F G H

readn

readdata readdata

Tsu


Slave Write TransferSlave Write Transfer

0 Setup Cyclesy0 Wait Cycles0 Hold Cycles

A B C Dclk

address,be_n

writedata

address, be_n

writedata

A B C D

writen

chipselect


Slave Write Transfer with Wait StatesSlave Write Transfer with Wait States

1 Setup Cycle0 Wait Cycles0 Wait Cycles1 Hold Cycle

B C D E FA G

clk

address,be_n

writedata

address, be_n

writedata

B C D EA

writen

chipselect


Multiple Clock Domains SupportedMultiple Clock Domains Supported

MasterMasterMasterClock Domain 1


MasterClock Domain 1

MasterClock Domain 2

CDX


CDX

Arbiter

Slave Clock Domain 2


Slave Slave

Clock Domain 2Slave

Clock Domain 2Clock Domain 2Clock Domain 2

Clock Domain 2 Clock Domain 2


CDX = Clock Domain Crossing Logic (inserted automatically by SOPC Builder)

Multi-Clock Domain SupportMulti-Clock Domain Support

MasterMaster MasterMasterMasterClock

Domain 1

MasterClock

Domain 2Clock

Domain 1Clock

Domain 1

CDX

Arbiter

CDX

CDX

Arbiter

Slave


Slave


Slave Clock Domain 3

S a eClock Domain 2


CDX = Clock Domain Crossing Logic

User-Defined Custom PeripheralsUser-Defined Custom PeripheralsWhat if I need to add a peripheral not included with the Nios II system?y− user wants to add own peripheral to perform some kind of

proprietary function or perhaps a standard function that is not yet included as part of the Nios kitnot yet included as part of the Nios kit

− Expand or accelerate system capabilities

We are now going learn how to connect our own design directly to the Nios II system via Avalon

As many peripherals contain registers we could also have− As many peripherals contain registers we could also have chosen to connect to a PIO rather than directly to the bus


Creating Avalon SlaveCreating Avalon SlaveNo Need to Worry about Bus InterfaceImplement Only Signals NeededImplement Only Signals NeededPeripherals Adapted to by Avalon Switch Fabric


Timing Handled AutomaticallyFabric Created for YouA bit G t d f Y User

Register File

Arbiters Generated for You User Logic

Concentrate Effort onPeripheral Functionality!


Peripheral Functionality!

New Component EditorNew Component Editor


Creates InterfaceCreates InterfaceConnect to Existing HDL or board componentMap into Nios II Memory SpaceMap into Nios II Memory SpaceCan be “Inside” or “Outside” Nios II System

Nios IICPU

I/O

I/ONios IICPU

I/O

I/OCPU

Aval

on

I/O

I/O

I/O

CPU

Aval

on

/O

I/O

I/O

Interfaceto UserLogic

Nios II SystemModule

External User

Peripheral

I/O

InternalUser

PeripheralNios II System

Module

I/O


Module Module

Create External Component InterfaceCreate External Component Interface

To communicate with off-chip peripherals

AMD29LV065AD CFI Flash Chip

off chip peripheralsBase interface type on data sheeton data sheet


Or Add HDL FilesOr Add HDL FilesFor peripheral that has been encoded for FPGA


Tri-State PeripheralsTri-State PeripheralsRequire Tri-State Bridge− Available as an SOPC Builder componentp

n ate e e to

og

ic Off Chip Off Chip Nios II

Processor

Aval

o

Tri-S

taB

ridge

Inte

rface

Use

r Lo PeripheralPeripheral

Tri-State peripheral is defined by the presence of

FPGA

a bi-direction data portOff-chip peripherals do not have to be tri-state


Define Component SignalsDefine Component Signals

Automatically populates port table from design files

Enter port type hereEnter port type here

Can also define ports manually


Define Interface for Each Signal TypeDefine Interface for Each Signal Type

Choose interface type Register Slave uses native alignment Memory Slave usesalignment, Memory Slave uses dynamic alignment

Control Read and Write Timing Add wait and hold states View dd a t a d o d states ewaveforms


Address Alignment – Narrow SlaveAddress Alignment – Narrow Slave32-BitNios II

Processor

Av

32Peripheral Registers

Base

Base + 0x1

aa

bbProcessor

8 Bit Peripheral

valon 8

Base + 0x1

Base + 0x2

Base + 0x3

bb

cc

dd

Dynamic Address Alignment (set as Memory Slave)

Base + 0x4 ee

− LD from Base + 0x0: dd cc bb aa− LD from Base + 0x4: uu uu uu ee

Native Address Alignment (set as Avalon Register Slave)− LD from Base + 0x0: uu uu uu aa− LD from Base + 0x4: uu uu uu bb


− LD from Base + 0x8: uu uu uu cc

Address Alignment – Narrow MasterAddress Alignment – Narrow Master

Av

32 Memory Contents

Base 77 66 55 44 33 22 11 00

32-BitNios II

Processor

64 Bit Memory

valon 64Base + 0x8

Base + 0x16ff ee dd cc bb aa 99 88

?? ?? ?? ?? ?? ?? ?? ??

Processor

Dynamic Address Alignment− LD from Base + 0x0: 33 22 11 00− LD from Base + 0x4: 77 66 55 44− LD from Base + 0x8: bb aa 99 88

Native Address AlignmentNative Address Alignment− LD from Base + 0x0: 33 22 11 00− LD from Base + 0x4: bb aa 99 88

LD from Base + 0x8: ?? ?? ?? ??


− LD from Base + 0x8: ?? ?? ?? ?? − High bytes are unobtainable – warning issued

Add Software FilesAdd Software Filesie. Header files and drivers


Add Software FilesAdd Software FilesHeader file and drivers can also be added directly to Application Project


Create Component WizardCreate Component WizardPublish and create a wizard for your component

Fill in fields Add component to SOPC Builder portfolioSOPC Builder portfolioCan add parameterizing capability to component


Add Component to SOPC SystemAdd Component to SOPC System

Default location is the User Logic folder


Intel PXA255 ExampleIntel PXA255 Example


VLIO as an Avalon Master Port VLIOVLIO as an Avalon Master Port VLIO

Intel PXA255 Variable Latency I/O (VLIO) Uses a Bi-Directional Data Path, RDY Signal to Add Wait StatesInterface Separates DATA into Read Data & Write Data PathsInterface Separates DATA into Read Data & Write Data Paths


Relevant Verilog Code to Relevant Verilog C d t I l tRelevant Verilog Code to Relevant Verilog C d t I l tCode to ImplementCode to Implement


Lab 4Adding A User PeripheralLab 4Adding A User Peripheralg pg p

30 mins30 mins


Custom InstructionsCustom Instructions



Add custom functionality to the Nios II design− To take full advantage of the flexibility of FPGATo take full advantage of the flexibility of FPGA

Dramatically Boost Processing Performancey g− With no Increase in fMAX required

Application Examples− Data Stream Processing (eg. Network Applications)

Application Specific Processing (eg MP3 Audio Decode)− Application Specific Processing (eg. MP3 Audio Decode)− Software Inner Loop Optimization



Augment Nios II Instruction Set− Mux User Logic Into ALU Path of Processor Pipelineg p


Several Levels of CustomizationSeveral Levels of CustomizationOptional Interface to FIFO, Memory, Other Logic

dataa

32datab Combinatorial result

32

clk

clk_enreset Multi-Cycle done

3232

n Extended

resetstart

Internal R i t Fil

a

b 5

readra

readrb

8


Register File5

5

c writerc


Integrated Into Nios II Development Tools− SOPC Builder design tool handles op-code assignmentSOPC Builder design tool handles op code assignment− Generates C and assembly-language macros

Similar to Nios Custom Instructions Except− Up to 256 different custom instructions possible− Multi-cycle instructions can have variable duration− Parameterization of custom instructions has changed


Custom Instructions TabCustom Instructions TabEnabled from the Custom Instructions tab in the Nios II CPU settings in SOPC Builderg


Custom Instructions TabCustom Instructions TabImport logic for the custom instructionCustom Instruction module can be of followingCustom Instruction module can be of following formats:− VHDL− Verilog HDL− EDIF− Quartus Block Diagram (.bdf)Quartus Block Diagram (.bdf)


Combinatorial Custom InstructionsCombinatorial Custom Instructions

Port list− All Custom Instruction Modules need these ports

Port names must match exactly


Multi-Cycle Custom InstructionsMulti-Cycle Custom Instructions

Port list for Multi-Cycle Custom Instructions− Must have all of these ports with exact names


Extended Custom InstructionsExtended Custom InstructionsUses n[7..0] port to select an operation to perform.


Register File Custom InstructionsRegister File Custom InstructionsCustom instructions can select inputs from internal registers or dataa, datab portsCustom instructions can write results to an internal register file

dataa[31..0]

result[31..0]

CustomLogicreada writec

a[4..0]

c[4..0]


Software Interface - CSoftware Interface - CNIOS II IDE generates macros automatically during build process

Macros defined in system h fileMacros defined in system.h file#define ALT_CI_<your instruction_name>(instruction arguments)

Example of user C-code that references Bitswap custom instruction:#include "system.h"int main (void){

int a = 0x12345678;int a 0x12345678;int a_swap = 0;

a_swap = ALT_CI_BSWAP(a);return 0;return 0;

}


Assembly Language Interface Assembly Language Interface Assembler syntax for the custom instruction:

custom N rC rA rBcustom N, rC, rA, rB

Custom Custom instruction instruction

opcode opcode numbernumber

Destination Destination register register

for resultfor result

Operand 1Operand 1 Operand 2Operand 2

Two Examples:r = Nios II processorr = Nios II processorcustom 0, r6, r7, r8

custom 3, c1, r2, c4

r = Nios II processor r = Nios II processor registerregister

c = Custom instruction c = Custom instruction internal registerinternal register


Why Custom Instruction?Why Custom Instruction?Reduce Complex Sequence of Instructions to One InstructionExample: Floating Point Multiply

float a b result slow result fast;float a, b, result_slow, result_fast;

result_slow = a * b; /* Takes 266 clock cycles */result_fast = ALT_CI_fpmult(a,b); /* Takes 6 clock cycles*/

Typical Flow

Significantly Faster!Typical Flow− Profile Code− Identify Critical Inner Loop− Create Custom Instruction LogicCreate Custom Instruction Logic

Replace One or All Instructions in Inner Loop− Import Custom Instruction Logic into Design− Call Custom Instruction from C or Assembly


Call Custom Instruction from C or Assembly

Custom Instruction vs PeripheralCustom Instruction vs Peripheral

Custom Instruction can execute in a single cycle− No overhead for call to custom HardwareNo overhead for call to custom Hardware

Custom Custom InstructionInstructionL1

L0L0

Access to same hardware as peripheral takes multiple cycles− Write DataA, then write DataB, and finally read Result

Result0x408

Peripheral memory map

DataBDataA

0x400

0x404

CustomCustomL0


Custom Custom PeripheralPeripheralL1

L0L0

Multi-Cycle Custom InstructionsMulti-Cycle Custom Instructions

Processor stalls while awaiting resultCl k l 3− Clock cycles = 3

DataA DataB

REGREG

truct

ion

custom

Cyc

les

REGREG usto

m In

st---

---

Next Instrios

Clo

ck C

CuNext InstrNi


Result

Pipelined Custom InstructionsPipelined Custom Instructions

Result not always needed for each inputCl k C l 1− Clock Cycles = 1

− Route start sig to reg clk_enDataA DataB

REGREG

truct

ion

custom

es t

REGREG usto

m In

st

Clo

ck C

ycle

custom

custom

custom

Cu

Next Instr

Nio

s C custom

custom


ResultNext Instr

Accelerating CRCAccelerating CRC

Implementing the shift and XOR for each bit takes many clock cycles ~50bit takes many clock cycles ~50Software algorithms tend to use look up t bl t t h b ttables to pre-compute each byteParallel Hardware is fastest

ft ft ft

in(15) in(14) in(0)

reg

xor/s

hif

xor/s

hif

xor/s

hif


CRC Custom InstructionCRC Custom Instruction

CRC16-CCITT needs to be preset to 0xFFFF at the start of each computationthe start of each computationCan use the Data B input to select between run and loadand load− Use of prefix would waste a clock cycle

CRCCustom Instruction

D A(31 0)

// reset crc ALT_CI_CRC(0xFFFF,1);

// run crc

Control

DataA(31-0)

DataB(0)

// run crc ALT_CI_CRC(word,0);

Data in

Init / nRun

CRC Reg Result(15-0)


Multi-Masters and Direct Multi-Masters and Direct Memory Access (DMA)Memory Access (DMA)


Traditional Multi-MastersTraditional Multi-Masters

Direct Memory Access (DMA)P W it F B D i DMA− Processor Waits For Bus During DMA

System CPU 100Base-TMasters(Master 1) (Master 2)

DMA B A bit Arbiter DeterminesC t lSystem

B l k DMA Arbitor

System Bus

DMA Bus Arbiter Arbiter Determines Which Master Has Access To Shared

Bus

Control direction

Bottleneck

I/O1

I/O2 Data

MemoryProgramMemorySlaves


yySlaves

Avalon Simultaneous Multi-Mastering BusAvalon Simultaneous Multi-Mastering Bus

Has Benefits of a Switch Fabric and Slave-Side Arbitration− Shared Bus & Share Arbiter are No Longer the Bottleneck

M lti l M t T ti C O t Si lt l− Multiple Master Transactions Can Operate Simultaneously As long as they don’t access the same slave in the same bus bycle

− I/O Devices Can be Grouped Based on Bandwidth RequirementT d OffTrade-Off − Hardware Resource Usage Increases Uses Fairness

Arbitrationautomatically automatically generated by generated by

CPU 0CPU 0 DMADMA

System Switch

Masters

SOPC BuilderSOPC Builder

CPU 1CPU 1

DisplayC t lDisplayC t l

Program M 0Program M 0 I/OI/O Custom

F tiCustomF ti

Data M 1

Data M 1

Switch Fabric

Program M 1Program M 1

Data M 0

Data M 0

ArbiterArbiter

Slaves

ArbiterArbiter


ControlControlMemory 0Memory 0 FunctionFunctionMemory 1Memory 1 Memory 1Memory 1Memory 0Memory 0

DMA PeripheralDMA PeripheralProvides Bus Master Capability to Any Nios II Peripheralp− FIFO Depth = 2

DMA Peripheral

Master Port1

Start Addr

Master Port2

Start Addr

FIFO

Start Addr

# Bytes

Addr Incr

Start Addr

# Bytes

Addr Incr

Control Port

Direction


Data Flow with DMA PeripheralData Flow with DMA PeripheralMaster 1

(Nios II CPU)SPI

I D

Master 2DMA

I D

Avalon Avalon

Arbiter

I/O1Program

MemoryData

Memory

I/O2


Memory 1

Accelerate Software ExecutionAccelerate Software ExecutionUse custom hardware peripheral with DMA− Processor & Accelerator Run Concurrently− More Work Per Clock− Lower fMAX, Power, Cost

Processor

DM

AD

MA

DM

AD

MAAccelerator

ArbiterArbiter ArbiterArbiterAvalonSwitch Fabric

ProgramMemory

DataMemory

DataMemory

Fabric


Accelerate Software ExecutionAccelerate Software ExecutionExample: CRC Algorithm (64 Kbytes)

20,000,000

25,000,000

15,000,000

, ,

lock

Cyc

les

53027

5,000,000

10,000,000Cl 530

TimesFaster

27 TimesFaster

HardwareAccelerator

0Software Only Custom

Instruction


Custom Streaming Slave PeripheralsCustom Streaming Slave Peripherals

For using DMA with other slow peripherals E l UART− Example: UART

Adds up to three outputs to Avalon Slave− dataavailable− readyfordata

control

adress

− endofpacket

Aval

on

Custom Custom StreamingStreaming

Sla eSla ereaddata

writedata

control

AvSlave Slave PeripheralPeripheral

endofpacket

Readyfordata

dataavailable


endofpacket

Streaming Slave Peripheral SignalsStreaming Slave Peripheral Signals

dataavailable− Indicates that the peripheral has data available to be readIndicates that the peripheral has data available to be read

by DMA or other master− ie, there is data in the rx buffer or register

readyfordata− Indicates that the peripheral is able to receive data written

by DMA or other masterby DMA or other master− Ie. the tx buffer or register is not full

endofpacketp− Usage not defined− DMA can be optionally set to end transfer


Custom Master PeripheralsCustom Master Peripherals

Can integrate DMA function− Eg VGA that takes data from memory directlyEg. VGA that takes data from memory directly

Simpler than Slave peripherals− Assert outputs until waitrequest is lowp q

Transaction are between Master and Avalon, not Slave

onCustom Custom control

address

Aval

o

Master Master PeripheralPeripheral

waitrequest

readdata

writedata


Master Read TransferMaster Read Transfer

Assert addr, be, readW it f it t ‘0’Wait for waitrequest = ‘0’Read in DataEnd of transfer


Master Write TransferMaster Write Transfer

Assert addr, be, readA t W it D tAssert Write DataWait for waitrequest = ‘0’End of transfer


Avalon Master-Slave ConnectionsAvalon Master-Slave Connections

View => Show Master ConnectionsObserve and configure Avalon connectionsObserve and configure Avalon connections


Master Arbitration SchemeMaster Arbitration SchemeNios II Multi-Master Avalon Switch Fabric Utilises Fairness Arbitration Scheme− Each Master/Slave pair is assign an integer “shares”− Upon conflict Master with most shares takes bus until all

shares are usedshares are used− Master with least shares then takes bus until all shares are

used− Assuming all Masters continuously request the bus they will− Assuming all Masters continuously request the bus, they will

each be granted the bus for a percentage of time equal to the percentage of total master shares that they own

CPU

SPI DMA 1 share

7 Shares


PCI DMA 2 shares

1 share

Set Arbitration PrioritySet Arbitration PriorityView => Show Arbitration Priorities


Avalon Arbitration BehaviorAvalon Arbitration Behavior

Master A Shares = 4Master A Master B

Master B Shares = 2Master A Master B

Arbiter

Slave

Arbiter (continuous accesses)

Master B

Master A


Master B

L b 5L b 5Lab 5Custom Instruction and Lab 5Custom Instruction and (optional) DMA Controller(optional) DMA Controller45 mins45 mins


45 mins45 mins

Working with the Development BoardWorking with the Development BoardDevelopment BoardDevelopment Board


Ensure Unused I/O are Tri-StateEnsure Unused I/O are Tri-StateThe FPGA may connect to components on the board not used by your designy y gThere is a connection between FPGA and MAX device to force reconfiguration

A ti l ll d hi h− Active low, pulled high

Assignments -> Device …For Stratix devices, be sure to set Dual Purpose pins toFor Stratix devices, be sure to set Dual Purpose pins to “Use as Regular IO”


Clock DistributionClock Distribution

FPGA Nios IINios II

w SDRAMSDRAM

PLLPLL

Zero

Ske

wB

uffe

r

ro S

kew

B

uffe

rCLK in

(50 MHz)

PLL required to meet SDRAM I/O timing

Zer B( )

PLL required to meet SDRAM I/O timing− Introduces -60° phase shift relative to Nios II

CLK in is socket crystal or external inputCLK in is socket crystal or external input− Resistor changes required for external

See board schematic and ref design


See board schematic and ref design

Hardware Configuration ProcessHardware Configuration ProcessFlash Configuration− Two FPGA images

Data

8 MB Flash

Stratix

Safe FPGA Safe FPGA ImageImage

0x700000o G agesSafe ImageUser Image A

ddrStratix

User FPGA Image

0x600000

0x700000

MAX® EPM7128 Configures FPGA from Flash

MAX

ress

− Upon power up or press of Reset ConfigMAX Device Loads User Image into FPGAIf Thi F il MAX D i L d S f IIf This Fails MAX Device Loads Safe Image

− Failure includes no user image present

− Upon press of Safe Config


MAX Device Loads Safe Image into FPGA

Flash Memory ConfigurationFlash Memory Configuration8 MB FlashSafe FPGA Safe FPGA

Image & S/WImage & S/W0x700000

Data

Stratix

User FPGA Image

0x600000

0x700000

Addres0x400000

0x500000

SRAMss

0x300000 User User SoftwareSoftware

0x100000

0x200000


0x000000

Configuration of FPGA From FlashConfiguration of FPGA From Flash

Data0xE00000

0x1000000

Stratix 0xC000008 MB RAM

0x800000

0xA00000Nios II

Controller

Safe FPGA Image Safe FPGA Image & S/W& S/W

User FPGA Image

0x600000

8 MB Flash

0x200000

0x400000

ApplicationApplicationCodeCode

ApplicationApplicationCodeCode

StartStart--up Codeup Code


0x000000

StartStart--up Codeup Code

Boot CopierBoot Copier

Loading RAMLoading RAM

Data0xE00000

0x1000000

Dynamic Dynamic MemoryMemory

Stratix 0xC000008 MB RAM

Application Application

MemoryMemory

0x800000

0xA00000Nios II

ppppCodeCode

StartStart--upup CodeCode

Safe FPGA Image Safe FPGA Image & S/W& S/W

User FPGA Image

0x600000

8 MB Flash

0x200000

0x400000ApplicationApplication

CodeCodeStartStart--up Codeup Code


0x000000Boot CopierBoot CopierStartStart--up Codeup Code

Boot CopierBoot CopierUse Flash for Program Storage

Running from Flash is slow

Data

Stratix User −Running from Flash is slow

Nios II IDE Automatically Prepends Boot Copier to

Addr

Stratix Software

Prepends Boot Copier to Program Code− if Reset Address is in Flash and

Program Memory is in RAM

SRAM

ress

8 MB Flash

For Custom Boards:(see again “Nios II Flash Boot Copier

fl h( gProgrammer User Guide”)− Must create your own flash

programmer design to transport data to the flash on your board

my_sw.elf

pmy_sw.flash


y

Nios II Flash ProgrammerNios II Flash ProgrammerDownloads flash content to CFI flash device− Communication is over JTAG interface− Can also download to any Altera EPCS Serial Configuration

Device connected to FPGA

Two step process:Two-step process: − Send Flash Programmer Design− Send Flash Content

Flash ContentFlash Content


Nios II Flash ProgrammerNios II Flash ProgrammerFlash Programmer Design contains− Nios II CPU− JTAG UART− Active serial memory interface

Tri state bridge− Tri-state bridge− CFI-compatible flash interface− System ID peripheral on-chip memory for firmware and buffers

Flash Content can include: − FPGA hardware configuration image

S ft t t− Software content− Arbitrary content


Nios II Flash ProgrammerNios II Flash ProgrammerCan program Flash from Nios II IDE or command line− Nios II IDE is recommended method


Nios II Flash ProgrammerNios II Flash ProgrammerCommand Line Utilities− elf2flash

− sof2flash

− Bin2flash

− elf2hex

− nios2-flash-programmerp g

(see “Nios II Flash Programmer User Guide” for details)


(see Nios II Flash Programmer User Guide for details)

Instantiating Flash in Target SystemInstantiating Flash in Target SystemMust set target board to appropriate development kit

Need CFI (Common Flash Interface) Flash Memory( ) y

EPCS Serial Flash Controller req’d if booting from EPCS device


Flash Programmer DesignFlash Programmer DesignWhat if I Have a Custom Board?

Import board settings into the SOPC Builder using− Import board settings into the SOPC Builder using mk_target_board script

Specify flash devices and designator numbersClock frequency Device family

C f SO C− Create flash programming design in SOPC Builder based on .PTF generated from above script

Generate SOF file for flash design− Generate .SOF file for flash design

See Nios II Flash Programmer User Guide for details


What If Safe Flash Image Overwritten?What If Safe Flash Image Overwritten?Open Nios II SDK Shell− Start > Programs > Altera > Nios II Development Kit

<installed version> > Nios II SDKShell

Change to factory-recovery directory for your development kitdevelopment kit− cd examples/factory_recovery/niosII_cyclone_1c20

Run flash-restoration scriptp− ./restore_my_flash

Follow the script’s instructions


Lab 6Lab 6Lab 6The Flash ProgrammerLab 6The Flash Programmer

10 mins10 mins


Thank YouThank YouThank YouThank You


Nios

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