Nios II Compact Configuration System for Cyclone V …Author: Paul Mayer Date: July 2016 Revision:...
Transcript of Nios II Compact Configuration System for Cyclone V …Author: Paul Mayer Date: July 2016 Revision:...
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Author: Paul Mayer
Date: July 2016
Revision: 1.0
Nios II Compact Configuration System for
Cyclone V DE0-CV
(Ported from Nios II Compact Configuration System for Cyclone V)
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Contents
INTRODUCTION ............................................................................................................................................. 3
Active Serial (AS) Configuration Scheme .................................................................................................. 3
Cyclone V Remote Update ........................................................................................................................ 4
EXAMPLE DESIGN .......................................................................................................................................... 5
Build Images .............................................................................................................................................. 6
Combine Images........................................................................................................................................ 9
Program Configuration Device ................................................................................................................ 10
Run the Design ........................................................................................................................................ 12
SUMMARY ................................................................................................................................................... 12
REFERENCE .................................................................................................................................................. 12
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INTRODUCTION
This example design is ported from the previous example design: Nios II Compact Configuration
System for Cyclone V. It demonstrates how to use Nios II processor to actively manage two
configuration images (a “Factory Image” and an “Application Image”) from an external flash. The
main difference between this design and the previous design on Cyclone III is the configuration
schemes being used. This design based on Cyclone V uses Active Serial (AS) configuration
scheme while the previous one based on Cyclone III uses Active Parallel (AP) configuration
scheme. Both Cyclone III and Cyclone V have built-in remote update circuitry which supports
the reconfiguration feature. These will be discussed in detail later.
This design is optimized to achieve the smallest possible utilization of FPGA resources and
software code footprint. You can easily adapt this design to any existing design to add
reconfiguration capability to the application.
Active Serial (AS) Configuration Scheme
First let’s talk about the difference between active configuration and passive configuration.
Active configuration allows an intelligent controller within the FPGA (such as the Nios II
processor) to perform configuration while passive configuration relies upon an external
controller (e.g. a microprocessor or a Complex Programmable Logic Device (CPLD)) to
configure the FPGA.
The DE0-CV Kit supports the AS configuration scheme. The configuration bit stream is
downloaded into the Altera EPCS64 serial configuration device. EPCS is an in-system
programmable NOR flash memory. This configuration is non-volatile, which means the
information is retained even when the power is turned off. When the board’s power is turned on
again, the configuration data in EPCS64 is automatically loaded into DE0-CV FPGA. For more
information about this device, click here.
To enable the AS configuration scheme for Quartus II design, perform the following steps in the
Quartus II software:
1. On the Assignments menu, click Device.
2. On the Device page, click Device and Pin Options.
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3. Click the Configuration tab and change settings as shown in
4. Figure 1.
5. Click OK.
Here the configuration scheme is chosen as AS × 1.
Figure 1 Configuration Setting in Quartus II
Cyclone V Remote Update
Cyclone V has built-in remote update circuitry, which allows you to update the system from a
remote location through a communication interface. Figure 2 shows the remote update mode of
Cyclone V. After the board is powered up, the factory image (stored at Page 0) will be loaded
automatically. Then the user can reconfigure the FPGA with an application image through
setting control registers. Note that for Cyclone V, if you want to reconfigure another application
image while the FPGA is now in an application configuration, you have to go back to the factory
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configuration first and then trigger the other application configuration. Also, if there is any error
during the configuration process, FPGA will be reconfigured with factory configuration again.
In this example design, we have two images stored at different address of EPCS64. The factory
image is stored at address 0x0 and the application image is stored at address 0x00320000.
These two images are symmetric. In factory configuration, you can push a button to trigger the
reconfiguration of the application image. In application image, you can push a button to trigger
the reconfiguration of factory image. Thus you can switch between these two configurations.
You can use Altera Remote Update IP Core to achieve the reconfiguration easily. To use
remote update feature, you also need to change the configuration mode to “Remote” in Quartus
II, as shown in Figure 1.
Figure 2 Cyclone V Remote Update Mode
EXAMPLE DESIGN
This example design is built in Quartus II 15.1, targeted to DE0-CV. You can download this
design from Altera Design Store: https://cloud.altera.com/devstore/platform/15.1.0/nios-ii-
compact-configuration/
You can build a folder called “compact_config_CV_factory” and put the .par file you downloaded
here. Start a new Quartus II project from this template. After this, you will see a Quartus
archive file called “compact_config_CV_application.qar” in this folder. Build another folder called
“compact_config_CV_application” and move the .qar file to it then restore the archived project
(The reason this project is packaged this way is because of the regression test requirements of
Altera Design Store.
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Now you have two project folders, one for factory image and one for application image. The
subfolder “software” inside these two folders contains the archived software project respectively.
You can import them to Nios II SBT in Eclipse to restore the workspaces. Factory image and
application image are basically the same except some slight difference: blinking different LEDs,
detecting different Push Button interrupts, and reconfiguring from different addresses.
Figure 3 shows a diagram of the design flow. We’ll talk about them in details later.
In the “master_image” folder in “compact_config_CV_factory”, there are two .sof files, one .jic
file and one .pof file, which are ready for programming. If you don’t want to build this project you
can skip the “Build Images” section below and use these programming files to achieve the
following steps.
Figure 3 Design Flow
Build Images
The hardware design is mainly implemented in Qsys, with the declaration of ports in Quartus
project. Figure 4 shows the block diagram of the hardware design. The Nios II/e controls the
active configuration. PLL is used to take the 50 MHz source clock and generate a 40 MHz clock
used by the Altera Remote Update module (the clock of this IP core must be no larger than 40
MHz). JTAG-UART is used for printing message in the console and for debug purpose.
EPCS64
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Figure 4 Hardware Design Block Diagram
In order to enable the use of interrupt of push buttons, we need to set the parameters for Push
Button PIO, as shown in Figure 5. Right-click on the “button” IP and selected “Edit.” Also,
remember to set an IRQ number for JTAG interrupt and PIO interrupt respectively.
Figure 5 PIO Parameters Setting in Qsys
To use Altera Remote Update (RU) properly, set configuration mode and device to the one we
are using and remember to check “Add support for Avalon Interface” and “Add support for
writing configuration parameters”, as shown in Figure 6.
EPCS64
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Figure 6 Altera Remote Update Parameter Setting in Qsys
Most functions in this design are implemented in the Nios II SBT in Eclipse. Figure 7 shows the
software program flow chart.
The Push Button PIO is initialized at the beginning of the software execution. The initialization
process includes enabling the PIO interrupt, resetting the interrupt edge capture register, and
registering the interrupt handler. The program prints messages to the host and blinks the LED,
indicating which configuration image is in use. The LED keeps on blinking until a push button is
pressed, which triggers the reconfiguration of another image.
Note there are some nuances in setting the address for reconfiguration. Depending on the
Quartus version, FPGA family and configuration device, you may need to shift the address by
certain bit so as to write proper value to the register. For more information, please refer to the
Altera Remote Update IP User Guide. For this design, we don’t need to shift the address.
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Figure 7 Flow Chart of the Software Program
After finishing the software design, we can generate a .hex for memory initialization. Right click
the project name in Eclipse and choose “Make Targets” -> “Build”, then click
“mem_init_generate” and click “Build”. A “niosII_onchip_memory.hex” file will be generated
under the folder “mem_init” under the Eclipse project.
Go back to Qsys and initialize the on-chip RAM with the .hex file we just generated.vi The
purpose is to integrate the Nios II executable into the hardware image, or rather, the .sof file.
Generate HDL again and compile the Quartus project. After compilation, we have a complete
image with both hardware design and software design.
Combine Images
After building factory image and application image, we have two separate .sof files. You can
also find the pre-built ones in the “master_image” folder: “compact_config_CV_factory.sof” and
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“compact_config_CV_application.sof”. In order to program the EPCS64 device, we need to
combine these two files to a .pof file or a .jic file.
Quartus II provides a convenient GUI for converting files. Launch it from “File” -> “Convert
Programming FIles”.
A .pof file (Program Object File) is a binary file used to program flash, such as the configuration
device EPCS64. Set parameters correctly, as shown in Figure 8. You can name the converted
file whatever you want and save it at a place that works for you. Click the button on the lower
right to add a sof page. Add a .sof file for each page. You can change the start address and end
address of each page by clicking it first and then click properties. In this case, the factory image
is stored at address 0x0, while the application image is stored at address 0x320000. Note that
the address has to be consistent with the one you set in your Nios II software and they have to
be started with the start of a subsector as specified in the EPCS Datasheet. Same for the end
address. Also, you can compress the file by checking the “compression” choice in the properties
of the two .sof files. This will make the .pof file to be generated smaller and make programming
faster. After finishing all the settings, hit “Generate” to generate the .pof file.
Figure 8 Covert Programming File (.pof)
A .jic file (JTAG Indirect File) is a binary file that contains not only the configuration data but also
a flash loader. Therefore you can use the JTAG chain to program the flash. Figure 9 shows the
setting for converting the two images to a .jic file. It’s pretty much like the previous one for .pof
file except that there is a Flash Loader at the beginning. Add device for the flash loader. In our
case, it’s 5CEBA4. After finishing all the settings, hit “Generate” to generate the .jic file.
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Figure 9 Covert Programming File (.jic)
Program Configuration Device
In Quartus, launch Programmer from “Tools” -> “Programmer”. The .pof file and .jic file are
equivalent. We’ll introduce how to program them respectively in this section. You can just
choose to program one of them.
Programming a POF File
To program the .pof file, set the mode to “Active Serial Programming” then click “Add File”.
Choose the .pof file we just generated. The device chain will show automatically, as shown in
Figure 10. Check the column under “Program / Configure” and Click “Start” to start
programming. This may take several minutes.
Before programming, make sure the configuration switch SW11 is switched to “PROG”. Switch
it back to “RUN” before running the design (after you turn the board off).
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Figure 10 Programmer Setting for Programming .pof File
Programming a .jic File
To program the .jic file, set the mode to JTAG then click “Auto Detect” and choose the correct
device. Double Click on the file and change it to the .jic file we just generated. The device chain
will show automatically, as shown in Figure 11. Check in the column “Program / Configure” and
Click “Start” to start programming. This may take several minutes. SW11 should be at “RUN”
to program the .jic file.
Figure 11 Programming Setting for Programming .jic File
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Run the Design
After programming the configuration device successfully, power off the board and power on
again. Cyclone V will be configured with the factory image of EPCS64 first. You will see LED2 is
on and LED0 is blinking. The following message will be printed in the Nios II console:
You can press Push Button 1 to trigger the reconfiguration of the application image. You will get
a message telling you that Push Button 1 is pressed and asks you to start a new terminal for the
application image. You can see LED3 is now on and LED1 starts blinking. After starting a new
terminal, you will see the following message:
Similarly, now you can press Push Button 0 to trigger the reconfiguration of the application
image. You will get a message telling you that Push Button 0 is pressed and asks you to start a
new terminal for the factory image. Also, you will see LED2 is on and LED0 starts blinking
again. In this way, you can switch between the factory image and the application image easily.
Remember programming in EPCS64 is non-volatile so data will not disappear after the power is
turned off. Every time you power the device on, it will start configuration with the factory image.
SUMMARY
This design aims at demonstrating the active configuration feature of the DE0-CV. It allows the
user to use a push button to control the reconfiguration. It’s also a good example design for the
Altera Remote Update IP core. This design only has two configuration images; users can add
more according to the design requirements.
REFERENCES
1. Nios II Compact Configuration for Cyclone V GC Starter Kit:
https://cloud.altera.com/devstore/platform/15.1.0/nios-ii-compact-configuration/
2. AN 548: Nios II Compact Configuration System for Cyclone III
https://www.altera.com/content/dam/altera-
www/global/en_US/pdfs/literature/an/an548.pdf
3. Remote Update for Cyclone V
http://www.alterawiki.com/wiki/Remote_update_for_Cyclone_V
4. EPCS Devices Datasheet
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https://www.altera.com/content/dam/altera-
www/global/en_US/pdfs/literature/hb/cfg/cyc_c51014.pdf
5. Altera Remote Update IP Core User Guide
https://www.altera.com/content/dam/altera-
www/global/en_US/pdfs/literature/ug/ug_altremote.pdf
6. Remote System Upgrade Lab (Max 10 Development Kit Board)
http://www.alterawiki.com/uploads/b/b8/Remote_System_Upgrade_Lab_-
_Development_Kit.pdf
7. Generic Nios II Processor Booting Guide
https://www.altera.com/content/dam/altera-
www/global/en_US/pdfs/literature/ug/niosii_generic_booting_methods.pdf