NGMP-DASIA10-Paper.pdf

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NEXT GENERATION MULTIPURPOSE MICROPROCESSOR

Jan Andersson(1), Jiri Gaisler(1), Roland Weiand(!)

(1)Aeroflex Gaisler, Kungsgatan 12, SE-411 91, Gteborg, Sweden, !an,!iri"#gaisler$%o&

(2)Euro'ean S'a%e Agen%, Ke'lerlaan 1 *+ ox 299, 222AG .oordw!i/ 0, 3e .et3erlands,

roland$weigand#esa$int

A"STRACT

The Next Generation Multipurpose Microprocessor(NGMP) is a SPARC V8(E) based ulti!core architec!

ture that pro"ides a si#ni$icant per$orance increase

copared to earlier #enerations o$ European space pro!

cessors% The NGMP is currentl& in de"elopent atAero$lex Gaisler in G'tebor# Seden in an acti"it&

initiated b& the European Space A#enc& (ESA)%

This paper describes the baseline architecture points out

*e& choices that ha"e been ade and ephasises desi#ndecisions that are still open% The so$tare tools and op!

eratin# s&stes that ill be a"ailable $or the NGMP to!#ether ith a #eneral o"er"ie o$ the ne +E,N-.T

icroprocessor are also described%

1 "AC#GROUN$

The +E,N pro/ect as started b& the European Space

A#enc& in late 0112 to stud& and de"elop a hi#h!per!$orance processor to be used in European space pro!

/ects% The ob/ecti"es $or the pro/ect ere to pro"ide an

open portable and non!proprietar& processor desi#ncapable to eet $uture re3uireents $or per$orance

so$tare copatibilit& and lo s&ste cost% Another ob!/ecti"e as to be able to anu$acture in a Sin#le E"ent

4pset (SE4) sensiti"e seiconductor process% To ain!tain correct operation in the presence o$ SE4s extens!

i"e error detection and error handlin# $unctions ereneeded% The #oals ha"e been to detect and tolerate one

error in an& re#ister ithout so$tare inter"ention andto suppress e$$ects $ro Sin#le E"ent Transient (SET)

errors in cobinational lo#ic%

The +E,N $ail& includes the $irst +E,N0 V5S6C

5ardare 7escription +an#ua#e (V57+) desi#n thatas used in the +E,NExpress test chip de"eloped in

%9: ; technolo#& to pro"e the $ault tolerance concept%The second +E,N9 V57+ desi#n as used in the pro!

cessor de"ice ATenand the acti"it& is currentl& in its architectural desi#n

phase% The de"elopent or* is scheduled to be $in!ished b& the 0sto$ 7eceber 90%

.i#% 0 depicts an o"er"ie o$ the NGMP architecture%The s&ste ill consist o$ $i"e A5? buses@ one 098!bit

Processor bus one 098!bit Meor& bus to =9!bit 6,buses and one =9!bit 7ebu# bus% The Processor bus

houses $our +E,N-.T cores connected to a shared +9cache% The Meor& bus is located beteen the +9 cache

and the ain external eor& inter$aces 77R9S7RAM and S7R S7RAM inter$aces on shared pins

and it ill include a eor& scrubber and possibl& on!

chip eor&% As an alternati"e to a lar#e on!chipeor& part o$ the +9 cache could be turned into on!chip eor& b& cache!a& disablin#%

The to separate 6, buses house all the peripheralcores% All sla"e inter$aces ha"e been placed on one bus

(Sla"e 6, bus) and all aster7MA inter$aces ha"ebeen placed on the other bus (Master 6, bus)% The Mas!

ter 6, bus connects to the Processor bus "ia an A5?brid#e that pro"ides access restriction and address trans!

lation (6,MM4) $unctionalit&% The to 6, buses in!clude all peripheral units such as tiers interrupt con!

trollers 4ARTs #eneral purpose 6, port PC6

astertar#et 5i#h!Speed Serial +in* Ethernet MACand SpaceBire inter$aces%

The $i$th bus a dedicated =9!bit 7ebu# bus connects a

debu# support unit (7S4) PC6 and A5? trace bu$$ersand se"eral debu# counication lin*s% The 7ebu# bus

allos $or non!intrusi"e debu##in# throu#h the 7S4and direct access to the coplete s&ste as the 7ebu#

bus is not placed behind an A5? brid#e ith access re!striction $unctionalit&%

The tar#et $re3uenc& NGMP desi#n is - M5> butdepends ultiatel& on the AS6C technolo#&%


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All 6, aster units in the s&ste contain dedicated

7MA en#ines and are controlled b& descriptors located

in ain eor& that are set up b& the processors% Re!ception o$ $or instance Ethernet and SpaceBire pac*ets

ill not increase CP4 load% The cores ill bu$$er in!

coin# pac*ets and rite the to ain eor& ithout

processor inter"ention%

!'1 LEON Miro*roessor and L! Ca+e

The +E,N- processor is the latest processor in the

+E,N series% +E,N- is a =9!bit processor core con!$orin# to the 6EEE!02:- (SPARC V8) architecture% 6t

is desi#ned $or ebedded applications cobinin# hi#hper$orance ith lo coplexit& and lo poer con!

suption% +E,N- ipro"eents o"er the +E,N= pro!cessor include

?ranch prediction

0!2-.e

/e.+

(ns)

Ma3' 24'

0!2-.e

a+e line

(M"5s)

Min

s-s'

/re6'

(M%7)

Ma3'

s-s'

/re6'

(M%7)

S7R PC0 0 =9 ! -

77R!- : :== 8< -

77R9!8 -9%: :09


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-77R9!8 eories re3uire hal$ the tie or less

to deli"er =9 b&tes o$ data copared to PC0 S7RAM%

=9 b&tes is the cache line si>e that ill be used b& the+9 cache% The third colun shos the axiu sus!

tainable bandidth hen $etchin# se"eral =9!b&te cache

lines bac*!to!bac*% 6n this case 77R eories o$$er

better per$orance copared to 77R9 eories% Thisis due to the cache line si>e ith lon#er cache lines alon#er burst eor& burst len#th can be used and

77R9 eories ill e"entuall& outper$or 77Reories since the actual data ill be $etched at a hi#h!

er cloc* $re3uenc& hen usin# 77R9 S7RAM%

The iportance o$ the iniu tie re3uired to $etchone sin#le cache line "ersus the axiu sustainable

bandidth hen $etchin# se"eral cache lines is hi#hl&

application dependent and depends on paraeters suchas eor& $ootprint and data access patterns% ,ne ob!

ser"ation that can be ade is that +9 cache hit rate canindeed be *e& to hi#h per$orance especiall& in MP

s&stes% The tar#et cloc* $re3uenc& o$ the NGMP is- M5> hich #i"es a cloc* period o$ 9%: ns% ,ne

cache line $etch $ro 77R9!8 eor& ill in otherords ta*e 02 cloc* c&cles% A hit in the +9 cache eans

that the data ill be deli"ered in less than one third o$the tie re3uired to access external eor&%

!'0 I5O In.er/aes

An earl& desi#n decision as to onl& include hi#h!speed

6, inter$aces on!chip hile le#ac& lo!speed inter!$aces can be placed in a copanion chip (.PGAAS6C)%

The reason $or this decision is that lo!speed inter$acessuch as CAN 69C 0::= 4ARTs etcetera do not #ener!

ate enou#h data rates to re3uire 7MA capabilities andcan easil& be ipleented o$$!chip and connected to the

NGMP usin# one o$ the hi#h!speed inter$aces% 5oe"era set o$ standard peripherals re3uired $or operatin# s&s!

te support is included on!chip% These include support

$or siple eor& apped 6, de"ices to basic con!sole 4ARTs and one 0

rupts and siple control%

The hi#h!speed inter$aces that are intended to be used in$li#ht are $our SpaceBire lin*s to 000 Mbit

Ethernet lin*s $our hi#h!speed serial lin*s and one =9!

bit PC6 9%= astertar#et inter$ace%

!'0'1 PCI In.er/ae

The currentl& used AT


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A 4S? 7ebu# Counications +in* (4S?7C+) core

pro"ides a debu# connection ith relati"el& hi#h band!

idth (9 Mbits)% The ide adoption o$ 4S? ill allothe NGMP s&ste to be debu##ed $ro nearl& an&

odern or*station ithout the need $or con$i#uration

that is norall& re3uired hen usin# an Ethernet 7ebu#

Counications +in*%The HTAG counication lin* pro"ides a lin* ith aodest bandidth o$ around : *bits t&picall& li!

ited b& the HTAG adapter% Bith odern 4S? HTAG ad!apters hoe"er it is possible to run the HTAG cou!

nication lin* at < Mbits%

A dedicated SpaceBire RMAP tar#et as included on

the 7ebu# bus in order to accoodate users ho usethe NGMP in SpaceBire netor*s% Bith a dedicated

SpaceBire debu# lin* it becoes eas& to use existin#in$rastructure to control the NGMP s&ste% The

SpaceBire RMAP tar#et ill t&picall& pro"ide a debu#

lin* bandidth o$ 9 Mbits%

!';


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!'@ Tare. .e+nolo-

?aseline is the European ST


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,ther operatin# s&stes that are alread& ported to

+E,N=- include

+&nx,s (+&nuxBor*s)

Thread (Express +o#ic)

Nucleus (Mentor Graphics)

Aero$lex GaislerLs bootloader creation tool MPR,M9ill be extended ith additional support $or bootin#AMP con$i#urations%

; CONCLUSION

The NGMP ill be a SPARC V8(E) based ulti!core

architecture that pro"ides a si#ni$icant per$orance in!crease copared to earlier #enerations o$ European

space processors ith hi#h!speed inter$aces such as

SpaceBire and Gi#abit Ethernet on!chip% The plat$orill ha"e ipro"ed support $or pro$ilin# and debu##in#

and ill ha"e a rich set o$ so$tare iediatel& a"ail!

able due to bac*ard copatibilit& ith existin#SPARC V8 so$tare and +E,N= board support pac*!

a#es% NGMP includes also speci$ic support $or AMPcon$i#urations and Tie!Space Partitionin#%

The NGMP is part o$ the ESA roadap $or standard i!croprocessor coponents% 6t is de"eloped under ESA

contract and it ill be coercialised under $air and

e3ual conditions to all users in the ESA eber states%The NGMP is also $ull& de"eloped ith anpoer loc!

ated in Europe and it onl& relies on European 6P

sources% 6t ill there$ore not be a$$ected b& 4S exportre#ulations%

The NGMP speci$ication and other related docuentsare posted at the $olloin# lin*

httpicroelectronics%esa%intn#pn#p%ht
http://microelectronics.esa.int/ngmp/ngmp.htmhttp://microelectronics.esa.int/ngmp/ngmp.htm

NGMP-DASIA10-Paper.pdf

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