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Content Issue No. 3:

I. Progress of HERMES in Year 3

II. EDA tools for ECP® technology

III. Design rules for reli-able component em-bedding

IV. Security demonstrator design realized with new EDA toolsg

V. Power demonstrator

VI. Motor management module

VII. SBP, an emerging tool for the semi-additive process

VIII. Embedding roadmap

IX. Final statement

HERMES consortium

Contact

Welcome to the third issue of the HERMES Newsletter!

Progress of HERMES in Year 3

”The driving focus for the last project year has been the implementation of the HERMES embedding technology into functional demonstrators.

Our end-users Bosch, Infineon and Thales have defined demonstrators for applica-tions in the automotive, industrial and security segments. In each case, there are clear requirements for high density and high power designs using embedded tech-nology. In Newsletter 4 we will give you an update on these applications and show you how we have used the powerfull capability of embedded component technology where conventional components are assembled on the top side of the module to re-duce overall system footprint.

We will also provide you an update on the design ecosystem. In Year 2, collabora-tive development for EDA (Electronic Design Automation) design tools for HERMES was initiated. Cadence, Mentor Graphics, Zuken and Pulsonix became the HERMES supporting group for EDA tool development, and, based on a gap analysis of existing capabilities, the need for new “embedding-friendly” tools was developed. In Year 3, Pulsonix and Cadence have released their tools which support nearly all the needs to design a board with embedded chips. We have outlined some of the key features in this Newsletter 3.

While working with Thales, we tackled another important task for the evaluation of board reliability of the T-RTV thermo-mechanical test vehicle with embedded daisy chain dies. Within this construction, we varied the die size between 3x3mm and 10x10 mm, and loaded the test board with passive discrete components. In total 27 different board build ups were manufactured and caracterized. Beside board evalu-ation, a FEM simulation model was generated to simulate the strain and stress situ-ation under different conditions. After combining the results from the board evalu-ation and the board simulation, design rules for reliability have been established which have been implemented in the different HERMES demonstrators.

During the third year of HERMES the ECP® production line at AT&S Leoben was upgraded for volume production by changing the equipment layout and installing a cleanroom environment for all embedding processes. Backend processes such as solder mask and electrical test as well as packing for shipment of the embedded products have been added to the ECP® facility. The installation of the Atotech Single Board Processor for volume production beginning of 2011 has been the latest imple-mentation highlight.

Serial production for modules with embedded dies has also started with first prod-ucts running off the line by mid 2010. With the development of the business the im-portance of embedded component technology has reached its highest level at AT&S. The exploitation of the ECP® technology resulting in business in the third year of HERMES was a big success.”

Hannes Stahr – HERMES Project Coordinator and Technology Manager, AT&S

EDA tools for ECP® technology

One of the big challenges in embedded component technology is the generation of the board design for embedded applications with currently existing tools. The current EDA (Electronic Design Automation) design tools do not support the requirements for chips components. During the first phase of the HERMES project, work-around solutions have been used to realize designs, with the risk of not having design rule checks available.

Recognizing this, the HERMES supporting group for EDA tool development was es-tablished, with its first activity being the evaluation of the EDA capabilities and the generation of a gap list. Since the start of this collaborative work two of the support-ers released their new versions of EDA tools and closed nearly all gaps which have been identified. The EDA 16.4 tool beta release of Cadence was used to design the most complex functional demonstrator – the Thales security demonstrator - in the HERMES project. Table 1 show the implementation status of the gap list of the new 16.5 tool which was released in April 2011.

HERMESigh density integration by

mbedding chips for

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Hannes Stahr – HERMES Project Coordinator and Technology Manager, AT&S

ECP® component placement between copper layers

ECP® component pads available for via interconnect

ECP® component with pads on top and bottom side

Possibility to flip and/or rotate each ECP® component separately

Component span over several copper layers

Additional layers for ECP® - assembly, glue spots, cavities

Separate assembly output for ECP® components

ODB++ support for ECP®

Gerber/Excellon support for ECP®

Via-in-pad technology

Filled/stacked via support for sequential buildup

Supported

Planned in the next release

Workaround

Table 1: Implementation of EDA tools for component embedding

This release has supported all critical elements to design the Thales security dem-onstrator. In addition, the new software release has been integrated in the design workflow at Thales to enable a well-defined design environment.

Figure 1 gives a view of the stack-up form of the released EDA tool from Cadence which includes the features specifically developed to accommodate the embedding of components on PCB inner layers. There are several options available which al-low the designer to place components automatically or manually, and to define the direction of the interconnection – chip up or chip down or teach the system which components must be embedded and which have an option to be embedded.

The EDA 16.4 tool beta release of Cadence was used to design themost complex functional demonstrator – the Thales security demon-strator - in the HERMES project. Table 1 shows the implementation sta-tus of the gap list of the new 16.5 tool which was released in April 2011.

At the heart of every physical design tool a system is responsible for validating the design data against physical, spacing, electrical and manufacturing specifica-tions. Components placed on inner layers need to have the support of all geometrical checks that exist with conventional surface layer placement. This includes rules that govern spacing between component package types. The following design checks are available in the new EDA tool release:

� Height checks – gap between component in cavity to adjacent metal layer � Conflicts between chip up/chip down methodologies � Component to cavity separation � Maximum cavity area � Maximum number of components in a cavity � Via within cavity area � Metal to cavity area � Extended cavity support based on component height

Design rules for reliable component embedding

In the frame of the HERMES project, numerous simulations and experimental vali-dations have been conducted in order to establish robust design rules and support the industrialization of embedded component technology.Various key design aspects have been taken into consideration, a strong effort have been devoted to characterize the thermo-mechanical behavior of embedded PCBs and how it’s impact the reliabilitySimulation and torsion test programs have been rolled out on specifically designed 260x125 mm² test vehicle PCBs including embedded daisy-chain silicon dies of 3x3 mm², 5x5 mm² and 10x10 mm² dimensions.

For strain measurements, 3-axis rosettes have been bonded to the external sides of the test board over the embedded chip locations. Strain gages of small active length (0.8mm) have been selected to avoid the effects of the strain gradient on measure-ments. In addition, dedicated gages with Cu terminations have also been embedded in some constructions in order to have accurate in-situ strain measurements at the chip level. An overview of an instrumented test vehicle board with strain gages is provided in Figure 2.

Figure 1: Embedded layer definition in the CAD tool.

View of the stack-up form of the released EDA tool from Cadence which includes the features specifically developed to accommodate the embed-ding of components on PCB inner layers.

Figure 2: Test board with strain gage

Figure 3: Strain simulation of embedded components

EmbeddedStrain Gages

Assembled Strain Gages

The effect of PCB thickness is clearly highlighted on figure 3: when PCB thickness decreases, strain in the corners of embedded silicon dies increases significantly es-pecially for the larger 10x10 mm² dies. Moreover, lesser strain is seen by the chips when located near the middle of the PCB thickness.

The analysis enabled the determination of the impact of various design parameters on the thermo-mechanical behavior of laminates with embedded active dies. With the results obtained, it has been possible to generate a first set of basic design rules in relationship with the sensitivity analysis summarize in Table 2. These results will be implemented in future reliability test vehicles as well as in the functional mod-ules and PCB demonstrators.

For strain measurements, 3-axis rosettes have been bonded to the external sides of the test board over the embedded chip locations. Strain gages of small active length (0.8mm) have been se-lected to avoid the effects of the strain gradient on measurements.

Security demonstrator design realized with new EDA tools

The high-end application in the HERMES project is without any doubt the security demonstrator from Thales. This application requires HDI technology with 50 µm conductor width and stacked Cu filled µvia interconnections. Figure 4 shows the construction of the board – it is a 4–2–4 construction with an embedded component “core” in the middle. In this core, four hundred components are embedded, including four complex dice (maximum dimension 8,4mm x 8,2mm), discrete capacitors, some discrete resistors and ESD diodes. The complex embedded die fan-outs are realized with stacked micro via, and with this construction extremely short interconnections can be achieved between the embedded component and the surface mounted devices above. This has a significant positive impact on signal noise and signal integrity.

Figure 4 : Board construction of the security application

The EDA design tool from Cadence enabled a dramatic footprint reduction and the implementation of important security features protecting the device against prohib-ited access to data. Figure5 shows the component layer of the embedded core.

The demanding combination of large dies and single small components demon-strates the process capabilities of the manufacturing processes established at AT&S.

Design parameter Conditions Results

PCB base material Material A vs. Material BHigh performance FR-4s vs. halogen free

Material A yields better perfor-mances than material B

Resin content 1080 vs. 2116 prepreg type

Prepreg-style 2116 yields bet-ter performances

PCB thickness 0.8mm vs. 2mm Higher thickness yields better performances

Embedded core thickness

0.2mm vs. 0.4mm 0.4mm core thickness yields better performances for thin boards (<1mm)No significant effect for thick boards

Interaction between embedded and assembled component

Overlap vs. No overlap Strain on silicon die increases when BGA overlaps silicon die for thick boards

Table 2: Embedded component sensitivity analysis summary

With the results obtained, it has been possible to generate a first set of basic design rules in rela-tionship with the sensitiv-ity analysis.

The high-end application in the HERMES project is without any doubt the se-curity demonstrator from Thales.In the ECP® core, four hundred components are embedded, includingfour complex dies (maxi-mum dimension 8,4mm x 8,2mm), discrete capaci-tors, some discrete resis-tors and ESD diodes.

Figure5: EDA data of ECP® assembly layer

As an example of a design layer, Figure 6 shows a pattern that is optimized for the semi-additive process. It is important to shield all copper lines with copper pattern to enable a uniform plating thickness of the copper pattern.

The need for shielding affects line impedances for critical lines, and this effect must be calculated and simulated during the design phase.

Figure 6: Inner layer 2 design

Design parameter Conditions Results

PCB base material Material A vs. Material BHigh performance FR-4s vs. halogen free

Material A yields better perfor-mances than material B

Resin content 1080 vs. 2116 prepreg type

Prepreg-style 2116 yields bet-ter performances

PCB thickness 0.8mm vs. 2mm Higher thickness yields better performances

Embedded core thickness

0.2mm vs. 0.4mm 0.4mm core thickness yields better performances for thin boards (<1mm)No significant effect for thick boards

Interaction between embedded and assembled component

Overlap vs. No overlap Strain on silicon die increases when BGA overlaps silicon die for thick boards

The EDA design tool from Cadence enabled a dra-matic footprint reduction and the implementation of important security features.

Optimized inner layer design for semi-additive patterning process ena-bles low plating thick-ness tolerances

The realization of the HERMES demonstrators

Power demonstrator

The design of the power module demonstrator is a balanced approach to optimize system performance based on thermal, electrical and cost considerations. Based on the results of the material and single chip test vehicle the final power module dem-onstrator combines a thermally enhanced power stage with four embedded IGBTs and a discrete driver stage. The IGBT dies are thinned down to 140 µm and have a Cu metallization on both front and backside in order to be compatible with the face-down embedding process.

All discrete parts are soldered on to a 4-layer PCB. When one compares the design of the embedded version with conventional packaging, 50% footprint reduction can be achieved – see Figure 7.

Figure 7: Design conventional and embedded version of power module

The build-up in Figure 8 of the embedded power demonstrator is a 4-layer structure, with micro via interconnection, SMD components on the top side and a thin dielec-tric on the bottom side. The backside of the assembly is completely covered with a lamination layer (only 50µm) to guarantee good thermal conductivity and high breakdown voltage for the required isolation.

Figure 8: Build-up of the power demonstrator

Cu (L3)

Cu (L2)

Cu (L1)

Cu (L0)

Die

Discrete IPM version Embedding IPM versionAdditional shrink possible:> embedding of diodes

more than 50% shrink

The final power module demonstrator combines a thermally enhanced power stage with four embedded IGBTs and a discrete driver stage.

The Figure 9 below shows the functional product with embedded IGBTs (the grey shadow beside the vertical resistor row). In the left part of the PCB the power semi-conductors are placed. The power diodes nearby the IGBTs will be embedded in the next version of integration for this module

Figure 9: SMD assembled power module

Motor management module

This module demonstrates the target design rules of the HERMES project, where 25µm lines/spaces in all 6 layers of the construction have been realized. The embed-ded processor has an x/y dimension of more than 8mm and 416 I/Os. Figure 10 below shows some details of the redistribution layer of the processor. The copper pads have a diameter of 150 µm. The pad pitch is 350 µm to be able to rout up to 3 lines through a pair of pads.

Figure 10: RDL on processor

A cross-section of the 6-layer board with the embedded chip with a thickness of 150 µm is shown in Figure 11. Stacked copper filled via are necessary to provide suffi-cient routing density to fan out the large number of lines from the processor.

Figure 11: Cross-section of the motor management module

Cu UBM,Cu Pad

Cu RDL, Cu traces

Chip Al Bondpads

Comparing the design ofthe embedded version with conventional packag-ing, 50% footprint reduc-tion can be achieved.

The motor management module demonstrates the target design rules of the HERMES project, where 25μm lines/spaces in all 6 layers of the construction have been realized.

The single board proces-sor is now available as industrial equipment and one of the first machines of its kind has been in-stalled in the ECP® pro-duction line at AT&S inLeoben.

SBP, an emerging tool for the semi-additive process

Highly integrated embedded PCB modules often require high density structures with lines/spaces down to 25µm/25µm and below. For such resolution, a semi-additive technology (SAT) must be used. Among others, SAT relies on ultra-thin copper foils as well as dedicated single board processor equipment for copper plating - see Fig-ure 12.

Figure 12: Single board plater and plating frame construction

During the plating process, maintaining an equal copper thickness distribu-tion over the whole panel is a key requirement for ultra-fine line technology. The concept of the single board processor enables the required plating tolerance and further important topics with the following features:

� Individual control of parameters of each panel � Handling of thin cores � Unique flow system � Pulse plating for via filling � Full traceability of process data � Single piece flow for improved flexibility and risk management

The single board processor is now available as industrial equipment and one of the first machines of its kind has been installed in the ECP® production line at AT&S in Leoben.

Embedding roadmap

The roadmap for ECP® has become a very important topic, with first products running in serial volumes for actual applications in the market. The required next technology steps are already seen with up and coming projects for 2012 showing increased complexity of the embedded silicon dies and decreasing feature sizes.

3D packaging and package-on-package technologies combined with embedding technology are on the roadmap for 2013. These packages will require the design rules that have been realized in the HERMES project.

Beyond 2013, integrated multi-chip modules and continuing focus on feature size reduction will of course drive ECP® in to higher technology applications.

Panel

Flood bars

Cathode frame

3D packaging and pack-age-on-package tech-nologies combined with embedding technology are on the roadmap for 2013. These packages will require the design rules that have been realized in the HERMES project.

When HERMES was originally conceived, the concept that real busi-ness could be achieved within the lifetime of the project was a vision, a dream. Thanks to theexcellent performance of the consortium and high levels of commitment from the partners, it is a dream that has become reality.

Final statement

“When HERMES was originally conceived, the concept that real business could be achieved within the lifetime of the project was a vision, a dream. Thanks to the excellent performance of the consortium and high levels of commitment from the partners, it is a dream that has become reality.

In April 2010, AT&S founded the new business line “Advanced Packaging” to capitalize on the growing need for next generation component packaging benefit-ing from embedded component technology. In July 2010, volume production with embedded silicon dies was started. These components have been running in serial volumes since January 2011.

In 2011, AT&S established a dedicated facility to design, engineer and produce ECP® laminate packages, and is looking optimistically to the future of this technol-ogy, thanks in large part to the work of the HERMES consortium.”

Mark Beesley COO - AT&S Advanced Packaging

Package

Embedded Die

Embedded Discrete - EDC

WLP - SiP

Embedded PoP

Embedded SiP Module

MEMS Packaging

2010 2011 2012 2013

Simple devices in 2/4 layer package, single stack die, 50µm line

1-2 chip in package combined with surface mount, single stack 35µm line

High end packaged die for ultra low profile PoP, 25µm line

Embedded Passives in Main Board – mainly discrete and simple integrated devices

MEMS package using AT&S 2.5D technol-ogy – microphone, loudspeaker, etc

Multi-chip, combining discrete devices. Digi-tal and RF, multi-stack, < 25µm line

www.hermes-ect.net

Contact Project Coordinator: Johannes Stahr AT&S Austria Technologie & Systemtechnik AG Fabriksgasse 13, 8700 Leoben, Austria Tel.: +43 3842 200-5714 E-mail: h.stahr@ats.net

AT&S has capabilities in manufacturing high density PCBs and knowledge on embedding technolo-gies. The main contribution will be to provide the manufacturing technology for the realisation for the end-user applications. The most important processes which will be developed in HERMES are: Semi-additive process for ultra fine line technology for 25 µm line/space and below, and a high speed Chip assembly process for thinned dies. AT&S is the coordinator of the HERMES project. Atotech is the PCB plating specialist in the HERMES consortium. They will develop electroless and electrolytic copper plating technologies by utilising the experimental plating Single Board Plater concept. They will connect embedded chips by means of conformal plated or filled micro via with the surface wiring circuitry of the PCB layer.

Bosch will primarily concentrate in the HERMES project on the evaluation of the feasibility of embedding technologies in automotive applications. In the HERMES project Bosch will provide the special requirements for automotive products and verify the benefit of embedding technologies on the basis of near-series demonstrators.

Circuit Foil is the copper foil manufacturer in the HERMES project and will develop a 2µ ultra-thin copper foil. This copper foil is the base for the development of a modified semi-additive technology.

IMEC, as a research institute will mostly concentrate on advanced technology developments. IMEC will also lead or participate in supporting tasks with a more generic character: DfX guidelines, design of test vehicles, test methodologies. Finally IMEC is well placed for dissemination at R&D level.

Infineon will primarily concentrate on the preparation issues of the wafers/chips for embedding into the PCB. Large co-operation with the other HERMES beneficiaries is necessary in this context for achieving a high-yield and low-cost embedding solution. The specific interest of Infineon in this project is on the Control Integrated Power System (CiPOS), an industrial control system for refrig-erators and air conditioners which contains power and logic chips.

FhG-IZM will be primarily responsible for the development of the ultra-fine line technology and for the chip surface adhesion research activities. Through their large expertise in the field they are well placed to take the lead of the main work package activity on ‘Embedding technologies’. This work package is at the core of the research and development work within the HERMES project.

Fundico is a consultancy company, responsible for the administrative management and coordina-tion of the HERMES project. It is organizing all consortium meetings and review meetings with the European Commission. It is also responsible for the organisation, coordination and quality assur-ance of the technical and financial reporting to the European Commission as well as for the support to the consortium in dealing with contractual issues, such as contract amendments.

Rood Testhouse is the test specialist within the project. Their role will be to develop the test meth-odology for embedded components. They will also be responsible for die testing and for functional test validation of the different end-user technology validation demonstrators.

Assembly Systems is responsible for the development of the large panel die assembly equipment. This is also a very unique position in the whole HERMES consortium.

Thales Communications will primarily concentrate on the evaluation of the proposed technology for its different product lines. In the HERMES project Thales Communications will bring in the special requirements for aerospace and security products and verify the benefit of embedding technologies on a dedicated security demonstrator.

Thales Corporate Services will concentrate its efforts on its main background based on technolo-gies and process knowledge, as well as design and reliability expertise. As leader of the Modelling and Reliability work package in HERMES, Thales CS will coordinate and manage the modelling and simulation activities of the various involved beneficiaries.

The HERMES consortium

The consortium of the HERMES Integrated Project is set up as a ‘lean’ consortium. Participants have been selected based on proven background expertise in one or more of the areas or research proposed in HERMES. The HERMES project consortium consists of eleven European participants, coming from six different Member States of the Euro-pean Union.