New xTCA Developments at SLAC
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New xTCA Developments at SLAC
CERN xTCA for Physics Interest Group Sept 26, 2011
Ray Larsen
SLAC National Accelerator Laboratory
New xTCA Developments at SLAC - R. Larsen
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Lexicon
• xTCA – Includes large board ATCA system favored by Telecom and small board AMC MicroTCA shelf with extensions for Physics
• AMC – Advanced Mezzanine Card in MicroTCA or ATCA Carrier Board• RTM, μRTM – Rear Transition Module for ATCA or MicroTCA • IPMI – Intelligent Platform Management Interface, core feature of xTCA
managed systems• SM – Shelf Manager card, 2 used in redundant shelf, non-payload slot• LCLS – Linac Coherent Light Source newest generation light sources
at SLAC, LCLSI operating, LCLSII approved for construction start 2013• BPM – Accelerator Strip-line or Cavity Beam Position Monitor, typically
4 channels with online calibration between beam pulses• PICMG3.8 – New Physics standard for interface from ATCA to RTM• MTCA.4 – Complete new 2-wide AMC standard with RTM for MicroTCA• AIP – Accelerator Improvement Program
New xTCA Developments at SLAC - R. Larsen
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I. Standards Progress
• Hardware, Software Technical Committees formed under PICMG
• 2 new HW standards approved– ATCA
• PICMG3.8 Standard IO interface to Rear Transition Module (RTM), IPMI extension & power connector
– MTCA• MTCA.4 Crate, 2-wide AMC & RTM, IO interface,
IPMI extension and power pins designated
New xTCA Developments at SLAC - R. Larsen
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Standard Extensions for Physics
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PICMG3.8 RTM Interface StandardRear View
120 - IO Channels (3x40)IPMI, Power Connector (blue)2 Mechanical Keys Courtesy M. Huffer, SLAC
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26-Sep-11 6Emerging New Electronics Standards - R. Larsen
MTCA.4 Prototype Shelves & Modules
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MTCA.4 - 12 Slot Shelf Dual Star
New xTCA Developments at SLAC - R. Larsen
12 Payload AMC-RTMs Dual Star Redundant Front View
Back-Plane
Dual PU slot
Dual MCH Slot
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II. SLAC xTCA Initiatives
• Major SLAC program is Linac Coherent Light Source (LCLS) Machines – LCLSI (now operating using last1/3 of main linac) – LCLSII (just approved, using middle 1/3 of linac)– Each machine supports 6 or more large
experimental areas (much larger than storage ring light source experiments)
– Linac machine instrumentation needs lots of upgrades via Accelerator Improvement Programs (AIPs)
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SLAC Initiatives 2
• Experimental Areas– ATCA Massively Parallel Processors (MPP)
generic module already deployed in several LCLSI experiments; 2nd generation MPP using new PICMG 3.8 interface
• Linac RF & Controls – MTCA.4 demonstrations in development include
• Reduced RF phase jitter to ~30 femtoseconds• Klystron FPGA-based interlocks• Beam Position Monitors for LCLSII Injector
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xTCA Status
• LLRF for Main Linac S-Band 50MW station– Prototype developed, accelerator test planned for
October 2011 (AIP program)– Struck digitizer AMC w/ SLAC designed RTM
• Klystron Interlocks– Prototype development near completion, test planned on
L-Band test station Q1-2 FY12– TEWS FPGA AMC w/ SLAC designed RTM
• BPM System– AIP program approved, commercial AMC digitizer w/
SLAC designed RTM, requirements in development
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LLRF MTCA & RF Chassis Testing
New xTCA Developments at SLAC - R. Larsen
MTCA.4 6-slot with AMC FPGA digitizer, timing, processor controlling intra-pulse feedback loop
RF head-end chassis in bench test
RTM SectionAMC Section
μRTMrear view
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RTM 10 Ch ADC-DAC, IPMI Interface
Emerging New Electronics Standards - R. Larsen
Rear Panel
• 25 MHz IF Signals In
• RF Ref In• Trigger in• Dual I&Q
DAC Out
Courtesy A. Young, SLAC
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RTM FPGA Interlocks
Emerging New Electronics Standards - R. Larsen
REAR PANEL
• INPUTS• DC and pulsed
signals• 2 KSps and 60
MSps 12bit digitizers on board
OUTPUTS• Multiplexed serial
to AMC via RTM interface
• Works for short pulse or long pulse machines
Courtesy D.G. Brown, SLAC
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8- BPM System Block Diagram
New xTCA Developments at SLAC - R. Larsen
AFE
AFE
AFE
AFE
AFE
AFE
AFE
MCH
CPU
EVR
ADC
ADC
ADC
ADC
ADC
ADC
- Front -
12-slot MicroTCA crateInjector BPM Crate 1; 8 BPMs
- Back -
1 ADC per BPM
1 AFE per BPM
Signal cables to tunnel4 per BPM
Timing data
EPICSChannel Access Network
ADC
ADC
EVR
AFE
TrigFanout
TrigFanout
Calibrator trigger1 per BPM
ADC trigger1 per BPM
EVR provides clock to ADCs along the backplane
Courtesy S. Hoobler et al, private communication
EVR – Event Receiver (trigger over serial network)
ADC – AMC BPM digitizer & FPGA processor,Industry units
AFE – Analog Front End RTM (buffers, filters, calibration circuits
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Conclusions
• PICMG3.8, MTCA.4 are major milestones• Software work continues
– Guidelines on architecture, protocols; need active feedback from user case studies
• SLAC Initiatives– ATCA Generic Massively Parallel Processors working in LCLSI
experiments, Improved version in process– MTCA Opportunities underway to evaluate for three major
subsystems– Industry providing infrastructure modules and key applications
modules, SLAC designing first RTMs successfully
• Goal is readiness for major LCLS system upgrades– Both lab and Industry COTS solutions critical
New xTCA Developments at SLAC - R. Larsen