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New TOT design for the LAV F.E. electronics

M. Raggi, P. ValenteG. Corradi, D. Tagnani LNF electronic serviceTDAQ Working Group

29/05/2009

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Energy deposit in the LAV (Riccardo) Maximum energy deposit into LAV > 20 GeV The core of the distribution extends up to 10 GeV 80% of deposited energy is confined in a single block We want to measure with good efficiency energy deposit >

50MeV

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Possible PMT working pointPMT working point for MIP

Gain ≈ (1-2)x106; Edep=80 MeV; Np.e./MeV=0.3 Collected charge for MIP QMIP≈5 pC Signal wdt=20 ns VMIP = 2*QMIP*50/20ns = 25 mV

PMT max expected signals No saturation observed in PMT for signals up to 25V VMAX <2*Q20GeV*50/20ns = 7 V max expected signal Variations within different blocks and fluctuations can

produce signals of order ≈ 10 V

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Immagini del segnale analogico

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Read out electronics requirementsRequirements

Energy resolution ≈ 10%/√ETime resolution < 500 psMax rate ≈ MHz x ch (will be lower in real life)Able to manage very large signals ≈10VMeasure energy 20 MeV – 20 GeV xblock range

StrategyUse Time Over Threshold to measure chargeUse Pisa TDC card for the readout (HPTDC)Use 1 Tell1 x RING to reduce cost

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Preliminary results of NINO tests with Pbgl cosmic ray signals

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Nino ASIC chip ALICE TOF system

– Charge range 0.2-2 pC– Eight channels per ASIC.– Differential input – LVDS output– Output pulse width dependent on the charge of the

input signal– Fast amplifier to minimize time jitter, i.e. first stage

with a peaking time of 1 ns;– Discriminator threshold in the range 10–100 fC

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Schematic of the NINO circuit

Input Stage Threshold adjust circuit 4 stages of low gain High BW differential

amplifiers. Pulse stretcher

– Output signal width from MRPC varies 2-6 ns– Add 10 ns to out signal width to match HPTDC

LVDS output driver to TDC

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The LAV-NINO adapter card 8 ch lemo input (+4 V -4V dynamics) Each input is divided by 1, 1/10, 1/100 and sent to

NINO 3x8 output channels into NINO board

Single channel layout

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Experimental setup

LAV adapter + NINO

VME READOUTDual Range

QDC+TDC(100ps)

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NINO dynamic range test

Experimental setup used to test NINO dynamic range:– Time wdt in the range 20-350 ns have been explored– Amplitude range 10-150 mV (20 ns)

Use the NIM signal to:– Evaluate efficiency (scaler)– Measure signal width (Oscilloscope)

LVDSto NIMPulser

FE+NINO

Oscilloscope

Scaler

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Range tests results

y = 0,9981x + 19,989R2 = 0,9999

-75

-25

25

75

125

175

225

275

325

375

425

0 50 100 150 200 250 300 350 400

Signal duration (ns)

NIN

O L

VDS

time

(ns

)

Using square waves we measure the time over threshold of corresponding NINO signalsThe NINO shows linear behavior up to 350 ns

The intercept of the fit is due to the time stretcher circuit of NINO

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Charge vs TOT test setupFE+NINO

Amplifier x10

Discr.

Bridge

TDC

ADC

Discr.

Scintillator

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Typical NINO signal with Pbgl input

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TDC hit map

Trigger

Signal The trigger on ch 31 shows cross talk @ 10-4 level in TDC

The signal shows cross talk between ch 6 and ch 5

@ 10-3 level (NINO ?)Signal

Signal

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Signal width VS charge

1.6E-19*3.5E6*0.35*70*10 = 140pC

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TOT vs charge fit

F=P1+P2X+ P3X2

Limited charge range due to cosmic ray trigger

Fit function can be improved

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Charge resolution using TOT only

AVERAGE RESOLUTION 8.5%

QQDC Q REC

QQDC

TDC LSB 200 ps

No correction appliedTDC resolution 200 ps

1 = 6%2 = 17.5%

Noise contribution high due to 1/100 attenuation used.

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Resolution VS charge

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Conclusion and to do on NINO Max nominal charge in NINO correspond to half a MIP in LAV PMTThreshold range 10-100 fc < 1 p.e. @ 106 gain too lowThe use of the Pbgl block in the trigger forced the charge to be too high in NINO (can use only 1/100 scale) Charge measurement with a precision <10% can be reached using TOT technique on LAV PMT signals

To do listBuild an external trigger based on scintillators or use the Pbgl test stand as a trigger systemSet the PMT gain near the defined working point (1-2)x106

Enlarge the charge range changing the gain of the PMT

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New TOT system for the LAV

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Basic IdeasBuild a low cost TOT system with larger

dynamic wrt NINO asic– Use commercial devices (not a dedicated ASIC)– Clamp system able to maintain the TOT of original

signal (needs very fast low capacitance diodes)– Amplify the signal a bit (x3) to allow correct

reduce overdrive and to enlarge signal width (>15 ns)

– Compare the amplified clamped signal with a low settable thr to start and stop the LVDS signal

– Send an LVDS out to the TDC

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Clamp stage: performance simulation

Clamp input signals > 300 mV Requires very fast low-capacity

HSMS-286C-TR1G schottky diodes

HSMS-286C-TR1G diodes can suffer for too much power on it

The power in excess is dissipated using properly dimensioned metal pads on the PCB

The clamp maintain the trailing edge time of the original signal!

No limit to maximum amplitude of signals to be measured using TOT!

VIn

VOut

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Single channel Layout

Clamp stage

AnalogInn

AnalogOut/2

Clamped

OutLVDSOut

Thr circuit

x3 Amplifier Comparator

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TOT resolution improvements TOT with low thr may suffer for noise on long signal

tails Adding a pole (T3) to signal tail allow a cleaner

definition of trailing edge T1 therefore better definition of the TOT

Consequences on dead time to be understoodthr

Original signalShaped signal

Dead time

0 mVPart of the dead time (T2-T1) is recovered by shortening the original signalChannel is no more considered dead [T1;T2] as it was for the original signal (risky business)

T0 T1 T2

T4T3

Total dead time (T4-T0) increased by (T4-T2)

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Board layout submitted4 channels prototype board submitted to firm include:

- 4 analog input channels- 4 direct analog out divided by 2- 4 clamped analog out- 4 independent thr adjust trimmers- LVDS out to CAEN TDC

Foreseen studies:- Time stability of clamp trailing edge for large signals- Death time and max rate measurements- Time resolution- Energy resolution using TOT- Efficiency VS thr for MIP signals

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Final readout scheme for VETO

F.E. board

F.E. board

F.E. board

F.E. board

F.E. board

For each ring

Veto Switch48x1Gb In out

VetoRing

Veto Event Builder

To ReadoutPc FARM

Whole LAV system1MHz x 2x32Bit x10 ch ~ 640 Mbit

160 ch

To L0trigger

1xTELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

5x32 ch In

<4x1 Gb

<1Gb/ring

Eth Gbit

5 board10x32 ch Out

256 ch8x32 ch In

8 board16x32 ch Out

<4x1 Gb

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Global L0 layout for LAV

TELL 1Eth receiver

6xEth 1Gbit

6xEth 1Gbit

Eth Gbit

L0 FPGA

6xEth 1Gbit

6xEth 1Gbit

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

TELL 1BOARD

TDC 128ch

TDC 128ch

Eth Gbit

L0 FPGA

TDC 128ch

TDC 128ch

Eth Gbit

Eth receiver under development @

Rome2

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# of electronics componentsANTI-N # blocks

(x ANTI)# F.E. card

(x ANTI)# channels

(x ANTI)# TDC

(x ANTI)# TELL1(x ANTI)

ANTI (1-5) 160 5 320 4 1

ANTI (6-7) 240 8 480 4 1

ANTI (8-12) 256 8 512 4 1

TOTAL 2560 81 (90) 5120 48(60) 12(15)

Assumptions– 1 scale for the whole dynamic range– 32 ch per front end card– 2 channels into TDC for each input (100%

redundancy)

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Naïve cost estimateItem NTOT TOT CostF.E. board (32 ch) 81(90) <200 K€ *TDC (Pisa) 48(60) 12(15) K€TDC cables ?? ≈400 ?? ?? 15K €** ??TELL1 12(15) 36(45) K€Readout PC 1 1 K€48X1Gbit switch 1 1 K €Total cost ≈260 K€ Does not include 12-24 crates + power supply * Cost is an upper limit driven by the request of on board FPGA (real cost estimate needs final board design) ** Cable type to be defined cost is just a guess Final cost will be < 300K€

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ConclusionsThe use of NINO in LAV electronic seem difficult

– Dynamic range too small max 2 pC thr 10-100 fC– 3xN channels to allow 1000 range – Strange behavior for high charge signal (not

understood)New TOT device:

– Much higher dynamic range (commercial electronic) – High performance clamping stage included – No need for multiple scales

Time scale for new prototype– Project submitted to firm on Monday this week – PCB delivery expected @ beginning of June– Test foreseen during July as soon as ANTI-A1 is finished