New RPC Front-End Electronics for HADES

New RPC Front-End Electronics for HADES Alejandro Gil

New RPC Front-End New RPC Front-End Electronics for HADESElectronics for HADES

A. Gil A. Gil aa, D. Belver , D. Belver bb, P. Cabanelas , P. Cabanelas bb, J. Díaz , J. Díaz aa, J.A. Garzón , J.A. Garzón bb, D. González-Díaz , D. González-Díaz bb, , W. Koenig W. Koenig cc, J.S. Lange , J.S. Lange cc, J. Marín , J. Marín dd, N. Montes , N. Montes bb, P. Skott , P. Skott cc, M. , M.

Traxler Traxler cc

aa IFIC (Centro Mixto UV-CSIC) Valencia, 46071, Spain. IFIC (Centro Mixto UV-CSIC) Valencia, 46071, Spain.bb LabCAF, Dpto. de Física de Partículas, Universidade de Santiago de LabCAF, Dpto. de Física de Partículas, Universidade de Santiago de

Compostela, Santiago de Compostela, 15782, Spain.Compostela, Santiago de Compostela, 15782, Spain.cc GSI, Darmstadt,64291, Germany. GSI, Darmstadt,64291, Germany.

dd CIEMAT, Avd. Complutense 22, Madrid, 28040, Spain. CIEMAT, Avd. Complutense 22, Madrid, 28040, Spain.

12th Workshop on Electronics for LHC and future Experiments 25-29 September 2006

Valencia (Spain)

- NEW FRONT-END ELECTRONICS FOR HADES RPC WALL – ALEJANDRO GIL (IFIC)

OUTLINEOUTLINE HADES EXPERIMENTHADES EXPERIMENT RESISTIVE PLATE CHAMBER (RPC) RESISTIVE PLATE CHAMBER (RPC)

WALLWALL RPC CELLSRPC CELLS RPC SIGNALSRPC SIGNALS ELECTRONIC CHAINELECTRONIC CHAIN FRONT-END ELECTRONICSFRONT-END ELECTRONICS RESULTSRESULTS IMPROVEMENTSIMPROVEMENTS SUMMARYSUMMARY


HADES EXPERIMENTHADES EXPERIMENTHADES is located at the SIS accelerator of HADES is located at the SIS accelerator of

GSI, Darmstadt (Germany)GSI, Darmstadt (Germany)

GSI

FAIRHADES


HADES EXPERIMENTHADES EXPERIMENT Detection of electron-Detection of electron-

positron pairs produced positron pairs produced in relativistic hadron-in relativistic hadron-nucleus and nucleus-nucleus and nucleus-nucleus collisions with nucleus collisions with the goal of studying the goal of studying vector meson properties vector meson properties in nuclear matter, both in nuclear matter, both normal and hot and normal and hot and compressed.compressed.

Consists of several Consists of several subdetectors subdetectors providing providing tracking, triggering, tracking, triggering, particle identification and particle identification and momentum momentum reconstruction reconstruction capabilitiescapabilities

High Acceptance DiElectonHigh Acceptance DiElecton SpectrometerSpectrometer

RPC detector


HADES EXPERIMENTHADES EXPERIMENT

Objective of the project:

Upgrade of HADES replacing the low angle TOFino detector for the an RPC wall

TOF: Time of Flight detector (100ps time resolution)

TOFino: Low angle Time of Flight detector (350ps time resolution)

(cross section of HADES)(cross section of HADES)

TOFino

RPC wall


RPC wallRPC wall

The RPC wall is The RPC wall is distributed in 6 distributed in 6 sectors, covering sectors, covering an active area of 7 an active area of 7 squared-meters.squared-meters.

(View from inside)


RPC wallRPC wallRPC wall contains 1024 double-sided readout

detectors (2048 channels)

80 times larger granularity Time resolutions of 70 ps Rates up to 700 Hz/cm2 collisions from C-C to Au-

AuDouble layer acceptance close to 100%


RPC cellsRPC cells

CHEAP MATERIALS:AluminiumGlass

SHIELDED CELLS:Crosstalk < 1%

GAS MIXTURE:Freon (85%)SF6 (15%)Isobutane (5%)

RPC Gas Box & cells(LIP-Coimbra,P. Fonte et al.)


RPC signalRPC signal Rise time ~500ps 5ns width Amplitudes up to

200mV Oscillations due to

impedance mismatch between the detector (20Ω) and the electronics (50Ω)

100ns

100mV


FEE design FEE design considerationsconsiderations

A large bandwidth to deal with short rise times A large bandwidth to deal with short rise times of RPC pulses (about 500ps rise time and 5ns of RPC pulses (about 500ps rise time and 5ns width).width).

Low electronic jitter and noise for good time Low electronic jitter and noise for good time resolutionsresolutions

Charge measurement for correctionCharge measurement for correction Output signal for the trigger logic of HADES.Output signal for the trigger logic of HADES.

Rate < 1kHz/cm2 RPC areax100cm2 =100kHzX31 channels = 3.1 MHz firing

Size restrictions Size restrictions two boards DB and MB two boards DB and MB Built with commercially available componentsBuilt with commercially available components Moderate power consumption to reduce heat. Moderate power consumption to reduce heat.

Front End set up on the RPC sector

Detector active area


DAUGHTERBOARDDAUGHTERBOARD Generates a time-window signal which contains information about the:Generates a time-window signal which contains information about the:

Arrival time of the RPC signal (for TOF measurement) Arrival time of the RPC signal (for TOF measurement) Charge of the RPC signal Charge of the RPC signal

5cm

4.5cm

1 2 3 4

6 Layer board6 Layer board 4 channels/board4 channels/board Micro Lemo inputsMicro Lemo inputs Hi-freq Samtec connectorHi-freq Samtec connector

2 4


DAUGHTERBOARDDAUGHTERBOARDAmplifier stage → GALI-S66 Discriminator stage: - Dual MAX 9601 comparator with histeresis

and latch enable (2 comparators/channel).PECL-LVDS TI SN65LVDT100 converter. BFT92 transistor for multiplicity trigger.

4 ch. out

C

C

Integrator

Amplifier

PECL-LVDS

ToF-Threshold

ToT-Threshold

In

OPA690 Wideband Op. Amplifier

GALI-S66 Monolithic(20dB, 2GHz)

MAX9601-2ch 500ps Propagation Delay

SN65LVDT100C

Latch enable

MAX9601-2ch

R

2k2 Trigger Out. Σ4ch.

SAMTEC16 diff. pins

BFT92 Wideband PNP Transistor

Comparator


RPC signalRPC signal

ToT

width~charge

Integrated signal

Amplified RPC signal

Output signal

RC integrator 2ns (to avoid tail)

Time (20ns/div)

Voltage (50mV/div)

xGToF

ToT

RPC signal

RPC arrival time

ƒ


MOTHERBOARDMOTHERBOARD

Main tasks:Main tasks:

Supply stable voltage to the DaughterboardSupply stable voltage to the Daughterboard +5V,-5V,+3.3V+5V,-5V,+3.3V

Conentrates the time-window signals from 8 Daughterboard to 1 Conentrates the time-window signals from 8 Daughterboard to 1 connector (then twisted pair cable to the TDC board).connector (then twisted pair cable to the TDC board).

Combines the 32 trigger signals coming out from the Daughterboard Combines the 32 trigger signals coming out from the Daughterboard to provide only 1 multiplicity signal.to provide only 1 multiplicity signal.

Allocates DACs for the threshold voltages of the comparators on the Allocates DACs for the threshold voltages of the comparators on the DaugherboardDaugherboard

Minor tasks:Minor tasks: Test signals multiplexing, LVDS repeaters,interface for DACs Test signals multiplexing, LVDS repeaters,interface for DACs

programming, etcprogramming, etc

40cm

6cm


MOTHERBOARDMOTHERBOARD Ripple filteringRipple filtering

Uses the plugged vias technique to:Uses the plugged vias technique to: reduce ESR and ESL layout effects in reduce ESR and ESL layout effects in filter capacitors and PCB dimensionsfilter capacitors and PCB dimensions

1) Supply stable voltage to the Daughterboard1) Supply stable voltage to the Daughterboard

Ferrite beadFerrite beadDifferent decades CDifferent decades C

DC-DC converter

Motherboard

+5V-5V

+3.3V



Interface: Low Voltage Differential Signaling (LVDS)Interface: Low Voltage Differential Signaling (LVDS)Also used for:Also used for: DACs programmingDACs programming Test signals deliveryTest signals deliveryAdvantages: Advantages:

Low power consumptionLow power consumption High noise inmunityHigh noise inmunity

Diferential impedance matching lines and termination resistors (100Diferential impedance matching lines and termination resistors (100ΩΩ) to ) to reduce signal reflections/distorsionsreduce signal reflections/distorsions

2)Conentrates the time-window signals from 8 Daughterboard 2)Conentrates the time-window signals from 8 Daughterboard to 1 connector (then twisted pair cable to the TDC board).to 1 connector (then twisted pair cable to the TDC board).



Low level trigger:Low level trigger: Two-stage circuitTwo-stage circuit Summing OPAMsSumming OPAMs OPA690OPA690

High slew rateHigh slew rate High output swingHigh output swing

-100mV contribution -100mV contribution

per channelper channel

3) Combines the 32 trigger signals coming out from the 3) Combines the 32 trigger signals coming out from the Daughterboard to provide only 1 multiplicity signal.Daughterboard to provide only 1 multiplicity signal.



DACs ThresholdsDACs Thresholds 8 DACs/Motherboard8 DACs/Motherboard 8 Channels/DAC8 Channels/DAC LTC2620LTC2620

12 bits resolution12 bits resolution Low noiseLow noise Low power consumptionLow power consumption

Daisy-chainedDaisy-chained SPI programmingSPI programming

TDC board

DO CS CLK

DAC1 DAC2 DAC8

Motherboard

4) Allocates DACs for the threshold voltages of the 4) Allocates DACs for the threshold voltages of the comparators on the Daugherboardcomparators on the Daugherboard


ELECTRONIC CHAINELECTRONIC CHAIN

Daughterboard 4 channelsMotherboard8 Daughterboards

Time Readout Board (TRB)4 Motherboards

DC-DC converter 2 MB.

RPC

DC-DC converter

TRB

MotherboardDaughterboard


TRBTRB

GSI (M. Traxler et al.)

Custom TDC-Readout-Custom TDC-Readout-Board Board

Muli-purpose 128-Muli-purpose 128-channelchannel

Requires 1 channel for Requires 1 channel for timingtiming

Based on the HPTDC Based on the HPTDC ASIC developed at ASIC developed at CERNCERN

Time Readout Board:Time Readout Board:


DC-DC converterDC-DC converter

Input: +48VInput: +48V Output:Output:+5V,-5V&+3.3V+5V,-5V&+3.3V 22xxDATEL 5V DATEL 5V

(12A)modules.(12A)modules.100mVpp ripple@20MHz100mVpp ripple@20MHz POLA 3.3VPOLA 3.3V

40mVpp ripple @20MHz40mVpp ripple @20MHz Extra filtering at the Extra filtering at the

input and output: input and output: 25mVpp ripple 25mVpp ripple @20MHz@20MHz

GSI (M. Traxler et al.)


RESULTSRESULTS

Output width vs charge correlation for gamma illumination using 60Co

sourceBeam results 1GeV C-C collisions

Full chain:

Detector+FEE+TRB

ToFToFThrThr=15mV=15mV

ToTToTThrThr=-20mV=-20mV

<0.5W/channel<0.5W/channel

Crosstalk<1%Crosstalk<1%

Jitter: 50psJitter: 50ps


IMPROVEMENTSIMPROVEMENTS

DAUGHTERBOARDDAUGHTERBOARD

-Only one comparator

-30% less consumption per channel

- Expected to improve the output width vs. charge correlation

Charge comparator removed


IMPROVEMENTSIMPROVEMENTS

MOTHERBOARDMOTHERBOARD Ripple filtering improvement Ripple filtering improvement

DACs readback to check that the data has DACs readback to check that the data has correctly receivedcorrectly received

Trigger system will be redesigned because Trigger system will be redesigned because the actual OPAMs produce big the actual OPAMs produce big overshootovershootlower slow ratelower slow rate


SUMMARYSUMMARY The actual FEE fits HADES requirements. The actual FEE fits HADES requirements. 2 Motherboards with 64 channels has been evaluated 2 Motherboards with 64 channels has been evaluated

under:under:- pulse generator- pulse generator- gamma source- gamma source- under beam- under beam

Still some improvements commented have to be Still some improvements commented have to be done, as well as some long term stability tests. done, as well as some long term stability tests. Noise/crosstalk measurements should be done in Noise/crosstalk measurements should be done in more detail.more detail.

Next step will be to cover 2 sectors of the actual Next step will be to cover 2 sectors of the actual detector in February 2007detector in February 2007


AcknowledgmentsAcknowledgments Hector Alvarez (LabCAF-Universidad Hector Alvarez (LabCAF-Universidad

de S. Compostela)de S. Compostela) Alberto Blanco (LIP-Coimbra) Alberto Blanco (LIP-Coimbra) Paulo Fonte (LIP-Coimbra)Paulo Fonte (LIP-Coimbra) Gerhard May (GSI)Gerhard May (GSI) Martin Zapata (LabCAF-Universidad Martin Zapata (LabCAF-Universidad

de S. Compostela)de S. Compostela)


Thanks for your Thanks for your attentionattention

New RPC Front-End Electronics for HADES

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