Cryptographic methods for privacy aware computing: applications.
New Energy-Aware Computing: Technology and Circuitsperla/ugrad/EAC/EAC1.pdf · 2017. 3. 28. ·...
Transcript of New Energy-Aware Computing: Technology and Circuitsperla/ugrad/EAC/EAC1.pdf · 2017. 3. 28. ·...
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Energy-Aware Computing: Technology and Circuits, 2017 Page 1
Computer Science and EngineeringChalmers University of Technology
Energy-Aware Computing:Technology and Circuits
Per Larsson-Edefors
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Computing Circuits Draw Current
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Power = Current * Voltage
• Physics 101:P(t) = I(t) * V(t).
• In our context, averaged quantities are more useful:– Pavg– Iavg– VDD (often constant)
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• Average current? • Consider the
instantaneous current throughout one cycle…
(Average) Current Drawn per Cycle
Iavg• …then take the average.
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• Pavg = Iavg * VDD, where VDD is the supply voltage of the system.
• Energy/cycle:Ec = Pavg * T, where T is the clock period.
• Pavg and Ec will both be used in this lecture.
Power and Energy Dissipated per Cycle
Iavg
T
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• Pavg and Ec... – depend on
what is being computed.
Varying Power and Energy Dissipation
– vary from cycle to cycle.
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• Power dissipation varies over time. Yet, the TDP (Thermal Design Power) defines certain Watt limit for CPU cooling.– Peak power is allowed to exceed TDP, but to what extent?
• Which benchmarks to establish the TDP value?
Power Measurements vs the TDP Metric
Source: EPM’14Source: Scythe (Kozuti Cooler)
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• Find typical energy/cycle:– Run system for
many cycles.– Use statistically relevant
benchmarks.• By associating the typical
energy/cycle with different hardware units, energy metrics can be used at software level.
Typical Energy/Cycle
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• Physical implementation impacts power dissipation. – Fabrication process technology (left).– Circuit implementation (right).
Technology and Circuits
Source: Concept Engineering
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Technology: Wires and Transistors
Source: wikipedia
Source: Univ. of Florida
Source: electronicecircuits.com
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Field-Effect Transistors (FETs)
Source: tek.no
The FET; the work horse of all digital systems
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• Voltage is applied on gate.• Electric field regulates
channel properties.• Threshold voltage, VT
(or VTH) is the gate voltage required to create a conducting channel.
Field-Effect Transistor Basics
Source: USC
Channel
Body electrode
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• Terminology:– MOSFET = Metal Oxide
Semiconductor FET.– CMOS = Complementary MOS.
• CMOS is the foundation for all digital circuits. – Key property: Gate isolated from
channel “no” current flows through gate insulator.
The CMOS Technique
0
The CMOS inverter
1
VDD
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• Analog circuits: biasing required transistors are always on.• Bipolar transistors: current flows into base; no isolation.
Contrast to BJTs and Analog Circuits
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• Dynamic power:– Switching power, Psw. – Switching logic levels, i.e., computation.– Charge and discharge, Q.
• Static power: – Leakage power, Pleak.– Mainly due to subthreshold current, Isub.– Caused by small-size effects, i.e.,
advanced FETs are never fully off.
Dynamic and Static Power Dissipation
Q0
IsubQ =
C VDD
VDD
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• Input transition 10 output node 01, requiring charge Q = C VDDfrom the power supply.
• Later, input 01 output node falls, draining the charge to the ground.
Switching Power Dissipation, Psw
Q
CQ
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• After one full transition, the energy of the charge has been converted into heat:Psw = E/T = (Q VDD)/T =
= (CVDD VDD) f.• This gives us this famous expression
Psw = f C VDD2where represents switching/cycle.
• To reduce switching power, focus on the supply voltage.
While Psw Mostly Depends on VDD …
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• We want to reducePsw = f C VDD2
• Aside from VDD, there are several implementation best design practices:– Reduce signal activity (),
e.g., by eliminating glitches.– Reduce nodal capacitance
(C), by optimizing layout of transistors and wires.
… All Tricks Are Necessary
Source: LPDE’09/Ch 3
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Impact of Speed (f) on Power and Energy
• Generally, reducing speed f saves power.• During implementation, “weaker” circuits can
be used. But then f can never be raised.– Use of weaker circuits means lower capacitance C.– Mainly this impacts power dissipation;
energy/cycle does not change significantly.
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• So VDD is decreased to save switching power.• Since performance deteriorates rapidly
as VDD approaches VT,VT has to be decreased as well.
Scaling Supply Voltage for Reduced Psw
Source: SSD’13
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Voltage Scaling Issues
Source: H. Iwai, Technology Scaling and Roadmap, IEDM'08/Short Course
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• Classic advantage of CMOS:High ION /IOFF ensures stable digital operation.
• Because of scaling, leakage increases IOFF increases.
• Degrading ION /IOFF ratio limits how far VDD can be scaled;especially serious for SRAMs.
CMOS Stability Reduces with VDD
0 1
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• Smaller FETs and decreasing VDD (and VT) increasing Isub.
• Isub function of semiconductor energy states (quantum mech.).
• Three important features:– Exponential dependence on VGS.– Exponential dependence on VT.
• Since VT depends on VDS, static power strongly depends on supply voltage!
– Temperature matters.
Subthreshold Current
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• VT variations impact leakage exponentially.– Variability increases with scaling.
• Generally, technology variations have a stronger impact on designs where VDD and VT are reduced.
CMOS Stability - Variability
Source: "Giga-scale Integration for Tera Ops Performance", P. Gelsinger, DAC'04
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Some Variations Are Random in Nature
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IOFF Isn’t 0 (Due to Leakage)
High IOFF high static power + stability issues!
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Note That IOFF Strongly Depends on VDD
• For short channels, VT increases with decreasing VDD.– Cause: Drain-induced barrier
lowering (DIBL).– DIBL lower in e.g. FinFETs.
IOFF
VT
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Reduce Speed to Save Power?
When speed goes down, Psw decreases whilePleak stays constant.
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• Lower speed f lower Psw:– Psw = f C VDD2
• and …reduced speed increased delay slack VDD can be reduced Psw dramatically reduced.
• Also Pleak is reduced due to reduced VDD, but the exponentially deteriorating performance makes Eleakvery significant.
Subthreshold/Nearthreshold Computing
Source: NTC’10
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• Subthreshold/nearthreshold operation is interesting because it leads to minimal energy/operation!
• Note though that performance is very poor in these regions.• Some simulations follow for 65nm GP_LVT and LP_LVT.
Subthreshold/Nearthreshold Computing
Source: NTC’10
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Delay vs VDD
LP_LVT is low performanceGP_LVT is high performance
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Energy/Operation vs VDD
LP_LVT has low leakageGP_LVT has high leakage
GP_LVT curve has a discernible minimum
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Subthreshold Swing/Slope Factor (S)
S > 60 mV/decade for MOSFETs.
• To efficiently reduce IOFF, a smaller subthreshold swing (S) than that of MOSFETs is desirable.– Priority: Good S for low VDDs.
• This, however, requires radical changes to the fundamental transistor operation.
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• S (called SS above) >= 2.3 * 0.026 = 59.8 mV/decade.• m = 1+ Cdepletion-layer/Cgate-oxide
Limited Subthreshold Swing of FETs
Source: BTBTFET’10
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The FinFET - A “3D Gate” FET
Source: Intel14nmSource: IBM14nm
• FinFETs:– Decent S at low VDD. – But still MOSFETs !– IBM – SOI-based FinFETs– Intel – bulk FinFETs
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• A lower subthreshold swing gives acceptable ION/IOFF ratios at low supply voltages.
Post/Beyond-CMOS - Tunnel-FETs ?
Source: BTBTFET’10
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• TFETs (e.g. HetJFET) are promising but CMOS is not doing that bad…
• The challenge is to make TFETs that can both have– subthreshold swings
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Conclusion
• Implementation aspects, technology and circuits, strongly impact power and energy dissipation.
• Several power dissipating mechanisms need different low-power techniques (next lecture).
• While reducing VDD is the most effective way to reduce power, this also has disadvantages:– Lower speed, which hurts performance, or– lower VT to maintain speed; this in turn increases leakage.– Larger impact of variability in any case.
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References• BTBTFET’10: “Band-to-Band Tunneling Field Effect Transistor for Low Power Logic and
Memory Applications”, S. A. Mookerjea, PhD Thesis, Penn State Univ, 2010.• CATPE’08: “Computer Architecture Techniques for Power-Efficiency”, S. Kaxiras and M.
Martonosi, Morgan & Claypool, 2008.• EPM’14: “The Evolution of Power Measurement”, K. Cameron, Computer, IEEE, Mar. 2014.• IBM14nm: “High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2
embedded DRAM and 15 Levels of Cu Metallization”, C.-H. Lin et al., IEDM 2014.• Intel14nm: “A 14nm logic technology featuring 2nd-generation FinFET, air-gapped
interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size”, S. Natarajan et al., IEEE Int. Electron Devices Meeting (IEDM), 2014.
• LPDE’09: “Low Power Design Essentials”, J. Rabaey, Springer, 2009.• NTC’10: “Near-Threshold Computing: Reclaiming Moore’s Law Through Energy Efficient
Integrated Circuits”, R. G. Dreslinski, et al., Proc. of IEEE, Feb. 2010.• OBCD'13: “Overview of Beyond-CMOS Devices and a Uniform Methodology for Their
Benchmarking”, D. E. Nikonov, Proc. of IEEE, Dec. 2013.• SSD’13: “Steep-Slope Devices: From Dark to Dim Silicon”, K. Swaminathan et al., IEEE
Micro, 2013.