New Corporate Identity Poster Design Department of Physics and Astronomy, University College London...
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Department of Physics and Astronomy, University College London Erdem Motuk <[email protected]>, Martin Postranecky <[email protected]>, Matthew Warren <[email protected]>, Matthew Wing <[email protected]> Poster Number 104 Topical Workshop on Electronics for Particle Physics ( TWEPP-2011 ) Vienna, Austria 26 to 30 Sept. 2011 Electronics for the EuXFEL Clock and Control System Design and Development of Electronics for the EuXFEL Clock and Control System • Clock and Control ( CC ) hardware and firmware designed for the EuXFEL DAQ system • The system exploits the data handling advances provided by the new telecommunication architecture standard for physics • The CC is responsible for synchronising the DAQ system to overall system timing • The hardware consists of a DESY designed MTCA.4 board and a UCL designed Rear Transition Module ( RTM ) • Each RTM controls up to 16 Front End Modules ( FEMs ) for a 1 Megapixel 2D detector • The CC system is designed to provide extendibility and scalability to support future upgrades to the DAQ or larger detectors Red LED – FPGA Prog. Xilinx PROM Prog. FPGA Switch GSI 18x4Mb SRAM Ext. 5V/3A Conn. Spartan3 E FPGA Clock MUX/PLL VME Base Address A<31-28> A<27- 24> 7x Supply Monitor Red LED 3x Supply OK 80.15733 MHz XTAL Osc. VME J2 Clk+4 Delay Lines VME J1 Blue LED 4x Supply OK Set Serial No. SER<7-4> SER<3-0> SIL JTAG for FPGA USB Reset Switc h IN<7-0> TTL/NIM Sel. Set Mod. Record MR<7-4> MR<3-0> CLK-IN<1-0> ECL/NIM Sel. CLK-OUT<1-0> ECL/NIM Sel. OUT<7-0> TTL/NIM Sel. DIL JTAG for USB MCU 40-pin DIL HEADER USB MCU JTAG Ext. +5V / 3A Power Conn. CLK-IN<1- 0> 2x LEMOs 00 Global Reset Switch ( FPGA, MCU ) 4-pin USB AUX. DIL 16x I/Os FPGA JTAG Prog. MODE Hex Switch. 3x STATUS LEDs ( Programmable ) 3x4 LEDs ( Programm. ) Programm. Reset Switch CLK-OUT<1-0> 2x LEMOs 00 DATA-IN<7- 0> 8x LEMOs 00 DATA-OUT<7-0> 8x LEMOs 00 40-pin DIL HEADER VME J1 VME J2 3x LEDs NIM ECL 12x LEDs 3 3 3 3 3 SHIFT REG. 2 CLKIN0 IN0 IN2 IN6 IN4 CLKIN1 CLKOUT0 OUT0 OUT2 OUT6 OUT4 CLKOUT1 SW SW SW 2 2 8 8 2 2 8 8 NIM ECL NIM TTL NIM TTL HEX SELECT 16-pin AUX. CONNECTOR USB J-TAG X-TAL 80.15733MHz MPX PLL :2 40/80MHz select CLK Master DELAY 4x Slave DELAYS 4 4 4 CLKIN select FPGA & PROM 2 8 4 8 16 6 2 16 ( incl. 2x diff. pairs 2V5 LVDS ) SW SERIAL NO. MOD. RECORD SW SW 24 40-pin DIL BREAK-OUT HEADER (incl. 4x diff. pairs 2V5 LVDS ) 6x POWER 2x GND pins 32 EXT. +5V IN FUSES +3V3 +2V5 +1V8 +1V2 -5V -2V 6x DC-DC VME J1 VME J2 +5V Buffers VME BASE ADDRESS A<31-24> 16 22 Data 4Mbx18 SRAM Address MP-UCL, 18 August 2011 20x LEMO-00 Buffers All POWER Monitor 8 7 2x LEDs 7 8 8 SHIFT REG. Xilinx Spartan3e XC3S1600E-5FGG400C 7 6x FUSES 4 USB MCU • The CC system consists of a MTCA.4 Advanced Mezzanine Card ( AMC ) board and a Rear Transition Module ( RTM ) • The MTCA.4 AMC board ( DAMC2 ) is designed by DESY as a multi- purpose FPGA hardware platform for various projects in DESY and provides the processing capability for the CC functionality. We have developed a custom RTM board according to the MTCA.4 standard which connects to the DAMC2 through two thirty-pair Advanced Differential Fabric ( ADF ) connectors • The connections to the FEM boards are realised on AC- coupled LVDS links on CAT5 RJ45 cables. The RTM board provides the number of channels to support up to 16 FEM modules for a 1 MPixel 2D detector. • Each channel comprises 4 LVDS pairs on an RJ45 connector : - Output clock ( FAST clock ) : ~99 MHz clock derived from the 4.5 MHz bunch clock. - Output data ( FAST data ) : trigger start signal and train ID data - Veto : bunch reject data encoded on a either 99 or 4.5 MHz clock - Status : status feedback from the FEMs • Need to design, develop and test receiver circuitry required for AC- coupling of the data signal on the FEMs and the status signal on the CCs • The CC system receives clock and system information from the EuXFEL Timing Receiver ( TR ) through MTCA.4 crate backplane • The CC system is designed to provide scalability to support multi- Megapixel detectors by using extra AMC and uRTM board pairs in the same crate with one pair designated as master, and sharing the clock and the data through the MTCA.4 backplane • Each CC board pair takes up two slots ( double full-size board ) on the crate which comes in either 6 or 12 slot configuration • The CC hardware and firmware designed to provide the flexibility, extendibility and scalability to support possible future upgrades to the DAQ or larger detectors • This approach reduces the cost and effort for developing the system by using a general-purpose MTCA.4 FPGA board as its processing platform and an RTM to provide the custom functionality European XFEL GmbH Youngman, Christopher <[email protected]> Deutsches Elektronen- Synchrotron
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Transcript of New Corporate Identity Poster Design Department of Physics and Astronomy, University College London...
Department of Physics and Astronomy, University College London Erdem Motuk <[email protected]>, Martin Postranecky <[email protected]>, Matthew Warren <[email protected]>, Matthew Wing <[email protected]>
Poster Number 104
Topical Workshop on Electronics for
Particle Physics ( TWEPP-2011 )
Vienna, Austria 26 to 30 Sept. 2011
Electronics for the EuXFEL Clock and Control System
Design and Development of Electronics for the EuXFEL Clock and Control System
• Clock and Control ( CC ) hardware and firmware designed for the EuXFEL DAQ system
• The system exploits the data handling advances provided by the new telecommunication architecture standard for physics
• The CC is responsible for synchronising the DAQ system to overall system timing
• The hardware consists of a DESY designed MTCA.4 board and a UCL designed Rear Transition Module ( RTM )
• Each RTM controls up to 16 Front End Modules ( FEMs ) for a 1 Megapixel 2D detector
• The CC system is designed to provide extendibility and scalability to support future upgrades to the DAQ or larger detectors
Red LED –FPGA Prog.
Xilinx PROM
Prog. FPGA Switch
GSI 18x4Mb SRAM
Ext. 5V/3A Conn.
Spartan3E FPGA
Clock MUX/PLL
VME Base Address A<31-28> A<27-24>
7x Supply Monitor
Red LED 3x Supply OK
80.15733 MHz XTAL Osc.
VME J2
Clk+4 Delay Lines
VME J1
Blue LED 4x Supply OK
Set Serial No.
SER<7-4>
SER<3-0>
SIL JTAG for FPGA
USB Reset Switch
IN<7-0> TTL/NIM Sel.
Set Mod. Record
MR<7-4>
MR<3-0>
CLK-IN<1-0> ECL/NIM Sel.
CLK-OUT<1-0> ECL/NIM Sel.
OUT<7-0> TTL/NIM Sel.
DIL JTAG for USB MCU
40-pin DIL HEADER
USB MCU JTAG
Ext. +5V / 3A Power Conn.
CLK-IN<1-0> 2x LEMOs 00
Global Reset Switch ( FPGA, MCU )
4-pin USBAUX. DIL 16x I/Os
FPGA JTAG
Prog. MODE Hex Switch.
3x STATUS LEDs ( Programmable )
3x4 LEDs ( Programm. )
Programm. Reset Switch
CLK-OUT<1-0> 2x LEMOs 00
DATA-IN<7-0> 8x LEMOs 00
DATA-OUT<7-0> 8x LEMOs 00
40-pin DIL HEADER
VME J1 VME J2
3x LEDs
NIM
ECL
12x LEDs
3
3
3
3
3
SHIFT
REG.
2
CLKIN0
IN0
IN2
IN6
IN4
CLKIN1
CLKOUT0
OUT0
OUT2
OUT6
OUT4
CLKOUT1
SW
SW
SW
22
88
22
88
NIM
ECL
NIM
TTL
NIM
TTL
HEX SELECT
16-pin AUX. CONNECTOR
USB
J-TAG
X-TAL
80.15733MHz
MPX
PLL
:2
40/80MHz select
CLK Master DELAY
4x Slave DELAYS 4
44
CLKIN select
FPGA &
PROM
2
8
4
8
16
6
2
16 ( incl. 2x diff. pairs 2V5 LVDS )
SW
SERIAL NO.
MOD. RECORD
SW
SW
24
40-pin DIL BREAK-OUT HEADER (incl. 4x diff. pairs 2V5 LVDS ) 6x POWER 2x
GND pins32
EXT. +5V IN
FUSES
+3V3 +2V5 +1V8 +1V2 -5V -2V
6x DC-DC
VME
J1
VME
J2
+5V
Bu
ffer
s
VME BASE ADDRESS A<31-24>
16
22
Data 4Mbx18 SRAMAddress
MP-UCL, 18 August 2011
20x
LE
MO
-00 Bu
ffer
s
All POWER Monitor
8
72x LEDs
7
8
8
SHIFT
REG.
Xilinx Spartan3e XC3S1600E-5FGG400C
7
6x FUSES
4 USBMCU
• The CC system consists of a MTCA.4 Advanced Mezzanine Card ( AMC ) board and a Rear Transition Module ( RTM )
• The MTCA.4 AMC board ( DAMC2 ) is designed by DESY as a multi- purpose FPGA hardware platform for various projects in DESY and provides the processing capability for the CC functionality. We have developed a custom RTM board according to the MTCA.4 standard which connects to the DAMC2 through two thirty-pair Advanced Differential Fabric ( ADF ) connectors
• The connections to the FEM boards are realised on AC-coupled LVDS links on CAT5 RJ45 cables. The RTM board provides the number of channels to support up to 16 FEM modules for a 1 MPixel 2D detector.
• Each channel comprises 4 LVDS pairs on an RJ45 connector :
- Output clock ( FAST clock ) : ~99 MHz clock derived from the 4.5 MHz bunch clock. - Output data ( FAST data ) : trigger start signal and train ID data - Veto : bunch reject data encoded on a either 99 or 4.5 MHz clock - Status : status feedback from the FEMs
• Need to design, develop and test receiver circuitry required for AC- coupling of the data signal on the FEMs and the status signal on the CCs • The CC system receives clock and system information from the EuXFEL Timing Receiver ( TR ) through MTCA.4 crate backplane • The CC system is designed to provide scalability to support multi- Megapixel detectors by using extra AMC and uRTM board pairs in the same crate with one pair designated as master, and sharing the clock and the data through the MTCA.4 backplane
• Each CC board pair takes up two slots ( double full-size board ) on the crate which comes in either 6 or 12 slot configuration
• The CC hardware and firmware designed to provide the flexibility, extendibility and scalability to support possible future upgrades to the DAQ or larger detectors
• This approach reduces the cost and effort for developing the system by using a general-purpose MTCA.4 FPGA board as its processing platform and an RTM to provide the custom functionality
European XFEL GmbH Youngman, Christopher <[email protected]>
Deutsches Elektronen-Synchrotron
