New CMOS DVCC realization and applications to instrumentation amplifier and active-RC filters

Int. J. Electron. Commun. (AEÜ) 64 (2010) 47–55

www.elsevier.de/aeue

NewCMOSDVCCrealizationandapplicationsto instrumentationamplifierand active-RC filters

Tarek M. Hassan, Soliman A. Mahmoud∗

Electrical and Electronics Engineering Department, Faculty of Information Engineering and Technology, German University in Cairo(GUC), Egypt

Received 1 June 2008; accepted 23 November 2008

Abstract

This paper presents a novel CMOS differential voltage current conveyor (DVCC) based on a wide linear range transcon-ductor with common mode detection. The DVCC exhibits a wide dynamic input range of ±0.9V. It is used to realize aninstrumentation amplifier, a multiple input single output filter, and a single input multiple output universal filter. PSPICE sim-ulations of the proposed DVCC and its based applications are given using 0.25�m CMOS technology from TMSC MOSISand dual supply voltages ±1.5V.� 2008 Elsevier GmbH. All rights reserved.

Keywords: Differential voltage; Current conveyor; Transconductor; Filter; Instrumentation amplifier

1. Introduction

Since its first introduction, by Sedra and Smith [1], thesecond-generation current conveyor (CCII) has proved to bea versatile analog building block that can be used to imple-ment numerous high frequency analog signal applications,like filters [2–6] and current-mode oscillators [7]. However,when it comes to applications demanding differential orfloating inputs like impedance converters and current-modeinstrumentation amplifiers, which also require two high in-put impedance terminals, a single CCII block is no moresufficient. In addition, most of these applications employfloating elements in order to minimize the number of usedCCII blocks. For this reason and in order to provide twohigh input impedance terminals, the differential voltage cur-rent conveyor (DVCC) was proposed in 1997 [8] as a four

∗Corresponding author. Fax: +2027581041.E-mail address: [email protected] (S.A. Mahmoud).

1434-8411/$ - see front matter � 2008 Elsevier GmbH. All rights reserved.doi:10.1016/j.aeue.2008.11.002

terminal device with the following properties (Fig. 1):⎡⎢⎣IY1IY2VXIZ

⎤⎥⎦=

⎡⎢⎣0 0 0 00 0 0 01 −1 0 00 0 1 0

⎤⎥⎦⎡⎢⎣VY1VY2IXVZ

⎤⎥⎦ (1)

While the X terminal voltage follows the voltage differenceof terminals Y1 and Y2, a current injected at the X terminalis being replicated to the Z terminal. An ideal DVCC exhibitszero input resistance at terminal X, and infinite resistance atboth Y terminals as well as the Z terminal. The flow directionof the output current follows the input current direction withboth currents flowing either into or out of the device. Sincethe DVCC exhibits two high input impedance terminals, itshows itself suitable for handling differential input signals.In addition, it has the advantage of minimizing the numberof floating elements inherent in many CCII applications.In this paper a new wide range CMOS DVCC operating

under a supply voltage of ±1.5V is proposed. The inputstage of the proposed DVCC is realized using two widelinear range transconductors. The output stage consists of

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48 T.M. Hassan, S.A. Mahmoud / Int. J. Electron. Commun. (AEÜ) 64 (2010) 47–55

Fig. 1. Block representation of the DVCC.

a Class-AB CMOS push–pull network, which guaranteeshigh current driving capability and low standby current. Inaddition, this paper proposes a new multiple input singleoutput (MISO) filter based on the presented DVCC. Further-more, a new single input multiple output (SIMO) universalfilter with grounded elements is demonstrated. This paper isorganized as follows: in Section 2 the proposed wide rangeDVCC circuit is presented. Thereafter, DVCC applicationsincluding the MISO and the SIMO filters are discussed inSection 3. PSPICE simulations for all proposed circuits areprovided using 0.25�m TSMC CMOS technology.

2. Proposed DVCC CMOS circuit realization

2.1. Circuit description

The circuit realization of the proposed DVCC (Fig. 2) isbased on equalizing the output currents of two wide linearrange transconductors, formed by transistors (M1–M18). Inaddition, (M19–M22) comprise a Class-AB output stage,providing current swings up to ±1mA. Moreover, the cur-rent at the X terminal is transferred to the Z terminal withthe aid of (M23, M24), which must be – for a unity currentgain – matched with (M21, M22), respectively. All transis-tors are assumed to be operating in saturation. The opera-tion of a wide linear range transconductor relies mainly onbiasing a long tail differential pair LTDP (M1–M2) witha dynamic tail current ISS that increases with V 2

id whereVid = VY1 − VY2. Since the output current produced at thedrains of M2 and M6 is expressed by

Iout = IM1 − IM2 = −KV id

√ISS/K − (Vid/2)2 (2)

where K represents the transconductance parameter of M1or M2, then if the tail current is set to

ISS = K [(Vid/2)2 + c2] (3)

A linear relation between the output current and the differ-ential input voltage can be obtained with

Iout = −KcV id (4)

Obviously, the value of c should be constant, which alongwith the transconductance parameterK is defining the overallgain of the transconductor. Concerning the dynamic input

range, it is well known that the differential input voltageapplied to a LTDP is limited by

−√2ISS/K < Vid <

√2ISS/K (5)

Hence, in order to increase the input range of the transcon-ductor the ratio ISS/K should be increased. Such conditionis spontaneously satisfied if the tail current is dynamicallyincreased as in Eq. (3), which ensures an extended differ-ential input range. Biasing the LTDP with a constant tailcurrent, on the other hand, will require a high ISS/K ratio.Unfortunately, this affects the minimum possible commonmode input voltage, whose value must maintain the tailbiasing transistor in saturation [9]. The main concern nowis how to realize Eq. (3). Considering the differential paircurrents, they are given by

IM1 = K

2(VY2 − VS − VT )

2 (6)

IM2 = K

2(VY1 − VS − VT )

2 (7)

So taking into account that the input signals of a differentialpair can be divided into a common mode voltage (VCM ) anda differential voltage (Vid ) with VY1 = Vid/2 + VCM andVY2 = −Vid/2 + VCM where VCM = (VY1 + VY2)/2, thenthe tail current can be expressed by

ISS = IM1+IM2 = K

[(V 2id

2

)+(VCM−VS−VT )

2

](8)

Obviously, ISS will follow the function given in Eq. (3), ifthe subsequent expression is set to a constant value:

VCM − VS − VT = c (9)

A simple source follower (M13), whose gate is connected tothe common mode voltage of the LTDP, and whose sourceis clamped to the differential pair coupled source, can beused to satisfy Eq. (9). In this case, the source followershould have a constant drain current, set by M11, so that c isequal to

c =√2IBK13

(10)

As a consequence, the current equations result into

IM1 = K

2

(−Vid

2+√2IBK13

)2

(11)

IM2 = K

2

(Vid2

+√2IBK13

)2

(12)

Iss = K

[(Vid2

)2

+ 2IBK13

](13)

T.M. Hassan, S.A. Mahmoud / Int. J. Electron. Commun. (AEÜ) 64 (2010) 47–55 49

Fig. 2. CMOS realization of the proposed DVCC.

Iout = −K

√2IBK13

Vid (14)

IM9 = ISS + IB = K

[(Vid2

)2

+ IB

(2

K13+ 1

K

)](15)

From the previous equations, the standby current of M1 andM2 is defined by the value 2IB/K13. For differential inputvoltages greater than twice the square root of 2IB/K13 M1turns off and the current flowing in M2 increases. On theother hand, as the differential input voltage is decreasedbelow twice the square root of 2IB/K13, M2 turns off and thecurrent flowing in M1 increases. In both cases, M9 shouldfeed the necessary current required for proper operation ofM1 and M2 even if it enters slightly in the linear region.Therefore, the problem with the minimum common modeinput voltage required to maintain the tail biasing transistorin saturation has less effect in this circuit. Furthermore, sincebothM1 andM2 are ‘ON’ at standby, this circuit exhibits lowdistortion. It should be also noted that the current flowingin M9 will change by feedback action, formed by M15, inorder to stabilize the value of VS . In addition, the dynamicdifferential input range is extended to

−2√2IB/K13 < Vid < 2

√2IB/K13 (16)

Consequently, the compromise between the differential in-put voltage range and the LTDP standby current limits theperformance of the transconductor. Concerning VCM , if theinput voltages are fully differential or balanced, VCM1 is aconstant value that can be applied directly to the gate ofM13. Otherwise, a common mode detection circuit like theone shown in Fig. 3 is used to track VCM . For proper op-eration of the common mode detection circuit, all transis-tors should be working in saturation mode, while M25–M28should be matched. The input dynamic range of this circuit

Fig. 3. Common mode detection circuit.

is limited by

−2√2IC/K25 < Vid < 2

√2IC/K25 (17)

Moving back to the DVCC circuit, the voltage followeris implemented by connecting the outputs of two identicaltransconductors, producing the following total current at thedrain of M2:

Iout1 + Iout2 = K

√2IBK13

[−(VY1 − VY2) + (VX − 0)] = 0

(18)

In consequence, the voltage at the X terminal follows thevoltage difference of terminals Y1 and Y2. This condition isvalid as long as both output currents are linear, which is guar-anteed over a wide range when using the proposed transcon-ductor. Concerning the gate voltage of M14, it should followthe common mode voltage of the input signals applied toM3 and M4. As these inputs are neither fully differential nor


Table 1. Transistor aspect ratios for the proposed DVCC.

Transistors W (�m) L (�m)

M1–M4 0.5 4M5–M8 1 1M9–M12, M19–M20,M25–M28

0.5 0.5

M13–M14 0.5 1M15–M16 5 0.5M17–M18 1 0.5M21–M24 20 0.25M29–M30 6 2M31–M32 5 2

Fig. 4. The X and Z terminal output voltages versus changesof Vid .

balanced, a common mode detection circuit becomes essen-tial for the second transconductor, producing VCM2=VX/2.

2.2. Simulation results

The performance of the proposed COMS DVCC wasverified by performing PSPICE simulations with supplyvoltages ±1.5V using 0.25�m TSMC CMOS technology.Simulations were carried out using balanced input volt-ages with transistor aspect ratios given in Table 1. Fig. 4presents the X and Z voltages versus the differential inputvoltage, when the proposed DVCC is used to realize aunity gain amplifier with 5k� load resistance. The DVCCshows good linearity for differential input voltages between±0.9V, with a total standby power dissipation of 1.74mW.In Fig. 5 the magnitude response of the DVCC with adifferential voltage ac-varying signal of 0.5V magnitudeand open-circuited output terminals is demonstrated. TheDVCC shows a flat response with 85MHz 3-dB BW. Theinput and output referred noise spectral densities are thendisplayed in Fig. 6. Thereafter, the Z terminal output cur-rent versus the X terminal input current is shown in Fig. 7with a ±1mA linear range, while the variation of the offsetvoltage across the X terminal with grounded Vid is illus-trated in Fig. 8. The X terminal input resistance RX is lessthan 9� and the offset voltage does not exceed 8.2mV.

Fig. 5. Magnitude frequency response of the voltage transfer gain.

Fig. 6. Input and output voltage referred noise spectral densities.

Fig. 7. The Z terminal output current versus changes of IX.

Fig. 9 clarifies the push–pull action of the Class-AB out-put stage with a standby current of 136�A. Moreover, themagnitude response of the DVCC with an ac-varying inputcurrent of 10�A magnitude and a short-circuited Z terminalis displayed in Fig. 10. The DVCC provides a 120MHz3-dB bandwidth. The time response to a 1MHz differentialsquare input voltage is tested in Fig. 11, resulting in a risetime in the vicinity of 7.5ns. Finally, the total harmonicdistortion is evaluated for different differential input voltageamplitudes (Fig. 12). A 1MHz sinusoidal input generates


Fig. 8. The offset voltage of the X terminal along with itsderivative.

Fig. 9. Driving capabilities of the output stage.

Fig. 10.Magnitude frequency response of the current transfer gain.

a THD factor less than 0.009. The power supply rejectionratio (PSRR) from the positive supply to the output hasa value of 41.27dB and from the negative supply to theoutput is 50.3dB. Table 2 compares the performance pa-rameters of the proposed DVCC with a DVCC employingconstant tail current (omitting M11–M18, and the commonmode detector circuit). The proposed circuit exhibits a 2.25times wider voltage range on the expense of a 49�W powerincrease, and a 39% BW loss.

Fig. 11. The X terminal voltage along with a 0.5V–1MHz differ-ential square input.

Fig. 12. X terminal total harmonic distortion (for frequencies100kHz and 1MHz).

3. Applications based on the proposed DVCC

In this section the proposed DVCC is used to realize an in-strumentation amplifier, a new MISO second-order LP–BPfilter, and a SIMO second-order universal filter. In allapplications one should recognize the benefits of usingdifferential voltage current conveyors, which focus on pro-viding high input impedance circuit designs with groundedelements.

3.1. Instrumentation amplifier

The first basic application that can be implemented us-ing a DVCC is an instrumentation amplifier as shown inFig. 13. An instrumentation amplifier takes a differential in-put voltage, multiplies it with a gain, and produces a single


Table 2. Performance comparison for the proposed DVCC.

Parameter Proposed DVCC Constant tail current DVCC

CMOS technology (�m) 0.25 0.25Power supply (VDD, VSS) (1.5V, −1.5V) (1.5V, −1.5V)No. of transistors 32 16Total power dissipation (mW) 1.74 1.25Tail current Dynamic 10�AStandby current of the output stage (ISB) (�A) 136 136PSRR+ (dB) 41.27 34.56PSRR− (dB) 50.3 50.1Input dynamic range with thel X terminal resistance 5k� −0.9V to 0.9V −0.4V to 0.4VVoltage transfer error 0.00136 0.00237Current driving capability (mA) ±1 ±1Current transfer error 0.0013 0.0051X terminal offset voltage withl Y and Z are ground (mV) 8.2 24X terminal input resistance (�) 9 32X terminal open circuit BW (MHz) 85 137Z terminal short circuit (MHz) 120 250X terminal THD at Vid = 0.2 sin 2� f 0.0013 at 1MHz 0.0069 at 1MHzRise time/fall time (pulse 0.25V at 1MHz) 7.48ns/6.24ns 3.2ns/3.1nsInput referred noise (nV/

√Hz) 130 94.64

Input referred noise (nV/√Hz) 132 94.56

Fig. 13. Circuit realization of the instrumentation amplifier.

ended output voltage. The relation between the output volt-age and the differential input can be described by the fol-lowing equation:

Vout = R2

R1Vid (19)

Obviously, the ratio of the Z terminal resistance to the Xterminal resistance defines the gain G of the amplifier. Inaddition, this circuit can realize an inverting or noninvert-ing amplifier, by simply connecting Y1 or Y2 to ground,respectively. One should also note that this circuit can beutilized as a voltage-controlled voltage source (VCVS). Inorder to verify the performance of the instrumentation am-plifier, PSPICE simulations were carried out using ±1.5Vsupply voltages. The X terminal resistance was set to 2k�,while the Z terminal resistance was scanned from 2 to 8k�in steps of 2k�. The length of the output stage transistorswas increased to 0.75�m to minimize the channel lengthmodulation effect. Fig. 14 displays the DC gain of the in-strumentation amplifier for G varying from 1 to 4, while

Fig. 14.DC transfer characteristics of the instrumentation amplifier(G = 1–4).

Fig. 15 is demonstrating the ac gain. The 3-dB BW provesto be constant for different gain values.

3.2. MISO BP–LP filter

In this section the proposed DVCC is used to realize aMISO second-order LP–BP filter as shown in Fig. 16. Twodifferent responses are achieved depending on the actualactive input. If the first input is active, while the second oneis grounded, an inverting bandpass response is obtained. Onthe other hand, grounding the first input while activatingthe second one generates a noninverting lowpass response.This can be verified through direct analysis, obtaining the


Fig. 15. Magnitude frequency response of the instrumentationamplifier (G = 1–4).

Fig. 16. Circuit realization of the MISO filter.

following transfer equations and gains:

VOV1

= − (S/C1R)

D(S)(20)

VOV2

= (1/C1C2R2R)

D(S)(21)

D(S) = S2 + S

R1C1+ 1

C1C2R2R(22)

AvBP = − R1

R(23)

AvLP = 1 (24)

From Eq. (22), �0 and Q and of the filter are given by

�0 =√

1

C1C2R2R(25)

Q = R1

√C1

C2R2R(26)

Simulation results prove the aforementioned relations withpassive element values given in Table 3. In Fig. 17 a low-pass response is generated by grounding V1 and applyingan ac-varying signal at V2. The cutoff frequency is around

Table 3. Passive elements of the MISO filter.

LPF elements Value BPF elements Value

R, R1–R2 1k� R 2k�C1 0.25nF R1 0.65k�C2 0.5nF R2 0.5k�

C1 0.8nFC2 0.2nF

Fig. 17. LP magnitude frequency response of the MISO filter.

Fig. 18. BP magnitude frequency response of the MISO filter.

465kHz, which is very close to the theoretical value. Next,the bandpass response is tested by grounding V2 and inject-ing the ac-varying signal at V1. The passive element valueswere optimized as shown in Table 3 to achieve a bandpassfilter with a 7.4 quality factor Q and a 690kHz center fre-quency f0 (Fig. 18).

3.3. SIMO filter

The filter configuration presented in Fig. 19 realizes aSIMO universal filter with noninverting HP, BP and LP out-puts. This filter employs four DVCC blocks, two groundedcapacitors, and five grounded resistors. The first two inputblocks operate as a summer and the last two are integra-tors, with their outputs fed back to the input DVCC blocks.This configuration, which resembles the CFOA based fil-ter proposed in [10], provides several advantages over the


Fig. 19. Circuit realization of the SIMO universal filter.

Fig. 20. LP and HP magnitude frequency responses of the SIMOfilter.

typical active filters with CFOA. First, it has infinite inputand output impedances. Second, all elements are grounded.By applying direct analysis to the filter blocks, the followingtransfer functions and gains are obtained:

VHP

Vi= (S2R(R3 + R4)/R3R4)

D(S)(27)

VBP

Vi= (SR(R3 + R4)/R1C1R3R4)

D(S)(28)

VLP

Vi= (R(R3 + R4)/R1C1R2C2R3R4)

D(S)(29)

D(S) = S2 + SR

C1R1R4+ R

C1C2R1R2R3(30)

AvHP = R(R3 + R4)

R3R4(31)

AvBP = 1 + R4

R3(32)

AvLP = 1 + R3

R4(33)

Table 4. Passive elements of the SIMO filter.

LPF, HPF elements Value BPF elements Value

R, R1–R4 1k� R, R2–R3 0.5k�C1 0.25nF R1, R4 2k�C2 0.5nF C1 0.2nF

C2 0.2nF

Fig. 21. BP magnitude frequency response of the SIMO filter.

From Eq. (30), �0 and Q and of the filter are given by

�0 =√

R

R1R2R3C1C2(34)

Q = R4

√R1C1

RR2R3C2(35)

Fig. 20 shows the simulated highpass and lowpass frequencyresponses with the design parameters given in Table 4. Thesimulated cutoff frequency equals to 469kHz which is veryclose to the theoretical value. The design parameters arethen optimized as shown in Table 4 to achieve a bandpassresponse with Q = 8 and f0 = 800kHz (Fig. 21).

4. Conclusion

In this paper, a novel CMOS DVCC based on a wide lin-ear range transconductor has been presented. The DVCChas demonstrated a wide dynamic range in the vicinity of±0.9V for the voltage follower and a ±1mA for the currentfollower. The DVCC was used to implement an instrumen-tation amplifier, a MISO LP–BP filter, and a SIMO universalfilter. The proposed DVCC circuit and the realized applica-tions have been verified using PSPICE simulations.

References

[1] Sedra A, Smith K. A second-generation current conveyorand its applications. IEEE Transactions on Circuit Theory1970;17:132–4.


[2] Mahmoud SA. Fully differential CMOS CCII based ondifferential difference transconductor. Analog IntegratedCircuits and Signal Processing 2007;50:195–203.

[3] Soliman AM. Current conveyors steer universal filter. AnalogAction 1995; 45–6.

[4] Mahmoud SA. New fully differential CMOS second-generation current conveyor. ETRI Journal 2006;28:495–501.

[5] Mahmoud SA. Fully differential CMOS CCII based ondifferential difference transconductor. Analog IntegratedCircuits and Signal Processing 2006;49:267–79.

[6] Mahmoud SA, Hashiesh MA, Soliman AM. Digitallycontrolled fully differential current conveyor. IEEETransactions on Circuits and Systems I 2005;52:2055–64.

[7] Soliman AM. Current feedback operational amplifier basedoscillators. Analog Integrated Circuits and Signal Processing2000;32:45–55.

[8] Elwan HO, Soliman AM. Novel CMOS differential voltagecurrent conveyor and its applications. IEE Proceedings1997;144:195–200.

[9] Ismail AM, Soliman AM. Novel CMOS linearized balancedoutput transconductance amplifier based on differential pairs.Frequenz 1999;53:170–4.

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Tarek Hassan was born in Cairo,Egypt, in 1978. He received the B.Sc.degree in Electronics and Communi-cations Engineering from Cairo Uni-versity, Cairo, Egypt, in 2002. Hewill be acquiring his M.Sc. degree inElectrical and Electronics Engineeringfrom the German University in Cairo,Cairo, Egypt, in 2007. He is currentlyworking as a research and teaching

assistant at the Electrical and Electronics Engineering Department,German University in Cairo. His research interests are in circuittheory; low-voltage analog CMOS circuit design, current-modeanalog signal processing, and mixed analog/digital programmableanalog blocks. He is currently also an IEEE student member.

Soliman Mahmoud was born in Cairo,Egypt, in 1971. He received the B.Sc.degree with honors in 1994, the M.Sc.degree in 1996, and the Ph.D. degreein 1999, all from the Electronics andCommunications Department, CairoUniversity, Egypt. He is currently anAssociate Professor at the ElectricalEngineering Department, Fayoum Uni-versity, Egypt. He is currently also a

visiting Associate Professor at the Electrical and Electronics Engi-neering Department, German University in Cairo, Egypt. In 2005,He was decorated with the Science Prize in Advanced EngineeringTechnology from the Academy of Scientific Research and Tech-nology. His research and teaching interests are in circuit theory,fully integrated analog filters, high-frequency transconductanceamplifiers, low-voltage analog CMOS circuit design, current-modeanalog signal processing, and mixed analog/digital programmableanalog blocks.

New CMOS DVCC realization and applications to instrumentation amplifier and active-RC filters

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