Network and Systems Laboratory nslab.ee.ntu.edu.tw 2011/12/23Wireless Sensor Network And Labs fall...

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Network and Systems Laboratorynslab.ee.ntu.edu.tw

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AdminSurvey Presentation next week

20 minutes presentation, 5 minutes Q&ADuring Q&A, next team prepareTerm project demo will reverse the sequence

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Time Team

9:10 am ~ 9:35 am Team 1

9:35 am ~ 10:00 am Team 2

Break

10:15 am ~ 10:40 am Team 3

10:40 am ~ 11:05 am Team 4

Break

11:20 am ~ 11:55 am Team 5

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AdministrationWeek 17 (1/6): Term Project workshop

No class, I will be here to help you work on your term project

Deadline for the lab exercises Demo and turn on your codes before 2011/1/6 23:59

Check Point Make your car move (forward, backward, turn) Avoid obstacle

When your car detect obstacle, it will turn

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OutlineMore peripherals

Watchdog TimerSupply Voltage Supervisor (SVS)Direct Memory Access (DMA)Flash Memory Controller

External 8Mbit Flash Memory: M25P80Temperature/humidity sensor: SHT11Low Power ModesMSP430 Software Coding Techniques

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Watchdog TimerMost embedded systems need to be self-reliantwatchdog timer is a hardware

that can watch for system hang reset the processor if any occur

It is a counter counts down from some initial value to zeromust select a counter valueperiodically restarts the counter

before it counts to zeroIf it counts to zero

trigger a system reset

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Watchdog timer on MSP43016-bit timer, four software-selectable time intervals

(clock source)/32768, (clock source)/8192, (clock source)/512, (clock source)/64

Can be configured into watchdog mode or interval modeWatchdog mode: generate a reset when timer expiredInterval mode: generate a interrupt when timer expired

When power up, it is automatically configured in the watchdog modeInitial ~32-ms reset interval using the DCOCLK.Must halt or setup the timer at the beginning

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UsageStop watchdog timer

WDTCTL = WDTPW + WDTHOLD;Change watchdog timer interval

WDTCTL = WDTPW+WDTCNTCL+(interval)Periodically clear an active watchdog

WDTCTL |= WDTPW+WDTCNTCL

ClockSource/32768:ClockSource/8192: WDTIS0ClockSource/512: WDTIS1ClockSource/64: WDTIS0 + WDTIS1

Password-protected: must include the write password

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ExampleSelect clock source: ACLKSelect clock source: ACLK Select timer interval:

(clock source)/8192 = 32768Hz/8192= 4Hz

Select timer interval: (clock source)/8192 = 32768Hz/8192= 4Hz

Reset watchdog counterReset watchdog counter

Reset watchdog counterReset watchdog counter

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Supply Voltage SupervisorMonitor the AVCC supply voltage or an

external voltageCan be configured to set a flag or generate a

reset when the supply voltage or external voltage drops below a user-selected threshold

Comparison14 threshold levels for AVCCExternal input: SVSIN

compared to an internal level of approximately 1.2 V

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SVS RegisterSVSCTL

VLDx

This bit will set to 1 if the voltage is below threshold

This bit will set to 1 if the voltage is below threshold

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Example

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Direct Memory AccessTransfers data from one address to another,

without CPU interventionIncrease throughput and decrease power

consumptionDMA on MSP430

Three independent transfer channelsConfigurable transfer trigger selections

Timer, UART, SPI, ADC, …..Byte or word and mixed byte/word transfer capabilitySingle, block, or burst-block transfer modesBlock sizes up to 65535 bytes or words

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DMA Addressing Modes

Source/destination address can be configured to be unchange/increment/decrement after each transfer

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DMA Transfer Modes Six transfer modes

Single transfer, block transfer, burst-block transfer, repeated single transfer, repeated block transfer, repeated burst-block transfer

Single transfer Each transfer requires a separate trigger, DMA is disable after

transfer Must re-enable DMA before receive another trigger

Repeated single transfer: DMA remains enable Another trigger start another transfer

Block transfer Transfer of a complete block after one trigger, DMA is disable after

transfer Repeated block transfer: DMA remains enable,

Another trigger start another transfer Burst-block transfer

Block transfers with CPU activity interleaved, Repeated burst-block transfer: DMA remains enable

Keep transferring CPU executes at 20% capacity

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DMA Triggers

A transfer is triggered when the CCIFG flag is set

A transfer is triggered when the CCIFG flag is setA transfer is triggered when USART0 receives new data

A transfer is triggered when USART0 receives new data

A transfer is triggered when USART0 is ready to transmit new data

A transfer is triggered when USART0 is ready to transmit new data

A transfer is triggered by an ADC12IFGx flag.A transfer is triggered by an ADC12IFGx flag.

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Initialization And Usage

Example

(DMACTL0)Configure transfer trigger

(DMACTL1)Select transfer mode, addressing mode, and/or other setting, and enable DMA

(DMA0SA)Configure source address

(DMA0DA)Configure destination address

(DMA0SZ)Configure block size

Use DMA to transfer a string to UART buffer, send it out through UART

Repeated single transferRepeated single transfer

Source address is incrementedSource address is incremented

source byte to destination byte

source byte to destination byte

DMA enableDMA enable2011/12/23

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Others About DMA DMA Transfer Cycle Time

DMA transfers are not interruptible by system interrupts

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Flash Memory ControllerMSP430 flash memory is bit-, byte-, and word-

addressable and programmableSegment erase and mass eraseMinimum VCC voltage during a flash write or

erase operation is 2.7 V

Program code are stored in the flashUnused flash memory can be use to store other

data

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Flash Memory CharacteristicsWrite in bit-, byte-, or word; erase in segmentMSP430F1611 segment size

Information memory: 128 bytesMain memory: 512 bytes

EraseMake every bit in the segment as logic 1

WriteGenerate logic 0 in the memory

Flash enduranceMaximum erase/write cyclesIn MSP430 datasheet

Minimum: 10000 cycles Typical: 100000 cycles

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Flash Memory OperationRead, write, erase mode

Default mode is read modeWrite/erase modes are selected with the

BLKWRT, WRT, MERAS, and ERASE bitsFlash Memory Timing Generator

Sourced from ACLK, SMCLK, or MCLKMust be in the range from ~ 257 kHz to ~ 476

kHz Incorrect frequency may result in unpredictable

write/erase operation

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Flash Memory Erase

Example

(FCTL2)Setup timing generator

(FCTL3)Unlock flash memory

(FCTL1)Configure the operation

Disable all interrupts and watchdog

Dummy write

(FCTL3)lock flash memory

Re-enable interrupt and watchdog

Wait until erase complete

Password protected

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Example

Flash Memory Write(FCTL2)Setup timing generator

(FCTL3)Unlock flash memory

(FCTL1)Configure the operation

Disable all interrupts and watchdog

Write to specific memory address

(FCTL3)lock flash memory

Re-enable interrupt and watchdog

Wait until write complete

Password protected

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OutlineMore peripherals

Watchdog TimerSupply Voltage Supervisor (SVS)Direct Memory Access (DMA)Flash Memory Controller

External 8Mbit Flash Memory: M25P80Temperature/humidity sensor: SHT11Low Power ModesMSP430 Software Coding Techniques

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M25P80External Flash storage on Taroko8 Mbit Flash MemorySPI Bus Compatible Serial InterfaceMemory organization

16 sectorsEach sector containing 256 pagesEach page is 256 bytes

OperationsErase: set all bit to 1Program(write): reset some bits to 0Read: read the content of the flash

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Signals And Connections

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SPIMaster–Slave modeSynchronous protocolAll transmissions are referenced to a common clockClock generated by the master (MCU)Four main signalsMaster Out Slave In (MOSI): data from master to slaveMaster In Slave Out (MISO): data from slave to masterSerial Clock (SCLK or SCK): clockChip Select (CS): select particular peripheral when

multiple peripherals are connected to master

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Memory organization

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Instruction Set

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OperationRead Data Bytes (READ)

Read data from memoryPage Program

Write bytes to a pageUp to 256 bytes each time

Sector Erasesets all bits to 1 inside the chosen sector

Bulk EraseErase (sets to 1) all memory data

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Device DriverDownload here

http://nslab.ee.ntu.edu.tw/courses/wsn-labs-spring-09/labs/m25p80Driver.rar

Important functions in hal_m25p80.cvoid halM25p80Init(void)void m25p80PowerUp(void);void m25p80PowerDown(void);void m25p80PageWrite(UINT16 add, UINT8 *buff,

UINT8 size);void m25p80PageRead(UINT16 add, UINT8 *buff,

UINT8 size);void m25p80SectorErase(UINT8 add);void m25p80BulkErase(void);

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Functionsvoid m25p80PageWrite(UINT16 add, UINT8 *buff, UINT8

size);address range from 0x0000 to 0x0fff (4096 pages in total)At most 256 bytesAlways write from the beginning of the pagevoid m25p80PageRead(UINT16 add, UINT8 *buff, UINT8

size);address range from 0x0000 to 0x0fff (4096 pages in total)At most 256 bytesAlways read from the beginning of the pagevoid m25p80SectorErase(UINT8 add);address range from 0x00 to 0x0f (16 sectors in total)Each sector is 65536 bytes

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Example

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OutlineMore peripherals

Watchdog TimerSupply Voltage Supervisor (SVS)Direct Memory Access (DMA)Flash Memory Controller

External 8Mbit Flash Memory: M25P80Temperature/humidity sensor: SHT11Low Power ModesMSP430 Software Coding Techniques

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SHT11Relative humidity and temperature sensors Digital output Manufacturer defined interface

two wires bi-direction

1. Use a GPIO pin as clock (SCK), it is always output direction

2. Use another GPIO as DATA, dynamic setting it to input(read) or output(write) direction

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Taroko Connections

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Start Transmission and Send CommandHow to start

What are the commands available

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An Example: SHT11Timing diagram

Pull-up

Data pin in output

direction

Set data pin to input direction,

then SHT11 controls the DATA line

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Software Implementation

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Software Implementation

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Software Implementation

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Convert to Physical Values 12-bit humidity, 14-bit temperatureTemperature

Humidity

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Device DriverDownload here

http://nslab.ee.ntu.edu.tw/courses/wsn-labs-spring-09/labs/sht11Driver.rar

Important functions in SHT1x_sensirion.cvoid sht1xInit();void sht1xReset();char sht1xMeasure(unsigned char *p_value,

unsigned char *p_checksum, unsigned char mode);

void sht1xCalculate(float *p_humidity ,float *p_temperature);

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Functionschar sht1xMeasure(unsigned char *p_value, unsigned

char *p_checksum, unsigned char mode);mode: { TEMP, HUMI }Store measured value to *p_valueStore 8-CRC checksum to *p_checksumvoid sht1xCalculate(float *p_humidity ,float

*p_temperature);Convert measured value to physical valuePut the measured value in *p_humidity, *p_temperatureResult will also place in *p_humidity, *p_temperature

(overwrite)

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Example

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OutlineMore peripherals

Watchdog TimerSupply Voltage Supervisor (SVS)Direct Memory Access (DMA)Flash Memory Controller

External 8Mbit Flash Memory: M25P80Temperature/humidity sensor: SHT11Low Power ModesMSP430 Software Coding Techniques

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MSP430digitally controlled oscillator

Low-frequency/high-frequency oscillator

high-frequency oscillator (optional)

MSP430 Clock System

LFXT1CLK

XT2CLK

DCOCLK

Clock ModulesMCLK:

Master Clock

SMCLK:Sub-main

clock

ACLK:Auxiliary

clock

Clock Signals

CPU

Peripherals:Timer, UART, …

32.768KHz fixed rate

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MSP430 Power Consumption CharacteristicsCurrent increase with clock frequencyCurrent increase with supply voltageSupply voltage vs frequency

More active peripherals means more current consumption

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Operating Modes MSP430 has six operating modesThe operating modes take into account three

different needsUltralow-power Speed and data throughput Minimization of individual peripheral current

consumption

Turn off different clocks in different operating mode

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Operating Modes

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Typical Current Consumption

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Low Power ModesDifferent low power mode disable different

clocks

Peripherals operating with any disabled clock are disabled until the clock becomes active

Wake up is possible through all enabled interruptsReturns to the previous operating mode if the

status register value is not altered during the ISR

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Code Flow

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Enter/Leave LPM

Intrinsic function

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Which LPM To Enter?Depends on your configurationMSP430 has a flexible clock system

Clock signal can select different clock sourcePeripheral can be configure to use different

clock signal

Which clock signal still require when system goes to sleepRemember the peripherals that use the clock

signal will also be disabled

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CautionsWakeup latency

Clock module require some time to get stable DCO: less than 6 μS Low frequency oscillator (32.768KHz): hundreds of

milliseconds

Temperature driftDCO change with temperatureIf temperature is possible to changes significantly,

re-calibrate DCO when leaving low power mode If DCO varying too large, some peripherals might not

function correctly, ex. UART

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MSP430digitally controlled oscillator

Typical Configuration

LFXT1CLK

XT2CLK

DCOCLK

Clock ModulesMCLK:

Master Clock

SMCLK:Sub-main

clock

ACLK:Auxiliary

clock

Clock Signals

CPU

Peripherals:Timer, UART, …

32.768KHz fixed rate

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Useful ModeLPM0

CPU, MCLK offDCO, SMCLK, ACLK onPower consumption: 60 μA (Taroko)SMCLK still required

Ex. UART use SMCLKLPM3

CPU, MCLK, DCO, SMCLK offACLK on Power consumption: 7 μA (Taroko)Only ACLK required

Timer use ACLK (time keeping)

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Principles for Low-Power ApplicationsMaximize the time in LPM3Use interrupts to wake the processor and

control program flowPeripherals should be switched on only when

neededUse low-power integrated peripheral modules

in place of software driven functionsFor example: Timer PWM, DMA

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MSP430 Software Coding Techniques

Using these methods can greatly reduce debug time and/or provide additional robustness in the field

Some should be used in every program, while some are situation dependent

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TechniquesFirst Things First: Configure the Watchdog and

OscillatorConfiguring the watchdog should be among the

first actions taken by any MSP430 programUsing a low-frequency crystal on LFXT1 with a

device from the 4xx or 2xx families, the code should configure the internal load capacitance (not for MSP430F1611)

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TechniquesAlways Use Standard Definitions From TI Header

FilesThis is what we do

Using Intrinsic Functions to Handle Low Power Modes and Other Functions

Intrinsic function

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TechniquesWrite Handlers for Oscillator FaultsIn MSP430F1611, you can only delay for some time

to ensure the low frequency oscillator to stable The other MSP430 family has specific circuit to detect

Increasing the MCLK FrequencyMake sure you have enough voltage level to operate

at the frequency you set Or unpredictable behavior

can occur

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TechniquesUsing a low-level initialization functionProblem

By default, when a C compiler generates assembly code, it creates code that initializes all declared memory and inserts it before the first instruction of the main() function

In the event that the amount of declared memory is large The time required to initialize the long list of variables

may be so long that the watchdog expires before the first line of main() can be executed

Solution Disables the initialization of memory elements that don't

need pre-initialization __no_init int x_array[2500];

Use a compiler-defined low-level initialization function

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TechniquesIn-System Programming (ISP)If using the MSP430 ISP functionality to write to flash

memory1. Set the correct timing value (257 kHz to ~ 476 kHz)2. Set the flash lock bit after the ISP operation is

complete3. Take care that the cumulative programming time4. Provide sufficient VCC

Using Checksums to Verify Flash IntegrityFlash memory data may corrupt, use checksum to

verify flash integrity periodically2011/12/23

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Electromagnetic CompatibilityEMI – Electromagnetic interference

Unintentional generation, propagation and reception of electromagnetic energy

EMC - Electromagnetic compatibilityFunction properly in its intended

electromagnetic environmentNot be a source of pollution

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EMC on SoftwareUsually EMC is consider as a hardware

problemBut some software techniques can greatly

improve the immunity of the systemWhat will EMC cause

False Signal DetectionCode RunawayDisable interruptsCorrupt register settingEtc.

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Software ImmunityReference

“Improving the Transient Immunity Performance of Microcontroller-Based Applications”

by: Ross Carlton, Greg Racino, John SuchytaFreescale Semiconductor, Inc.

They refer these techniques as “defensive programming”You can find more on www

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Digital Input Pins ErrorMajority vote

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Update Registers SettingDigital Outputs and Crucial Registers

In main system software loop frequently update outputs and other critical

registersIncluding

Data direction registers I/O modules that can be modified by software RAM registers that are used for vital pieces of the

application

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Token Passing

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Filling Unused MemoryFill unused memory with a single byte

instructionSWI (software interrupt)NOP (no operation)

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Some OthersBoundary Checking

Validating input signalsFor example: timer capture

Unused Interrupt VectorsDefine all interrupt vectorsVectors from unused MCU functions should be

pointed to a safe routine2011/12/23

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TAR (counter)

EventsTACCR_1 = 15000 TACCR_2 =

60000Noise TACCR_n = 15100 Filter this capture if it is too shortFilter this capture if it is too short

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Choose What You NeedThese techniques come with some cost

Increase code sizeComplexity

Probably wouldn’t need these in this classBut they might help in the future

Choose the one you needFor simple one (periodic update register, fill

unused memory, define all interrupt vectors), Should probably do it every time

For more complicated, depends on you

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Thank You

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