NetStaQ ADMA-100 Breaking the Bottlenecks By Curtis E. Stevens Don Doan.

NetStaNetStaQQ ADMA-100 ADMA-100

Breaking the BottlenecksBreaking the Bottlenecks

ByBy

Curtis E. StevensCurtis E. Stevens

Don DoanDon Doan

31-JUL-0131-JUL-01 Pacific Digital CorporationPacific Digital Corporation Slide Slide 22

AgendaAgenda

• Introduction to ADMA

• Performance Statistics


LegacyLegacyCommand & Interrupt FlowCommand & Interrupt Flow

Application File System

Miniport

PCI Bus

ControllerDrive

InterruptHandler

Port Driver



Miniport

PCI Bus

ControllerDrive

InterruptHandler

Port Driver




Miniport

PCI Bus

ControllerDrive

InterruptHandler

Port Driver

Drive dead time




Miniport

PCI Bus

ControllerDrive

InterruptHandler

Port Driver



Legacy Transfer StatisticsLegacy Transfer Statistics

• Ultra DMA data transfer

• 8 I/O’s per command– Includes 7 I/O’s for storing the command– Includes 1 I/O to read the status register in

the interrupt

• Additional I/O’s to setup DMA controller

• 1 Interrupt per command


ADMAADMACommand & Interrupt FlowCommand & Interrupt Flow


ADMA Transfer StatisticsADMA Transfer Statistics

• Ultra DMA data transfer

• No I/O– ADMA registers are memory mapped– ADMA uses normal PCI memory reads and

writes to retrieve commands

• 1 Interrupt per group of I/O requests– Commands that complete while an ADMA

interrupt is processed will not generate an additional interrupt


ADMA Command ChainsADMA Command ChainsCPB Next Address

RegisterCPB

PRD Pointer

Next CPBPointer

CPB

PRD Pointer

Next CPBPointer

CPB

PRD Pointer

Next CPBPointer

CPB Lookup Table

CPB AddressCPB AddressCPB Address...

CPB Lookup TableAddress Register

PRD PRD PRD

PRD PRD PRD

PRD PRD PRD


ADMA Block DiagramADMA Block DiagramATA/ATAPI Bus

PCI Bus

ATA/ATAPIBus

8/1

6-B

its

32

/64

-Bit

s

Channel YChannel X8

/16

-Bit

s

PCI ConfigurationHeader Registers

InterruptController

ATA Core

8/1

6-B

its

PCI Channel Arbiter

PCI Core

Legacy PIOMode

BIOS

4K

B F

IFO

4K

B F

IFO

16

-Bit

s

ADMA Mode

16

-Bit

sATA

Sequencer

PCISequencer

FIFOController


Performance StatisticsPerformance Statistics


Test ConditionsTest Conditions• System (Micron)

– 500Mhz P3

– 192MB RAM

– NT 4.0 SP6

– Intel 82801 Chipset

– 33Mhz PCI slot on a 66Mhz bus

– Micron Northbridge

• Iometer– Fileserver access pattern

– 100% Random, 80% Reads, 60% 4k blocks (remainder spread from 512 bytes to 64kbytes)

• Process– Boot using motherboard controller (same drive for all tests)

– UDMA-100 card has for drives attached

– ADMA card is in the same slot using the same 4 drives


File Server Access PatternFile Server Access Pattern

050

100150200250300350400450500550600

Outstanding I/O's

I/O's

per

Sec

on

d

1 Ultra-100 Queued

2 Ultra-100 Queued

3 Ultra-100 Queued

4 Ultra-100 Queued

Ultra-100 controller using drives that support queueing. The Ultra-100 controller does not using the queing capability of the drive.



050

100150200250300350400450500550600

Outstanding I/O's

I/O's

per

Sec

on

d

1 Ultra-100 Non-Queued




Ultra-100 controller using drives that do not support queueing.



050

100150200250300350400450500550600

Outstanding I/O's

I/O's

per

Sec

on

d

1 ADMA Queued

2 ADMA Queued

3 ADMA Queued

4 ADMA Queued

ADMA controller using drive queing capability



050

100150200250300350400450500550600

Outstanding I/O's

I/O's

per

Sec

on

d

1 Ultra-100 Queued2 Ultra-100 Queued3 Ultra-100 Queued4 Ultra-100 Queued1 ADMA Queued2 ADMA Queued3 ADMA Queued4 ADMA Queued

Overlay of Ultra-100 controller using drives that support queingwith ADMA controller using queued capability. The Ultra-100 controller does not using the queing capability of the drive.


Any QuestionsAny Questions

NetStaQ ADMA-100 Breaking the Bottlenecks By Curtis E. Stevens Don Doan.

Documents

Transcript of NetStaQ ADMA-100 Breaking the Bottlenecks By Curtis E. Stevens Don Doan.