Device-Level BTI-induced Timing Jitter Increase in Circuit-Speed Random Logic Operation

J.W. Lu, C. Vaz, J.P. Campbell, J.T. Ryan, G.F. Jiao, G. Bersuker, C.D. Young

NISTSEMATECH

University of Texas at Dallas

K.P. Cheung

Bias-Temperature-Instability (BTI) serious reliability problem.Design-in reliability circuit solution to device reliability problem.

Hot topics in advanced CMOS:

Question:What is the circuit impact of the fast transients in BTI?

Grasser, T. and B. Kaczer, ESSDERC 2007.

Zhao, K., J. Stathis, et al., IRPS 2012

NBTI PBTI

Standard BTI (n or p) reliability focus on “permanent” (non-recoverable) part of the degradation.

Most circuit reliability simulator follow this “simple” approach.Some newer reliability simulator include the fast recovery, but mostly as degradation reduction.

Background

A report has shown that the fast transient can cause SRAM failure

Another report showed that the fast transient can cause problem in analog circuit such as differential amplifiers and fast comparators.

The problem is largely considered a curiosity with little consequence.

As fabricated some defects (hopefully low density).After BTI stress defect density increase.

Charges flow in during ON period VTH shift (reduce gate overdrive)Charges flow out during OFF period VTH shift (recover gate overdrive)

The fast transients are the result of traps filling and emptying.

For a given defect densityLonger ON time more complete trap fillingLonger OFF time more complete trap emptying

Effect is larger as the device ages.

For random logic running at high speed:

Significant increase in signal timing jitter (random skew) should be expected.

randomskewradation tt ∆+∆+ deg

randomskewradation tt ∆+∆+ deg

Ring oscillators cannot detect this effect …

Constant ON and OFF time

For timing jitter in random bit pattern, eye diagram is a powerful technique.

Jitter Distribution

CrossingI D

Time

OFF

ON

Absence of Jitter

Jitter Distribution

I D

Time

Presence of Jitter

Threshold Signal Level

Measurement Setup

RF probe (Gate)

S

G

G50Ω

DSO100 GHzR3R2

R1

Pick-off tee

50Ω

Out

50Ω

Clock

50Ω

𝑽𝑽𝒊𝒊𝒊𝒊

Pattern Generator20 GB/s

Input

Permits high-speed eye diagram and conventional

“DC” measurements.

Gate Bit Patterns

15 bits7.5 ns

15 bits7.5 ns

Slow RO30,000 bits

Fast ROV G

[V] 0 V

Time

1 bit (500 ps)-1.3 V

32,000 bits

PRBS1532,767 bits

1 bit (500 ps)

Volt

age

Time

(a)

25 mV 84 ps

Volt

age

Time

25 mV84 ps

(b)

Volt

age

Time

25 mV 84 ps

(c)

Overshoot → parasitic pad capacitance (480 fF).Limits bit rate to 2 Gbit/s.

Experimental sequence, all at 100 °C

• Measure– Eye diagram at operation voltage.– DC parametric (Vth, Idlin, etc.).

• Stress (various times) at acceleration voltage+2V for PBTI and -2V for NBTI

• Recovery– All contacts floating for several hundred seconds.

• Measure and repeat

10 μm x 0.18 μm GSG MOSFETs (1 nm SiO2/2 nm HfO2)9 to 18 nominally identical devices for each condition

Details

NBTI Degradation-8

-6

-4

-2

0

-450-400-350-300-250-200-150-100

-500

-1.5-1.0-0.5

Id,sat [mA]I d,

lin[µ

A]

Gate Voltage [V]

0 s

5000 s

5000 s

0 s

100 101 102 103 1040

5

10

15

20

25

Devi

ce D

egra

datio

n [%

]

Stress Time [s]

Id,satId,linVth

-4

-3

-2

-1

0

1

0 1 2 3

I D[m

A]

Time [ns]

NBTI

NBTI continue …

Large timing shifts ∝ to Vth.---- Expected and captured in RO studies

0

2500

5000

7500

10000

-40 -20 0 20 40

Coun

t

Time [ps]

Pre-stressPost-stress

Fast-RO

Falling Edge

Rising Edge

0

250

500

750

1000

-60 -30 0 30 60Time [ps]

Pre-stressPost-stress

Slow-RO

Falling Edge

Rising Edge

0

100

200

300

-60 -30 0 30 60Time [ps]

Pre-stressPost-stress

PRBS15

Falling Rising PRBS15 – peak width increase.Random timing jitter.Not observable in RO studies.

As a function of stress time …

Large jitter increase for PRBS15.– Consistent with stress induced Vth

increase (defect generation).

100 101 102 103 1040

5

10

15

Δjitt

er [p

s]

Stress Time [s]

Rising EdgeFalling Edge

PRBS15

100 101 102 103 104-0.2

0

0.2

0.4

0.6

Δjitt

er [p

s]

Stress Time [s]

Rising EdgeFalling Edge

Fast-RO

100 101 102 103 104-0.2

0

0.2

0.4

0.6

Δjitt

er [p

s]Stress Time [s]

Rising EdgeFalling Edge

Slow-RO

Jitter increase negligible for RO

Recall: measure is after long (600s) relaxation.

Note that this is from one transistor!!!12/15

For PBTI …

0%

2%

4%

6%

8%

10%

10 100 1,000 10,000

Vth

cha

nge

Stress Time (s)

PBTINBTI

DC StressDC Measure

-0.20

-0.10

0.00

0.10

0.20

0.30

0.40

0.50

10 100 1,000 10,000Δ

Jitt

er (

pS)

Stress Time (s)

PBTINBTI

DC StressRO Measure

0

0

0.5

1

1.5

2

0.00

2.00

4.00

6.00

8.00

10.00

12.00

14.00

10 100 1,000

ΔJitt

er -

PBTI

(ps)

ΔJitt

er -

NBT

I (pS

)

Stress Time (s)

NBTI

PBTIDC Stress

PRBS Measure

PBTI degradation is ~40% of NBTI for similar stress level.

Jitter increase is ~10% of NBTI for similar stress level.

Similar to NBTI case, no meaningful jitter increase in RO.

Volt

age

Time

25 mV 84 ps

(c)

The small jitter increase may or may not be due to random trap filling and emptying…

A part of the jitter increase is simply the result of lower ON current

0%

1%

2%

3%

4%

5%

6%

100 1,000 10,000

Vth

Deg

rada

tion

Stress Time (s)

PRBS-PBTI StressDC-PBTI stressRO-PBTI stress

DC Measure

Random bit pattern can also be used for stress to mimic real circuit …

For PBTI, random bit pattern stress is similar to AC stress – 50% average duty cycle.

No frequency effect …

-0.20

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

100 1,000 10,000

Jitt

er in

crea

se (

pS)

Stress Time (s)

With RO waveform

With PRBS waveformRO-PBTI stressJitter measure

-0.50

0.00

0.50

1.00

1.50

2.00

100 1,000 10,000

Jitte

r in

crea

se (p

S)

Stress Time (s)

With RO waveform

With PRBS waveformPRBS-PBTI stressJitter measure

Jitter increase is also similar

0%

1%

2%

3%

4%

5%

6%

100 1,000 10,000

Vth

Deg

rada

tion

Stress Time (s)

PRBS-PBTI StressDC-PBTI stressRO-PBTI stress

DC Measure

0

0.2

0.4

0.6

0.8

1

1.2

DC-PBTI RO-PBTI PRBS-PBTI

ΔJi

tter

for

dif

fere

nt

Bia

s co

ndit

ion

(ps)

With RO waveformWith PRBS waveform

Surprise: under same stress, DC stress produces more degradation, but the jitter increase is similar for all three stress types.

From jitter perspective, AC stress does not have more margin than DC stress.

SummaryTransients due to charge flowing in and out of traps can produce large random VTHfluctuation under random logic operation, leading to significant timing jitter (random skew).

Eye diagram is a very suitable method to investigate this problem.

The timing jitter increase is very large (in case you forget, the data are from a single transistor) when consider large logic depth.

For PBTI, the jitter increase is much smaller than NBTI.

For PBTI, random bit pattern stress is similar to AC stress, suggesting pure duty factor effect and no frequency dependent.

For PBTI and from jitter perspective, DC and AC stress produce similar degradation.