© Semiconductor Components Industries, LLC, 2020

March, 2020 − Rev. 01 Publication Order Number:

NCP10970/D

High-Voltage Switcher withLinearly Regulated Output

NCP10970The NCP10970 includes a high−voltage switcher, linear regulator

and a dedicated comparator circuitry. The switcher is suitable forbuilding output voltage up to 16 V (adjustable by resistor divider onFB pin) protected against short−circuit. Dedicated internal circuitryprevents continuous conduction mode (CCM) operation improves thesurge robustness, efficiency and EMI. In no−load/light−loadconditions, the part enters skip cycle operation and ensures lowstandby power consumption.

A proprietary technique ensures high efficiency in thedown−conversion process from output switcher voltage rail to raw subvoltage rail supplying a linear regulator.

A dedicated comparator circuitry provides a means to instruct thecontrol section that an over−temperature point has been reached. Thecomparator input is biased by a precise constant current source andoutput is an open−drain type.

To ensure the very low no−load standby power, the device isequipped with a very effective standby mode with a low wake−up timefor return to the normal operation mode.

Features• Built−in 670 V, 18 � RDS(on) Lateral MOSFET

• High−voltage Start−up Current Source

• Fixed−frequency DCM Current−mode Control Scheme

• End of Demagnetization Detection Ensures DCM Operation only

• Short−circuit Protected Switcher Output with Auto−recoveryFunction

• 4 ms Soft Start

• Internal Linear Regulator with Short−circuit Protected Output

• Internal Comparator with Open Drain Output

• Internal Thermal Shutdown

• 16−pin SO Package with Creepage Distance

• These are Pb−Free Devices

Typical Applications• Power Management for Smart Lighting Application

• Power Management for White Goods, IoT Application, etc.

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SOIC−16 NB, LESS PIN 15CASE 752AC

MARKING DIAGRAM

See detailed ordering and shipping information on page 22 ofthis data sheet.

ORDERING INFORMATION

1

16

1097xyyG

1097xyy = Specific Device Code(x = 0, yy = A1, B1)

A = Assembly LocationWL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package

AWLYWWON

PIN CONNECTIONS

1

2

3

16

DMG

VCC

SOURCE DRAIN

4

5

NC

FB

6

7

VCCLV

INT

8

VRAW

14

13

12

11

10

9

COMP

GND

CMPIN

STBY

LDOOUT

CMPOUT

NCP10970

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Figure 1. Application Schematic

PIN FUNCTION DESCRIPTION

Pin No. Pin Name Function Description

1 SOURCE The switcher ground This pin is connected to the buck source/inductor junction and grounds theswitcher circuitry. The dissipated heat of the transistor is conducted outthrough this pin.

2 VCC Supplies the switcher section The switcher VCC voltage up to 20 V.

3 DMG Demagnetization detection This pin monitors the inductor magnetic activity.

4 FB Feedback pin This pin senses the output voltage through a resistive divider.

5 COMP Loop compensation The error amplifier output is available on this pin. The network connectedbetween this pin and ground adjusts the control loop bandwidth.

6 NC Not connected pin Not connected pin for better isolation between high voltage and low voltagepins.

7 INT The intermediate buck point This is the input to generate the raw dc voltage.

8 VCCLV Supplies the low−voltage section The VCCLV voltage biases the MOSFET driver, Comparator and LDO circuitry.

9 CMPOUT Comparator output Open−drain output pin of internal comparator. This pin is pulled low whenthe CMPIN passes above 1 V.

10 STBY Standby pin This pin affects the speed of comparator and IC consumption. Standbymode (grounded pin) – slow comparator. Active mode (> 3 V on pin) – fastcomparator.

11 LDOOUT LDO output A short−circuit protected 3.3 V or 5 V rail.

12 VRAW The intermediate bus rail This is the raw voltage driving the LDO.

13 CMPIN Comparator input Input of the internal comparator, internally biased by a 120 �A currentsource.

14 GND The ground of low−voltage section –

15 – – Creepage distance.

16 DRAIN Drain connection The connection to the lateral MOSFET drain.

NCP10970

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Figure 2. Simplified Block Diagram

CMPIN

PWM

UVLO

VDMG (th)

+

_

VREF

dmg

errorvoltage

+_

Vstop

Iref 1

OTD flagLow when fault

raw dc voltageLDO input

_+

_+

VSW(VCCLV ),L

VSW(INT),L

VCCLV

+

HVvoltage

+

Switcheroutput

SWINT

SWVCCLV

SWCMP

VCCLV

+

_

RegLinIN OUT

GROUND

Rint

DMG

VCC

SOURCE DRAIN

INT

FB

NC

VCCLV

COMP

VRAW

CMPOUT

GND

LDOOUT

STBYStandbycircuit

Comparator

Regulateddc voltageLDO output

VCCLV

VCCLV

NCP10970

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MAXIMUM RATINGS

Symbol Rating Value Unit

SWITCHER PINS – VOLTAGE ON PINS RELATED TO SOURCE PIN

BVDSS Drain voltage −0.3 to 670 V

VCC Power Supply voltage pin, continuous voltage −0.3 to 20 V

VFB, VCOMP, VDMG Voltage on FB, COMP and DMG pins −0.3 to 10 V

IDMG,clamp Maximum current of clamped DMG pin (voltage on pin is clamped to −0.7 V / 10 V) −2 / 3 mA

LOW VOLTAGE PINS – VOLTAGE ON PINS RELATED TO GND PIN

VCCLV, VINT Power Supply voltage pins, continuous voltage −0.3 to 20 V

VCMPIN, VLDOOUT,VSTBY

Voltage on CMPIN, STBY and LDOOUT pins, continuous voltage −0.3 to 5.5 V

VCMPOUT, VRAW Voltage on CMPOUT, VRAW pins, continuous voltage −0.3 to VCC + 0.3 V

COMMON PARAMETERS

TJ,max Maximum Junction Temperature 150 °C

Tstorage Storage Temperature Range −60 to +150 °C

ESDHBM ESD Capability, Human Body Model 2 kV

ESDCDM ESD Capability, Charged−Device Model 1 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. This device series incorporates ESD protection and is tested by the following methods:

• ESD Human Body Model tested per JEDEC Standard JESD22−A114F• ESD Charged−Device Model tested per JEDEC Standard JESD22−C101F• Latch−up protection and exceeds 100 mA per JEDEC standard JESD78

THERMAL CHARACTERISTICS

Symbol Rating Value Unit

RθJ−ASW Thermal Resistance Junction−to−Air – switcher section only 150 °C/W

RθJ−ALV Thermal Resistance Junction−to−Air – low−voltage section only 150 °C/W

ELECTRICAL CHARACTERISTICS − HIGH−VOLTAGE SWITCHER (VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C)

Symbol Parameter Test Conditions Min Typ Max Unit

SUPPLY SECTION AND VCC MANAGEMENT

VCC(on) VCC increasing level at which the switcherstarts operation

8.4 9.0 9.5 V

VCC(min) VCC decreasing level at which the HV current source restarts

7.0 7.4 7.8 V

VCC(off) VCC decreasing level at which the switcherstops operation (UVLO)

6.7 7.0 7.2 V

ICC1 Internal IC consumption fSW = 65 kHz − 1 − mA

ICCskip Internal IC consumption VCOMP = 0 V (No switching MOSFET) − 340 − �A

POWER SWITCH CIRCUIT

RDS(on) Power Switch Circuit on−state resistance ID = 50 mA, TJ = 25°CID = 50 mA, TJ = 125°C

−−

1833

2338

�

BVDSS Power Switch Circuit & Startup breakdownvoltage

ID(off) = 120 �A, TJ = 25°CFigure 9 shows the temp. dependency

670 − − V

IDSS(off) Power Switch & Startup off−state leakagecurrent

TJ = 125 °C, VDS = 670 VTJ = 125 °C, VDS = 400 V

−−

52

−−

�A

tr Turn−on time (90% − 10%) RL = 50 �, VDS set for Idrain = 0.7 x IPK − 35 − ns

NCP10970

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ELECTRICAL CHARACTERISTICS − HIGH−VOLTAGE SWITCHER (continued)(VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C)

Symbol UnitMaxTypMinTest ConditionsParameter

POWER SWITCH CIRCUIT

tf Turn−off time (10% − 90%) − 10 − ns

ton(min) Minimum on time − 300 − ns

INTERNAL START−UP CURRENT SOURCE

Istart1 High−voltage current source VCC = VCC(on) – 200 mV 4 8 12 mA

Istart2 High−voltage current source VCC = 0 V − 0.4 − mA

VCC(th) VCC transient level for Istart1 to Istart2 toggling point

− 1.3 − V

VHV(min) Minimum startup voltage VCC = VCC(on) – 200 mV − − 22 V

CURRENT COMPARATOR

IPK Maximum internal current setpoint (Note 2) TJ = 25°C 325 350 375 mA

IPK(SW) Final switch current with a primary slope of320 mA/�s

fsw = 65 kHz − 370 − mA

tSS Soft−start duration − 4 − ms

tprop Propagation delay from current detection todrain OFF state

− 70 − ns

tLEB Leading Edge Blanking Duration − 130 − ns

INTERNAL OSCILLATOR

fOSC Oscillation frequency (Note 3) TJ = 25°C 59 65 71 kHz

Dmax Maximum duty ratio 62 66 72 %

DEMAGNETIZATION DETECTION BLOCK

VDMG(th) Input threshold Voltage is decreasing 15 50 85 mV

VDMG(th,H) Hysteresis Voltage is increasing − 25 − mV

tdem Demag propagation delay − 70 − ns

tblank Blanking time after turn off the switchertransistor

Step from negative voltage value (equal to−1 mA) to positive voltage 1 V

0.5 1.0 − �s

Rint DMG pin internal resistance − 40 − k�

Cint DMG pin internal capacitance Guaranteed by design − 10 − pF

ERROR AMPLIFIER SECTION

VREF Error amplifier reference voltage 3.2 3.3 3.4 V

IFB Input Bias Current VFB = 3.3 V − 1 − �A

GM Transconductance − 2 − mS

IOTAlim OTA maximum current capability VFB > VOTAen − ±150 − �A

VOTAen FB voltage to disable OTA 0.7 1.3 1.7 V

COMPENSATION SECTION

ICOMPfault COMP current for which fault is detected − −40 − �A

ICOMP100% COMP current for which internal currentset−point is 100% (IPK)

− −44 − �A

ICOMPfreeze COMP current for which internal currentsetpoint is IFreeze

− −80 − �A

ICOMPskip The COMP pin current level to enter skipmode

− −120 − �A

VCOMP(REF) Equivalent pull−up voltage in linear regulation range

Guaranteed by design − 2.7 − V

NCP10970

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ELECTRICAL CHARACTERISTICS − HIGH−VOLTAGE SWITCHER (continued)(VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C)

Symbol UnitMaxTypMinTest ConditionsParameter

COMPENSATION SECTION

RCOMP(up) Equivalent feedback resistor in linear regulation range

Guaranteed by design − 17.7 − k�

IFreeze Internal minimum current setpoint ICOMP < ICOMPFreeze − 110 − mA

PROTECTIONS

tSCP Fault validation before error flag is asserted ICOMP > ICOMPfault 35 48 − ms

trecovery OFF phase in fault mode − 400 − ms

VOVP VCC voltage at which the switcher stopspulsing

17.0 18.0 18.8 V

tOVP Filter of VCC OVP comparator − 80 − �s

TEMPERATURE MANAGEMENT

TSD Temperature shutdown Guaranteed by design 150 160 − °C

TSDHYST Hysteresis in shutdown Guaranteed by design − 20 − °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.2. There is no compensation ramp in this switcher as CCM operation is prevented by the demagnetization detector.3. Oscillator frequency is measured with grounded DMG pin. The frequency fOSC doesn’t have to be observed in application due to active

Demagnetization Detection Block.

ELECTRICAL CHARACTERISTICS − LOW VOLTAGE SECTION (VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C)

Symbol Parameter Test Conditions Min Typ Max Unit

SUPPLY SECTION

VCCLV(on) VCCLV increasing level for activation theinternal switches SWINT and SWVCCLV

− 8.4 − V

VCCLV(Hyst) VCCLV hysteresis for deactivation − 4.7 − V

ICCLV1 Internal IC consumption in standby(grounded pin STBY)

Low voltage section is biased, no switchingof internal MOSFETs SWINT and SWVCCLV,no Iref1

− 270 360 �A

ICCLV4 Internal IC consumption in active mode (pinSTBY in High state)

Low voltage section is biased, no switchingof internal MOSFETs SWINT and SWVCCLV,no Iref1

− 350 − �A

RAW VOLTAGE GENERTION

RDS(on),INT RDS(on) of internal MOSFET SWINT IDS = 200 mA, TJ = 25°CIDS = 200 mA, TJ = 125°C

−−

5−

710

�

RDS(on),VCCLV RDS(on) of internal MOSFET SWVCCLV IDS = 50 mA, TJ = 25°CIDS = 50 mA, TJ = 125°C

−−

15−

2030

�

VSW(VCCLV),L Voltage for turn−on the switch SWVCCLV· A version (3.3 V)· B version (5 V)

voltage is decreasing, TJ = 25°C3.565.25

3.605.30

3.645.35

V

VSW(VCCLV),H Voltage for turn−off the switch SWVCCLV· A version (3.3 V)· B version (5 V)

voltage is increasing−−

3.655.35

−−

V

VSW(INT),L Voltage for turn−on the switch SWINT· A version (3.3 V)· B version (5 V)

voltage is decreasing−−

3.805.50

−−

V

VSW(INT),H Voltage for turn−off the switch SWINT· A version (3.3 V)· B version (5 V)

voltage is increasing−−

3.855.55

−−

V

tdel(SW) Propagation delay of switches INT and VCCLV

voltage is decreasing/increasing − 1.5 − �s

NCP10970

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ELECTRICAL CHARACTERISTICS − LOW VOLTAGE SECTION (continued)(VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C)

Symbol UnitMaxTypMinTest ConditionsParameter

LOW DROPOUT REGULATOR (Input capacitances CRAW = 22 �F, Output capacitances COUT = 10 �F)

ILDOOUT(max) Output current capability (Note 4) − 100 − mA

ICL Maximum limitation of output current Figure 27 shows the temp. dependency 130 260 420 mA

VLDOOUT Output voltage accuracy· A version (3.3 V)· B version (5 V)

IOUT = 1.0 mA, TJ = 25°C (Note 5)3.2674.95

3.3005.00

3.3335.05

V

VDO Dropout voltage· A version (3.3 V)· B version (5 V)

IOUT = 100 mA − 150 250 mV

RegLINE Line regulation A version: 3.6 V < VIN < 4 V, IOUT = 1 mAB version: 5.4 V < VIN < 6 V, IOUT = 1 mA

− − 10 mV

RegLOAD Load regulation IOUT = 1.0 to 60 mAIOUT = 1.0 to 100 mA

−−

59

1520

mV

TranLOAD Load transient response IOUT = 3.0 to 30 mA, trise = tfall = 1 �sIOUT = 50 to 100 mA, trise = tfall = 1 �s

−−

3540

−−

mV

PSRR Power Supply Rejection Ratio VIN = 3.7 V for A versionVIN = 5.5 V for B versionVIN(pk−pk) = 0.1 V, f = 1 kHz, IOUT = 60 mA(Guaranteed by design)Figure 31 shows the freq. dependency

60 − − dB

VNOISE Output noise IOUT = 60 mA, f = 100 Hz to 100 kHzFigure 32 shows the freq. dependency

− 300 − �Vrms

COMPARATOR

VCMP(on) VCCLV increasing level for activation thecomparator

− 4.4 − V

VCMP(Hyst) VCCLV hysteresis for deactivation − 0.6 − V

Vstop Voltage above which the COMPOUT pin ispulled down

0.95 1 1.06 V

Vrestart Voltage below which the COMPOUT pin isin high impedance state

0.75 0.8 0.85 V

Iref1 Current source biasing the CMPIN pin 114 120 126 �A

Rdrain Internal MOSFET RDS(on) − 10 20 �

ICMPOUT Current capability of internal MOSFET –current flowing into COMPOUT pin

Guaranteed by design 10 − − mA

tdel1 Debouncing time constant on the comparator output from High to Low

− 0 − �s

tdel2 Debouncing time constant on the comparator output from Low to High

− 0 − �s

tdel Comparator propagation delay − active mode− standby mode

Step 0.5 V to 1.2 V−−

60220

105−

ns

TEMPERATURE SHUTDOWN

TSD(LV) Temperature shutdown Guaranteed by design 150 160 − °C

TSD(LV)HYST Hysteresis in shutdown Guaranteed by design − 20 − °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.4. The accuracy of output voltage is guaranteed up to output current value specified by ILDOOUT(max). For higher output current value, the

accuracy can be improved by using a higher capacitances CRAW/COUT.5. The output voltage VLDOOUT of LDO is guaranteed for 25°C only. The temperature dependency graph shows the temperature dependency

for −40°C to 125°C.

NCP10970

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TYPICAL CHARACTERISTICS − HIGH VOLTAGE SWITCHER

8.80

8.85

8.90

8.95

9.00

9.05

9.10

−40 −20 0 20 40 60 80 100 120

VC

C(o

n) [V

]

Temperature [°C]

7.30

7.32

7.34

7.36

7.38

7.40

7.42

7.44

7.46

7.48

−40 −20 0 20 40 60 80 100 120

6.84

6.86

6.88

6.90

6.92

6.94

6.96

6.98

−40 −20 0 20 40 60 80 100 1200.93

0.94

0.95

0.96

0.97

0.98

0.99

1.00

−40 −20 0 20 40 60 80 100 120

260

280

300

320

340

360

380

400

−40 −20 0 20 40 60 80 100 1205

10

15

20

25

30

35

40

−40 −20 0 20 40 60 80 100 120

Temperature [°C]

Temperature [°C] Temperature [°C]

Temperature [°C] Temperature [°C]

VC

C(m

in) [

V]

VC

C(o

ff) [V

]

I CC

1 [m

A]

I CC

skip

[�A

]

RD

S(o

n) [�

]

Figure 3. VCC(on) vs. Temperature Figure 4. VCC(min) vs. Temperature

Figure 5. VCC(off) vs. Temperature Figure 6. ICC1 vs. Temperature

Figure 7. ICCskip vs. Temperature Figure 8. RDS(on) vs. Temperature

NCP10970

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TYPICAL CHARACTERISTICS − HIGH VOLTAGE SWITCHER

700

720

740

760

780

800

820

−40 −20 0 20 40 60 80 100 1200

1

2

3

4

5

−40 −20 0 20 40 60 80 100 120

Vds = 400 V

Vds = 670 V

330

335

340

345

350

355

−40 −20 0 20 40 60 80 100 12099

100

101

102

103

104

105

106

107

−40 −20 0 20 40 60 80 100 120

4

5

6

7

8

9

10

11

12

−40 −20 0 20 40 60 80 100 12016.0

17.0

18.0

19.0

20.0

21.0

−40 −20 0 20 40 60 80 100 120

BV

DS

S [V

]

Temperature [°C] Temperature [°C]

Temperature [°C] Temperature [°C]

Temperature [°C] Temperature [°C]

I DS

S(o

ff) [�

A]

I PK [m

A]

I Fre

eze

[mA

]

I sta

rt1

[mA

]

VH

V(m

in) [

V]

Figure 9. Breakdown voltage vs. Temperature Figure 10. IDSS(off) vs. Temperature

Figure 11. IPK vs. Temperature Figure 12. IFreeze vs. Temperature

Figure 13. Istart1 vs. Temperature Figure 14. VHV(min) vs. Temperature

NCP10970

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TYPICAL CHARACTERISTICS − LOW VOLTAGE SECTION

220

240

260

280

300

320

340

−40 −20 0 20 40 60 80 100 1208.42

8.43

8.44

8.45

8.46

−40 −20 0 20 40 60 80 100 120

2

3

4

5

6

7

8

9

−40 −20 0 20 40 60 80 100 1208

10

12

14

16

18

20

22

−40 −20 0 20 40 60 80 100 120

Temperature [°C] Temperature [°C]

Temperature [°C] Temperature [°C]

I CC

LV1

[�A

]

VC

CLV

1 [V

]

RD

S(o

n),IN

T [�

]

RD

S(o

n),V

CC

LV [�

]

Figure 15. ICCLV1 vs. Temperature Figure 16. VCCLV(on) vs. Temperature

Figure 17. RDS(on),INT vs. Temperature Figure 18. RDS(on),VCCLV vs. Temperature

NCP10970

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TYPICAL CHARACTERISTICS − RAW VOLTAGE GENERATION FOR A1 VERSION (3.3 V OUTPUT)

3.59

3.60

3.61

3.62

−40 −20 0 20 40 60 80 100 1203.64

3.65

3.66

3.67

−40 −20 0 20 40 60 80 100 120

3.79

3.80

3.81

3.82

−40 −20 0 20 40 60 80 100 1203.84

3.85

3.86

3.87

−40 −20 0 20 40 60 80 100 120

VS

W(V

CC

LV),

L [V

]

Temperature [°C] Temperature [°C]

Temperature [°C] Temperature [°C]

VS

W(V

CC

LV),

H [V

]

VS

W(I

NT

),L

[V]

VS

W(I

NT

),H

[V]

Figure 19. VSW(VCCLV),L vs. Temperature Figure 20. VSW(VCCLV),H vs. Temperature

Figure 21. VSW(INT),L vs. Temperature Figure 22. VSW(INT),H vs. Temperature

NCP10970

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TYPICAL CHARACTERISTICS − RAW VOLTAGE GENERATION FOR B1 VERSION (5 V OUTPUT)

5.30

5.31

5.32

5.33

−40 −20 0 20 40 60 80 100 1205.35

5.36

5.37

5.38

5.39

5.40

−40 −20 0 20 40 60 80 100 120

5.49

5.50

5.51

5.52

5.53

−40 −20 0 20 40 60 80 100 1205.55

5.56

5.57

5.58

5.59

−40 −20 0 20 40 60 80 100 120

VS

W(V

CC

LV),

L [V

]

Temperature [°C] Temperature [°C]

Temperature [°C] Temperature [°C]

VS

W(V

CC

LV),

H [V

]

VS

W(I

NT

),L

[V]

VS

W(I

NT

),H

[V]

Figure 23. VSW(VCCLV),L vs. Temperature Figure 24. VSW(VCCLV),H vs. Temperature

Figure 25. VSW(INT),L vs. Temperature Figure 26. VSW(INT),H vs. Temperature

NCP10970

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TYPICAL CHARACTERISTICS − LOW DROPOUT REGULATOR

230

240

250

260

270

280

290

300

310

−40 −20 0 20 40 60 80 100 1203.29

3.30

3.31

3.32

−40 −20 0 20 40 60 80 100 120

4.98

4.99

5.00

5.01

5.02

−40 −20 0 20 40 60 80 100 1201.3

1.4

1.5

1.6

1.7

1.8

−40 −20 0 20 40 60 80 100 120

0

10

20

30

40

50

60

70

80

1E−2 1E−1 1E+0 1E+1 1E+2 1E+3 1E+4

PS

RR

[dB

]

Frequency [kHz]

Cout = 1 �FCout = 2.2 �FCout = 4.7 �FCout = 10 �F

0

1

2

3

4

5

6

1.E−02 1.E−01 1.E+00 1.E+01 1.E+02 1.E+03

Noi

se S

pect

ral D

ensi

ty [�

Vrm

s/√H

z] Cout = 1 �FCout = 2.2 �FCout = 4.7 �F

Frequency [kHz]

I CL

[mA

]

Temperature [°C] Temperature [°C]

Temperature [°C] Temperature [°C]

VLD

DO

OU

T [V

]

VLD

OO

UT [V

]

VD

O [V

]

Figure 27. ICL vs. Temperature Figure 28. VLDOOUT vs. Temperature (A Version)

Figure 29. VLDOOUT vs. Temperature (B Version) Figure 30. VDO vs. Temperature

Figure 31. PSRR vs. Frequency Figure 32. Noise vs. Frequency

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TYPICAL CHARACTERISTICS − COMPARATOR

4.30

4.35

4.40

4.45

4.50

4.55

4.60

4.65

4.70

−40 −20 0 20 40 60 80 100 1200.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

−40 −20 0 20 40 60 80 100 120

0.99

1.00

1.01

1.02

1.03

−40 −20 0 20 40 60 80 100 1200.79

0.80

0.81

0.82

0.83

−40 −20 0 20 40 60 80 100 120

119.0

119.2

119.4

119.6

119.8

120.0

120.2

120.4

120.6

−40 −20 0 20 40 60 80 100 12045

50

55

60

65

70

75

−40 −20 0 20 40 60 80 100 120

VC

MP

(on)

[V]

Temperature [°C] Temperature [°C]

Temperature [°C] Temperature [°C]

Temperature [°C] Temperature [°C]

VC

MP

(Hys

t) [V

]

Vst

op [V

]

Vre

star

t [V

]

I ref1

[�A

]

t del

[ns]

Figure 33. VCMP(on) vs. Temperature Figure 34. VCMP(Hyst) vs. Temperature

Figure 35. Vstop vs. Temperature Figure 36. Vrestart vs. Temperature

Figure 37. Iref1 vs. Temperature Figure 38. tdel vs. Temperature

NCP10970

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APPLICATIONS INFORMATION

This NCP10970 integrated circuit associatesa high−voltage switcher configured to drive a buck topologywith a low−voltage die hosting a linear regulator anddedicated comparator circuitry. The buck circuit deliversoutput voltage up to 16 V (adjustable by resistor divider onFB pin) from universal mains input and using a proprietarydownstream converter technique creates 3.3 V or 5 V in aneffective way.

Current−mode operation with detection end ofdemagnetization: the high−voltage switcher usesfixed−frequency current−mode control architecture.A dedicated pin DMG permanently monitors the magneticactivity in the inductor and prevents from entering thecontinuous conduction mode (CCM). The DMG pin has tobe connected through proper resistor value to the end of theinductor.

670 V MOSFET: the switcher contains a high−voltagelow−power MOSFET with a 18 � RDS(on) @ TJ = 25°C. Thedissipated heat of the power transistor is conducted outthrough the SOURCE pin.

Dynamic Self−Supply contains an internal high−voltagestart−up current source. This device can be used inapplications in which no auxiliary winding providesa supply voltage or in application with low output voltage,for example 5 V. For power dissipation concerns but also forbest stand−by power performance, we recommend todisable DSS operation by providing a self−supply to theswitcher.

Short circuit protection is permanently monitoring theCOMP pin activity. The controller is able to detect theshort−circuit condition and immediately reduce the outputpower for a total system protection. A fault timer is startedas soon as the COMP current is below a threshold,ICOMPfault, which indicates the maximum peak current. Ifthe fault is still present at the end of this timer, then the deviceenters a safe, auto−recovery burst mode, affected by a fixedtimer recurrence, trecovery. Once the short has disappeared,the controller resumes operations.

Built−in VCC Over Voltage Protection is monitoring thevoltage on the VCC pin. When the voltage exceeds a levelof VOVP (18 V typically), the controller immediately stopsswitching and waits for a time period given by a trecoverybefore attempting to restart. If the fault is gone, the controllerresumes operation. If the fault is still there, the controller isagain in protection mode and waits another time periodtrecovery before attempting to restart.

Soft−Start: a 4 ms soft−start ramp ensures a smoothstartup sequence and reduces output overshoots.

Current control ensures a good efficiency for changingoutput power demands. The controller observes the COMP

pin and control the current peak value. The switchingfrequency is setup to its maximum and keep based on theload condition by DMG control.

Skip operation ensures a good efficiency when the outputpower demand diminishes. By skipping un−neededswitching cycles, the NCP10970 drastically reduces thepower wasted during light load conditions.

Integrated linear regulator provides a 3.3 V or 5 V (basedon chosen version) of output voltage on short−circuitprotected output. Supplied by a raw dc voltage derived fromthe high−voltage buck in a proprietary way, it maintainsa good efficiency while offering low quiescent current.

Comparator circuitry can be used for over−temperaturedetection. The input pin of comparator – CMPIN pin – ispermanently biased by a precise constant current source. Byconnecting a pull−down PTC thermistor to this pin, thecircuit can deliver a low signal in case a temperaturerunaway is sensed. The low signal is present on output pinof comparator – CMPOUT pin – that is an open drain type.

Standby circuit affects the speed of the Comparator tdeland also the current consumption of the Low Voltage part –ICCLV1 vs ICCLV4. If the STBY pin is suddenly grounded (orafter startup of the IC), the IC goes to the standby mode after20 ms. When the IC is in standby mode and STBY pin goesto High State (>3 V on pin, pin max rating is 5.5 V), the ICgoes to active mode after 4 �s max – it is called as wake−uptime from standby mode to active mode.

Start−up Sequence of SwitcherDuring start−up sequence of NCP10970, the supply

voltage for switcher (VCC pin) is created by an internalhigh−voltage start−up current source. This startup−upcurrent source can be used as a DSS (Dynamic self−supply)in case that supply voltage is not present or doesn’t reach thenecessary voltage value.

The internal HV start−up current source is active when thevoltage on DRAIN pin is above VHV(min) level. This start−upcurrent source can charges up the CVCC capacitor connectedto VCC pin by typical current value Istart1. In case ofdamaged or missing CVCC capacitor, the device is protectedagainst self−destruction by limiting the start−up current toIstart2 value till the voltage on VCC pin is higher than VCC(th)value. If the VCC voltage touches the VCC(on) level, thecurrent source is turned off and the internal DRV pulses ofswitcher transistor are authorized. If the VCC voltagedecreases below the VCC(min) level, the current source isturned on again till the VCC voltage increase to VCC(on)level, than the current source is turned off again. Figure 39shows the internal start−up logic for control thehigh−voltage start−up current source.

NCP10970

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Figure 39. Internal Control Logic of HV Start−up Current Source

VCC

SOURCE DRAIN

+

HVvoltage

+

CBulk

CVCC

+

_

+

_

VCC(min)

Q

Q

S

RIstart 2

+

_

VDRV

Toggle Istart 1 / Istart 2

Istart 1

VCC(on)

VCCth

Soft−startThe NCP10970 features 4 ms soft−start ramp which

reduces the power−on stress but also contributes to lowerovershoot of output voltage. Figure 40 shows a typical

operating waveform. Soft−start ramp is applied during firststart of application and upon every restart, i.e.auto−recovery restart of application after fault state.

Figure 40. The 4 ms Soft−start Ramp during Start−up Sequence

t

t

vCC (t)

t4 ms soft−start ramp

IPK(max)

t

VCCth

vDRV (t)Internal

signal

iPK (t)

vOUT (t)Switcher

outputvoltage

VCC(on)

Demagnetization DetectionTo avoid the CCM operation during heavy load

conditions, the switcher in NCP10970 is equipped bydemagnetization detection block.

Demagnetization detection block affects the switchingfrequency of the switcher as it shown in Figure 41.Switching frequency is determined by a frequency oscillatorwhen on−time plus off−time are shorter than switchingperiod time. Otherwise, the switcher is forced to wait for theend of the inductor demagnetization although the end of the

switching period came as first. Therefore, thedemagnetization detection block doesn’t authorize newswitching cycle till the inductor demagnetization phase isnot finished.

The end of demagnetization is sensed by threshold voltagelevel VDMG(th) which is valid for decreasing voltage. Thenew DRV pulse is present after propagation delay tdem of thedemagnetization detection block. The unwanteddemagnetization detection is secured by a hysteresis ondemagnetization threshold level and blanking time.

NCP10970

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Figure 41. Switching Waveforms with Demagnetization Detection during Light and Heavy Load Operation

iPK (t)

tdemVDMG (th)

vDMG (t)

vDRV (t)t

t

TSW = 15.4 µs

tblank

Recommended connection of DMG pin shows Figure 42.External resistor R1 and internal resistor Rint create resistordivider. The divider ratio should be chosen with respect toVDMG(th) value, which is important for proper end of

demagnetization detection. Resistance of external resistorR1 has to be chosen based on maximum current valueIDMG,clamp flowing through the clamp diode.

Figure 42. Recommended Connection of DMG Pin

DMG

SOURCE

VDMG(th)

+

_

Cint RintClampdiode

R1

Current and Switching Frequency ControlThe improvement of the efficiency during light load and

reduction of no−load standby power requires change of theswitching frequency and current peak setpoint depending onthe state of the load. Therefore, this device implementsa current and switching frequency control when the COMPcurrent passes a certain levels.

The current peak control mechanism is clearly describedin Figure 43. The switching frequency control is based oninterrupting of the switching in Skip mode. Out of the Skipmode, the full switching frequency is setup, but withlimiting by the demagnetization detection block. It means,the switching frequency is determined by the application,not by a device itself.

Figure 43. By Observing the Current on the COMP Pin, the Controller Changes its Current Peak Setpoint andSwitching Frequency to Improved Performance at Light Load Conditions

ICOMPskip−120 �A

IFreeze

Skipmode

Frozen peak

Full peak350 mA

110 mA

ICOMP[�A]ICOMPfreeze

−80 �AICOMP100%−44 �A

IPk

Ipk [mA]

COMP PinFigure 44 depicts the relationship between COMP pin

voltage and current. The COMP pin operates linearly as theabsolute value of COMP current (ICOMP) is above 40 �A. In

this linear operating range, the dynamic resistance is17.7 k� typically (RCOMP(up)) and the effective pull−upvoltage is 2.7 V typically (VCOMP(REF)). When ICOMP isdecreases, the COMP voltage is increased to 3.2 V.

NCP10970

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Figure 44. COMP Pin Voltage vs. COMP Current

0,0

0,5

1,0

1,5

2,0

2,5

3,0

3,5

4,0

0 20 40 60 80 100 120 140 160

VC

OM

P [V

]

ICOMP [�A]

FB Pin FunctionThe portion of the output voltage is connected into the pin.

The pin voltage is compared with internal VREF (3.3 V)using Operation Transconductance Amplifier (Figure 45).The OTAs output is connected to COMP pin. Thecompensation resistor network is connected to the COMPpin. The current capability of OTA is limited to −150 �Atypically. The positive current is defined by internalRCOMP(up) resistor and VCOMP(ref) voltage. If FB path loopis broken (i.e. the FB pin is disconnected), an internal currentIFB (1 �A typ.) will pull up the FB pin and the IC stopsswitching to avoid uncontrolled output voltage increasing.

Figure 45. FB Pin Connection Schematic

FB

COMP

RCOMP (up)

VCOMP (REF)

OTA out = 0 Aif FB = 0 V

OTA

IFB

ICOMP

VREF

IOTAlim

Auto−recovery Over−Voltage ProtectionThe particular switcher of NCP10970 arrangement offers

a simple way to prevent output voltage runaway when thecompensation network fails. Therefore, a comparatormonitors the VCC pin. If there is an over−voltage conditionon the CVCC capacitor, the controller considers it as an OVPsituation. To avoid some unwanted OVP situation, there isimplemented filter with time constant tOVP. If fault is presentfor whole tOVP time, the fault is confirmed and the internalpulses are immediately stopped. The controller enters toauto−recovery protection mode, and normal operation willbe resumed after trecovery time constant. If the fault conditionstill exists, the device enters to the protection mode again.

Figure 46. Realization of OVP Protection on VCC Pin

VOVP Source

VCC

Shut downInternal DRV

80 �sfilter

CVCC

Figure 47. The Switcher Auto−recovers to Normal Operation after Over−voltage on VCC Pin

VCC

ICOMP

TIMER

DRVinternal

VCC(min)

VCC(on)

VOVP

Fault level

48 ms typ.

400 ms typ.

NCP10970

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Auto−recovery Short−Circuit ProtectionAs soon as VCC reaches VCC(on), drive pulses are

internally enabled. If everything is correct, the outputvoltage rises and starts to supply the VCC capacitor. Whenthe output voltage is not regulated, the current comingthrough COMP pin is below ICOMPfault level (40 �Atypically), which is not only during the startup period butalso anytime an overload situation occurs, an internal errorflag is asserted, Ipflag is indicating that the system has

reached its maximum current limit setpoint. The assertion ofthis Ipflag triggers a fault counter tSCP (48 ms typically). IfIpflag remains asserted when the tSCP counter elapses, alldriving pulses are stopped and in trecovery duration (about400 ms). A new attempt to re−start occurs and will last 48 msproviding the fault is still present. When the fault disappears,the power supply quickly resumes operation. Figure 48depicts this particular mode.

Figure 48. In Case of Short�circuit or Overload, the Switcher of NCP10970 Protects Itself and the Power Supplyvia a Low Frequency Burst Mode. The VCC is Maintained by the DSS Function of the Start−up Current Source

VCOMP

IpFlag

VCC

Timer

DRVinternal

400 ms typ.

Fault

Open loop FB

VCC

VCC

48 ms typ.

(min)(on)

Start−up Sequence of Low Voltage SectionThe switcher starts switching when the supply voltage

VCC reaches VCC(on) level and therefore the output voltageof the switcher is ramping−up. The supply pin VCCLV of thelow voltage section is connected to the switcher outputvoltage. When the VCCLV voltage reaches the VCCLV(on)level, the switch SWINT is active to ramp−up the VRAW

voltage to its nominal value given by a VSW(INT),H. Duringthis start−up sequence is active the switch SWINT only, i.e.the switch SWVCCLV is blocked until the VRAW voltagereaches the VSW(INT),H voltage level. The LDO outputvoltage is ramping−up after the VRAW reaches its nominalvalue to achieve smooth and linear rise ramp of this voltage.Figure 49 shows the operation during start−up sequence.

NCP10970

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Figure 49. Startup Waveforms of the Switcher and Low Voltage Section with LDO

VSW(VCCLV ),L

Switch SWVCCLV is blocked

VSW(INT),HVSW(INT),L

t

t

Switcher starts operate

t

VLDOOUT

SW(INT)Internal DRV

pulses

Switchis OFF

VCCLV(on)

VRAW – LDO input voltageVLDOOUT – LDO output voltage

t

VSW(VCCLV ),H

VCC – supply voltage for switcher dieVCCLV – output voltage of a switcher and supply

voltage for Low Voltage die

Switchis ON

vRAW (t)vLDOOUT (t)

vCCLV (t)vCC (t)

VCC(on)

VCCth

SW(VCCLV)Internal DRV

pulses

Steady−state and Transient Operation of Switcher andLDO

During steady−state operation, the switch SWINT isswitching to supply the LDO. If this energy delivering is notenough, there is a switch SWVCCLV, which can supply theLDO from the output capacitor connected to switcher outputrail. The switch SWVCCLV is turned−on especially during

transient states. Figure 50 shows the behavior of theswitches during steady state and transient state, when theLDO output rail is heavy loaded. Both switches areturned−on when the VRAW voltage touches the turn−onvoltage reference, i.e. VSW(INT),L and VSW(VCCLV),L, andturned−off when the VRAW voltage touches turn−off voltagereference VSW(VCCLV),H and VSW(INT),H.

Figure 50. Steady State Waveforms of the Switcher and Low Voltage Section with LDO

Steady−state operation

t

VSW(INT),H

VSW(INT),L

VSW(VCCLV),H

VSW(VCCLV),L

Heavy load on LDOoutput rail

Drop on switcher output rail forcethe switcher to deliver more energy

Switchis OFF

Switchis ON

SW(INT)Internal DRV

pulses

vSWOUT (t)Switcher

output rail

vRAW (t)

SW(VCCLV)Internal DRV

pulses

t

t

Power−down Operation of Switcher and LDOThis operation mode is showing the behavior of the

controller when the input HV voltage is unplugged. Whenthe input voltage is no longer present, the energy for LDO

cannot be ensured through INT switch, so the energy istransferred from capacitor on switcher output voltage railthrough VCCLV switch. Figure 51 shows the behavior of theswitches during power−down.

NCP10970

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Figure 51. Power−down Behavior of the Switcher and Low Voltage Section with LDO

HV inut voltageUnplugged

t

Switcher off due toVCC = UVLO

VSW(INT),H

VSW(INT),L

VSW(VCCLV),H

VSW(VCCLV),L

t

t

t

t

t

Switchis OFF

Switchis ON

SW(INT)Internal DRV

pulses

vSWOUT (t)Switcher

output rail

vHV (t)

SW(VCCLV)Internal DRV

pulses

vRAW (t)

vDRV (t)Switcher DRV

pulses

Linear RegulatorThe integrated LDO regulator is an NMOS type for better

output stability. The output voltage is fixed 3.3 V or 5 Vbased on chosen version (see ordering information table onpage 22) and output current is limited to 260 mA @TJ = 25°C as a short−circuit protection of LDO output.

The input voltage of LDO regulator is VRAW voltage andthe LDO is supplied from VCCLV voltage.

ComparatorThe input of this circuitry is CMPIN pin, which is biased

by a current source during all operational conditions.Comparator connected to the CMPIN pin turns−on and offthe internal MOSFET transistor connected to COMPOUTpin – this pin is open−drain. The Speed of the Comparatoris determined by the active or standby of the IC, i.e. theComparator is in standby mode when the STBY pin is

grounded. Standby mode affects the propagation delay tdelof the comparator.

Over−temperature detection is based on pull−down PTCthermistor connected to CMPIN pin. Internal current sourceforce the current value Iref1 = 120 �A through the PTC. If theover−temperature condition appears, the resistance of thePTC thermistor increases, i.e. the sensed voltage reaches thevalue Vstop = 1 V and the comparator turned−on the internalMOSFET, which force the CMPOUT pin to the Low state.The de−bouncing time constants tdel1 = 50 �s andtdel2 = 10 �s on comparator output can be implemented as anoption. The CMPOUT pin goes back to High Z state, whenthe sensed voltage on PTC decreases below the valueVrestart = 0.8 V. Figure 52 shows the comparator operationwith/without de−bouncing filter based on input voltage onCMPIN pin.

Figure 52. Over−temperature/Over−current Detection with/without De−bouncing Filter

VCMPOUT (t)t

t

t

With debouncing filter

Without debouncing filter

Vstop = 1 V

tdel1

VCMPIN (t)

Vrestart = 0.8 V

tdel1

tdel2 tdel2

NCP10970

www.onsemi.com22

The CMPOUT pin is forced low during startupindependently of voltage on CMPIN pin when the supplyvoltage is between 2.5 V and VCMP(on) = 4.4 V. When thesupply voltage VCCLV touches the VCMP(on) = 4.4 V level,the CMPOUT pin is forced low or keep in High Z state basedon input voltage on CMPIN pin. If the CMPIN voltage is

above 0.8 V when the VCCLV touches the VCMP(on) level, theCMPOUT pin is forced to low.

The internal current source Iref1 has its nominal valuewhen supply voltage VCCLV is above 3.7 V. Figure 53 showsthe behavior of the comparator based on supply voltageVCCLV.

Figure 53. Operational Condition of the Comparator Based on Supply Voltage

t

t

t

t

2.5 V 3.7 V

tGreen line for VCMPIN > 0.8 V

2.5 V3.7 V4.4 V

Low stateHigh Z

Low stateHigh Z High Z

120 �A

VCMPOUT (t)

VCMPIN (t) Green line for VCMPIN > 0.8 V

Blue line for VCMPIN < 0.8 V

Blue line for VCMPIN < 0.8 V

VCMPOUT (t)

Iref1 (t)

VCCLV (t)

Thermal ShutdownInternal TSD protects the silicon against self−destruction

due to high temperature. If the temperature on siliconreaches 160°C typically, LDO output and input of

over−temperature detection are disabled. The CMPOUT pinis set to Low state as an indication of the over−temperaturecondition. All components are enabled again when thesilicon temperature fall by 20°C.

ORDERING INFORMATION

DeviceMaximum Peak

Current VCCLV (on)

VCCLV SwitchINT SwitchReferences

LDO OutputVoltage Package Shipping†

NCP10970A1DR2G 350 mA 8.4 V 3.60 V / 3.65 V

3.80 V / 3.85 V

3.3 V SOIC−16NB(Pb−Free)

2500 / Tape & Reel

NCP10970B1DR2G 350 mA 8.4 V 5.30 V / 5.35 V

5.50 V / 5.55 V

5 V SOIC−16NB(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

SOIC−16 NB, LESS PIN 15CASE 752AC−01

ISSUE ODATE 28 JAN 2011SCALE 1:1

NOTES:1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL BE0.13 TOTAL IN EXCESS OF THE b DIMENSION ATMAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLDPROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

1 8

16 9

SEATINGPLANE

L

M

h x 45�

e15X

H E

D

M0.25 B M

A1

A

DIM MIN MAXMILLIMETERS

D 9.80 10.00E 3.80 4.00

A 1.35 1.75

b 0.35 0.49

L 0.40 1.25

e 1.27 BSC

C 0.19 0.25

A1 0.10 0.25

M 0 7

H 5.80 6.20h 0.25 0.50

� �

6.40

15X0.58

15X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

16

8 9

M0.25 A S

b15X

T B S

A B

C

C

XXXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package

GENERICMARKING DIAGRAM*

*This information is generic. Please referto device data sheet for actual partmarking. Pb−Free indicator, “G”, mayor not be present.

1

16XXXXXXXXXXXXGXXXXXXXXXXXXX

AWLYWW

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98AON55422EDOCUMENT NUMBER:

DESCRIPTION:

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