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Design Approach towards High Performance AddressableMemory for Future Search Engines Using 45nm CMOS

TechnologyNupur G. Nanoti Shital A. Dhanfule Prathamesh V. Phadke Siddharth K. Ganvir

Abstract —Addressable Memory (CAM) is a keyelement in wide variety of applications. A major challenge inrealization of such systems is the complexities of scaling MOStransistors. Convergence of disparate technologies, which arecompatible with CMOS processing, may allow extension ofMoore’s Law for a few more years.

This paper provides a new approach towards the designand modeling of memristor based CAM (MCAM) using acombination of MOS devices to form a core of a memory or logiccell that forms the building block of the CAM architecture. Thenon-volatile characteristics and the nanoscaled geometry togetherwith compatibility of the memristor with CMOS processingtechnology increases the packing density, provides for the newapproaches towards power management through disabling CAMblocks without loss of stored data, reduces power dissipation, andhas scope for speed improvement as the technology matures.

Semiconductor memory arrays capable of storing largequantities of digital information are essential to all digitalsystems. The amount of memory required in a particular systemdepends on the type of application, but, in general, the number oftransistors utilized for the information (data) storage function ismuch larger than the number of transistors used in logicoperations and for other purposes. The Microwind 3.1 softwarewill allow designing and simulating an integrated circuit atphysical description level. The main novelties related to the 45nmtechnology are the high-k gate oxide, metal gate and very low-kinterconnect dielectric. The effective gate length required for45nm technology is 25nm. An efficient chip area is designed using45nm CMOS technology of high speed memristor based CAM i.e.MCAM cell.

Key Words — Content addressable memory (CAM), memoryresistor-based CAM (MCAM), memory resistor (memristor)-MOS hybrid architecture, modeling.

I. INTRODUCTION

The research for a new model that will attainprocessing speed in order of an exaflop (1018 floating pointoperations per second) and further into the zetaflop (1021 flops)is a major challenge for both circuit designers and systemarchitects. The evolutionary progress of networks such asInternet also brings about the need for realization of newcomponents and related circuits that are compatible withCMOS process technology as CMOS scaling begins to slowdown.[7] As Moore’s law becomes more difficult to fulfill,integration of significantly different technologies such asspintronics [7], carbon nano tube field effect transistors [11],optical nanocircuits based on metamaterials [8], and morerecently the memristor, are gaining more focus thus creatingnew possibilities towards realization of innovative circuits andsystems within the System on System (SOS) domain.

This paper explores the conceptualization, design andmodeling of memory cell as a part of a Memristor basedContent Addressable Memory (MCAM) architecture using acombination of switch having some fixed resistance value asmemristor and n-type MOS devices (i.e. NOR-TYPE MCAMCELL and NAND-TYPE MCAM CELL). A typical ContentAddressable Memory (CAM) cell forms a SRAM cell that hastwo n-type and two p-type MOS transistors, which requiresboth VDD and GND connections as well as well-plugs withineach cell. Construction of a SRAM cell that use memristortechnology, which has a non-volatile memory behavior and canbe fabricated as an extension to a CMOS process technologywith nanoscaled geometry, addresses the main thread ofcurrent CAM research towards reduction of powerconsumption. The design of a CAM cell is based on fourthpassive circuit element, the memristor predicted by Chua in1971 and generalized by Kang. Chua postulated that newcircuit elements defined by the single valued relationshipdø=Mdq must exist; whereby current moving throughmemristor is proportional to the flux of magnetic field thatflows through the material. Therefore memristor-based CAMcells have the potential for significant saving in powerdissipation. [14]

Power has become one of the most importantparadigms of design convergence for multi gigahertzcommunication systems such as optical data links, wirelessproducts, microprocessor & ASIC/SOC designs. This projectintroduces design aspects for layout design of static RAMmemory cell, conventional CAM memory cell and memristor-based CAM (MCAM) memory cell using VLSI technology.These cells are designed using latest 45nm CMOS technologyparameters, which in turn offer high speed performance at lowpower. There is a large variety of types of ROM and RAM thatare available. These arise from the variety of applications andalso the number of technologies available. This means thatthere are a large number of abbreviations or acronyms andcategories for memories ranging from Flash to MRAM, PROMto EEPROM, and many more.

Effort has been taken to design Low Power, Highperformance Static RAM, using VLSI technology. The designprocess, at various levels, is usually evolutionary in nature. Itstarts with a set of requirement. When the requirements are notmet, the design has to be improved. More simplified view ofthe VLSI technology consists of various representations,abstractions of design, logic circuits, CMOS circuits andphysical layout.

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II. LITERATURE REVIEW

From the rigorous review of related work andpublished literature, it is observed that many researchers havedesigned MOS content addressable memory by applyingdifferent techniques. Researchers have undertaken differentsystems, processes or phenomena with regard to design andanalyze MOS content addressable memory and attempted tofind the unknown parameters. Since in the real world todayVLSI/CMOS is in very much in demand, from the carefulstudy of reported work it is observed that very few researchershave taken a work for designing MOS content addressablememory with CMOS/VLSI technology.

Memristor was originally envisioned in 1971 bycircuit theorist Leon Chua as a missing non-linear passive twoterminal electric component relating electric charge andmagnetic flux linkage. Leon Chua more recently argued thatthe definition should be generalized to cover all forms of 2-terminal non-volatile memory devices based resistanceswitching effects although some experimental evidencecontradicts this claim. [1]

In March 2006, K. Pagiamtzis and A.Sheikholeslami reviewed CAM-design techniques at thecircuit level and at the architectural level. The main CAM wasdesigned to reduce power consumption associated with thelarge amount of parallel active circuitry, without sacrificingspeed or memory density. [4]

In July 2008, B. Amelifard, F. Fallah andM.Pedram was worked on a method which based on dual-Vtand dual-Tox assignment to reduce the total leakage powerdissipation of static random access memories(SRAM).[10]

In April 2010, S. Shin, K. Kim, and Sung-Mo Kangdeveloped their compact models for current-controlled andvoltage-controlled memristors. These models were developedbased on the fundamental relationships between charge andflux of memristors. [14]

In September-Octomber 2010, Dr. UjwalaA.Belorkar has researched on application of 45nm VLSItechnology to design layout of static RAM memory. [15]

In August 2011, K. Eshraghian, Kyoung-Rok Cho,O. Kavehei, Soon-Ku Kang, D. Abbott and Sung-Mo S.Kang has researched on Memristor MOS Content AddressableMemory (MCAM): Hybrid Architecture for Future HighPerformance Search Engines. [16]

In this paper Memristor MOS Content AddressableMemory (MCAM): Hybrid Architecture for Future HighPerformance Search Engines is implemented by using CMOStechnology.

Both the conventional CAM and MCAM circuits havebeen implemented using Dongbu HiTech 0.18-µm technologywhere 1.8 V is the nominal operating voltage for the CAM.The MCAM cell is implemented using nMOS devices andmemristors without the need for voltage source.

From the careful study of reported work, it isobserved that researchers have proposed various techniques todesign the chip and to improve its characteristics and variousparameters but up to the result of my survey regardingmemristor based MCAM design. From the continuous survey itis observed that foundry of technology and supply voltage

range is continuously decreases with the advancement oftechnology.

It is also well known to that; VLSI technology is thefastest growing field today. And according to Moore’s lawwhich state that the numbers of transistors on an integratedcircuit will double every 18 months. By scaling down thetechnology, we can optimize the parameters like powerconsumption. The current technology up to 2008 was lowerrange of nm technology. Hence considering the advancementof future technology and the advantage of 45 nm technologiesover 65 and 90 nm technologies, the proposed project has beendecided to do with the selection of higher order of 45nmtechnology.

Considering all this constraint regarding the demandof today’s fast communication world, the research has beentaken to design low power MCAM using 45nm VLSItechnology.

III. MEMORY ARCHITECTURE OF PROPOSED MCAM

CELL

A. MemristorA memristor is a two-terminal device with a variable

resistance that can be used as memory.

Fig.1. Memristor Symbol

Fig.2. Nano-sized MemristorThe memristor behaves as a switch, much like a

transistor. However, unlike the transistor, it is a two terminalrather than a three-terminal device and does not require powerto retain either of its two states. A memristor changes itsresistance between two values and this achieved via themovement of mobile ionic charge within an oxide layer. Thisbehavior influences the architecture of CAM systems, wherethe power supply of CAM blocks can be disabled without lossof stored data. Therefore, memristor-based CAM cells have thepotential for significant saving in power dissipation.

(a) “ON” state, (b) “OFF” state,Low resistance high resistance

Fig.3. Memristor switching behaviorThe key feature of memristor is it can remember the

resistance once the voltage is disconnected. In (a) “doped” and“undoped” regions are related to Ron and Roff, respectively. Thedopant consists of mobile charges. In (b), L and W are the thin-film thickness and doped region thickness, respectively. The

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memristor can be modeled in terms of two resistors in series,namely the doped region and undoped region each havingvertical width of w and L-w, respectively, as shown in Fig.3.

B. Generic Memristor n-MOS CircuitFig.4 shows the basic structure for a memristor-nMOS

storage cell. For writing logic “1,” the memristor receives apositive bias to maintain an “ON” state. This corresponds tothe memristor being programmed as logic “1.” To program a“0” a reverse bias is applied to the memristor, which makes thememristor resistance high. This corresponds to logic “0” beingprogrammed.

(a) Structure of write mode

(b) Basic cell

© Program “Low” resistance “1”

(d) Program “High” resistance “0”

Fig.4. Basic memristor-nMOS storage cell and the timingdiagram

(a) Shows write mode part of the ith cell in a row. (b) Basiccell circuit without the match line transistor. (c) “Low”resistance, RON, programming, equivalent to logic “1”. (d)“High” resistance, ROFF, programming, equivalent to logic “0”.

C. The Proposed MCAM Cell DesignIn this section, variations of MCAM cells as well as

brief architectural perspective are introduced. A CAM cellserves two basic functions: “bit storage” and “bit comparison”.

There are varieties of approaches in design of basic cell such asNOR-based match line, NAND-based match line, etc. This partprovides the properties of conventional SRAM based CAMand a possible approach for the design of content addressablememory based on memristor. [16]

D. Proposed MCAM Cell StructureFig.5 illustrates several variations of the MCAM core

whereby bit-storage is implemented by memristors ME1 andME2. Bit comparison is performed by either NOR oralternatively NAND-based logic as part of the match-line MLi

circuitry. The matching operation is equivalent to logicalXORing of the search bit (SB) and stored bit (D). The match-line transistors (ML) in the NOR-type cells can be consideredas part of a pull-down path of a precharged NOR gateconnected at the end of each individual MLi row. The NAND-type CAM functions in a similar manner forming the pull-down of a precharged NAND gate. Although each of theselected cells in Fig.5 have their relative merits, the approachin Fig.5 (a) where Data bits and Search bits share a commonbus is selected for detailed analysis. The structure of the 7-TNAND-type, shown in Fig.5 (b), and the NOR-type areidentical except for the position of the ML transistor. In theNOR-type, ML makes a connection between shared ML andground while in the NAND-type; the ML transistors act as aseries of switches between the MLi and MLi+1.

(a) 7-T NOR-type MCAM cell

(b) 7-T NAND-type MCAM cellFig.5. Cell configurations of possible MCAM structure

E. Layout Design of Proposed MCAM Cell1. 7-TRANSISTOR NOR-TYPE MCAM CELL

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Fig.6. Layout design of 7 transistor, 2-Memristor NOR-typeMCAM cell

2. 7-TRANSISTOR NAND-TYPE MCAM CELL

Fig.7. Layout design of 7 transistors, 2-Memristor NAND-typeMCAM cell

Fig 6 and fig 7 are the layout design of 7-T NOR-typeMCAM cell and 7-T NAND-type MCAM cell respectively.Match Line i.e. ML is connected in parallel and series to 7-TNOR-type MCAM cell and 7-T NAND-type MCAM cellrespectively to form array of cell. ML is a DC supply havingDC voltage level at 0.4V. As this both cells do not have the p-MOS transistor, there is reduction in the chip silicon area. Alsoin fig 6 both memristor have the same resistance value of 1000ohm and in fig 7 first memristor ME1 has resistance value of200 ohm and second memristor ME2 has resistance value of2000 ohm.

IV. SIMULATION RESULT

1. 7-T NOR-TYPE MCAM CELL

Fig.8. Simulation for 7 transistor, 2-Memristor NOR-typeMCAM cell

2. 7-T NAND-TYPE MCAM CELL

Fig.9. Simulation for 7 transistors, 2-Memristor NAND-typeMCAM cell

The simulation of the 7T NOR-type MCAM cell and7T NAND-type MCAM cell is proposed in Fig 8 & 9respectively. ML is applied to 7T NOR-type MCAM cell and7T NAND-type MCAM cell in series and parallel respectively.Match Line (ML) is used only to connect one cell with anothercell i.e. to form an array structure. Supply is given from WSLINE. When WS LINE is at logic 1 value then the transistorsN6 and N4 are ‘ON’ and when WS LINE is at logic 0 valuethen the transistors N6 and N4 are ‘OFF’.

When WS LINE is at logic 1 value, SB LINE gives itsinput data to output data i.e. D/S LINE and SB BAR LINEgives its input data to output data i.e. D BAR/S BAR LINE.When WS LINE is at logic 0 value, current flows through ME1and ME2 via VDD/2 voltage supply having fixed resistancevalue. It means, when power supply is ‘OFF’ then also SBLINE takes its input data from ME1 and occurs this input datato output data i.e. D/S LINE while SB BAR LINE takes itsinput data from ME2 and occurs this input data to output datai.e. D BAR/S BAR LINE. This means that, memristor givesoutput even if power supply is OFF.

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From Fig, when WS LINE is at logic 1 value then SBLINE shows its output at D/S LINE and SB BAR LINE showsits output at D BAR/S BAR LINE. When WS LINE is at logic0 value, then also SB LINE shows its output at D/S LINE andSB BAR LINE shows its output at D BAR/S BAR LINEbecause of memristor.

From Fig 8 & 9, it is observed that, at time 0.0ns, WSLINE is at logic 1 value and SB LINE is at logic 0 value, so theoutput at D/S LINE is also at logic 0 value and SB BAR LINEis at logic 1 value, so the output at D BAR/S BAR LINE is atlogic 1 value. At time 0.2 ns, WS LINE is at logic 1 value andSB LINE is at logic 1 value, so the output at D/S LINE is alsoat logic 1 value. At time 0.4ns, WS LINE is at logic 0 valueand SB LINE is at logic 0 value but the output at D/S LINE isalso at logic 1 value.

This means that, SB LINE shows its output at D/SLINE even if the WS LINE (i.e. supply is OFF) is at logic 0value. SB LINE shows its output at D/S LINE as it is until thenext WS LINE is selected to logic 1 value. The powerconsumed by 7T NOR-type MCAM cell chip is 0.027µW and7T NAND-type MCAM cell chip is 0.178mW.

CONCLUSIONThe proposed Memory is designed using 45 nm

CMOS/VLSI technology with Microwind 3.1. The mainnovelties related to the 45 nm technology are the high-k gateoxide, metal gate and very low-k interconnect .The Softwareused in program allows us to design and simulate an integratedcircuit at physical description level. The non-volatilecharacteristic and nanoscaled geometry of the memristortogether with its compatibility with CMOS process technologyincreases the memory cell packing density, reduces powerdissipation and provides for new approaches towards powerreduction and management through disabling blocks ofMCAM cells without loss of stored data.

ACKNOWLEDGMENTI am presenting the paper on “Design Approach

towards High Performance Addressable Memory forFuture Search Engines Using 45nm CMOS Technology”.While working on the paper I realized that knowledge iseventually gained at every stage of paper. I have immensepleasure in expressing my whole-hearted sense of gratitudetowards my paper guide Prof. P. D. Gawande, Department ofElectronics & Telecommunication, Sipna College ofEngineering and Technology, Amravati for their valuableguidance, spontaneous encouragement and continuousinspiration, and also for the valuable time that they devoted tome for my present work.

REFERENCES

[1] L. O. Chua, “Memristor—The missing circuit element,” IEEE Trans. Circuits Syst.,vol. 18, no. 5, Sept. 1971, pp. 507–519.[2]M. M. Ziegler and M. R. Stan, “CMOS/nano co-design for crossbar-based molecularelectronic systems”, IEEE Trans. Nanotechnology, vol. 2, no. 4, Dec. 2003, pp. 217-230.[3] K. Zhang et al., “SRAM design on 65-nm CMOS technology with dynamic sleeptransistor for leakage reduction,” IEEE J. Solid-State Circuits, vol. 40, no. 4,Apr. 2005,pp. 895-901.[4]K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuitsand architectures: A tutorial and survey,” IEEE J. Solid- State Circuits, vol. 41, no. 3,Mar. 2006, pp. 712–727.

[5] M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K.Yanagisawa, and T. Kawahara, “90-nm process-variation adaptive embedded SRAMmodules with power line-floating write technique,” IEEE J. Solid-State Circuits, vol. 41,no. 3, Mar.2006, pp. 705–711.[6] S. K. Lu and C. H. Hsu, “Fault tolerance techniques for high capacity RAM,” IEEETrans. Reliab., vol. 55, no. 6, Jun. 2006, pp. 293–306.[7] G. I. Bourianoff, P. A. Gargini, and D. E. Nikonov, “Research directions in beyondCMOS computing,” Solid-State Electron., vol. 51, no. 11–12, 2007, pp. 1426–1431.[8] N. Engheta, “Circuits with light at nanoscales: Optical nanocircuits inspired bymetamaterials,” Science, vol. 317, no. 5845, Sept 2007, pp. 1698–1702.[9] Michael Wieckowski, Student Member, IEEE, Sandeep Patil, Student Member, IEEE,and Martin Margala, “Portless SRAM—A High-Performance Alternative to the 6TMethodology,”IEEE J. Solid-State Circuits, vol. 42, no. 11, Nov 2007, pp.2600-2610.[10] B. Amelifard, F. Fallah and M.Pedram, “Leakage Minimization of SRAM Cells in aDual-Vt and Dual-Tox Technology” IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 16, No. 7, July 2008,pp.851-860.[11] D. Akinwande, S. Yasuda, B. Paul, S. Fujita, G. Close, and H. S. P.Wong,“Monolithic integration of CMOS VLSI and Carbon Nanotubes for HybridNanotechnology Applications,” IEEE Transactions On Nanotechnology, vol. 7, no. 5, Sept2008,pp.636-639.[12] S.M.Kang & Y.Leblebici “CMOS Digital Integrated Circuits Analysis andDesign,”3rd edition TATA McGraw Hill Edition, pp.405-474.[13] E. Sicard, Syed Mahfuzul Aziz, “Introducing 45 nm technology in Microwind3”Microwind application note.[14] S. Shin, K. Kim, and Sung-Mo Kang, “Compact Models for Memristors Based onCharge–Flux Constitutive Relationships,” IEEE Transactions On Computer-Aided DesignOf Integrated Circuits And Systems, Vol. 29, No. 4, April 2010,pp.590-598.[15] Ujwala A. Belorkar, Dr. S. A. Ladhake, “Application of 45 nm VLSI Technology to

Design Layout of Static RAM Memory,” International Journal of Advanced Research inComputer Science, vol. 1, no. 3, Sept-Oct 2010, pp.288-292.[16] K. Eshraghian, Kyoung-Rok Cho, Member, IEEE, O. Kavehei, Student Member,IEEE, Soon-Ku Kang, D. Abbott, Fellow, IEEE, and Sung-Mo S. Kang, Fellow, IEEE,“Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture forFuture High Performance Search Engines,” IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems, vol. 19, no. 8, August 2011,pp.1407-1417.

AUTHOR’S PROFILENupur G. NanotiI have completed B.E. (EXTC) in 2012 and M.E.(ENTC) in 2014 from Sipna C.O.E.T. Amravati.Now working as lecturer in P.R.Patil InstitutePolytechnic and Technology, Amravati.

Shital A. DhanfuleI have completed M.E. (Digital Electronics) in 2011from Shri Sant Gajanan Maharaj College ofEngineering, Shegaon. Now working as a H.O.D. inElectronics Department in P.R.Patil InstitutePolytechnic and Technology, Amravati.

Prathamesh V. PhadkeI have completed B.E.(2012) Degree in Computer Scienceand Engineering from Sant Gadge Baba AmravatiUniversity, Amravati

Siddharth K. GanvirI have completed B.E from IBSS coe ghatkhed,Amravati in July 2012 and now persuing mastersdegree from HVPM COET Amravati, Maharashtra.