Silicon Accelerators

An Introduction

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What is It?

How Does it Work?

What are the Applications?

The Team?

Next Steps?

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Scientific Accelerators

Row 1 Row 2 Row 3 Row 40

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Column 1

Column 2

Column 3

Large Hadron Collider Stanford Linear Accelerator

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Silicon Accelerator

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Stacked 3D IC

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Silicon Accelerator A Fundamental Invention

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Patent Issued

1. A particle controller, comprising: an input port configured to receive a particle stream; a semiconductor cell comprising a cavity through which at least a portion of the particles comprising the particle stream is directed; and one or more electrodes coupled to the cavity and configured to facilitate creation of an electromagnetic field for directing the at least portion of particles through the cavity; wherein the cell is part of a set of semiconductor cells whose cavities are aligned to form a tube through which the at least portion of particles is directed

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How it works

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2D Single Chip Particle AcceleratorCornell University

DARPA funded project 2011

Designed by MEMS Dept.

Single beam per chip

Energy of 30 Kev

Proves that an IC can accelerate a particle beam at high energies.

Proves beam deflection~50 degrees

Demonstration of high acceleration value

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Silicon Accelerator3D particle path

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Silicon Accelerator – how it works

Changing electric field

Accelerating region in IC

Drift tubes of equal lengths

Frequency and phase of each stage under digital control of I.C.’s

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3D SIC

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Through Silicon Via

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Silicon AcceleratorElectrodes

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Front side of Chip

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Silicon AcceleratorElectrostatic Lens

Simon simulation SAI confidential

Electric Fields

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Cathode

+Electrostatic lens

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-Anode

Single Stage

High Speed IC

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Silicon Accelerator3D SIC

Digital Processor

Beams

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Side View of Stacked Single Stage

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Multiple Stages

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Silicon AcceleratorSummary

Solid State Linear Particle Accelerator

Enabled by 3D SIC and TSV (through silicon via)

3D SIC per accelerating stage

Each 3D SIC contains • Accelerating electrodes

• Drift tubes

• Electrostatic lens

• Digital and Timing controls

• Sensors

• Scanning electrodes

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Silicon AcceleratorNanobeam Ion Implantation

A new method for Integrated Circuit manufacturing

“IC's making IC's”

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Semi ManufacturingIn Crisis

Fab capital cost at 14 nanometers >$10 Billion

Next Generation Steppers (EUV) >$100M

Mask sets approaching $10M

FinFet transistors at 25 nm going to 10 nm

Wafer size increasing to 450mm

Consolidation of ~4 Major Fab Manufacturing at 14 nanometers

IC product volume threshold >millions of units

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Nanobeam ImplanterA Million Beams

Current Ion Implant

NBI

Single Beam ~cm

Bream ArrayNanometer beams

Silicon Accelerator

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Silicon AcceleratorsBandwidth

Massive Beam Array:

1 cm chip at 10 micron pitch ----1 Million beams

Electrostatic micron-sized lens ----Gigahertz scanning

Bandwidth is million beams times Gigahertz per beam

Embedded Digital processing & EDA database

Fully automated and robotic wafer handling

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Nanobeam ImplanterIC Doping Comparison

Current implant Method NBI

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Photo-lithography Digital-lithography

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NBIDigital Lithography

Photo-lithography NBI

photons ions

UV laser SiliconAccelerator

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Mask

Maskless electron beam lithography has the potential to extend semiconductor manufacturing to the sub-10 nm technology node. KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL) for high-volume 10 nm logic (16 nm HP). This paper reviews progress in the development of the REBL system towards its goal of 100 wph throughput for High Volume Lithography (HVL) at the 2X and 1X nm nodes. In this paper we introduce the Digital Pattern Generator (DPG) with integrated CMOS and MEMs lenslets that was manufactured at TSMC and IMEC.

KLA

The lenslet consists of a densely packed array of 4µm deep cylindrical holes with a 1.4 µm diameter and top spacing of only 200nm. The electron beam entering the lenslet holes is focused through a set of 4 ring electrodes. The ring electrodes can be tuned to focus the electron beams by applying static voltages up to 50V on the ring electrodes. The bottom of each hole consists of a small metal plate that can be switched by a CMOS circuitry below, either reflecting or absorbing the incoming electrons. In this way, the incoming electron beam is split into 1 million smaller beamlets, a strategy designed to enable higher throughput for the e-beam writing process through parallelization.

Read more at: http://phys.org/news/2012-11-imec-customized-lenslet-array-kla-tencor.html#jCp

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NBIMarket Opportunity

Worldwide Semiconductors market is >$300 Billion

Served by Equipment Market >$50 Billion• Fab equipment: new and upgrades

• Back-end: Test and Assembly

Fab Segments impacted by NBI

Mask making

Photo-lithography: steppers

Resist: Track systems

Ion Implant

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NBI Economic Potential

No Tooling cost: eliminates mask cost tooling• Small production lots

• Low prototyping cost

• Customized even a few chip per wafer

Lower Fab Capital Cost• Smaller Fabs economical: $millions versus

$billions

• Better clean room utilization: smaller footprint

• Lower Fab Inventory; less inventory risk

• Fewer Processing Steps: higher yields

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Performance ImpactMultiple processes simplified

• DRAM+Logic+Flash+Analog

Mixed Technologies Practical

• MEM's,LED,Laser,DLP

Improved Analog

• Wide materials selection for

– Resistors, super-capacitorsTransistor Structures

• different depth and doping across wafer

Advanced Technologies

• Graphene transistors, magnetoresistive RAM

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NBISummary

New Methodology of Semiconductor Manufacturing

Nanobeam Ion Implantation (NBI) Million beam Silicon Accelerators High bandwidth Digital Lithography

Replaces Photo-lithography Lower cost Higher yields High IC performance

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Nanofusion

A safe portable clean power source

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Power of the Sun

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Fusion

Light elements—hydrogen—combine into helium

No radioactive by products—no meltdown possible

First discovered in 1930 using linear accelerator

Fission splits heavy elements---Uranium

---radioactive isotopes are by products

Research to develop Fusion Engine began in 1950

Fusion requires a hot dense compressed plasma

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Fusion

Light elements—hydrogen—combine into helium

No radioactive by products—no meltdown possible

First discovered in 1930 using linear accelerator

Fission splits heavy elements---Uranium

---radioactive isotopes are by products

Research to develop Fusion Engine began in 1950

Fusion requires a hot dense compressed plasma

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Fusion

Why fusion been so hard to achieve?

Plasmas expands:

• No physical container possible: extremely hot

• Reaction time ~ plasma density

Hot Plasma loses energy:

• The electrons radiate light when hot

• Fusion energy must exceed loses

How to compress plasma at >100 million degrees?

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National Ignition FacilityFusion Experiment

The target chamber is hoisted by a crane and prepared for installation in the NIF target bay.

c

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National Ignition Facility

World's most powerful Laser system: 192 Laser beams

~2 million joules at 500 Terra-watts

Inertial Confinement Fusion

Millimeter diameter hydrogen fuel pellet

Idea is to heat and compress fuel with laser beams

Fuel failed to ignite due to:

Poor beam uniformity, jitter, coupling inefficiencies

NIF funding for fusion ignition dropped

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Nanofusion

Ion manifold

Silicon Accelerators

NanobeamsTarget Region

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NanoFusionPlasma compression

Plasma compression

Ignited Core

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Conditions for FusionLawson Criterion

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NanofusionBoron

CoulombBarrier

Boron Nucleus

proton

StrongForce Fusion

HeliumIons

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Nanofusion

Millions of beams focused into nanometer region

– Uniform compression of hot plasma

– Sub-picoseconds timing reduces beam jitter to nanometer

– Ion energy of 100K electron volts = 160 Million degrees

– Density of plasma is sum of beam densities

Fuel is hydrogen and boron

– Converted to fast moving ions of helium

– Energy of helium ions re-converted into electricity

Nanofusion is a portable power source

– About the size of basketball

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A few Other Apps

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Nano Technology Cancer Therapy Holography

Data Archive Quantum ComputingInstrumentation

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Member Role History

Alok Mohan Executive Leadership NCR-VPSCO-CEO

Sam Brown Technology strategy NCR—MicroelectronicsAlpine Semi-CEO

Tom Brummet Business Development NCR---MicroelectronicsSilego Semi -VP Marketing

Marcelo Martinex IC Design PrincipalAdvanced Analog Design

Jonathan Wurtele Technical Adviser BerkeleyProfessor of PhysicsSenior Scientist LNL

Ed Pheil Technical Adviser General DynamicsNuclear Engineer

John Bryant Technical Adviser Atmel: VP Marketing

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Next StepsPrinted Circuit Board

Identify Semiconductor Partner

Expand Team

Release Analog IC

Release Digital IC

Nanobeam prototype

Release Development Kit

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Confidence Factors

1. Manufacturing: Very High-Processes are In Production

2. Competition: No Direct Competitor at this Time

• Strong-Broad Patents-Trade Secrets

3. Engineering: Digital IC~Block Diagram complete. Analog IC: critical circuits simulated. Need to Identify Partner

4. Theory of Operation: Proven in 2D chip

5. Market Entry: Acceptance of Development Tool-Intel's Microprocessor Model

6. First Revenues:

• Now Partnership R&D Licenses

• Development Systems 18 Months