N Terry Jernberg T March 2012 I V E

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CONFIDENTIAL

Terry Jernberg

March 2012

Basic Signal Integrity

August 29, 2012 Cadence 2

Who needs to be concerned with Signal Integrity?

What is Signal Integrity?

When is Signal Integrity a concern and when in the design process should it be addressed?

How do we address them?

Where do the problems typically show up?

Why are they becoming such an issue?


Driver sends a signal to a receiver which must arrive within known thresholds

while the signal integrity engineers clear the path.


• Signal Integrity is a field of study half-way between

digital design and analog circuit theory.

• It’s about ringing, crosstalk, ground bounce, and power

supply noise.

• It’s all about how to build really fast digital hardware that

really works.

• It’s about practical, real-world solutions to high-speed

design problems.

Dr. Howard Johnson

Ask the experts

www.sigcon.com

http://www.sigcon.com/index.html


Dr. Eric Bogatin

Ask the experts

www.bethesignal.com

• You either have signal integrity problems or your about

to.

• It’s about Impedance control, crosstalk, ground bounce,

and rail collapse.

• It’s all about managing the white space on the

schematic.

• “Rule of thumb” approach has value but is no longer

adequate.

http://www.bethesignal.com/

In one sentence… What are we trying to do?


0011001101100 0011001101100

0011001101100 ?01?00?10?1??

(not exactly sure)

0011001101100 Is it sending

something?

Lets take a closer look


• Electrical Noise: Signal Integrity and EMI

• Timing: setup, hold, propagation delay, and skew

Interconnect

First and foremost,

as these are digital signals,

we need to be able to

distinguish 1’s and 0’s

High Speed problems

How do we know what the signal will look like when it reaches the receiver?


Models


Interconnect Device

Circuit Equivalent

Behavioral Model

Spice

IBIS

RLGC

S-Parameter


Simulation


Driver Model

Receiver Model

Distortion


C1

Isolating a single trace…

…apply a pulse input

…and observe the response

RLC values are responsible for the shape of the distortion and can be defined mathematically


Simple test….


Simulate

Expected Results What Happened ???

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CONFIDENTIAL


Transmission Lines & Reflections

Basic Transmission Line Types

W

H

er

tand t

W

t

H

Microstrip

Stripline

Dielectric constant (Relative permittivity) (er )

• Describe a materials ability to hold charge compared

to vacuum when used in a capacitor.

• The permittivity of a vacuum is: e0 = 8.85419 ·10-10

• The permittivity of a material is: e = e0 er

• If we put a dielectric material between two capacitor

plates of area A and a distance D the capacitance in

Farad is:

C = e A

D [F]

Loss tangent ( tand )

• Describe the materials “resistance” to change of

polarization

• s is the conductivity of the dielectric at frequency .

(S/m)

• e is the permittivity of the material. (F/m)

tan d =

s

2 f e

Magnetic permeability (m)

The magnetic permeability describe a magnetic

property of a material. It is the ratio between the

magnetic flux density (B) and the external field

strength (H).

m = B

H

The relative permeability of a material is the permeability relative

to vacuum.

µ = µ r µ 0

µ 0 = 4

10 7

[H/m]

Some Transmission Line Properties

• Signal velocity (m/s)

– Influenced by dielectric constant of materials

• Impedance

– Mostly influenced by dielectric constant of material, width of line

and distance to ground plane(s)

• Loss

– Influenced by conductivity of conducting material, frequency of

signal and loss tangent of the material.

• Dispersion

– Influenced by frequency dependant dielectric constant

Signal velocity ( )

• The signal velocity is measured in m/s

• For a practical calculations the signal velocity is only

dependant on the relative dielectric constant er

• With c0 the velocity of light in vacuum, we get:

v = c 0

e r

[m/s]

Impedance ( Z0 )

• Impedance is measured in Ohms

• Impedance describes the AC resistance a driver will

see when driving a signal into a indefinitely long

transmission line.

Z 0 = R + L j G + C j

For a loss less line this simplifies to:

Z 0 = L

C

[ohm]

[ohm]

Loss ( a )

• Loss a is measured in dB / m

• Loss is the reduction of signal voltage along a line

due to resistance and leakage

• The resistive losses is due to resistance in

conductor and ground plane.

• The dielectric losses is due to the energy needed to

change polarization of the dielectric material.

• The radiation losses is the energy sent from the

conductor acting as an antenna.

Resistive losses ( aC )

The resistance is based on the cross-section of the

conductor and the bulk resistivity of the conductor

material:

R = 1

s t

a = 8,68589 R

2 Z 0

The loss factor is then calculated by:

[dB/m]

[ohm]

s = bulk conductivity [S/m]

w = line width [m]

t = line thickness [m]

Skin depth ( ds )

At higher frequencies only a thin layer of the conductor transport the

current. The thickness where the current density is reduced to 1/e is

called the skin depth ds.

d s = 1

s µ f [m]

Resistance at higher frequencies

When the conductor is much thicker than the skin depth one have

to substitute the skin depth for the thickness in the resistance

formula:

[ohm]

The resistance has now become frequency dependent !

R = 1

s d s

R = 1

s 1

s µ f

Dielectric loss ( aD )

The dielectric loss aD is due to the energy needed to change the

polarization of the dielectric material. The conductance is then:

G = 2 f C tan d

a D

= 1

2 8,68589 G Z 0

[S/m]

The dielectric loss is then:

[dB/m]

Radiation loss

• All lines are radiating more or less

• Radiation loss is often negligible from a signal integrity

standpoint but important from a EMC standpoint.

• Radiation loss is difficult to calculate

Dispersion

• Dispersion is an effect caused by different velocities for

the different frequency components. The result is a

different phase change for each of the frequency

components.

• The reason for this is that the dielectric constant of the

material vary with frequency.

• Dispersion is one of many sources of signal distortion.

• It is not easy to calculate dispersion because the lack of

frequency dependant material data.

• Dispersion may cause trouble when exact edge position

is important.

Simple test….


Simulate

Expected Results What Happened ???

Mismatch…

We don’t need to play this to know it won’t end well…


Mismatches in Engineering Generally cause problems…


Civil Engineers get it, you wouldn’t see these connected

Mechanical Engineers get it, these connections don’t exist either

But Electrical Engineers do it all the time

15 ft

15 ohms

15 mm

75 ohms

75 mm

75 ft

1000 ohms

1000 ft

1000 mm

What happens when a signal hits a mismatch?


ZLEFT > ZRIGHT

ZLEFT < ZRIGHT

The result is defined by the direction and magnitude of the mismatch


Reflected Wave

Incident Wave Composite Wave

It’s called REFLECTION COEFICIENT and is defined as:

Z2 – Z1

------------

Z2 + Z1

Signal continues to Split, BOUNCE, and possibly invert at EVERY Discontinuity


A BOUNCE DIAGRAM is used to mathematically calculate: The magnitude of the incident wave AND The magnitude of the reflected wave

Let’s look at a real net: a single DDR3 data line


Geometry based transmission line models


Introducing…


It’s easy, all you have to do is

plug the geometry for each structure

Into these equations.

James Clerk Maxwell

(1831–1879) …and everyone realized

how easy that would be


(Coarse)

(Medium)

(Fine)

1. Rules of thumb

2. Analytical approximations

3. Numerical simulations

The four describing parameters

• R Resistance per unit length [ohm / m]

• C Capacitance [ F / m ]

• L Inductance [ H / m]

• G Conductance [ S / m ]

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CONFIDENTIAL


Topologies & Termination

August 29, 2012 Cadence Confidential: Cadence Internal Use Only 46

• Routing topologies

• Termination

• Signal return path

Issues for Routing

Topologies


Point to Point Topology

• This is the ideal topology but not very efficient in that

it requires a lot of extra buffers.

• Always use this topology for critical clock trees.

• Use low skew clock buffers

• Skew can be compensated with delay lines

Fan / Star topology

• This topology is routing efficient but put heavy load

on the driver, especially where several lines fan out.

• Use drivers with low output impedance.

• Terminate properly at each receiver or reflections will

propagate back and forth in the net.

• Be careful with the high power consumption of many

terminated lines

T - Topology

• This split will cause a 33% negative reflection if all

lines are of same impedance.

• All ends (also driver) should be terminated properly

for larger nets

• The driver will have to drive twice the amount of DC

into the termination resistors.

Daisy Chain

• The preferred topology for high speed digital.

• Terminate in both ends.

• Allow no stubs

• Keep tap load low.

• Keep distance between loads so high that the signal

can recover.


Termination

Why terminate signals ?

• Termination is a method to match the driver, line and

receiver in such way that no reflections are

generated.

• Generally the ideal would be to do a parallel

termination in the line impedance

• Terminate critical lines that are longer than 1/3 of the

rise time. On FR-4 this mean that a 1ns rise signal,

the longest un-terminated line is 2 inches.

• Reflections can cause double trigging, if using non-

terminated nets do not use data before the reflections

have settled.

Series Termination

• Used to match driver impedance

• Slow rise and fall times (Some times good, for

instance to achieve low crosstalk)

• Absorb reflections if matched to line

Thevenin Termination

• Ideal for bus termination or lines with 3-State drivers.

• 330 Ohm & 220 Ohm is often used.

• Faster switching from 3-state

• Does NOT correctly terminate the line, reflections will

occur

Parallel Termination

• The termination of choice for high speed digital,

especially for ECL, PECL and other technologies

intended for termination.

• High power consumption.

• 100% clean signals possible

RC Termination

• AC termination, better for technologies not intended

for termination.

• Low power consumption (No DC consumption)

• Be careful with inductive capacitors, select capacitors

with care.

Diode Termination

• Kills large over and undershoot

• Not generally useful in high-speed systems. (A

design needing this type of termination have probably

greater problems elsewhere)

Signal return path

The high frequency signals follow a mirror image of the

trace on the ground plane. Do not degrade this return

by:

• Changing to layers which have another ground-plane

without placing a ground-ground via close to the signal

via. If the new reference plane is a power plane a low

inductance decoupling is placed close to the signal via

• Using split reference planes.

• Using one small via for several returns, this may cause

common mode problems.

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Basic Principals of Signal Integrity CROSSTALK

Chapter 03

What is Crosstalk?

In electronics, the term crosstalk (XT) has the following meanings:

Undesired capacitive, inductive, or conductive coupling from one

circuit, part of a circuit, or channel, to another.

Any phenomenon by which a signal transmitted on one circuit or

channel of a transmission system creates an undesired effect in

another circuit or channel.

The term Crosstalk comes from the early analog phone lines where you

could actually hear voices from neighboring lines due to EM coupling.

Crosstalk is when the switching on one signal causes noise on an

adjacent line.

Crosstalk is due to Electric and/or Magnetic Fields interacting with a

transmission line element in such a way that an unintended current is

produced.

Cross talk is due to the capacitance and inductance between

conductors, which we call "Mutual Capacitance"

(CM)

"Mutual Inductance" (LM)

62

• Backward / Forward

• Near End (NEXT) / Far End (FEXT)

• Capacitive / Inductive

• Odd Mode / Even Mode

Crosstalk Terminology

Near End

Far End

Forward Backward

Coupling

Crosstalk is the coupling of energy from one line to another by way of:

Mutual capacitance (electric field) & Mutual inductance (magnetic field)

Model the Coupling

( mirrored view

)

“lossless” T-line

Geometry &

Materials

E & M Field

Solutions

Circuit Equivalent

Models

Geometry such as trace width,

separation and distance from the

reference plane all influence the

degree of coupling. Properties of the

materials used (such as dielectric

constant) also play a significant role. Equation based or the more accurate

field solver based methods are used

to determine an equivalent model of

the transmission line. For PCB etch, these models are

typically constructed as an RLGC

ladder circuit. For simplicity, traces will be treated

as “lossless”.

The use of distributed transmission line models is helpful for visualizing concepts

behind crosstalk

Single distributed TL

model

Coupled distributed TL

model

Distributed

models spread

Capacitance and

Inductance over

repeated

segments

alternate view…

A wave front is transmitted

from the aggressor's driver…

This continues until the wave

front reaches the Aggressor’s

receiver…

Current continues to flow

across the mutual inductance

the entire length of the coupled

traces (Td-delay)… It takes additional time (equal

to the prop delay) for the

current originating at the far

end mutual capacitance to

propagate back to the victim’s

near end where it dissipates at

the near end termination.

Current in the forward direction

accumulates…

Current reaching the victim

trace, is split sending half in

each direction…

As it propagates, it produces

current thru the mutual

capacitance…

Mutual

Capacitance

Capacitive Crosstalk

Near End (NEXT)

Far End (FEXT) The near and far end victim line currents sum to

produce the near and the far end crosstalk noise

Zs

Zo

Zo

Zo

Zs

Zo

Zo

Zo

ICm Lm

near

far

near

far

ILm

LmCmfarLmCmnear IIIIII

The Rise Time of the Aggressor:

The faster the rise time -> The

greater the cross talk.

The Voltage Swing of the Aggressor:

The larger the voltage swing of the driver -> The

greater the cross talk.

The Physical Implementation:

The farther from a reference plane

The larger the dielectric constant

The smaller the distance between traces -> The greater

the cross talk.

Crosstalk is the coupling of energy from one line to another via:

Mutual capacitance (electric field)

Mutual inductance (magnetic field)

Mutual Inductance and Capacitance

Zs

Zo

Zo

Zo

Mutual Capacitance, Cm Mutual Inductance, Lm

Zs

Zo

Zo

Zo

Cm

Lm

near

far

near

far

The near and far end victim line currents sum to produce the near and the far end crosstalk noise

Crosstalk Induced Noise “Coupled Currents”

Zs

Zo

Zo

Zo

Zs

Zo

Zo

Zo

ICm Lm

near

far

near

far

ILm

LmCmfarLmCmnear IIIIII

August 29, 201212/4/2002

Cad

ence

Conf

ident

ial:

Cad

ence

Inter

nal

Use

Only

Cros

stalk

Over

view

Near end crosstalk is always positive Currents from Lm and Cm always add and flow into the node

For PCB’s, the far end crosstalk is “usually” negative

Current due to Lm larger than current due to Cm Note that far and crosstalk can be positive

Crosstalk Induced Noise “Voltage Profile of Coupled Noise”

Driven Line

Un-driven Line “victim”

Driver

Zs

Zo

Zo

Zo

Near End

Far End

Take home message: Remember the shape!

Incident wave

Near end Crosstalk

Far end Crosstalk

FEXT (Far End Crosstalk)

• Is generally negative for PCBs • Minimal (almost negligible) for stripline

– Inductive and Capacitive components are opposite in sign and nearly equal in magnitude

• Is predictable in it’s shape

– Inverted spike with minimal duration – Increases in amplitude as the coupled

length increases

NEXT (Near End Crosstalk)

• Represents the greatest concern for PCB designs

• Is predictable in it’s shape – Continues to increase in amplitude

for the duration of the rise time

– Levels off, or saturates, after the rise duration

– Increases in pulse width as the coupled length increases

Reminder: We

typically use eye

diagrams to look at

time domain data for

both single ended and

differential signals

This allows us the

ability to view many

cycles and all

combinations of data

patterns

simultaneously

Crosstalk consumes margin on both Axis

Without active aggressors With active aggressors

Control Parallelism

It would be impossible to

achieve the densities

needed if we always took

the most pessimistic

approach

We need to filter the

“possible crosstalk” to

better identify “actual

crosstalk” which could

hinder functionality

Estimated Crosstalk

• Provides a conservative (aka pessimistic) status of “potential” crosstalk.

• Estimations are based on table values with limited granularity.

• Quick refresh due to the look-up mechanism, significantly faster than a simulated result.

• Can be used in both a preventative and verification methodology.

Estimated Crosstalk

• Provides an estimation based on data within the board

– A table is constructed utilizing a combination of data within the file and user defined preferences.

– Crosstalk for a selected net is then estimated by combining the worst case potential voltage injected on the victim by each neighboring aggressor.

– The accumulated voltage is compared against pre-defined thresholds to determine if a violation exists.

• Significantly faster than a crosstalk simulation

• Identifies areas of “potential crosstalk”

• Provides instant feedback as DRC’s and Constraint Manager Violations

XTALK DRC’s Thresholds Must be Set for Allegro PCB SI

Max XTALK (Cumulative from all aggressors)

Max PEAK XTALK (From any one aggressor)

Typical Noise Budget Values:

Max XTALK = 10% of IO Voltage Swing

(3.3V => 330mv)

(2.4V => 240mv)

Max PEAK XTALK = 5% of IO Voltage Swing

(3.3V => 165mv)

(2.4V => 120mv)

Defining Crosstalk Budget

Estimated Crosstalk – Table Construction

Multiple tables can

exist simultaneously

Tables can be stored

within the file and can

be imported and

exported

Granularity with

respect to impedance

and separation is

controlled at the time of

table construction.

For each combination, a simulation

occurs and the resulting

crosstalk per unit length and

saturation length is stored in the

table

Results are available as Constraint Manager values, Reports and DRC’s

Victim Aggressor 1 Aggressor 2

Aggressor A

Aggressor 3 Aggressor 4

Aggressor B Aggressor C

The waveform seen at the receiver is the sum of the signals. We combine the deliberate signal from the driver with all aberrant signals from each aggressor

Crosstalk has a cumulative effect

At every clock cycle, not every net is active (producing crosstalk), nor are they sensitive (susceptible to crosstalk).

Complex boards frequently share real estate between functional blocks.

Many nets are functional only during specific modes of operation and remain static during others. For Example: Programming signals Interrupts JTAG and test signals Configuration Lines

Estimated Crosstalk – Timing Windows

• Basic estimated crosstalk produces an overly pessimistic view of the noise on the victim net.

– An aggressor only induces noise on the victim when that aggressor is

changing states.

– Only during transition (the rise and fall duration) does each aggressor induce a voltage on it’s neighbors.

– The conservative nature of the Estimated Crosstalk methodology must assume every aggressor is switching simultaneously.

Refining the Pessimism…

• Crosstalk on a victim is only a problem if that noise is present at the receiver at the time the receiver is sampling (or reading) the signal.

• Remembering that the Estimated Crosstalk combines every potential aggressor, all neighbors are assumed to be switching at the exact time the receiver is sampling the signal.

Consideration of known timing relationships can radically reduce the number of aggressors

Reset Configuration

Signals

Other bussed nets

(only switching when victim is also switching)

Like false path reduction in timing simulation, we can refine the crosstalk estimates to be “design aware”

• Methods of Removing nets from the Crosstalk Estimate

– Ignoring outright

– Defining timing windows

• Active windows

• Sensitive windows

Accurately defining timing windows yields higher densities without risking crosstalk defects Knowledge of the logic function is a must.

• Constraint Manager provides the link for these control features via the schematic, board layout, and simulation tools

Estimated Crosstalk Uses pre-simulated transmission line models to estimate crosstalk during real time etch editing.

Reports and corner case studies can be used for a directed approach

to resolution. Without this, repeated iterations could result in massive

etch edits that move crosstalk from net to net with no significant

reduction.

Know what your fixing.....

• Attack the largest aggressors first ... May not be the signal with the greatest amount of coupled length (remember driver edge rate is a strong influence)

• Understand the limits... Reducing three inches of coupled length between signals that are four inches beyond the saturation length will not help NEXT amplitude.

• Work with the Logic Engineer to understand the timing windows... Don’t create harmful crosstalk fixing meaningless crosstalk.

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Timing

Dynamic / Static Timing Analysis

• Timing analysis is integral part of design flow.

• Many other things can be compromised but not timing!

• Timing analysis can be static or dynamic.

– Dynamic timing analysis verifies functionality of the design by

applying input vectors and checking for correct output vectors.

– Static Timing Analysis checks static delay requirements of the

circuit without any input or output vectors.

Combinational / Sequential

• Digital System Design circuit can be characterized as a 'Combinational circuit' or a 'Sequential Circuit' and while calculating for Timing we will have to first identify what type of circuit is involved.

• If a circuit has only combinational devices (e.g.. gates like AND, OR etc and MUX(s))and no Memory elements then it is a Combinational circuit. If the circuit has memory elements such as Flip Flops, Registers, Counters, or other state devices then it is a Sequential Circuit. Synchronous sequential circuits will also have a clearly labeled clock input.

• Static Timing Analysis (or simply STA) is a method of

computing the expected timing of a digital circuit

STA involves three main steps:

1. Design is broken down into sets of timing paths.

2. Delay of each path is calculated.

3. Path delays are checked to see if timing constraints have been

met.

Definitions

• The critical path is defined as the path between an input and an output with the maximum delay. Once the circuit timing has been computed by one of the techniques below, the critical path can easily found by using a traceback method.

• The arrival time of a signal is the time elapsed for a signal to arrive at a certain point. The reference, or time 0.0, is often taken as the arrival time of a clock signal. To calculate the arrival time, delay calculation of all the component of the path will be required. Arrival times, and indeed almost all times in timing analysis, are normally kept as a pair of values - the earliest possible time at which a signal can change, and the latest.

• The required time. This is the latest time at which a signal can arrive without making the clock cycle longer than desired. The computation of the required time proceeds as follows. At each primary output, the required times for rise/fall are set according to the specifications provided to the circuit. Next, a backward topological traversal is carried out, processing each gate when the required times at all of its fanouts are known.

• The slack associated with each connection is the difference between the required time and the arrival time. A positive slack s at a node implies that the arrival time at that node may be increased by s without affecting the overall delay of the circuit. Conversely, negative slack implies that a path is too slow, and the path must sped up (or the reference signal delayed) if the whole circuit is to work at the desired speed.

Basic Timing

Setup time is the minimum amount

of time the data signal should be

held steady before the clock event

Hold time is the minimum amount

of time the data signal should be

held steady after the clock event

Fundamental timing issues

The data signal must arrive and stabilize at the receiver for a sufficient time prior to the clock event.

The data signal must remain stable at the receiver for a sufficient time following the clock event to allow the Read or Write operation to complete.

from SI Waveform to Timing Data

Start with simulated waveform…

For the purpose of timing, we are only

concerned with the time when a signal

is guaranteed to be either HI or LO

By extending these reference lines, we

define both the earliest and latest time

for this transition

This signal will switch from HI to LO no

sooner than 8 and no later than 12

units of time as shown

Latest

transition

Earliest

transition

Simulated Waveform

Four measurements

are need

RISINGand FALLING

EARLIEST POSSIBLE

(First Switch Delay)

LATEST POSSIBLE

(Final Settle Delay)

Types of Paths for Timing analysis:

• Data Path

• Clock Path

• Clock Gating Path

• Asynchronous Path

Common Clock

Strobe Signal

Data Signal

Like any timing relationship, we must account for variation.

TVB TVA

TVB TVA S

S = Skew

Source

Synchronous

TVB S TVA S

(TVB + Skew_neg) (Skew_pos + TVA)

Bit Period

BP-offset Offset

TVB S TVA S

Setup

When Skew_neg = 0, then TVB = Offset

When Skew_neg <> 0, then TVB = Offset – Skew_neg

Hold

When Skew_pos = 0, then TVA = BP - Offset

When Skew_pos <> 0, then TVA = BP - Offset – Skew_pos

Derating

Serial Link Signal (+)

Signal (-)


Reminder: We

typically use eye

diagrams to look at

time domain data for

both single ended and

differential signals

This allows us the

ability to view many

cycles and all

combinations of data

patterns

simultaneously

Measurement

Signal Integrity / Timing Relationship

What is available after the SI simulation?

Loop Analysis / System Performance

Timing Diagrams

Timing diagrams are graphical representations, they

inherently describe relationships between pairs of events

in the timing chronology.

• An event is represented as an edge in the diagram,

a transition from one state (or logic level) to another for a

specific signal (waveform).

• The relationship between two events consists of

specifying minimum () and/or maximum () times of

separation.

• Low level to supply voltage

• Transition Low -> High

• Unstable data / Differential Crossing

• Data Switching

• High Impedance

Timing Diagram State Condition

Timing Diagram Relationships

Grouped Signals

A bus is a multi-bit signal.

The timing diagram supports 3 types of buses plus a differential signal

• · Virtual Bus is a single signal defined as multiple bits. This is the most common and easiest to work with because all of the normal signal editing techniques work on it.

• · Group Bus displays the aggregate values of its member signals. This is handy way to manage lots of single bit signals that have been imported from other sources.

• · Simulated Bus is a simulated signal defined as a concatenation of it member signals. This is primarily designed for the testbench products so that both a member signal and the whole bus can be passed to models as needed.

• · Differential Signals are two-bit group buses that display a superimposed image of the member signal waveforms.

Timing Budgets


Orange: Account for Setup and hold

(This comes directly from the memory manufacturer’s datasheet)

.

Green: Routing skews in package and PCB

Purple: Contributions from controller

(This includes control logic delay, skew, jitter, and phase offset)

All you have left is the BLUE.

(It must capture all remaining uncertainties)

(crosstalk, impedance mismatch, termination, losses)

tcycle= tco+ tfinalsettling+ tsetup+ tskew+ tjitter +tSSO+ tISI

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