N- and P-Channel 20 V (D-S) MOSFET · Package PowerPAK SO-8 Lead (Pb)-free and halogen-free...
Transcript of N- and P-Channel 20 V (D-S) MOSFET · Package PowerPAK SO-8 Lead (Pb)-free and halogen-free...
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 1 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
N- and P-Channel 20 V (D-S) MOSFETFEATURES• TrenchFET® power MOSFETs
• Thermally enhanced PowerPAK®
• 100 % Rg tested
• Material categorization:for definitions of compliance please seewww.vishay.com/doc?99912
APPLICATIONS• DC/DC converters
• Synchronous buck converter
• Synchronous rectifier
• Load switch
• Motor drive switch
Notesa. Based on silicon capability only.b. Surface mounted on 1" x 1" FR4 board.c. t = 10 s.d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is notrequired to ensure adequate bottom side solder interconnection.
e. Rework conditions: Manual soldering with a soldering iron is not recommended for leadless components.f. Maximum under steady state conditions is 80 °C/W.
PRODUCT SUMMARYN-CHANNEL P-CHANNEL
VDS (V) 20 -20
RDS(on) () at VGS = ± 4.5 V 0.0150 0.0280
RDS(on) () at VGS = ± 2.5 V 0.0195 0.0430
Qg typ. (nC) 8.5 16
ID (A) a, b 12 9
Configuration N- and p-pair
PowerPAK® SO-8 Dual
Top View
1
6.15 mm
5.15 mm
Bottom View
4G2
4
1S12
G13S2
D1
8D2
6
D1
7D2
5
N-Channel MOSFET
G1
D1
S1
S2
G2
D2
P-Channel MOSFET
ORDERING INFORMATIONPackage PowerPAK SO-8Lead (Pb)-free and halogen-free Si7540ADP-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER SYMBOLN-CHANNEL P-CHANNEL
UNIT10 s STEADY 10 s STEADY
Drain-source voltage VDS 20 -20V
Gate-source voltage VGS ± 12
Continuous drain current (TJ = 150 °C) a, b TA = 25 °CID
12 8 -9 -6.1
ATA = 70 °C 9.8 6.5 -7.3 -4.9
Pulsed drain current IDM 35 -25Continuous source current (diode conduction) b IS 2.9 1.3 -2.9 -1.3
Maximum power dissipation bTA = 25 °C
PD3.5 1.6 3.5 1.6
WTA = 70 °C 2.3 1 2.3 1
Operating junction and storage temperature range TJ, Tstg -55 to +150°C
Soldering recommendations (peak temperature) d, e 260
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOLN-CHANNEL P-CHANNEL
UNITTYP. MAX. TYP. MAX.
Maximum junction-to-ambient b, f t 10 s RthJA 25 35 25 35°C/W
Maximum junction-to-case (drain) Steady state RthJC 4.6 6 4.8 6.3
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 2 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX UNIT
Static
Drain-source breakdown voltage VDSVGS = 0 V, ID = 250 μA N-Ch 20 - -
VVGS = 0 V, ID = -250 μA P-Ch -20 - -
VDS temperature coefficient VDS/TJID = 250 μA N-Ch - 17 -
mV/°CID = -250 μA P-Ch - -11 -
VGS(th) temperature coefficient VGS(th)/TJID = 250 μA N-Ch - -3.7 -
ID = -250 μA P-Ch - 5.5 -
Gate threshold voltage VGS(th) VDS = VGS, ID = 250 μA N-Ch 0.6 - 1.4
VVDS = VGS, ID = -250 μA P-Ch -0.6 - -1.4
Gate-body leakage IGSS VDS = 0 V, VGS = ± 12 V N-Ch - - ± 100
nAP-Ch - - ± 100
Zero gate voltage drain current IDSS
VDS = 20 V, VGS = 0 V N-Ch - - 1
μAVDS = -20 V, VGS = 0 V P-Ch - - -1
VDS = 20 V, VGS = 0 V, TJ = 55 °C N-Ch - - 10
VDS = -20 V, VGS = 0 V, TJ = 55 °C P-Ch - - -10
On-state drain current b ID(on) VDS 5 V, VGS = 4.5 V N-Ch 20 - -
AVDS -5 V, VGS = -4.5 V P-Ch -20 - -
Drain-source on-state resistance b RDS(on)
VGS = 4.5 V, ID = 12 A N-Ch - 0.0115 0.0150
VGS = -4.5 V, ID = -9 A P-Ch - 0.0220 0.0280
VGS = 2.5 V, ID = 9 A N-Ch - 0.0150 0.0195
VGS = -2.5 V, ID = -6 A P-Ch - 0.0330 0.0430
Forward transconductance b gfs VDS = 10 V, ID = 12 A N-Ch - 55 -
SVDS = -10 V, ID = -9 A P-Ch - 24 -
Dynamic a
Input capacitance Ciss
N-channelVDS = 10 V, VGS = 0 V, f = 1 MHz
P-channelVDS = -10 V, VGS = 0 V, f = 1 MHz
N-Ch - 915 -
pF
P-Ch - 1310 -
Output capacitance CossN-Ch - 235 -
P-Ch - 310 -
Reverse transfer capacitance Crss N-Ch - 110 -
P-Ch - 270 -
Total gate charge Qg
VDS = 10 V, VGS = 10 V, ID = 12 A N-Ch - 18 27
nC
VDS = -10 V, VGS = -10 V, ID = -9 A P-Ch - 32 48
N-channelVDS = 10 V, VGS = 4.5 V, ID = 12 A
P-channelVDS = -10 V, VGS = -4.5 V, ID = -9 A
N-Ch - 8.5 13
P-Ch - 16 24
Gate-source charge Qgs N-Ch - 1.8 -
P-Ch - 2.3 -
Gate-drain charge Qgd N-Ch - 2.2 -
P-Ch - 6 -
Gate resistance Rg f = 1 MHzN-Ch 0.6 3.2 6.4
P-Ch 0.2 1 2
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 3 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notesa. Guaranteed by design, not subject to production testing.b. Pulse test; pulse width 300 μs, duty cycle 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.
Dynamic a
Turn-on delay time td(on)
N-channelVDD = 10 V, RL = 2
ID 5 A, VGEN = 4.5 V, Rg = 1
P-channelVDD = -10 V, RL = 2
ID -5 A, VGEN = -4.5 V, Rg = 1
N-Ch - 12 25
ns
P-Ch - 15 30
Rise time trN-Ch - 45 90
P-Ch - 50 100
Turn-off delay time td(off) N-Ch - 22 45
P-Ch - 30 60
Fall time tfN-Ch - 12 25
P-Ch - 11 20
Turn-on delay time td(on)
N-channelVDD = 10 V, RL = 2
ID 5 A, VGEN = 10 V, Rg = 1
P-channelVDD = -10 V, RL = 2
ID -5 A, VGEN = -10 V, Rg = 1
N-Ch - 6 15
P-Ch - 10 15
Rise time trN-Ch - 21 40
P-Ch - 23 45
Turn-off delay time td(off) N-Ch - 20 40
P-Ch - 26 50
Fall time tfN-Ch - 10 20
P-Ch - 10 20
Drain-Source Body Diode Characteristics
Continuous source-drain diode current IS TA = 25 °C N-Ch - - 2.9
AP-Ch - - -2.9
Pulse diode forward current (t = 100 μs) ISMN-Ch - - 35
P-Ch - - -25
Body diode voltage VSDIS = 2.9 A, VGS = 0 V N-Ch - 0.8 1.2
VIS = -2.9 A, VGS = 0 V P-Ch - -0.81 -1.2
Body diode reverse recovery time trr
N-channelIF = 5 A, dI//dt = 100 A/μs, TJ = 25 °C
P-channel IF = -5 A, dI/dt = -100 A/μs, TJ = 25 °C
N-Ch - 20 40ns
P-Ch - 30 60
Body diode reverse recovery charge QrrN-Ch - 10 20
nCP-Ch - 20 40
Reverse recovery fall time taN-Ch - 8.5 -
nsP-Ch - 18 -
Reverse recovery rise time tbN-Ch - 11.5 -
P-Ch - 12 -
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX UNIT
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 4 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0
I D -
Dra
in C
urre
nt (A
)
VDS - Drain-to-Source Voltage (V)
VGS = 2 V
VGS = 5 V thru 2.5 V
VGS = 1.5 V
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0 5 10 15 20 25 30 35
RD
S(o
n) -
On-
Res
ista
nce
(Ω)
ID - Drain Current (A)
VGS = 2.5 V
VGS = 4.5 V
0
2
4
6
8
10
0 4 8 12 16 20
VG
S -
Gat
e-to
-Sou
rce
Vol
tage
(V)
Qg - Total Gate Charge (nC)
VDS = 16 V
VDS = 5 V
VDS = 10 V ID = 12 A
0
4
8
12
16
20
0.0 0.4 0.8 1.2 1.6 2.0
I D -
Dra
in C
urre
nt (
A)
VGS - Gate-to-Source Voltage (V)
TC = 25 °C
TC = 125 °C
TC = - 55 °C
0
300
600
900
1200
1500
0 4 8 12 16 20
C -
Cap
acita
nce
(pF)
VDS - Drain-to-Source Voltage (V)
Ciss
Coss
Crss
0.6
0.8
1.0
1.2
1.4
1.6
- 50 - 25 0 25 50 75 100 125 150
RD
S(o
n) -
On-
Res
ista
nce
(Nor
mal
ized
)
TJ - Junction Temperature (°C)
ID = 12 A VGS = 4.5 V, 2.5 V
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 5 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
Threshold Voltage
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power (Junction-to-Ambient)
Safe Operating Area, Junction-to-Ambient
0.1
1
10
100
0.0 0.2 0.4 0.6 0.8 1.0 1.2
I S -
Sou
rce
Cur
rent
(A)
VSD - Source-to-Drain Voltage (V)
TJ = 150 °C
TJ = 25 °C
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
- 50 - 25 0 25 50 75 100 125 150
VG
S(th
) (V
)
TJ - Temperature (°C)
ID = 250 μA
0.00
0.01
0.02
0.03
0.04
0 1 2 3 4 5
RD
S(o
n) -
On-
Res
ista
nce
(Ω)
VGS - Gate-to-Source Voltage (V)
TJ = 125 °C
TJ = 25 °C
ID = 12 A
0
10
20
30
40
0.001 0.01 0.1 1 10 100 1000
Pow
er (W
)
Time (s)
0.01
0.1
1
10
100
0.1 1 10 100
I D -
Dra
in C
urre
nt (
A)
VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified
10 s
Limited by IDM
Limited by IDon
100 ms
Limited by RDS(on)*
1 ms
TA = 25 °C
BVDSS Limited
10 ms
100 μs
1 s
DC
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 6 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Current Derating a Power Derating
Notea. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below thepackage limit.
0
5
10
15
20
25
30
35
0 25 50 75 100 125 150
I D -
Dra
in C
urre
nt (
A)
TC - Case Temperature (°C)
Package Limited
0
5
10
15
20
25
25 50 75 100 125 150
Pow
er (W
)
TC - Case Temperature (°C)
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 7 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Thermal Transient Impedance, Junction-to-Case
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10 100 1000
Nor
mal
ized
Eff
ectiv
e Tr
ansi
ent
Ther
mal
Imp
edan
ce
Square Wave Pulse Duration (s)
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
Single Pulse
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 80 °C/W
3. TJM - TA = PDMZthJA(t)
t1t2
t1t2
Notes:
4. Surface Mounted
PDM
0.1
1
0.0001 0.001 0.01 0.1
Nor
mal
ized
Eff
ectiv
e Tr
ansi
ent
Ther
mal
Imp
edan
ce
Square Wave Pulse Duration (s)
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
Single Pulse
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 8 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
5
10
15
20
25
0.0 0.5 1.0 1.5 2.0 2.5 3.0
I D -
Dra
in C
urre
nt (A
)
VDS - Drain-to-Source Voltage (V)
VGS = 2 V
VGS = 2.5 V
VGS = 5 V thru 3 V
VGS = 1.5 V
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0 5 10 15 20 25
RD
S(o
n) -
On-
Res
ista
nce
(Ω)
ID - Drain Current (A)
VGS = 2.5 V
VGS = 4.5 V
0
2
4
6
8
10
0 5 10 15 20 25 30 35
VG
S -
Gat
e-to
-Sou
rce
Vol
tage
(V)
Qg - Total Gate Charge (nC)
VDS = 16 V
VDS = 5 V
VDS = 10 V ID = 9 A
0
3
6
9
12
15
0.0 0.4 0.8 1.2 1.6 2.0
I D -
Dra
in C
urre
nt (
A)
VGS - Gate-to-Source Voltage (V)
TC = 25 °C
TC = 125 °C
TC = - 55 °C
0
500
1000
1500
2000
2500
0 4 8 12 16 20
C -
Cap
acita
nce
(pF)
VDS - Drain-to-Source Voltage (V)
Ciss
Coss
Crss
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
- 50 - 25 0 25 50 75 100 125 150
RD
S(o
n) -
On-
Res
ista
nce
(Nor
mal
ized
)
TJ - Junction Temperature (°C)
ID = 9 A VGS = 4.5 V, 2.5 V
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 9 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
Threshold Voltage
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
Safe Operating Area, Junction-to-Ambient
0.1
1
10
100
0.0 0.2 0.4 0.6 0.8 1.0 1.2
I S -
Sou
rce
Cur
rent
(A)
VSD - Source-to-Drain Voltage (V)
TJ = 150 °C
TJ = 25 °C
0.5
0.6
0.7
0.8
0.9
1.0
1.1
- 50 - 25 0 25 50 75 100 125 150
VG
S(th
) (V
)
TJ - Temperature (°C)
ID = 250 μA
0.00
0.02
0.04
0.06
0.08
0.10
0 1 2 3 4 5
RD
S(o
n) -
On-
Res
ista
nce
(Ω)
VGS - Gate-to-Source Voltage (V)
TJ = 125 °C
TJ = 25 °C
ID = 9 A
0
10
20
30
40
0.001 0.01 0.1 1 10 100 1000
Pow
er (W
)
Time (s)
0.01
0.1
1
10
100
0.1 1 10 100
I D -
Dra
in C
urre
nt (
A)
VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified
10 s
Limited by IDM
Limited by IDon
100 ms
Limited by RDS(on)*
1 ms
TA = 25 °C
BVDSS Limited
10 ms
100 μs
1 s
DC
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 10 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Current Derating a Power Derating
Notea. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below thepackage limit.
0
5
10
15
20
25
0 25 50 75 100 125 150
I D -
Dra
in C
urre
nt (
A)
TC - Case Temperature (°C)
Package Limited
0
5
10
15
20
25 50 75 100 125 150
Pow
er (W
)
TC - Case Temperature (°C)
Si7540ADPwww.vishay.com Vishay Siliconix
S16-2274-Rev. C, 14-Nov-16 11 Document Number: 62951For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see www.vishay.com/ppg?62951.
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10 100 1000
Nor
mal
ized
Eff
ectiv
e Tr
ansi
ent
Ther
mal
Imp
edan
ce
Square Wave Pulse Duration (s)
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
Single Pulse
Notes:
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 80 °C/W
3. TJM - TA = PDMZthJA (t)
t1
t2
4. Surface Mounted
t1
PDM
t2
0.1
1
0.0001 0.001 0.01 0.1
Nor
mal
ized
Eff
ectiv
e Tr
ansi
ent
Ther
mal
Imp
edan
ce
Square Wave Pulse Duration (s)
Duty Cycle = 0.5
0.2
0.1
0.05 0.02
Single Pulse
Package Informationwww.vishay.com Vishay Siliconix
Revison: 13-Feb-17 1 Document Number: 71655
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PowerPAK® SO-8, (Single/Dual)
DIM.MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044A1 - 0.05 0 - 0.002b 0.33 0.41 0.51 0.013 0.016 0.020c 0.23 0.28 0.33 0.009 0.011 0.013D 5.05 5.15 5.26 0.199 0.203 0.207
D1 4.80 4.90 5.00 0.189 0.193 0.197D2 3.56 3.76 3.91 0.140 0.148 0.154D3 1.32 1.50 1.68 0.052 0.059 0.066D4 0.57 typ. 0.0225 typ.D5 3.98 typ. 0.157 typ.E 6.05 6.15 6.25 0.238 0.242 0.246
E1 5.79 5.89 5.99 0.228 0.232 0.236E2 3.48 3.66 3.84 0.137 0.144 0.151E3 3.68 3.78 3.91 0.145 0.149 0.154 E4 0.75 typ. 0.030 typ.e 1.27 BSC 0.050 BSCK 1.27 typ. 0.050 typ.
K1 0.56 - - 0.022 - -H 0.51 0.61 0.71 0.020 0.024 0.028L 0.51 0.61 0.71 0.020 0.024 0.028
L1 0.06 0.13 0.20 0.002 0.005 0.008 0° - 12° 0° - 12°W 0.15 0.25 0.36 0.006 0.010 0.014M 0.125 typ. 0.005 typ.
ECN: S17-0173-Rev. L, 13-Feb-17DWG: 5881
3. Dimensions exclusive of mold flash and cutting burrs.
1.Notes
2Inch will govern.Dimensions exclusive of mold gate burrs.
Backside View of Single Pad
Backside View of Dual Pad
Detail Z
D
D1
D2
c
θA
θ
E1θ
D1
E2
D2e
b
1
2
3
4
H
4
3
2
1
θ1
2
3
4 b
L
D2
D3
(2x)
Z
A1
K1
K
D
E
W
L1
D5
E3
D4
E4
E4K
LHE2
D4
D5
M
E3
2
2
V I S H A Y S I L I C O N I X
Power MOSFETs Application Note AN821
PowerPAK® SO-8 Mounting and Thermal Considerations
AP
PL
ICA
TIO
N N
OT
E
Revision: 16-Mai-13 1 Document Number: 71622
For technical questions, contact: [email protected] DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com
by Wharton McDanielMOSFETs for switching applications are now available withdie on resistances around 1 m and with the capability tohandle 85 A. While these die capabilities represent a majoradvance over what was available just a few years ago, it isimportant for power MOSFET packaging technology to keeppace. It should be obvious that degradation of a highperformance die by the package is undesirable. PowerPAKis a new package technology that addresses these issues.In this application note, PowerPAK’s construction isdescribed. Following this mounting information is presentedincluding land patterns and soldering profiles for maximumreliability. Finally, thermal and electrical performance isdiscussed.
THE PowerPAK PACKAGEThe PowerPAK package was developed around the SO-8package (figure 1). The PowerPAK SO-8 utilizes the samefootprint and the same pin-outs as the standard SO-8. Thisallows PowerPAK to be substituted directly for a standardSO-8 package. Being a leadless package, PowerPAK SO-8utilizes the entire SO-8 footprint, freeing space normallyoccupied by the leads, and thus allowing it to hold a largerdie than a standard SO-8. In fact, this larger die is slightlylarger than a full sized DPAK die. The bottom of the dieattach pad is exposed for the purpose of providing a direct,low resistance thermal path to the substrate the device ismounted on. Finally, the package height is lower than thestandard SO-8, making it an excellent choice forapplications with space constraints.
Fig. 1 PowerPAK 1212 Devices
PowerPAK SO-8 SINGLE MOUNTINGThe PowerPAK single is simple to use. The pin arrangement(drain, source, gate pins) and the pin dimensions are thesame as standard SO-8 devices (see figure 2). Therefore, thePowerPAK connection pads match directly to those of theSO-8. The only difference is the extended drain connectionarea. To take immediate advantage of the PowerPAK SO-8single devices, they can be mounted to existing SO-8 landpatterns.
Fig. 2
The minimum land pattern recommended to take fulladvantage of the PowerPAK thermal performance seeApplication Note 826, Recommended Minimum PadPatterns With Outline Drawing Access for Vishay SiliconixMOSFETs. Click on the PowerPAK SO-8 single in the indexof this document.
In this figure, the drain land pattern is given to make fullcontact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and topof the drawn pattern. This extension will serve to increasethe heat dissipation by decreasing the thermal resistancefrom the foot of the PowerPAK to the PC board andtherefore to the ambient. Note that increasing the drain landarea beyond a certain point will yield little decreasein foot-to-board and foot-to-ambient thermal resistance.Under specific conditions of board configuration, copperweight and layer stack, experiments have found thatmore than about 0.25 in2 to 0.5 in2 of additional copper(in addition to the drain land) will yield little improvement inthermal performance.
Standard SO-8 PowerPAK SO-8
PowerPAK® SO-8 Mounting and Thermal Considerations
AP
PL
ICA
TIO
N N
OT
EApplication Note AN821
www.vishay.com Vishay Siliconix
Revision: 16-Mai-13 2 Document Number: 71622
For technical questions, contact: [email protected] DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PowerPAK SO-8 DUALThe pin arrangement (drain, source, gate pins) and the pindimensions of the PowerPAK SO-8 dual are the same asstandard SO-8 dual devices. Therefore, the PowerPAKdevice connection pads match directly to those of the SO-8.As in the single-channel package, the only exception is theextended drain connection area. Manufacturers can likewisetake immediate advantage of the PowerPAK SO-8 dualdevices by mounting them to existing SO-8 dual landpatterns.
To take the advantage of the dual PowerPAK SO-8’sthermal performance, the minimum recommended landpattern can be found in Application Note 826,Recommended Minimum Pad Patterns With OutlineDrawing Access for Vishay Siliconix MOSFETs. Click on thePowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. Thismatches the spacing of the two drain pads on thePowerPAK SO-8 dual package.
REFLOW SOLDERINGVishay Siliconix surface-mount packages meet solder reflowreliability requirements. Devices are subjected to solderreflow as a test preconditioning and are thenreliability-tested using temperature cycle, bias humidity,HAST, or pressure pot. The solder reflow temperature profileused, and the temperatures and time duration, are shown infigures 3 and 4.
For the lead (Pb)-free solder profile, seewww.vishay.com/doc?73257.
Fig. 3 Solder Reflow Temperature Profile
Fig. 4 Solder Reflow Temperatures and Time Durations
Ramp-Up Rate + 3 °C /s max.
Temperature at 150 - 200 °C 120 s max.
Temperature Above 217 °C 60 - 150 s
Maximum Temperature 255 + 5/- 0 °C
Time at MaximumTemperature 30 s
Ramp-Down Rate + 6 °C/s max.
260 °C
3 °C(max) 6 ° C/s (max.)
30 s
217 °C
150 s (max.)
Reflow Zone 60 s (min.)
Pre-Heating Zone
150 - 200 °C
Maximum peak temperature at 240 °C is allowed.
PowerPAK® SO-8 Mounting and Thermal Considerations
AP
PL
ICA
TIO
N N
OT
EApplication Note AN821
www.vishay.com Vishay Siliconix
Revision: 16-Mai-13 3 Document Number: 71622
For technical questions, contact: [email protected] DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performanceis the junction-to-case thermal resistance, RthJC, or thejunction-to-foot thermal resistance, RthJF This parameter ismeasured for the device mounted to an infinite heat sink andis therefore a characterization of the device only, in otherwords, independent of the properties of the object to whichthe device is mounted. Table 1 shows a comparison ofthe DPAK, PowerPAK SO-8, and standard SO-8. ThePowerPAK has thermal performance equivalent to theDPAK, while having an order of magnitude better thermalperformance over the SO-8.
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8can be mounted on an existing standard SO-8 pad pattern.The question then arises as to the thermal performanceof the PowerPAK device under these conditions. Acharacterization was made comparing a standard SO-8 anda PowerPAK device on a board with a trough cut outunderneath the PowerPAK drain pad. This configurationrestricted the heat flow to the SO-8 land pads. The resultsare shown in figure 5.
Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path
Because of the presence of the trough, this result suggestsa minimum performance improvement of 10 °C/W by usinga PowerPAK SO-8 in a standard SO-8 PC board mount.
The only concern when mounting a PowerPAK on astandard SO-8 pad pattern is that there should be no tracesrunning between the body of the MOSFET. Where thestandard SO-8 body is spaced away from the pc board,allowing traces to run underneath, the PowerPAK sitsdirectly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading copper, tothe drain pad to aid in conducting heat from a device. It ishelpful to have some information about the thermalperformance for a given area of spreading copper.
Figure 6 shows the thermal resistance of a PowerPAK SO-8device mounted on a 2-in. 2-in., four-layer FR-4 PC board.The two internal layers and the backside layer are solidcopper. The internal layers were chosen as solid copper tomodel the large power and ground planes common in manyapplications. The top layer was cut back to a smaller areaand at each step junction-to-ambient thermal resistancemeasurements were taken. The results indicate that an areaabove 0.3 to 0.4 square inches of spreading copper gives noadditional thermal performance improvement. Asubsequent experiment was run where the copper on theback-side was reduced, first to 50 % in stripes to mimiccircuit traces, and then totally removed. No significant effectwas observed.
Fig. 6 Spreading Copper Junction-to-Ambient Performance
TABLE 1 - DPAK AND POWERPAK SO-8EQUIVALENT STEADY STATE PERFORMANCE
DPAK PowerPAKSO-8
StandardSO-8
Thermal Resistance RthJC
1.2 °C/W 1 °C/W 16 °C/W
Si4874DY vs. Si7446DP PPAK on a 4-Layer BoardSO-8 Pattern, Trough Under Drain
Pulse Duration (sec)
)sttaw/
C( e cnadepmI
0.0001
0
1
50
60
10
100000.01
40
20
Si4874DY
Si7446DP
100
30
Rth vs. Spreading Copper(0 %, 50 %, 100 % Back Copper)
Spreading Copper (sq in)
)sttaw/
C( ecnadepmI
0.00
56
51
46
41
36
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
0 %
50 %
100 %
PowerPAK® SO-8 Mounting and Thermal Considerations
AP
PL
ICA
TIO
N N
OT
EApplication Note AN821
www.vishay.com Vishay Siliconix
Revision: 16-Mai-13 4 Document Number: 71622
For technical questions, contact: [email protected] DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SYSTEM AND ELECTRICAL IMPACT OFPowerPAK SO-8In any design, one must take into account the change inMOSFET RDS(on) with temperature (figure 7).
Fig. 7 MOSFET RDS(on) vs. Temperature
A MOSFET generates internal heat due to the currentpassing through the channel. This self-heating raises thejunction temperature of the device above that of the PCboard to which it is mounted, causing increased powerdissipation in the device. A major source of this problem liesin the large values of the junction-to-foot thermal resistanceof the SO-8 package.
PowerPAK SO-8 minimizes the junction-to-board thermalresistance to where the MOSFET die temperature is veryclose to the temperature of the PC board. Consider twodevices mounted on a PC board heated to 105 °C by othercomponents on the board (figure 8).
Fig. 8 Temperature of Devices on a PC Board
Suppose each device is dissipating 2.7 W. Using thejunction-to-foot thermal resistance characteristics of thePowerPAK SO-8 and the standard SO-8, the dietemperature is determined to be 107 °C for the PowerPAK(and for DPAK) and 148 °C for the standard SO-8. This is a2 °C rise above the board temperature for the PowerPAKand a 43 °C rise for the standard SO-8. Referring to figure 7,a 2 °C difference has minimal effect on RDS(on) whereas a43 °C difference has a significant effect on RDS(on).
Minimizing the thermal rise above the board temperature byusing PowerPAK has not only eased the thermal design butit has allowed the device to run cooler, keep rDS(on) low, andpermits the device to handle more current than the sameMOSFET die in the standard SO-8 package.
CONCLUSIONSPowerPAK SO-8 has been shown to have the same thermalperformance as the DPAK package while having the samefootprint as the standard SO-8 package. The PowerPAKSO-8 can hold larger die approximately equal in size to themaximum that the DPAK can accommodate implying nosacrifice in performance because of package limitations.
Recommended PowerPAK SO-8 land patterns are providedto aid in PC board layout for designs using this newpackage.
Thermal considerations have indicated that significantadvantages can be gained by using PowerPAK SO-8devices in designs where the PC board was laid out forthe standard SO-8. Applications experimental data gavethermal performance data showing minimum andtypical thermal performance in a SO-8 environment, plusinformation on the optimum thermal performanceobtainable including spreading copper. This furtheremphasized the DPAK equivalency.
PowerPAK SO-8 therefore has the desired small sizecharacteristics of the SO-8 combined with the attractivethermal characteristics of the DPAK package.
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125 150
V GS = 10 V I D = 23 A
On-Resistance vs. Junction Temperature
T J - Junction Temperature (°C)
)dezilamro
N(( ecnatsise
R-nO -
R)no(
SD
)
0.8 °C/W
107 °C
PowerPAK SO-8
16 C/W
148 °C
Standard SO-8
PC Board at 105 °C
Application Note 826Vishay Siliconix
www.vishay.com Document Number: 7260016 Revision: 21-Jan-08
A
PP
LIC
AT
ION
NO
TE
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Dual
0.17
4
(4.4
2)
Recommended Minimum PadsDimensions in Inches/(mm)
0.260
(6.61)
0.024(0.61)
0.06
5
(1.6
5)
0.150
(3.81)
0.05
0
(1.2
7)
0.050
(1.27)
0.032
(0.82)
0.040
(1.02)
0.026(0.66) 0.
154
(3.9
1)
0.06
5
(1.6
5)0.024(0.61)
Return to IndexReturn to Index
Legal Disclaimer Noticewww.vishay.com Vishay
Revision: 01-Jan-2021 1 Document Number: 91000
Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED