Myon II - support.keith-koep.com · The Myon II is powered by NXP i.MX 8M Mini processor, which is...

Managing Director:

Volker Keith & Dipl.-Phys. Ing. Luitger Koep

Rev.1.5

Technical modifications reserved,

errors excepted

www.keith-koep.com

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42109 Wuppertal

Tel. +49 (202) 25253-0

Fax +49 (202) 25253-33

Myon II

Documentation version 1.2

Introduction

The Myon II is the second module based on the Myon SOM standard.

The Myon II is powered by NXP i.MX 8M Mini processor, which is designed to meet the latest

market requirements of connected streaming audio/video devices, scanning/imaging devices and

various devices demanding high-performance and low-power.

The i.MX 8M Mini family of processors features advanced implementation of a quad ARM®

Cortex®-A53 core, which operates at speeds of up to 1.8GHz (consumer version) and 1.6GHz

(industrial version). A general purpose Cortex®-M4 core processor is for low-power processing. A

32-bit LPDDR4 is used for memory.

There are a number of i.MX 8M Mini interfaces for connecting peripherals, such as displays,

cameras, GPS and sensors, which are extended by module components such as a stereo, hi-fi

quality audio-codec.

Additional peripherals may be added through two 100pin Hirose DF40 connectors. The pinning of

both connectors is to a large extent compatible to Myon I.

The main differences are:

+ an additional USB2.0 port

+ a second SDIO card interface

+ PCIE

+ RGMII Gbit Ethernet interface

+ SPDIF and Stereo Line-In

+ a mounting option for +3V3 or 1.8V IO-voltage.

It misses the following Myon I features:

- Li-Ion Battery charger.

- second 2ch MIPI-Camera port.

- on-board wireless chipset.

Evaluation-Version

Version with LVDS Display interface, size 48,5 x 32,5 x 4.2 mm (size of 2 SD-Cards):

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Simplified Block Diagram of Myon II

Figure 0-1

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Features and Interfaces

Features

Processor:

NXP i.MX 8M ARM® Quad symmetric Cortex-A53 at up to 1.8GHz (consumer), 1.6GHz (industrial)

NXP i.MX 8M ARM® Cortex-M4

Memory:

1 or 2 GByte of 32-bit LPDDR4-3200. Higher densities are available on request.

Storage:

4 or 8 GByte eMMC. Higher densities are available on request.

Wireless:

No wireless option.

Please use the SDIO, PCIE or USB interface to connect a preferred wireless chipset externally.

Power:

PMIC to generate internal and external voltages.

Dimensions:

(Length x Width x Height): 48,5 x 32,5 x 4.2 mm

Overall height from your baseboard to the upper edge of the Myon II depend on the connector-

receptible used and is either 4.5 or 7 mm.

Interfaces / Signals accessible over extension connectors

– Power Supply through +5V or +3.3V or Battery

– Regulated 1.8V and 3.3V outputs

– Two USB2.0 OTG ports (USB Host or Slave)

– Two SD/SDIO Card Interfaces

– 8 IO-Ports configurable for different interfaces: GPIO, UART, SPI, I2C, I2S

– PCIE

– 1Gbit RGMII Ethernet interface

– Quad-SPI

– MIPI Camera (4ch) interface

– MIPI Display (4ch) or LVDS Display interface

– Stereo Headphone output

– Stereo Line-In

– 1W Speaker output

– SPDIF In and Out

– Microphone inputs

– \RESET_OUT, \RESET_IN, JTAG and other Control-Signals

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1 Pin-Description

The Myon II got two Hirose DF40C-100DP-0.4V pin-headers J70 and J71.

These can be mated with following receptibles:

DF40C-100DS-0.4V (1.5mm stack height)

DF40C-3.0-100DS-0.4V (3.0mm stack height)

All signals needed for operation are placed on the main connector J70.

J74: JTAG connector.

Figure 1-1: Connectors

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1.1 Pin-Description (Primary Function)

Pins not assigned to a signal are not connected on Myon II and are reserved for future use.

Do not connect.

(See next page for tables)

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J70: Main Connector

Signal Pin Pin Signal

VBAT 1 2 VBAT

VBAT 3 4 VBAT

VBAT 5 6 VBAT

VBAT 7 8 VBAT

n.c. 9 10 VDD_SPEAKER

n.c. 11 12 n.c.

GND 13 14 GND

GND 15 16 GND

VBUS 17 18 VBUS

VBUS 19 20 VBUS

VBUS 21 22 VBUS

VBUS 23 24 VBUS

USB1_VBUS 25 26 USB2_VBUS

USB1_DM 27 28 ONOFF

USB1_DP 29 30 RESET_IN_N

USB1_ID 31 32 RESET_OUT_N

GND 33 34 GND

GND_CFILT 35 36 GND

MIC2 37 38 JTAG_MODE

MIC_BIAS 39 40 BOOT_MODE_0

HEADPHONE_L 41 42 +3V3

HEADPHONE_R 43 44 +3V3

HEADPHONE_REF 45 46 VDD_1V8

HEADSET_DETECT 47 48 VDD_1V8

MIC1 49 50 VDD_ENET

MIC_BIAS1 51 52 VDD_IO

LINEIN_L 53 54 P3_MOSI_TXD

LINEIN_R 55 56 P3_MISO_RTS

SPEAKER_P 57 58 P3_CLK_RXD

SPEAKER_N 59 60 P3_CS_CTS

P1_TXD 61 62 P4_GPIO1

P1_RXD 63 64 P4_GPIO2

P1_RTS 65 66 P4_SCL

P1_CTS 67 68 P4_SDA

P2_TXD 69 70 DSI0_RESET

P2_RXD 71 72 DSI0_ENABLE

P2_RTS_SCL 73 74 BACKLIGHT_PWM

P2_CTS_SDA 75 76 BACKLIGHT_ENABLE

GND 77 78 GND

VDD_SDCARD_PWR 79 80 DSI0_DAT0_N / LVDS_TXN0

VDD_SDCARD_IO 81 82 DSI0_DAT0_P / LVDS_TXP0

SD2_CMD 83 84 DSI0_DAT1_N / LVDS_TXN1

SD2_CLK 85 86 DSI0_DAT1_P / LVDS_TXP1

SD2_DAT0 87 88 DSI0_DAT2_N / LVDS_TXN2

SD2_DAT1 89 90 DSI0_DAT2_P / LVDS_TXP2

SD2_DAT2 91 92 DSI0_DAT3_N / LVDS_TXN3

SD2_DAT3 93 94 DSI0_DAT3_P / LVDS_TXP3

SD2_CARDDETECT_N 95 96 DSI0_CLK_N / LVDS_CLKN

SD2_WRITEPROTECT 97 98 DSI0_CLK_P / LVDS_CLKP

GND 99 100 GND

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J71: Aux Connector

Signal Pin Pin Signal

BOOT_MODE_1 1 2 LED0_QSPIa_SCLK

CLKO1_USB2_PEN 3 4 LED1_QSPIa_DAT0

HDMI_INT_USB2_OC 5 6 KYPD0_QSPIa_DAT1

P5_MOSI_TXD 7 8 KYPD1_QSPIa_DAT2

P5_MISO_RTS 9 10 KYPD2_QSPIa_DAT3

P5_CLK_RXD 11 12 LED2_QSPIa_SS0

P5_CS_CTS 13 14 LED3

P6_GPIO1 15 16 LED4

P6_GPIO2 17 18 USB_HUB_RESET_N

P6_SCL 19 20 USB_SW_SEL

P6_SDA 21 22 USB1_PEN

I2S1_DAT0 23 24 USB1_OC

I2S1_DAT1 25 26 JTAG_TMS

I2S1_SCK 27 28 JTAG_TRST

I2S1_MCLK 29 30 JTAG_TCK

I2S1_WS 31 32 JTAG_TDO

I2S2_DAT0 33 34 JTAG_TDI

I2S2_DAT1 35 36 USB2_ID

I2S2_SCK 37 38 USB2_DP

I2S2_WS 39 40 USB2_DM

GND 41 42 GND

SD3_CMD 43 44 PCIE_RXN_P

SD3_CLK 45 46 PCIE_RXN_N

SD3_DAT0 47 48 PCIE_CLKREQ

SD3_DAT1 49 50 PCIE_WAKE

SD3_DAT2 51 52 PCIE_TXN_P

SD3_DAT3 53 54 PCIE_TXN_N

GND 55 56 GND

SPDIF_CLK 57 58 PCIE_REFCLK_P

SPDIF_IN 59 60 PCIE_REFCLK_N

SPDIF_OUT 61 62 DISPLAY_ENABLE

CAM_TORCH 63 64 POWERFAIL

CAM_FLASH 65 66 ENET_RESET

CAM_I2C_SCL 67 68 ENET_INT

CAM_I2C_SDA 69 70 ENET_MDC

CSI0_RESET 71 72 ENET_MDIO

CSI0_PWDN 73 74 ENET_TXCTL

CSI0_MCLK 75 76 ENET_TXC

GND 77 78 GND

CSI0_CLK_N 79 80 ENET_TD0

CSI0_CLK_P 81 82 ENET_TD1

CSI0_DAT0_N 83 84 ENET_TD2

CSI0_DAT0_P 85 86 ENET_TD3

CSI0_DAT1_N 87 88 ENET_RD0

CSI0_DAT1_P 89 90 ENET_RD1

CSI0_DAT2_N 91 92 ENET_RD2

CSI0_DAT2_P 93 94 ENET_RD3

CSI0_DAT3_N 95 96 ENET_RXCTL

CSI0_DAT3_P 97 98 ENET_RXC

GND 99 100 GND

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J74: JTAG Connector

This flex-cable-connector uses the Keith & Koep JTAG connector standard. An Adapter to Multi-ICE

pin-header is available.

Pin Signal

1 VDD_IO

2 GND

3 JTAG_TMS

4 JTAG_TRST_N

5 JTAG_TCK

6 JTAG_TDO

7 JTAG_TDI

8 JTAG_SRST_N

JTAG-pins are also routed to pins J71-26..34 of the Aux Connector.

1.2 Pin-Mux Information

Several pins are GPIOs which may be configured for different functions by software.

Please check with the processor datasheet for additional pin-mux information. Signals in [] are

mounting options. Contact Keith & Koep for details.

PIN Name Mux1 Mux2 Mux3 Mux4

J70-61 P1_TXD GPIO5_25 UART2_TXD

J70-63 P1_RXD GPIO5_24 UART2_RXD

J70-65 P1_RTS GPIO5_28 UART2_RTS UART4_RXD

J70-67 P1_CTS GPIO5_29 UART2_CTS UART4_TXD

J70-69 P2_TXD GPIO5_23 UART1_TXD SPI3_MOSI

J70-71 P2_RXD GPIO5_22 UART1_RXD SPI3_CLK

J70-73 P2_RTS_SCL GPIO5_26 UART1_RTS UART3_RXD [I2C4_SCL]

J70-75 P2_CTS_SDA GPIO5_27 UART1_CTS UART3_TXD [I2C4_SDA]

J70-54 P3_MOSI_TXD GPIO5_7 UART3_TXD SPI1_MOSI

J70-56 P3_MISO_RTS GPIO5_8 UART3_RTS SPI1_MISO

J70-58 P3_CLK_RXD GPIO5_6 UART3_RXD SPI1_CLK

J70-60 P3_CS_CTS GPIO5_9 UART3_CTS SPI1_CS

J70-62 P4_GPIO1 GPIO3_23 SAI5_RXD2_TCLK SAI5_TXD4_TSYNC

J70-64 P4_GPIO2 GPIO3_4 QSPI1b_SS1

J70-66 P4_SCL GPIO5_16 ENET_EVENT1_IN I2C2_SCL

J70-68 P4_SDA GPIO5_17 ENET_EVENT1_OUT I2C2_SDA

J71-7 P5_MOSI_TXD GPIO5_11 UART4_TXD SPI2_MOSI

J71-9 P5_MISO_RTS GPIO5_12 UART4_RTS SPI2_MISO

J71-11 P5_CLK_RXD GPIO5_10 UART4_RXD SPI2_CLK

J71-13 P5_CS_CTS GPIO5_13 UART4_CTS SPI2_CS

J71-15 P6_GPIO1 GPIO1_0 EXT_CLK1 [SPI2_MOSI]

J71-17 P6_GPIO2 GPIO1_13 PWM2 [SPI2_MISO]

J71-19 P6_SCL [SPI2_CLK] I2C3_SCL

J71-21 P6_SDA [SPI2_SS0] I2C3_SDA

J71-23 I2S1_DAT0 GPIO3_24 SAI5_RXD3 SAI5_TXD0 PDM_BIT3

J71-25 I2S1_DAT1 GPIO3_21 SAI5_RXD0 PDM_BIT0

J71-27 I2S1_SCK GPIO3_20 SAI5_RXC PDM_CLK

J71-29 I2S1_MCLK GPIO3_25 SAI5_MCLK SAI4_MCLK

J71-31 I2S1_WS GPIO3_19 SAI5_RXFS

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PIN Name Mux1 Mux2 Mux3 Mux4

J71-33 I2S2_DAT0 GPIO5_1 SAI3_TXD0 SAI5_RXD3 GPT1_CMP3

J71-35 I2S2_DAT1 GPIO4_30 SAI3_RXD0 SAI5_RXD0 GPT1_CMP1

J71-37 I2S2_SCK GPIO4_29 SAI3_RXBCLK SAI5_RBCLK GPT1_CPT2

J71-39 I2S2_WS GPIO4_28 SAI3_RXSYNC SAI5_RSYNC GPT1_CPT1

J71-43 SD3_CMD GPIO3_18 SD3_CMD

J71-45 SD3_CLK GPIO3_17 SD3_CLK

J71-47 SD3_DAT0 GPIO3_10 SD3_DAT0 QSPIb_DAT0




J71-57 SPDIF_CLK GPIO5_5 PWM1

J71-59 SPDIF_IN GPIO5_4 PWM2

J71-61 SPDIF_OUT GPIO5_3 PWM3

J71-63 CAM_TORCH GPIO4_21 SAI2_RXSYNC SAI5_TXSYNC

J71-65 CAM_FLASH GPIO3_16

J71-69 CAM_I2C_SDA GPIO5_14 ENET_MDC I2C1_SCL

J71-67 CAM_I2C_SCL GPIO5_15 ENET_MDIO I2C1_SDA

J71-71 CSI0_RESET GPIO1_6 ENET_MDC

J71-73 CSI0_PWDN GPIO1_3

J71-75 CSI0_MCLK GPIO5_2 SAI3_MCLK SAI5_MCLK PWM4

J70-70 DSI0_RESET GPIO5_0 SAI3_TXC SAI5_RXD2 GPT1_CMP

J70-72 DSI0_ENABLE GPIO1_4

J70-74 BACKLIGHT_PWM GPIO1_1 PWM1

J70-76 BACKLIGHT_ENABLE GPIO3_22 SAI5_RXD1_TSYNC SAI1_TXD3_TSYNC

J70-95 SD2_CARDDETECT_N GPIO2_12

J70-97 SD2_WRITEPROTECT GPIO2_20

J71-3 CLKO1_USB2_PEN GPIO1_14 PWM3 USB2_PWR CLKO1

J71-5 HDMI_INT_USB2_OC GPIO1_15 PWM4 USB2_OC CLKO2

J71-2 LED0_QSPIa_SCLK GPIO3_0 QSPIa_SCLK

J71-4 LED1_QSPIa_DAT0 GPIO3_6 QSPIa_DAT0

J71-6 KYPD0_QSPIa_DAT1 GPIO3_7 QSPIa_DAT1



J71-12 LED2_QSPIa_SS0 GPIO3_1 QSPIa_SS0

J71-14 USR_LED3 GPIO3_3 QSPIb_SS0

J71-16 USR_LED4 GPIO3_5 QSPIb_SCLK

J71-18 USB_HUB_RESET_N GPIO3_15 QSPIb_DQS

J71-20 USB_SW_SEL GPIO1_10

J71-22 USB1_PEN GPIO1_12

J71-24 USB1_OC GPIO1_13 PWM2

J71-48 PCIE_CLKREQ GPIO5_20 PCIE_CLKREQ PWM2

J71-50 PCIE_WAKE GPIO3_2 QSPIa_SS1

J71-62 DISPLAY_ENABLE GPIO1_5

J71-64 POWERFAIL GPIO4_31 SAI3_TXFS SAI5_RXD1 GPT1_CLK

J71-66 ENET_RESET GPIO1_9

J71-68 ENET_INT GPIO1_11

J71-70 ENET_MDC GPIO1_16 ENET_MDC

J71-72 ENET_MDIO GPIO1_17 ENET_MDIO

J71-74 ENET_TXCTL GPIO1_22 ENET_TXCTL

J71-76 ENET_TXC GPIO1_23 ENET_TXC ENET_TXER

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J71-80 ENET_TD0 GPIO1_21 ENET_TD0


J71-84 ENET_TD2 GPIO1_19 ENET_TD2 ENET_TXCLK


J71-88 ENET_RD0 GPIO1_26 ENET_RD0




J71-96 ENET_RXCTL GPIO1_24 ENET_RXCTL

J71-98 ENET_RXC GPIO1_25 ENET_RXC ENET_RXER

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1.3 Electrical Pin-Information

PI: Power Input

PO: Power Output

CO: Charger Output

AI: Analog Input

AO: Analog Output

ADI: Analog Differential Input

ADO: Analog Differential Output

ADIO: Analog Differential Input/Output

DI: Digital Input

DO: Digital Output

DIO: Digital Input/Output

PD: Pull-Down (PDp: Pull-Down, Pull-behavior can be changed by software)

PU: Pull-Up (PUp: Pull-Up, Pull-behavior can be changed by software)

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PIN Name Type Voltage Connected to

J70-1 VBAT PI Typ. 3.7V BD71847

J70-3 VBAT

J70-5 VBAT

J70-7 VBAT

J70-9

J70-11

J70-13 GND

J70-15 GND

J70-17 VBUS PI Typ. 5V BD71847

J70-19 VBUS

J70-21 VBUS

J70-23 VBUS

J70-25 USB1 _VBUS DI (5V) i.MX8M-Mini

J70-27 USB1_DM ADIO i.MX8M-Mini

J70-29 USB1_DP ADIO i.MX8M-Mini

J70-31 USB1_ID i.MX8M-Mini

J70-33 GND

J70-35 GND_CFILT Analog Audio Ground WM8983

J70-37 MIC2 AI WM8983

J70-39 MIC_BIAS AO WM8983

J70-41 HEADPHONE_L AO WM8983

J70-43 HEADPHONE_R AO WM8983

J70-45 HEADPHONE_REF AO WM8983

J70-47 HEADSET_DETECT AI WM8983

J70-49 MIC1 AI WM8983

J70-51 MIC_BIAS AO WM8983

J70-53 LINEIN_L AI WM8983

J70-55 LINEIN_R AI WM8983

J70-57 SPEAKER_P AO WM8983

J70-59 SPEAKER_N AO WM8983

J70-61 P1_TXD DIO,PDp VDD_IO i.MX8M-Mini

J70-63 P1_RXD DIO,PDp VDD_IO i.MX8M-Mini

J70-65 P1_RTS DIO,PDp VDD_IO i.MX8M-Mini

J70-67 P1_CTS DIO,PDp VDD_IO i.MX8M-Mini

J70-69 P2_TXD DIO,PDp VDD_IO i.MX8M-Mini

J70-71 P2_RXD DIO,PDp VDD_IO i.MX8M-Mini

J70-73 P2_RTS_SCL DIO,PDp VDD_IO i.MX8M-Mini

J70-75 P2_CTS_SDA DIO,PDp VDD_IO i.MX8M-Mini

J70-77 GND

J70-79 VDD_SDCARD_PWR PO 3.3V

J70-81 VDD_SDCARD_IO PO NVCC_SD2

1.8V/3.3V

BD71847

J70-83 SD2_CMD DIO,PDp NVCC_SD2 i.MX8M-Mini

J70-85 SD2_CLK DIO,PDp NVCC_SD2 i.MX8M-Mini

J70-87 SD2_DAT0 DIO,PDp NVCC_SD2 i.MX8M-Mini




J70-95 SD2_CARDDETECT_N DIO,PDp NVCC_SD2 i.MX8M-Mini

J70-97 SD2_WRITEPROTECT DIO,PDp NVCC_SD2 i.MX8M-Mini

J70-99 GND

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J70-2 VBAT PI Typ. 3.7V BD71847

J70-4 VBAT

J70-6 VBAT

J70-8 VBAT

J70-10 VDD_SPEAKER PI WM8983

J70-12

J70-14 GND

J70-16 GND

J70-18 VBUS PI Typ. 5V BD71847

J70-20 VBUS

J70-22 VBUS

J70-24 VBUS

J70-26 USB2_VBUS DI (5V) i.MX8M-Mini

J70-28 ONOFF DI,PU Int.Voltage,

Only switch to

GND by

external circuit.

i.MX8M-Mini

J70-30 RESET_IN_N DI,PU BD71847

J70-32 RESET_OUT_N DO VDD_IO i.MX8M-Mini

J70-34 GND

J70-36 GND

J70-38 JTAG_MODE DI,PD VDD_IO i.MX8M-Mini

J70-40 BOOT_MODE_0 DI,PD VDD_IO i.MX8M-Mini

J70-42 +3V3 PO

+3.3V BD71847

J70-44 +3V3

J70-46 VDD_1V8 PO +1.8V BD71847

J70-48 VDD_1V8

J70-50 VDD_ENET PO +1.8 .. 3.3V BD71847

J70-52 VDD_IO PO VDD_IO BD71847

J70-54 P3_MOSI_TXD DIO,PDp VDD_IO i.MX8M-Mini

J70-56 P3_MISO_RTS DIO,PDp VDD_IO i.MX8M-Mini

J70-58 P3_CLK_RXD DIO,PDp VDD_IO i.MX8M-Mini

J70-60 P3_CS_CTS DIO,PDp VDD_IO i.MX8M-Mini

J70-62 P4_GPIO1 DIO,PDp VDD_IO i.MX8M-Mini


J70-66 P4_SCL DIO,PDp VDD_IO i.MX8M-Mini

J70-68 P4_SDA DIO,PDp VDD_IO i.MX8M-Mini

J70-70 DSI0_RESET DIO,PDp VDD_IO i.MX8M-Mini

J70-72 DSI0_ENABLE DIO,PDp VDD_IO i.MX8M-Mini

J70-74 BACKLIGHT_PWM DIO,PDp VDD_IO i.MX8M-Mini

J70-76 BACKLIGHT_ENABLE DIO,PDp VDD_IO i.MX8M-Mini

J70-78 GND

J70-80 DSI0_DAT0_N /

LVDS_TXN0

ADO VDD_1V8

i.MX8M-Mini /

SN65DSI83

J70-82 DSI0_DAT0_P /

LVDS_TXP0

ADO VDD_1V8 i.MX8M-Mini /

SN65DSI83


LVDS_TXN1


SN65DSI83


LVDS_TXP1


SN65DSI83


LVDS_TXN2


SN65DSI83

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LVDS_TXP2


SN65DSI83


LVDS_TXN3


SN65DSI83


LVDS_TXP3


SN65DSI83

J70-96 DSI0_CLK_N /

LVDS_CLKN


SN65DSI83

J70-98 DSI0_CLK_P /

LVDS_CLKP


SN65DSI83

J70-

100

GND


J71-1 BOOT_MODE_1 DI,PD VDD_IO i.MX8M-Mini

J71-3 CLK01_USB2_PEN DIO VDD_IO i.MX8M-Mini

J71-5 HDMI_INT_USB2_OC DIO,PDp VDD_IO i.MX8M-Mini

J71-7 P5_MOSI_TXD DIO,PDp VDD_IO i.MX8M-Mini

J71-9 P5_MISO_RTS DIO,PDp VDD_IO i.MX8M-Mini

J71-11 P5_CLK_RXD DIO,PDp VDD_IO i.MX8M-Mini

J71-13 P5_CS_CTS DIO,PDp VDD_IO i.MX8M-Mini



J71-19 P6_SCL DIO,PDp VDD_IO i.MX8M-Mini

J71-21 P6_SDA DIO,PDp VDD_IO i.MX8M-Mini

J71-23 I2S1_DAT0 DIO,PDp VDD_IO i.MX8M-Mini


J71-27 I2S1_SCK DIO,PDp VDD_IO i.MX8M-Mini

J71-29 I2S1_MCLK DIO,PDp VDD_IO i.MX8M-Mini

J71-31 I2S1_WS DIO,PDp VDD_IO i.MX8M-Mini



J71-37 I2S2_SCK DIO,PDp VDD_IO i.MX8M-Mini

J71-39 I2S2_WS DIO,PDp VDD_IO i.MX8M-Mini

J71-41 GND

J71-43 SD3_CMD DIO,PDp VDD_IO i.MX8M-Mini

J71-45 SD3_CLK DIO,PDp VDD_IO i.MX8M-Mini

J71-47 SD3_DAT0 DIO,PDp VDD_IO i.MX8M-Mini




J71-55 GND

J71-57 SPDIF_CLK DIO,PDp VDD_IO i.MX8M-Mini

J71-59 SPDIF_IN DIO,PDp VDD_IO i.MX8M-Mini

J71-61 SPDIF_OUT DIO,PDp VDD_IO i.MX8M-Mini

J71-63 CAM_TORCH DIO,PDp VDD_IO i.MX8M-Mini

J71-65 CAM_FLASH DIO,PDp VDD_IO i.MX8M-Mini

J71-67 CAM_I2C_SCL DIO,PDp VDD_IO i.MX8M-Mini

J71-69 CAM_I2C_SDA DIO,PDp VDD_IO i.MX8M-Mini

J71-71 CSI0_RESET DIO,PDp VDD_IO i.MX8M-Mini

J71-73 CSI0_PWDN DIO,PDp VDD_IO i.MX8M-Mini

J71-75 CSI0_MCLK DIO,PDp VDD_IO i.MX8M-Mini

J71-77 GND

J71-79 CSI0_CLK_N ADI VDD_1V8 i.MX8M-Mini

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J71-81 CSI0_CLK_P ADI VDD_1V8 i.MX8M-Mini

J71-83 CSI0_DAT0_N ADI VDD_1V8 i.MX8M-Mini

J71-85 CSI0_DAT0_P ADI VDD_1V8 i.MX8M-Mini







J71-99 GND


J71-2 LED0_QSPIa_SCLK DIO VDD_IO i.MX8M-Mini

J71-4 LED1_QSPIa_DAT0 DIO VDD_IO i.MX8M-Mini

J71-6 KYPD0_QSPIa_DAT1 DIO,PDp VDD_IO i.MX8M-Mini



J71-12 LED2_QSPIa_SS0 DIO,PUp VDD_IO i.MX8M-Mini

J71-14 LED3 DIO VDD_IO i.MX8M-Mini

J71-16 LED4 DIO VDD_IO i.MX8M-Mini

J71-18 USB_HUB_RESET_N DO VDD_IO i.MX8M-Mini

J71-20 USB_SW_SEL DIO,PUp VDD_IO i.MX8M-Mini

J71-22 USB1_PEN DIO,PDp VDD_IO i.MX8M-Mini

J71-24 USB1_OC DIO,PDp VDD_IO i.MX8M-Mini

J71-26 JTAG_TMS DI,PU VDD_IO i.MX8M-Mini

J71-28 JTAG_TRST DI,PU VDD_IO i.MX8M-Mini

J71-30 JTAG_TCK DI,PU VDD_IO i.MX8M-Mini

J71-32 JTAG_TDO DO,PU VDD_IO i.MX8M-Mini

J71-34 JTAG_TDI DI,PU VDD_IO i.MX8M-Mini

J71-36 USB2_ID i.MX8M-Mini

J71-38 USB2_DP ADIO i.MX8M-Mini

J71-40 USB2_DM ADIO i.MX8M-Mini

J71-42 GND

J71-44 PCIE_RXN_P ADIO VDD_IO i.MX8M-Mini

J71-46 PCIE_RXN_N ADIO VDD_IO i.MX8M-Mini

J71-48 PCIE_CLKREQ DIO,PDp VDD_IO i.MX8M-Mini

J71-50 PCIE_WAKE DIO,PDp VDD_IO i.MX8M-Mini

J71-52 PCIE_TXN_P ADIO VDD_IO i.MX8M-Mini

J71-54 PCIE_TXN_N ADIO VDD_IO i.MX8M-Mini

J71-56 GND

J71-58 PCIE_REFCLK_P ADIO VDD_IO i.MX8M-Mini

J71-60 PCIE_REFCLK_N ADIO VDD_IO i.MX8M-Mini

J71-62 DISPLAY_ENABLE DIO,PDp VDD_IO i.MX8M-Mini

J71-64 POWERFAIL DIO,PDp VDD_IO i.MX8M-Mini

J71-66 ENET_RESET DIO,PDp VDD_IO i.MX8M-Mini

J71-68 ENET_INT DIO,PDp VDD_IO i.MX8M-Mini

J71-70 ENET_MDC DIO,PDp VDD_IO i.MX8M-Mini

J71-72 ENET_MDIO DIO,PDp VDD_IO i.MX8M-Mini

J71-74 ENET_TXCTL DIO,PDp VDD_ENET i.MX8M-Mini

J71-76 ENET_TXC DIO,PDp VDD_ENET i.MX8M-Mini

J71-78 GND

J71-80 ENET_TD0 DIO,PDp VDD_ENET i.MX8M-Mini



- 16 of 33 -


J71-88 ENET_RD0 DIO,PDp VDD_ENET i.MX8M-Mini




J71-96 ENET_RXCTL DIO,PDp VDD_ENET i.MX8M-Mini

J71-98 ENET_RXC DIO,PDp VDD_ENET i.MX8M-Mini

J71-

100

GND

Note on Display-Interface:

The module can be configured for Mipi-DSI or LVDS display-output by mounting option.

Note on VDD_IO:

VDD_IO can be configured by mounting options either to +3V3 or +1V8.

Note on VDD_ENET:

VDD_ENET can be controlled by LDO5 of BD71847 PMIC. U-Boot defaults to set this to VDD_IO

voltage level. A mounting option exist to supply this voltage externally through J70-50.

2. Interfaces This chapter includes a short description of all interfaces of the Myon II.

Please consult the processor datasheet for detailed information.

2.1 Power Supply

There are two main power supply scenarios. Battery power supply and external power supply.

The Myon II got two power-inputs which are treated equal (VBUS and VBAT) through an ideal OR

diode. In comparison to the Myon I, the Myon II does not have a battery-charger.

For cost savings a mounting option exist to override the ideal OR diode.

Name Description

VBAT Main power input.

VBUS Auxiliary power input.

VDD_SPEAKER 2.5V .. 5.5V Audio Speaker Supply.

+3V3 +3.3V power output (max. 600mA)

VDD_1V8 +1.8V power output (max. <50mA)

Note that this regulator also supplies on-board

peripherals. So the current available for use by the

baseboard is less than 50mA.

VDD_ENET +1.8V...+3.3V power output (max. 300mA)

VDD_IO +1.8V or +3V3 power output (max. <300mA)

Note that this regulator also supplies on-board

peripherals. So the current available for use by the

baseboard might be less than 300mA. If possible the

IO-voltage of the baseboards peripherals should be

connected to this supply.

- 17 of 33 -

2.2 Control-Signals

Name Description

ONOFF Connect to power-on/off button. The signal got a

pull-up to an internal voltage. Only pull signal to

ground by external circuit.

RESET_IN_N Negated reset input. 0: reset device, 1: normal

operation.

RESET_OUT_N Negated reset output. 0: device in reset, 1: normal

operation.

JTAG_MODE Leave unconnected for JTAG Native Mode / normal

operation.

Connect to VDD_IO for JTAG Boundary Scan testing.

USB1_VBUS Connect to VBUS(+5V) of USB-OTG-connector. Used

by software to detect if USB-Slave cable got

connected.

USB2_VBUS Connect to VBUS(+5V) of USB-OTG-connector. Used

by software to detect if USB-Slave cable got

connected.

Boot_Mode[1:0] Boot Type

00 Boot from fuses

01 Serial downloader

10 Internal boot (development)

11 Reserved

- 18 of 33 -

2.3 IO-Ports 1–6

Name Description

P1_TXD GPIO5_25; UART2_TXD output

P1_RXD GPIO5_24; UART2_RXD input

P1_RTS

(RXD)

GPIO5_28; UART2_RTS output;

(UART4_RXD input)

P1_CTS

(TXD)

GPIO5_29; UART2_CTS input;

(UART4_TXD output)

P2_TXD GPIO5_23; UART1_TXD output

P2_RXD GPIO5_22; UART1_RXD input

P2_RTS_[SCL]

(RXD)

GPIO5_26; UART1_RTS output; (UART3_RXD input);

I2C4_SCL as mounting option *1)

P2_CTS_[SDA]

(TXD)

GPIO5_27; UART1_CTS input; (UART3_TXD output);

I2C4_SDA as mounting option *1)

P3_MOSI_TXD GPIO5_7; SPI1_MOSI output; UART3_TXD output

P3_MISO_RTS GPIO5_8; SPI1_MISO input; UART3_RTS output

P3_CLK_RXD GPIO5_6; SPI1_CLK output; UART3_RXD input

P3_CS_CTS GPIO5_9; SPI1_CS output; UART3_CTS input

P4_GPIO1 GPIO3_23;

P4_GPIO2 GPIO3_4;

P4_SCL GPIO5_16; I2C2_SCL output

P4_SDA GPIO5_17; I2C2_SDA

P5_MOSI_TXD GPIO5_11; SPI2_MOSI output; UART4_TXD output

P5_MISO_RTS GPIO5_12; SPI2_MISO input; UART4_RTS output

P5_CLK_RXD GPIO5_10; SPI2_CLK output; UART4_RXD input

P5_CS_CTS GPIO5_13; SPI2_CS output; UART4_CTS input

P6_GPIO1_[MOSI] GPIO1_0;

SPI6_MOSI output as mounting option *1)

P6_GPIO2_[MISO] GPIO1_13;

SPI6_MISO input as mounting option *1)

P6_SCL_[CLK] I2C6_SCL output

SPI6_CLK as mounting option *1)

P6_SDA_[CS] I2C6_SDA

SPI6_CS as mounting option *1)

*1) Functions in brackets [] are only available as non-standard mounting option. Contact Keith &

Koep GmbH for details.

() Additional UARTs on P1 and P2, if RTS and CTS are not used.

- 19 of 33 -

2.3.1 GPIO

GPIO pins may be configured as input or outputs and with pull-up, pull-down or no pull, hysteresis,

open-drain –behavior. The pins have a programmable drive-strength and slew-rate settings.

Please view the i.MX 8M Mini datasheet on which settings are possible for each individual pin.

2.3.2 UART

Baudrate: High-speed TIA/EIA-232-F compatible, up to 1Mbit/s,

IrDA-compatible up to 115.2kBit/s

Data-Bits: 7 or 8 bits (RS232) or 9 bit (RS485)

Stop-Bits: 1, 2

Parity: None, Event, Odd

Features: Hardware-flow-control (RTS, CTS)

Figure 2-3-2-1: Application Diagram RS232

Figure 2-3-2-2: Application Diagram RS485

On default, the UART on P2_TXD/RXD is used for bootloader and linux-console in- and output

(115kBaud, 8N1).

2.3.3 SPI / ECSPI Enhanced Configurable Serial Peripheral Interface

The serial peripheral interface is a programmable synchronous serial port,

which may be used to connect to a multiple of different peripherals.

The IO-Ports only define a 4-pin SPI with one chip-select. Extra SPI-chip-selects

can be found on other GPIOs ( see “1.2 Pin-Mux Information“).

Speed: up to 23Mbit/s

Features: Master & Slave mode.

2.3.4 I2C

Speed: Standard mode, up to 100 kbit/s

Fast mode, up to 400 kbit/s

Features: Multimaster operation.

I2C Specification Version 2.1

- 20 of 33 -

2.4 I2S-IO-Ports

The Inter-IC sound interface is used to connect to audio codecs.

The i.MX 8M Mini features a Synchronous Audio Interface (SAI) that supports full-duplex serial

interfaces with frame synchronization such as I2S, TDM and codec/DSP interfaces.

Name Description

I2S1_DAT0 First I2S-port: SAI5_TXD0

I2S1_DAT1 First I2S-port: SAI5_RXD0

I2S1_SCK First I2S-port: SAI5_RXC

I2S1_WS First I2S-port: SAI5_RXFS

I2S1_MCLK First I2S-port: SAI5_MCLK / SAI4_MCLK

I2S2_DAT0 Second I2S-port: SAI3_TXD0

I2S2_DAT1 Second I2S-port: SAI3_RXD0

I2S2_SCK Second I2S-port: SAI3_RXBCLK

I2S2_WS Second I2S-port: SAI3_RXSYNC

This interface is highly configurable and SAI pins are also routed to other Myon-pins (See 1.2 Pin-

Mux Information).

2.5 SPDIF

The Sony/Philips Digital Interface audio block is a stereo transceiver that allows the processor to

receive and transmit digital audio.

Name Description

SPDIF_CLK External Clock signal

SPDIF_IN Input line

SPDIF_OUT Output line

- 21 of 33 -

2.6 SD-Card

The SD-Card Interface may be used to connect a SD-Card, eMMC or SDIO-hardware to the Myon

board.

Name Description

VDD_SDCARD_PWR Power supply output for the attached SD/SDIO-

peripheral (1.8V – 3.3V)

VDD_SDCARD_IO IO-Voltage for SD2_xxx signals ( 1.8V / 2.95V)

SD2_CMD SD-card command output

SD2_CLK SD-card clock output

SD2_DAT0 SD-card data bit 0




SD2_CARDDETECT_N SD-card detect: 0: card inserted, 1: card removed

SD2_WRITEPROTECT SD-card write-protect

Compared to Myon I, the Myon II got a second external SD-Card interface:

Name Description

SD3_CMD SD-card command output

SD3_CLK SD-card clock output





SD3 uses VDD_IO as IO-voltage.

Figure 2-5-1: Application Diagram SD-Card-Socket

- 22 of 33 -

2.7 USB

The Myon II got two high-speed USB 2.0 OTG ports which may work as host or as slave.

Name Description

USB1_VBUS Connect to VBUS (+5) of USB-Slave or USB-OTG

port. This pin is used to detect if the port is

connected to a host when the Myon works as USB-

slave.

USB1_DM USB HS data minus

USB1_DP USB HS data plus

USB1_ID USB OTG ID pin.

USB1_PEN Power-Enable Output. May be used for other purpose

(i.e. GPIO) if not needed.

USB1_OC Over-Current Input. May be used for other purpose

(i.e. GPIO) if not needed.

USB2_VBUS Connect to VBUS (+5) of USB-Slave or USB-OTG

port. This pin is used to detect if the port is

connected to a host when the Myon works as USB-

slave.

USB2_DM USB HS data minus

USB2_DP USB HS data plus

USB2_ID USB OTG ID pin.

CLK01_USB2_PEN Power-Enable Output. May be used for other purpose

(i.e. CLKO1) if not needed.

HDMI_INT_USB2_OC Over-Current Input. May be used for other purpose

(i.e. GPIO/HDMI_IN) if not needed.

Speed: 480Mbps

Features: USB2.0 high-speed.

2.8 PCIe Name Description

PCIE_REFCLK_P Reference Clock

PCIE_REFCLK_N Reference Clock

PCIE_TXN_P Transmit output – positive

PCIE_TXN_N Transmit output – negative

PCIE_RXN_P Receive input – positive

PCIE_RXN_N Receive input – negative

PCIE_CLKREQ Clock-Request

PCIE_WAKE Wake GPIO

Features: Single lane supporting PCIe Gen2

- 23 of 33 -

2.9 Display

The Myon II has two different mounting options for the display-port pins:

- MIPI signals (DSI0_xxx) or

- LVDS signals ( LVDS_xxx)

Name Description

DSI0_DAT0_N /

LVDS_TXN0

Display data lane 0 – negative

DSI0_DAT0_P /

LVDS_TXP0

Display data lane 0 – positive

DSI0_DAT1_N /

LVDS_TXN1


DSI0_DAT1_P /

LVDS_TXP1


DSI0_DAT2_N /

LVDS_TXN2

Display data lane 2 - negative

DSI0_DAT2_P /

LVDS_TXP2

Display data lane 2 - positive

DSI0_DAT3_N /

LVDS_TXN3


DSI0_DAT3_P /

LVDS_TXP3


DSI0_CLK_N /

LVDS_CLKN

Display data clock – negative

DSI0_CLK_P /

LVDS_CLKP

Display data clock – positive

DSI0_RESET Display reset (output)

DSI0_ENABLE Display enable (output)

BACKLIGHT_PWM Backlight PWM (output)

BACKLIGHT_ENABLE Backlight enable (output)

HDMI_INT HDMI interrupt input

Features: 1080p 60fps

MIPI DSI 4-lane

- 24 of 33 -

2.10 Camera

The Myon II got one MIPI camera interface.

Name Description

CSI0_CLK_N Main camera clock input – negative

CSI0_CLK_P Main camera clock input – positive

CSI0_DAT0_N Main camera data lane 0 – negative

CSI0_DAT0_P Main camera data lane 0 – positive







CSI0_RESET Main camera reset

CSI0_PWDN Main camera power-down / enable

CSI0_MCLK Main camera master clock output

CAM_TORCH Camera torch on / light on

CAM_FLASH Camera flash

CAM_I2C_SCL Camera I2C clock

CAM_I2C_SDA Camera I2C data

CSI0 Features: MIPI CSI 4-lane

2.11 Audio

The Myon II uses a Cirrus Logic WM8983 audio-codec.

Name Description

GND_CFILT Analog ground for audio.

MIC1 Main mic input.

Connected through 1uF with LIP(1).

MIC_BIAS Microphone bias output.

Connected to MICBIAS(32).

MIC2 Headset mic input.

Connected through 1uF with RIP(4).

LINEIN_L Left channel line input.

Connected through 1uF with L2(3).

LINEIN_R Right channel line input

Connected through 1uF with R2(6).

HEADPHONE_L Headphone left channel output

Connected to LOUT1(30).

HEADPHONE_R Headphone right channel output.

Connected to ROUT1(29).

HEADPHONE_REF Headphone ground sensing input.

Connected to OUT4(21).

HEADSET_DETECT Headset detect input.

Connected to CSB/GPIO1 (15).

SPEAKER_P 1W into 8R @5V Speaker output ( + or L/R).

Connected to ROUT2 (23).

SPEAKER_N 1W into 8R @5V Speaker output ( - or L/R).

Connected to LOUT2 (25)

- 25 of 33 -

2.12 JTAG

The JTAG interface may be used for debugging and boundary-scan testing.

For security purpose JTAG-functionality can be limited or disabled through a processor-fuse.

Name Description

JTAG_TMS JTAG mode-select input

JTAG_TRST_N JTAG reset

JTAG_TCK JTAG clock input

JTAG_TDO JTAG data output

JTAG_TDI JTAG data input

JTAG_SRST_N JTAG reset for debug

2.13 Ethernet

The i.MX 8M Mini processor includes a Gbit-Ethernet MAC, which can be connected to

an ethernet-PHY.

Name Description

ENET_TXCTL Transmit Enable output

ENET_TXC / TXER Transmit Clock output

ENET_TD0 Transmit Data 0 output


ENET_TD2 / TXCLK Transmit Data 2 output


ENET_RXCTL Receive Data Valid

ENET_RXC / RXER Receive Clock input

ENET_RD0 Receive Data 0 input




ENET_MDC Management data clock

ENET_MDIO Management data

ENET_INT Interrupt GPIO input

Speed: 10/100Mbit, 1Gbit

Features: 802.3-2002 standard

Connects to: 4-bit MII @2.5/25MHz

4-bit MII-Lite @2.5/25MHz

2-bit RMII @50MHz

4-bit RGMII @125MHz

View i.MX 8M datasheet or ask Keith & Koep for details on how to connect to ethernet-phy.

- 26 of 33 -

2.14 Miscellaneous Signals

There are some other GPIO pins not covered in the previous chapter of this document.

As all GPIOs you are free to use them for your special purpose. This list only names the purpose,

as they are used on the evaluation-boards.

Name Description

CLK01_USB2_PEN Configurable Clock-Output

HDMI_INT_USB2_OC Interrupt GPIO input from MIPI to HDMI converter.

KYPD0_QSPIa_DAT1 Keypad 0



LED0_QSPIa_SCLK User LED

LED1_QSPIa_DAT0 User LED

LED2_QSPIa_SS0 User LED

LED3 User LED

LED4 User LED

USB_HUB_RESET_N Reset GPIO output for an external USB hub.

USB_SW_SEL GPIO output to force USB1 function:

0: USB mode detected by connected cable

1: USB in host mode

2.15 Realtime Clock

If it is needed, it is recommended to use an external Realtime-Clock i.e. EPSON RTC-8564JE to

keep the time during low-power or power-off -modes.

- 27 of 33 -

3. Specifications

3.1 Absolute Maximum Ratings

Absolute maximum ratings reflect conditions that the module may be exposed outside of the

operating limits, without experiencing immediate functional failure. Functional operation is only

expected during the conditions indicated under “Recommended Operating Conditions”. Stresses

beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the

module. Exposure to absolute-maximum rated conditions for extended periods may affect device

reliability.

Name Pin Min Max Unit

Supply Voltage VBAT

VBUS

VDD_SPEAKER

-0.3

-0.3

-0.3

6

6

7

V

V

V

Storage Temperature TStorage -40 85 °C

3.3 Recommended Operating Conditions

Name Pin Min Typ Max Unit

Supply Voltage An option exist, where VDD_SPEAKER is connected to VSYS (VBAT or VBUS) internally on the module.

Ask Keith & Koep how a specific module is configured.

VBAT

VBUS

VDD_SPEAKER

3.0

3.0

2.5

3.3

3.3

3.3

5.5

5.5

5.5

V

V

V

Supply current (typ.) Measured on i-PAN M7.

Power consumption dramatically depends on the usage scenario.

This includes things like if the processors operating point (frequency) can be set to a lower level; if the GPU can be used by an application; the selected display-resolution or if the module supplies external peripherals i.e. a speaker.

We recommend to use a 2A voltage-regulator to supply the module.

VBAT @ 3.3V

Suspend

Idle

Using/Running/

Stressapptest

350

t.b.d

t.b.d

370

1100

mA

mA

mA

Operating

temperature The chip temperature of processor or LPDDR4 might get hotter. The max. case temperature of i.MX 8M Mini is specified with +95°C (consumer) and +105°C (industrial).

A higher refresh-rate-setting is needed when case temperature of LPDDR4 is expected to rise above +85°C.

Temperature of eMMC influence the achievable Data Retention.

TConsumer

TExtended

TIndustrial

0

-25

-40

+25

+25

+25

+85

+85

+85

°C

°C

°C

- 28 of 33 -

3.2 ESD Ratings

Name Description Max Unit

V(ESD) Electrostatic

discharge

Human body model (HBM)

Charged-device model (CDM)

±1000

±250

V

- 29 of 33 -

3.4 Electrical Characteristics

Parameter Min Max Unit

VIL_gpio Low-level input voltage -0.3 0.3 * VDD_IO V

VIH_gpio High-level input voltage 0.7 * VDD_IO VDD_IO + 0.3 V

VOH_gpio High-level output voltage 0.8 * VDD_IO VDD_IO V

VOL_gpio Low-level output voltage 0 0.2 * VDD V

RP_gpio Pull-Resistance (1) 12 69 kΩ

1) i.MX 8M Mini only supports internal pull-up or pull-down for VDD_IO = 1.8V or 2.5V (it is

not supported for VDD_IO = 3.3V).

- 30 of 33 -

3.5 Mechanical Specification

We strongly recommend the use of plastic screws (for example M2.0x8mm, DIN 84 / ISO 1207 PA

6.6) as mounting parts to prevent possible short-circuits.

- 31 of 33 -

4.0 Ordercodes for Myon II

1-2 3 4 5 6 7 8 9 10 11 12 13-15 16-18

60 Processor RAM PCB . Temp I/O Audio Display Store . Hxx Syy

60 A 2 0 . C 0 1 1 2 . H00 S00

Processor:

0 1.8GHz SoloLite CT

1 1,6GHz SoloLite IT 2 1.8GHz Solo CT 3 1.6GHz Solo IT 4 1.8GHz DualLite CT 5 1.6GHz DualLite IT 6 1.8GHz Dual CT 7 1.6GHz Dual IT 8 1.8GHz QuadLite CT 9 1.6GHz QuadLite IT

A 1.8GHz Quad CT

B 1.6GHz Quad IT

Software/Firmware:

S00 Standard Software

S01 …

Hardware:

H00 Standard

H01 …

Defines custom mounting option

Storage:

1 EMMC 4GB, MLC 2 EMMC 8GB, MLC 3 EMMC 16GB, MLC 4 EMMC 32GB, 3D

RAM:

0 512 MB 1 1 GB 2 2 GB 4 4 GB 8 8 GB

Display:

0 MIPI 1 LVDS

PCB Revision:

0 V1R1L4 1

Audio:

0 No Audio Codec 1 With Audio Codec

WM8983 (C+E Temp)

WM8978 (I Temp)

Temperature:

C 0 .. 70°C

E -25 .. 85°C

I -40 .. 85°C

I/O Voltage:

0 1.8V 1 3.3V

For example:

Order Code

60…

Myon II (without image)

60A20.C0112. H00S00

Myon II Quad/CT1800/R2G/EMMC8G/LVDS/COD/RoHS

(i.MX 8M Mini Quad Core, CT 1.8 GHz, 2 GB RAM, 8 GB eMMC, LVDS, Codec)

60B20.E0103.

H81S00 Myon II Quad/IT1600/R2G/EMMC16G/no LVDS/COD/

RoHS

(i.MX 8M Mini Quad Core, IT 1.6 GHz, 2 GB RAM, 16 GB eMMC, no LVDS, Codec)

- 32 of 33 -

5. Important Notice

- 33 of 33 -

6. Document History

Rev. Date Author Changes

1.1 15.10.2019 SH Initial Version.

1.2 16.10.2019 SH Correction: SD2_CMD and SD3_CMD have

programmable Pull-Down enabled after reset.

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