MURI Device-level Radiation Effects Modeling Hugh Barnaby, Jie Chen, Ivan Sanchez Department of...
-
Upload
camron-greatorex -
Category
Documents
-
view
217 -
download
0
Transcript of MURI Device-level Radiation Effects Modeling Hugh Barnaby, Jie Chen, Ivan Sanchez Department of...
MURIDevice-level Radiation Effects
Modeling
Hugh Barnaby, Jie Chen, Ivan SanchezDepartment of Electrical EngineeringIra A. Fulton School of Engineering
Arizona State University
Topics
• Target of Research
• Radiation Effect Modeling: A TCAD-based approach
• Example: Drain-source leakage in deep-submicron bulk CMOS
Goals
• Model the effects of TID and DD defectson advanced device technologies
• Identify the continuing and emerging radiation threats to these technologies
• Model the defects: implement physical models, dynamics of buildup
• Radiation effects testing (Co60, neutrons, low temperature testing)
Radiation Concerns
• Total ionizing dose
• Displacement damage
• Single event damage and micro-dose
Technologies and Techniques
• Ultra Thin Oxides
• Shallow Trench Isolation
• Buried Oxides
• Implants
• Heterojunctions
• Gate technologies
Device Categories
• Ultra Small Bulk CMOS
• Silicon on Insulator (dual gate operation)
• Strained Silicon CMOS
• SiGe HBTs
ASU has a strong relationship with FreeScale semiconductor.
Effects
• Oxide Damage and Reliability• Defect buildup• Leakage• Breakdown• Annealing and other temperature dependent
processes
• Semiconductor Effects• Electrostatics• Carrier recombination and removal• Mobility effects• Annealing and other temperature dependent
processes
Testing
• Co60 -sources• ASU (100 rd/s, 1 rd/s, ~10mrd/s)• UA (100 rd/s, 10 md/s)
• Neutron Sources (UA – Triga and Rabbit Reactors)
• Low temperature Co60 irradiations (down to 70k)
TCAD Modeling and Simulation
PROCESS DEVICE CIRCUIT
To EDA
ProcessSim.
DeviceSim.
CircuitSim.
OPTIMIZE ELECTRICALPERFORMANCE
Process and LayoutDescription
Bias Conditions Design
OPTIMIZESTRUCTURE GEOMETRY
NET DOPING
2D cross section of LOCOSparasitic nMOSFET
2D potential contoursin parasitic nMOSFET
SRAM Schematic includingparasitic nMOSFET element
Leakage current vs.drain voltage
Ileak
Vd
POTENTIAL
TCAD Flow
Radiation Effects Modeling
TotalDose
Process and LayoutDescription
BiasConditions
OPTIMIZE GEOMETRYAND PRECURSORS
Strain effects, energy to defect conv., doping profiles
heating, defect formation, tunneling.
Displace.Damage
Defect precursors
Device
carrier transport in dielectric,
defect formation and approximations
Process
Example: D-S Leakage
Due to aggressive scaling into the deep sub-micron, the threat of significant threshold voltage shifts caused by charge buildup in the gate oxide has been reduced. Instead threats have shifted elsewhere, such as drain-to-source leakage caused by charge buildup in the isolation oxide (shallow trench – STI)
Polysilicon gate
N+ drain
N+ Source
Leakage
++
STIshallow trenchisolation oxide
++++
+ +++
Leakage
TID effects on off-state leakage
1E-15
1E-13
1E-11
1E-09
1E-07
1E-05
1E-03
-0.5 0 0.5 1 1.5 2
Gate Voltage (V)
Dra
in C
urr
ent
(A)
0
50K
100K
150K
200K
250K
300K
400k
500k
PA
TSMC 0.18 mNMOS Minimum Geometry
VG = 1.8 V
72 rad/s
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
250 300 350 400
Dose (krad(Si))
IDo
ff(A
)
1E-15
1E-13
1E-11
1E-09
1E-07
1E-05
1E-03
-0.5 0 0.5 1 1.5 2
Gate Voltage (V)
Dra
in C
urr
ent
(A)
0
50K
100K
150K
200K
250K
300K
400k
500k
PA
0
50K
100K
150K
200K
250K
300K
400k
500k
PA
0
50K
100K
150K
200K
250K
300K
400k
500k
PA
TSMC 0.18 mNMOS Minimum Geometry
TSMC 0.18 mNMOS Minimum Geometry
VG = 1.8 V
72 rad/s
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
250 300 350 400
Dose (krad(Si))
IDo
ff(A
)
3.2 nm/STI
After Lacoe NSREC SC 2003
• Increase in off-state leakage (ID @ Vgs = 0V) increases to 100nA after 400 krad of exposure.
• Problem in SRAM arrays (power, overheating, and failure)
TI-MSC1211 A/D Converter
AIN+
AIN-
DVDD AVDD
REFIN
Processor
Flash memory
UART
RAM A/D
5V Supply
5V Supply
GND
Comp. Terminal
• 24-bit Delta-Sigma ADC
• Internal reference generator
• Intel 8051 microcontroller
• Timers
• Universal asynchronous receiver and transmitter
• RAM, ROM, and flash memory
measure specifications
Temperature monitor, RTD(resistant temperature device),
mounted on package
Isupply
Vsupply
Offset Calibration
Other specs include: full scale, and ENOB
-2
-1.5
-1
-0.5
0
0.5
1
0 5 10 15 20 25 30
Dose (krads(Si))
chan
ge in
OCR
(ppm
)
post_rad
control
failure point
• Bit-error outputfor differential input
• High frequency datarepresents noiseinduced offsets
• Mean value determinedby device mismatch,temp variation, etc.
Supply Current and Temperature
Field oxide leakage path
0
50
100
150
200
250
300
0 5 10 15 20 25 30 35
dose (krads (Si))
Cur
rent
(mA
)
Id
0
10
20
30
40
50
60
70
80
0 10 20 30
dose (krads (Si))
Tem
p (C
)Temp
Digital Supply Current vs. DOSE
Package Temperature vs. DOSE
TID leads to increase inoperating temperatureof device.
Photoemission Analysis
Field oxide leakage path
Vsupply
Increased power dissipationand die temperature causedby high static current densityin pre-charge devices of SRAM array.
Mechanism
bit cell
bit cell
bit cell
bit cell
Column select
sense amp
bit cell
bit cell
bit cell
bit cell
bit cell
bit cell
bit cell
bit cell
Precharge_n
WD0
WD1
WD127
Col(1:0)
b bn
W_Rn
DIN DIN_n
Sense_n
Dout(0) Dout(1) Dout(2) Dout(7)
VDD
B0 B0_n B1_n B2_n B3_n B1 B2 B3
Increased current density reveals impact of radiation-induced leakagemechanism: the parasitic nMOSFET.
L
W
L
W
STI
L
W
L
W
STI
Parasitic nMOSFET
“as drawn” nMOSFET
parasitic nMOSFET
VT
VT (0)VT (1011)VT (1012)VT (1013)
“as drawn” nFET parasitic nFET
Drive current
Drive current
Increasing TID
PRE-RADDue to its greater oxide thickness, the parasiticnMOSFET has a much higher VT and lower drivecurrent compared to “as drawn” device.
POST-RADDue to its greater oxide thickness, oxide-chargebuildup in the parasitic nMOSFET is much greater,causing large shifts in VT drive current.
Parasitic nMOSFET Parameters
VCC_CIRCLE
VCC_CIRCLE
0
ParasiticnFET
“As Drawn” nFET “As Drawn” Parasitic
tox
Weff
Vt
Circuit modeling of leakagerequires accurate extractionof key parasitic parameters:threshold voltage, effectivewidth, and oxide thickness
2D Modeling Approach
+ +
+++
Standard 2-edge device
Drain Source
Gate
Not
Not
Cutline
2D Cross-section along cutline
Si
STI
gate
++++++
uniform oxidecharge (Not)
Modeling on IBM 0.13um 8RF CMOS
2D Modeling Results
Not = 5x1012 cm2 (uniform)
Vgs = 0.2V
Combination of Not, gate bias,and device properties createselectron inversion layer at theSTI edge
++++++
+++
*
electroninversion
layer
Definition of Threshold Voltage
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
energ
y [eV
]
NOT=5E12 C/cm^2NOT=2E12 C/cm^2NOT=7E12 C/cm^2Ef [eV]
Silicon STI
surface potential
Ef- Ei(0) = s
cutline
Threshold voltage is thegate voltage at which theinversion potential () equalsthe bulk potential.
Note: dependent on Not
density and cutline depth.
bulk potential(B)
Inversion potentialEf – Ei(0) =
-2
0
2
4
6
8
10
12
14
16
18
1 3 5 7
Th
resh
old
vo
ltag
e [V
]Extracting Cox and tox
2F/cm10 x 4.6 8
T
otox ΔV
NqC
Oxide Trapped Charge (1012 cm-2)
Cross overindicates TIDsusceptibility
VT of “as drawn”
VT of parasitic
Slope Cox
nm 76
ox
oxox C
t
Effective width (Weff.)
Parasitic nMOSFET width (Weff.) is dependent on oxide charge, gate bias,and other parameters.
Not = 2x1012 cm2
Vgs = 0.2V
Not = 5x1012 cm2
Vgs = 0.2V
Not = 7x1012 cm2
Vgs = 0.2V
W(2) W(5) W(7)
Effective width (Weff.)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-0.005 0.005 0.015 0.025 0.035 0.045
Width (STI-FET) [um]
Su
rfac
e p
ote
nti
al (
Si/S
TI O
xid
e in
terf
ace)
[V
]
Weff
B
s
Weff is calculated at afixed gate bias and chargedensity over a specifieddepth (Wo).
nm 42
oW
0 SB
eff dw1
W
Volumetric TID Simulations
++++++
… use TCAD rad effects modeling togenerate NOT as function of precursors,dose, dose rate, and electric field
Sheet Charge Trapped Charge vol. distribution
How to relate device response todose, process, and bias conditions …
New CMOS Processing Issues
Retrograde Channel dopingNon uniform doping profile used formodeling variation in channel doping.
NS ~ 1018 (ITRS 2002)
NB > 1019 (Brews TED 8-00)
d = 25 nm (ITRS 2002)
Strained silicon“Both [IBM and Intel] introduced strained silicon” in 90 nm.
- Semiconductor Insights
strained Sichannel
Impact of Retrograde
Without retrograde- wide channel- hi leakage
Examine leakagechannel inside box
With retrograde- thin channel- lo leakage
Will D-S leakage be a problem for 90 nm?