MunEDA Tools and R&D Roadmap

MunEDA WiCkeD 6Integration into Design Architect ICOktober 2008

Christian PargSenior Application EngineerMENTOR GRAPHICS Central Europe

Dr. Volker GlöckelSenior Technical Account ManagerMunEDA GmbH

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Agenda

Mentor IC-Flow— Frontend Overview

MunEDA WiCkeD Overview

MunEDA WiCkeD Integration to DA-IC

On Semi customer reference cases using WiCkeD/DA-IC integration

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Mentor Graphics Custom IC-FlowInteractive Design & Analysis— Interactive Simulation control— DSPF Flow: Parasitic debug— Case frames & Function blocks

Interactive Layout & Verification— In-line Calibre DRC/LVS— Real-time DRC with Calibre rules— IRoute: Interactive routing— Aroute: Integrated auto routing— Device generators and editing— Connectivity-driven layout & ECO

Interactive Data Management— ICstudio environment— Revision control & multi-site collaboration

Migration from Competing flows— Compatible Use models and UI— Design conversion

Design kits (TDKs): Enabling interactive design— TDK Automation

Functional Verification

Eldo, Eldo RFADMS

VerificationExtraction

Calibre DRC/LVSCalibre xRC

LayoutIC Station

AssemblyICassemble

GDS

InteractiveAnalysis

SchematicCapture

DA-IC

SimulationControl

DA-IC SimICstudio

Design & DataManagement

VerilogVHDL

Verilog-AMSVHDL-AMS

3rd PartySynthesis

P&R

RevisionControl

powered byCliosoft

DesignSync

InteractiveVerification

Schematic-drivenLayout

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AgendaInteractive Simulation Control

Interactive Design & Analysis— Interactive Simulation control— DSPF Flow: Parasitic debug— Case frames & Function blocks






Eldo, Eldo RFADMS



LayoutIC Station

AssemblyICassemble

GDS

InteractiveAnalysis

SchematicCapture

DA-IC

SimulationControl

ICanalystICstudio


VerilogVHDL

Verilog-AMSVHDL-AMS

3rd PartySynthesis

P&R

RevisionControl

powered byCliosoft

DesignSync



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Design Architect-ICUnified Design Capture Cockpit

Modern, productive schematic entry with rich feature set

Supports mixed-mode design— Schematic, VHDL, Verilog, SPICE, VHDL-

AMS, or Verilog-A

Special constructs for effective circuit modeling— Case frames, function blocks

Multiple power supply support

Integrated design checking

Integrated netlisting, simulation, and result viewing for:— Eldo, Eldo-RF, ADMS, ModelSim

Back annotation of simulation data— Parasitics, model selections, DCOP, transient

values

Interactive parasitic debug with visual cross-probing

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DA-IC’s Built-in Simulation EnvironmentRapid Setup & Control of Simulation inside DA-IC

Drive analogue, mixed signal, & RF simulations from single cockpitIntegrated netlisting, simulation, and cross-probing of waveformsMulti-run capabilities: sweep, corner case, Monte Carlo setupBack annotation— Parasitics (DSPF) — Digital delays (SDF) — Simulation data: model selections, DCOP,

transient valuesRun

View WavesCross Probe

End Sim

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DA-IC’s Built-in Simulation EnvironmentEfficiently Verify Mixed-signal designs with ADMS

Registration of HDL modelsColors-coded signal typesAutomated insertion of A2D/D2A elementsHierarchical model selectorEZwave cross-probing

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AgendaInteractive Debug of Errors Due to Parasitics

Interactive Design & Analysis— ICanalyst: Interactive Simulation— DSPF Flow: Parasitic debug— Case frames & Function blocks






Eldo, Eldo RFADMS



LayoutIC Station

AssemblyICassemble

GDS

InteractiveAnalysis

SchematicCapture

DA-IC

SimulationControl

ICanalystICstudio


VerilogVHDL

Verilog-AMSVHDL-AMS

3rd PartySynthesis

P&R

RevisionControl

powered byCliosoft

DesignSync



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Challenge: Post-layout Verification Critical to Si-Success Solution: DSPF Flow – Interactively Isolate Problems

Parasitic browsingSelective net expansionX-probe between schematic, layout, waveform

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AgendaDesign Re-Use in DA-IC

Interactive Design & Analysis— ICanalyst: Interactive Simulation— DSPF Flow: Parasitic debug— Case frames & Function blocks






Eldo, Eldo RFADMS



LayoutIC Station

AssemblyICassemble

GDS

InteractiveAnalysis

SchematicCapture

DA-IC

SimulationControl

ICanalystICstudio


VerilogVHDL

Verilog-AMSVHDL-AMS

3rd PartySynthesis

P&R

RevisionControl

powered byCliosoft

DesignSync



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Challenge: Schematic Re-use Solution: Case Frames

Use Case Frames in DA-IC to model:— Pre-Layout parasitics— Off-Chip components— Testbench components— Bondwires

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Challenge: Accelerate Design EntrySolution: Function Blocks to Model Repeated Circuits

Full adder schematic

8-bit adder schematic

8-bit adder function block

Single-bit adder schematic

8-bit adder schematic

8-bit adder function block

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Agenda


MunEDA Wicked Overview

MunEDA Wicked Integration to DA-IC


MunEDA WiCkeD* – Focus: Analysis & Optimization of Circuit Designs

Software tool suit for circuit designersAnalog & mixed-signal transistor levelFull custom digital & library cells

Numerous analysis & optimization modules

* WiCkeD: Worst Case Distances

Improve and optimize Circuit design feasibility & functionalityCircuit design performances & robustnessCircuit design yield & reliability

Seamlessly integrated into Cadence-, Mentor-, Synopsys-based design environmentsNetlist-based standalone & customer SPICE environmentsIndustrial standard SPICE support e.g. Spectre, ELDO, HSpice

MunEDA DFM-DFY Modules & Features

• MunEDA offers a tool suite for circuit analysis, diagnosis, modeling & optimization • All tools are well integrated with industrial standard and in-house design

environments and simulators

Analysis and Sizing of AMS Circuits in Designflow with MunEDA WiCkeD Tools

Microchip-Development

Customer Specification LayoutDesign

time to market

Trash

SalesMicrochip-Production

TestProcess Higher Yield !

Design of AMS & Library Components

Topology-design Simulation

MunEDA: Analysis, Modeling and Optimization of Analog, Mixed-Signal and Digital Circuits & Libraries

Faster by 10-100X!!!

MunEDA Tools Application Flow

Circuit Schematic or Netlist DFM & DFY

Analysis and Optimization

Modules & FlowSized & Optimized Circuit Schematic

or Netlist

Nominal or Statistical Process

Data (PDK)

Analyze & Optimize for Performance, Robustness & Yield

Input Output

Layout

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Agenda





WiCkeD – Eldo Integration Overview

Three MunEDA WiCkeD flows supporting Mentor Graphics Eldo simulator:Standalone—WiCkeD is launched from command line—without cross probing to schematic— result: back-annotated Eldo netlist

Mentor Graphics DA-IC (available in WiCkeD 6) —WiCkeD is launched from DA-IC (both in ICStudio and classic mode) — cross probing to DA-IC schematic— result: back-annotated DA-IC schematic

Cadence Virtuoso-ADE—WiCkeD is launched from ADE— cross probing to Virtuoso schematic— result: back-annotated Virtuoso schematic

WiCkeD Integration Into DA-IC Overview

Mentor Graphics DA-IC integration supports:

Launch WiCkeD from a DA-IC menu entry

Eldo netlist automatically passed to WiCkeD

Cross probing between DA-IC schematic and WiCkeD:—Selection of instances—Highlighting of instances

Back-annotation to DA-IC schematic of:—design parameters like width and length—operating parameters like supply voltage and temperature

WiCkeD integration into DA-IC

Launch WiCkeD from a DA-IC menu entry


Cross probing between DA-IC schematic and WiCkeD— Selection of instances

—Highlighting of instances


Back-annotation to DA-IC schematic of:— design parameters like width and length— operating parameters like supply voltage and temperature

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Agenda





ON Semiconductor®

Optimization of Oscillator Design and Error Amplifier with MunEDA’s WiCkeD

David J. CretellaSenior Design Engineer

Automotive Business Unit, ON Semiconductor, East Greenwich, RI

MTF08-BostonMunEDA Technical Forum 2008 Boston

Tuesday, June 17th 2008Andover, MA

Agenda

• Design Optimization Project 1: Reusing an Oscillator Design (in PS5) By Optimizing using MunEDA’s WiCkeD

• Design Optimization Project 2: Optimizing a Voltage Error Amplifier Using MunEDA’s WiCkeD

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Reusing an Oscillator Design (in PS5)By Optimizing using MunEDA’s WiCkeD

Dave Cretella, Naveen Lokam (ON Semiconductor)

Executive Summary

• Circuit:– Sawtooth oscillator in PS5 process– Previously designed for f = 500 kHz

• Goal:– Architecture re-use for target frequency of 2 MHz– Minimize temperature influence on frequency and duty

cycle• Outcome:

– Using WiCkeD (MunEDA’s tool suite for optimization and analysis), a useful sizing is found in under 2 hrs

– Expected effort for manual transistor tuning: 1 week31

Summary

• Fast design re-use with WiCkeD with Eldo in DA-IC for a 2MHz oscillator in PS5

• Challenge: balance comparators to minimize temperature dependency of duty cycle and frequency

• Optimization with WiCkeD is particularly useful to speed up iterative fine-tuning from 1 week (manually) to 2 hours (WiCkeD)

• Using WiCkeD, all specs fulfilled. Frequency vs. temperature spread reduced by 75%.

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Optimizing a Voltage Error AmplifierUsing MunEDA’s WiCkeD

ON Semiconductor, East Greenwich

WiCkeD Design Project in PS5

Naveen LokamDavid CretellaMarie CrowleySesha AkkinapallyMike Tedeschi

David CretellaNaveen LokamMarie CrowleySesha AkkinapallyMike Tedeschi

Volker GloeckelTom VogelsAndreas Ripp

Rich DesMaraisAndy Nydell

Project Team

Design:DST:

Executive Summary

• Circuit: Voltage Error Amplifier (PS5 process) • Goal:

– Meet aggressive specifications for Gain, Bandwidth, Phase margin, Gain margin.

– Test drive (phase 1) integration of WiCkeD with Eldo and DA-IC / IC Studio in ON Semi environment.

• Outcome:– Using WiCkeD, a useful sizing is found in under 2 days– Expected effort for manual transistor tuning: 2 weeks– WiCkeD enables specification-driven design reuse.

WiCkeD is MunEDA’s tool suite for optimization and analysis

• Circuit optimization results meet expectations from designer:– Found best trade-off among all four performance goals– Used minimal changes of design sizes to meet goals

• Increased quality and efficiency of design phase:– Automatic and interactive circuit sizing facilitates specification-

driven approach– Architecture re-use and exploration of alternatives becomes

reasonable and accessible for designers

• Next steps:– Analyze process and mismatch sensitivities (once mismatch

models are part of setup for PS5)

Summary

Initials Presentation Subject Month 2005/200637

MunEDA Tools and R&D Roadmap

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