Multiprocessors and...

Multiprocessors and Multithreading

Jason Mars

Sunday, March 3, 13

Parallel Architectures for Executing Multiple Threads

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• Multiprocessor – multiple CPUs tightly coupled enough to cooperate on a single problem.

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• Multithreaded processors (e.g., simultaneous multithreading) – single CPU core that can execute multiple threads simultaneously.

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• Multicore processors – multiprocessor where the CPU cores coexist on a single processor chip.

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Multiprocessors

• Not that long ago, multiprocessors were expensive, exotic machines – special-purpose engines to solve hard problems.

• Now they are pervasive.

Cache

Processor

Cache

Processor

Cache

Processor

Single bus

Memory I/O

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Classifying Multiprocessors

• Flynn Taxonomy

• Interconnection Network

• Memory Topology

• Programming Model

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Flynn Taxonomy

• SISD (Single Instruction Single Data)• Uniprocessors

• SIMD (Single Instruction Multiple Data)• Examples: Illiac-IV, CM-2, Nvidia GPUs, etc.

• Simple programming model• Low overhead

• MIMD (Multiple Instruction Multiple Data)• Examples: many, nearly all modern multiprocessors or multicores

• Flexible• Use off-the-shelf microprocessors or microprocessor cores

• MISD (Multiple Instruction Single Data)• ???

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Interconnection Networks

• Bus• Network• pros/cons?

Cache

Processor

Cache

Processor

Cache

Processor

Single bus

Memory I/O

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Memory Topology

• UMA (Uniform Memory Access)• NUMA (Non-uniform Memory Access)• pros/cons?

cpu

cpu

cpu

cpu

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M

M

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Network

Cache

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Cache

Processor

Cache

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Single bus

Memory I/O

Network

Cache

Processor

Cache

Processor

Cache

Processor

Memory Memory Memory

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Programming Model

• Shared Memory -- every processor can name every address location• Message Passing -- each processor can name only it’s local memory.

Communication is through explicit messages.• pros/cons?

Network

Cache

Processor

Cache

Processor

Cache

Processor


Sunday, March 3, 13

Programming Model

• Shared Memory -- every processor can name every address location• Message Passing -- each processor can name only it’s local memory.

Communication is through explicit messages.• pros/cons?

Network

Cache

Processor

Cache

Processor

Cache

Processor


find the max of 100,000 integers on 10 processors.

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Parallel Programming

• Shared-memory programming requires synchronization to provide mutual exclusion and prevent race conditions• locks (semaphores)• barriers

Processor A index = i++;

Processor B index = i++;

i = 47

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i = 47

load i;inc i;

store i;

load i;inc i;

store i;

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i = 47

load i;inc i;

store i;load i;inc i;

store i;

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i = 47

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i = 47

load i;

inc i;

store i;

load i;

inc i;

store i;

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But...

• That ignores the existence of caches

• How do caches complicate the problem of keeping data consistent between processors?

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Multiprocessor Caches (Shared Memory)

• the problem -- cache coherency

• the solution?

Cache

Processor

Cache

Processor

Cache

Processor

Single bus

Memory I/O

ii

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• the solution?

Cache

Processor

Cache

Processor

Cache

Processor

Single bus

Memory I/O

i

inc i;

i

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• the solution?

Cache

Processor

Cache

Processor

Cache

Processor

Single bus

Memory I/O

i

inc i;load i;

i

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What Does Coherence Mean?

• Informally:

• Any read must return the most recent write

• Too strict and very difficult to implement

• Better:

• A processor sees its own writes to a location in the correct order.

• Any write must eventually be seen by a read

• All writes are seen in order (“serialization”). Writes to the same location are seen in the same order by all processors.

• Without these guarantees, synchronization doesn’t work

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Solutions

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Solutions

• Snooping Solution (Snoopy Bus):• Send all requests for unknown data to all processors• Processors snoop to see if they have a copy and respond accordingly • Requires “broadcast”, since caching information is at processors• Works well with bus (natural broadcast medium)• Dominates for small scale machines (most of the market)

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Solutions

• Snooping Solution (Snoopy Bus):• Send all requests for unknown data to all processors• Processors snoop to see if they have a copy and respond accordingly • Requires “broadcast”, since caching information is at processors• Works well with bus (natural broadcast medium)• Dominates for small scale machines (most of the market)

• Directory-Based Schemes• Keep track of what is being shared in one centralized place (for each

address) => the directory• Distributed memory => distributed directory (avoids bottlenecks)• Send point-to-point requests to processors (to invalidate, etc.)• Scales better than Snooping for large multiprocessors

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Implementing Coherence Protocols

• How do you find the most up-to-date copy of the desired data?

• Snooping protocols

• Directory protocols

Cache tagand data

Processor

Single bus

Memory I/O

Snooptag

Cache tagand data

Processor

Snooptag

Cache tagand data

Processor

Snooptag

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Implementing Coherence Protocols

• How do you find the most up-to-date copy of the desired data?

• Snooping protocols

• Directory protocols

Cache tagand data

Processor

Single bus

Memory I/O

Snooptag

Cache tagand data

Processor

Snooptag

Cache tagand data

Processor

Snooptag

Write-Update vs Write-Invalidate

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Dean Tullsen

Simultaneous Multithreading

(A Few of Dean Tullsen’s 1996 Thesis Slides)

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Dean Tullsen

Hardware Multithreading

Conventional Processor

PC

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Dean Tullsen



PC

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Multithreaded

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Dean Tullsen



PC

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CPU

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PC

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Multithreaded

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Dean Tullsen



PC

regs

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PC

regsPC

regs

Multithreaded

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Dean Tullsen



PC

regs

CPU

inst

ruct

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stre

am

PC

regs

PC

regsPC

regs

Multithreaded

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Superscalar (vs Superpipelined)

(multiple instructions in the same stage, same CR as scalar)

(more total stages, faster clock rate)

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Dean Tullsen

Superscalar Execution

Issue SlotsTime (proc cycles)

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Dean Tullsen


Issue SlotsTime (proc cycles) Vertical waste

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Dean Tullsen


Issue SlotsTime (proc cycles) Vertical waste

Horizontal waste

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Dean Tullsen

Superscalar Execution with Fine-Grain Multithreading


Thread 1

Thread 2

Thread 3

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Dean Tullsen



Thread 1

Thread 2

Thread 3

Thread 4

Thread 5

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Dean Tullsen

SMT Performance

0

1.7500

3.5000

5.2500

7.0000

1 2 3 4 5 6 7 8

Thro

ughp

ut (I

nstru

ctio

ns p

er C

ycle

)

Number of Threads


Fine-Grain Multithreading

Conventional Superscalar

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Multicore Processors (aka Chip Multiprocessors)

• Multiple cores on the same die, may or may not share L2 or L3 cache.

• Intel, AMD both have quad core processors. Sun Niagara T2 is 8 cores x 8 threads (64 contexts!)

• Everyone’s roadmap seems to be increasingly multi-core.

CPU CPU CPU

CPU CPU CPU

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The Latest Processors

Tegra 3 (5 Cores) Intel Nehalem (4 Cores)Multicore Multicore + SMT

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Nehalem

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Nehalem

Fetch

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Nehalem

Fetch

Decode

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Nehalem

Fetch

Decode

Execute

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Nehalem

Fetch

Decode

Execute

Mem/WB

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CSE 141 Dean Tullsen

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Nehalem in a Nutshell

• Up to 8 cores (i7, 4 cores)• 2 SMT threads per core• 20+ stage pipeline• x86 instructions translated to RISC-like uops• Superscalar, 4 “instructions” (uops) per cycle (more with fusing)• Caches (i7)

• 32KB 4-way set-associative I cache per core• 32KB, 8-way set-associative D cache per core• 256 KB unified 8-way set-associative L2 cache per core• 8 MB shared 16-way set-associative L3 cache

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Key Points

Sunday, March 3, 13

Key Points

• Network vs. Bus

Sunday, March 3, 13

Key Points

• Network vs. Bus

• Message-passing vs. Shared Memory

Sunday, March 3, 13

Key Points

• Network vs. Bus


• Shared Memory is more intuitive, but creates problems for both the programmer (memory consistency, requiring synchronization) and the architect (cache coherency).

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Key Points

• Network vs. Bus



• Multithreading gives the illusion of multiprocessing (including, in many cases, the performance) with very little additional hardware.

Sunday, March 3, 13

Key Points

• Network vs. Bus



• Multithreading gives the illusion of multiprocessing (including, in many cases, the performance) with very little additional hardware.

• When multiprocessing happens within a single die/processor, we call that a chip multiprocessor, or a multi-core architecture.

Sunday, March 3, 13

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