Int. J. Electron. Commun. (AEÜ) 113 (2020) 152947

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International Journal of Electronics andCommunications (AEÜ)

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Regular paper

Multiplierless chaotic Pseudo random number generators

https://doi.org/10.1016/j.aeue.2019.1529471434-8411/� 2019 Elsevier GmbH. All rights reserved.

⇑ Corresponding author.E-mail address: aayman@nu.edu.eg (A.A. Rezk).

Ahmed A. Rezk a,⇑, Ahmed H. Madian a,c, Ahmed G. Radwan a,b, Ahmed M. Soliman d

aNISC Research Center, Nile University, Cairo, EgyptbDept. of Engineering Mathematics and Physics, Cairo University, EgyptcRadiation Engineering Dept., NCRRT, Egyptian Atomic Energy, Authority, Egyptd Electronics and Comm. Eng. Dept., Cairo University, Egypt

a r t i c l e i n f o

Article history:Received 8 August 2019Accepted 6 October 2019

Keywords:PRNGFPGANISTChaos

a b s t r a c t

This paper presents a multiplierless based FPGA implementation for six different chaotic Pseudo RandomNumber Generators (PRNGs) that are based on: Chua, modified Lorenz, modified Rössler, FrequencyDependent Negative Resistor (FDNR) oscillator, and other two systems that are modelled using the simplejerk equation. These chosen systems can be employed in high speed applications because they don’t uti-lize any hardware multiplier. The proposed PRNGs have been implemented using VHDL, synthesized onXilinx, using the FPGA: XC5VLX50T, and tested using the NIST statistical suite. Furthermore, a comparisonhas been established between the performance of all the PRNGs, regarding the implementation area,speed, and the statistical randomness quality. It has been found that the modified Lorenz PRNG hasthe best randomness quality and the best hardware performance as it can pass all the NIST tests whileoperating at 298.597 MHz and utilizing only 0.23% and 0.62% from the FPGA’s slice registers and Look-Up-Tables (LUTs) respectively.

� 2019 Elsevier GmbH. All rights reserved.

1. Introduction

Random number generators have been used in a wide variety ofapplications, such as cryptography [1,17,18], Monte Carlo simula-tors [2], and Artificial Neural Networks [3]. Random number gener-ators are classified into two main families: True Random NumberGenerators (TRNGs) and Pseudo Random Number Generators(PRNGs) [4].

The TRNGs are used to generate random numbers by exploitingphysical processes, such as the thermal noise or jitter. However,the TRNGs are not employed in encryption applications becausethey cannot generate two identical sequences of random numbersfor the ciphering and deciphering operations respectively. The onlypossible solution for this problem is to store the generated randomnumbers in a memory. Furthermore, the TRNGs suffer from a lowbit generation rate, in the range of hundreds of kilobits per second;hence, they are not used in high speed applications [4].

On the other hand, the PRNGs are based on deterministic func-tions that continuously update the PRNG’s current state leading toa sequence of random states. Moreover, the PRNGs are imple-mented in the digital domain using computers or FPGAs; therefore,they can be employed in high speed applications. However, in the

digital world there is only a finite number of states that can be pro-duced. For example, in case the PRNG’s states are representedusing k-bits, the PRNG will produce up to 2 k different randomstates and then will repeat the same sequence of states again. Toovercome this problem, the PRNGs designers must increase theperiodic length as much as possible. Accordingly, a lot of researchhas been conducted to find the suitable state transition matricesthat can deal with many state bits, k, and maintain the maximumperiodic length 2 k as well [4,5].

The Chaos based PRNGs are characterized by having an infiniteperiodic length; however, since they are solved using numericalmethods on computers, the finite precision of the digital domainwill lead to a finite periodic length. This problem can be solvedin FPGAs by simply increasing the number of fractional bits atthe expense of degrading the implementation area and speed [6].Furthermore, the chaotic PRNGs are very sensitive to the initialcondition; thus, they are used in many encryption applicationswhere the initial condition is set according to the encryption key.

The Lorenz [7] and Rössler [8] are considered the most famouschaotic systems and they have been used in a lot of cryptographicapplications [9,10]. However, these systems are based on non-linear multiplications that degrade the system’s performance,regarding the number of utilized hardware resources and speed.Therefore, newer versions, called the modified Rössler and modi-fied Lorenz, were presented in [11,12]. These modified versions

2 A.A. Rezk et al. / Int. J. Electron. Commun. (AEÜ) 113 (2020) 152947

do not require the hardware expensive multipliers that limit thesystem’s performance. Moreover, there are a lot of other chaoticsystems [13,14] that do not require hardware multipliers; andtherefore, are considered attractive for small area and high-speedapplications.

This paper presents a design methodology for realizing multi-plierless chaotic PRNGs that are based on Chua [13], modifiedRössler [11], modified Lorenz [12], Frequency Dependent NegativeResistor (FDNR) oscillator [11], in addition to other two systemsthat capture the double scroll and Rössler dynamics using the sim-ple jerk equation [11,12]. A performance comparison for all thementioned PRNGs have been presented in this paper, regardingthe NIST [15] statistical randomness quality, implementation area,and speed. The paper is organized as follows. Section 1 presents theintroduction. Section 2 presents the FPGA implementation of thePRNGs. Section 3 presents the synthesis and NIST results. Section 4presents the conclusion.

2. The FPGA implementation of the chaotic PRNGs

Chaotic systems are modelled by differential equations that canbe solved using numerical methods. The Euler’s method is usuallyemployed in high speed PRNGs where the approximation error isnot a matter of high concern [16]. Hence, in this paper, the chaoticsystems are solved using Euler’s method as shown in (1) where Xi

is the system’s variable, _Xi is the system’s differential equation, thesubscript i is the iteration index, and h is the step size.

Xiþ1 ¼ Xi þ h � _Xi ð1ÞEq. (1) is realized using a loadable accumulator as shown in

Fig. 1. The hardwired shifter (�m), which doesn’t utilize any hard-ware resource, is used to perform the multiplication by the stepsize h where h is equal to 2�m. The Reset signal and the multiplexerare used to set the initial point, X0, of the Register. The 2’s comple-ment fixed point scheme is used in this paper where the fractionalpart of all the calculated values is represented using the samenumber of bits, N bits. On the other hand, the amount of integerbits is adjusted according to the ranges of the variables.

2.1. PRNG1: Chua

The Chua system is modelled using (2) where a, b, m0, and m1

are the system’s parameters [13].

_X ¼ a Y � hðXÞð Þ ð2-aÞ

_Y ¼ X � Y þ Z ð2-bÞ

_Z ¼ �b � Y ð2-cÞ

h Xð Þ ¼m1X þm0 �m1; X � 1m0X; Xj j � 1m1X �m0 þm1; X � �1

8><>: ð2-dÞ

X Reg

01

+Xi+1

X0Reset

XiẊi>>m

Clk

Fig. 1. The Hardware realization of Euler’s method.

In this paper, the parameters and the step size (a, b, m0, m1, h)are set to (23, 24, �2�3, 2�2, 2�4) respectively; hence, all the multi-plications are performed using hardwired shifters. Furthermore,the truncation rounding scheme is performed after any multiplica-tion in order to maintain the same N fractional bits. Moreover,based on MATLAB simulations, the ranges of the system’s variablesare �2.36 � X � 2.36, �0.54 � Y � 0.54, and �3.73 � Z � 3.73.Therefore, the sizes of the loadable accumulators of the X, Y, andZ variables are (3 + N)-bits, (1 + N)-bits, and (3 + N)-bits respec-tively. The hardware realization of the system is presented in Fig. 2.

The most complex part of the circuit is the realization of (2-a)because of the comparisons that are available in the function h(X). From (2-d), in case the absolute value of X is less than 110, Xwill be multiplied by m0, otherwise X will be multiplied by m1.However, m0 is negative; therefore, the multiplication by m0 can-not be performed using a hardwired shifter only because an adderis needed to compute the 2’s complement of the shifted value. Tooptimize the design, this adder is merged with the last adder/sub-tractor that is available in the path that leads to Xi. Accordingly, (2-a) and (2-d) are realized as follows. First a comparator is used tocompare |X| with 110 by using the 3 Most Significant integer Bits(MSBs) of X, and then the comparator’s output, S, is used to controla multiplexer that selects between �m0X and m1X. The output ofthis multiplexer will have at most 1 integer bit. Moreover, accord-ing to the comparator’s output and the sign of X, the multiplexer’soutput will be added to ±(�m0 + m1), or 010. These two options canbe represented as 00SS2 using 1 integer bit and 3 fractional bitsonly. Therefore, only a 4-bit adder/subtractor, which is controlledby the sign bit of X, is needed because the remaining fractional bitswill remain unchanged. Finally, the second (1 + N)-bit adder/sub-tractor, which is controlled by S, is used to finalize the computationof (2-a). Thus, the critical path that generates Xi includes two logicgates, one multiplexer, one 4-bit adder/subtractor, one (1 + N)-bitadder/subtractor, in addition to the (3 + N)-bit loadableaccumulator.

The hardware realization of (2-b) and (2-c) is simple. (2-c) isrealized using the loadable accumulator only. On the other hand,(2-b) is more complicated and requires another (3 + N)-bit adderand (3 + N)-bit subtractor. Thus, the critical path that generates Yiincludes one (3 + N)-bit adder, one (3 + N)-bit subtractor, and the(1 + N) loadable accumulator.

2.2. PRNG2: modified Rössler

The modified Rössler system, which doesn’t include any non-linear multiplication as in the case of the original Rössler system,is modelled as shown in (3) where A, C, a1, and a2 are the system’sparameters [11].

_X ¼ � Y þ Zð Þ ð3-aÞ

_Y ¼ X þ AY ð3-bÞ

_Z ¼ BX � CZ ð3-cÞ

B ¼ a1; X � 1a2; X < 1

�ð3-dÞ

The system’s variables and the step size (A, C, a1, a2, h) areadjusted to (2�2, 1, 22, 0, 2�4) respectively. By simulating the sys-tem on Matlab it has been revealed that the ranges of the variablesare �1.64 � X � 1.58, �2.14 � Y � 1.31, and 0 � Z � 3.38. There-fore, the sizes of the loadable accumulators of the X, Y, and Z vari-ables are (2 + N)-bits, (3 + N)-bits, and (3 + N)-bits respectively. Theblock diagram of the system is presented in Fig. 3.

01

—

Z0

Yi Zi+1 Zi—+

Xi

>>4 + 01

Y0

Yi+1

01

X0

>>1 +Xi+1

Reset

Reset Reset

01

>>3

>>2+/–+/–

Xi (2+N)

Xi (1+N)

Xi (N)

SS

‘00SS0..0’Clk Clk

Clk

3+Nbit

Reg

3+Nbit

Reg

1+Nbit

Reg

Fig. 2. The block diagram of the Chua system.

Reset

>>4 +

X0

01

Yi+1– 01

Xi+1

+ 01

Zi+1

+Xi

Zi

Yi

>>2

>>4+

Xi (N+1)

×

Xi (N)

<<2 – >>4

Y0

Z0

Reset

Reset

Clk Clk

Clk

2+Nbit

Reg

3+Nbit

Reg

3+Nbit

Reg

Fig. 3. The block diagram of the modified Rössler system.

A.A. Rezk et al. / Int. J. Electron. Commun. (AEÜ) 113 (2020) 152947 3

The hardware realization of (3-a) and (3-b) is straight forward.The critical path that generates Yi includes one (2 + N)-bit adder inaddition to the (3 + N)-bit loadable accumulator. Similarly, the crit-ical path that leads to Xi includes a (3 + N)-bit adder and the (2+ N)-bit loadable accumulator.

On the other hand, the hardware realization of (3-c) and (3-d)requires a comparator that adds extra overhead to the system. For-tunately, the small number of integer bits in X has been exploitedto speed up the comparison between X and 110 by using only twologic gates that deal with the 2 MSBs of X. The comparator’s outputwill be multiplied by a1. X using AND gates only. In this way, ifX � 1, X will be multiplied by a1 = 22, otherwise, X will be multi-plied by 010. The rest of the design is straight forward. The criticalpath that leads to Zi includes three logic gates, one (4 + N)-bit sub-tractor and the (3 + N)-bit loadable accumulator.

2.3. PRNG3: modified Lorenz

The modified Lorenz system, which doesn’t utilize non-linearmultipliers as the original Lorenz system, is modelled as shownin (4) where a, b, and c are the system’s parameters. [12]

_X ¼ a Y � Xð Þ ð4-aÞ

_Y ¼ �sgn Xð Þ:ðZ � bÞ ð4-bÞ

_Z ¼ sgn Xð Þ:X � cZ ð4-cÞ

sgnðXÞ ¼ þ1; X � 0�1; X < 0

�ð4-dÞ

4 A.A. Rezk et al. / Int. J. Electron. Commun. (AEÜ) 113 (2020) 152947

The system’s variables and the step size (a, b, c, h) are adjustedto (2�1, 2�1, 2�2, 2�4) respectively. The ranges of the system’s vari-ables are �0.45 � X � 0.71, �1.25 � Y � 1.01, and 0.012 � Z � 1.01.Therefore, the sizes of the loadable accumulators of the X, Y, and Zvariables are (1 + N)-bits, (2 + N)-bits, and (2 + N)-bits respectively.The block diagram of the system is presented in Fig. 4.

The critical path that leads to Xi includes one (2 + N)-bit sub-tractor in addition to the (1 + N)-bit loadable accumulator. Simi-larly, the critical path that leads to Zi includes a (1 + N)-bitadder/subtractor, which is controlled by the sign bit of X, in addi-tion to the (2 + N)-bit loadable accumulator. On the other hand,the critical path that leads to Yi can be optimized by taking intoconsideration that b, which is equal to 0.510, can be representedusing 1 fractional bit and 1 integer bit only. Hence, (Z–b) is com-puted using a 3-bits subtractor that deals with the 2 integer bitsof Z in addition to its most significant fractional bit. The rest ofthe fractional bits of (Z–b) will be connected directly to the corre-sponding fractional bits of Z. In this way the critical path that leadsto Yi will include a 3-bit subtractor in addition to the (2 + N)-bitloadable accumulator that performs addition or subtraction basedon the MSB of X.

2.4. PRNG4: FDNR based chaotic oscillator

The FDNR based chaotic system is modelled using (5) where a,b, e1, e2, and k are the system’s parameters [11].

_X ¼ 1e1

Y � X � Zð Þ ð5-aÞ

€Y ¼ 1k

X � Y � e2 _Y � f Yð Þ� �

ð5-bÞ

_Z ¼ bX ð5-cÞ

f ðYÞ ¼ aY � 1; Y � 10; Y < 1

�ð5-dÞ

In this paper, the parameters and the step size (a, b, e1, e2, k, h)are adjusted to (26, 2�5, 2�5, 1, 23, 2�5) respectively. Accordingly,the system is solved using Euler’s method as shown in (6). Thechoice of equalizing h and e1 has simplified the calculation of thevariable Xi+1 as shown in (6-a).

Xiþ1 ¼ Yi � Zi ð6-aÞ

Reset

>>4

Y0

+/– 01

Yi+1 Yi–

0.510

Xi (N)

Clk

2+Nbit

Reg

Fig. 4. The block diagram of th

_Yiþ1 ¼ _Yi þ 2�8 Xi � Yi � _Yi � f Yið Þ� �

ð6-bÞ

Yiþ1 ¼ Yi þ 2�5 _Yi ð6-cÞ

Ziþ1 ¼ Zi þ 2�10Xiþ1 ð6-dÞ

f ðYiÞ ¼ 26 Yi � 1; Yi � 10; Yi < 1

�ð6-eÞ

The ranges of the system’s variables are �1.89 � X � 1.67,�2.15 � Y � 1.17, �0.62 � Z � 0.29, and �0.467 � _Y � 0.44. There-fore, the sizes of the loadable accumulators of the X, Y, Z, and _Y are(2 + N)-bits, (3 + N)-bits, (1 + N)-bits, and (1 + N)-bits respectively.The block diagram of the PRNG is presented in Fig. 5.

In this PRNG, (6-a) cannot be realized using the loadable accu-mulator because Xi+1 doesn’t depend directly on Xi. Hence, the crit-ical path that leads to Xi includes a (3 + N)-bits subtractor and amultiplexer. On the other hand, the hardware realization of (6-c)and (6-d) is straight forward and is realized using the loadableaccumulators only.

The most complex part of the circuit is the comparison in (6-e).Like the previous circuits, the small number of integer bits in Y hasbeen exploited to optimize the comparator by examining only the3 MSBs of Y. Furthermore, the small number of integer bits in Y hasreduced the size of the subtractor that computes (Yi � 110) to a 3-bit subtractor only because the fractional bits of Yi and (Yi � 110)are the same. The hardware realization of (6-e) is completed bymultiplying (Yi � 110) by the comparator’s output using AND gatesonly. The rest of the hardware realization of Eq. (6-b) is straightforward. The critical path that leads to _Yi includes a 3-bit subtrac-tor, 1 logic gate, a (3 + N)-bit adder, (9 + N)-bits subtractor, and the(1 + N)-bits loadable accumulator.

2.5. PRNG5: simple equation modelling for the double scroll-likedynamics

A simple double scroll chaotic system is modelled using (7)where a is the system’s parameter [12]. In this paper the valuesof a and the step size h are set to 2�1 and 2�6 respectively.

Xv¼ �a €X þ _X þ X � sgn Xð Þ

� �ð7Þ

+ 01

Xi+1

– 01

Zi+1

–

Zi

Xi>>5

+/– >>4

X0

Z0

Reset

Reset

>>2

Clk

Clk

1+Nbit

Reg

2+Nbit

Reg

e modified Lorenz system.

01

>>10 +Zi+1 ZiXi

01

–Xi+1Yi

01

+Yi+1>>5

X0 Z0Y0Reset Reset Reset

01

+Ẏi+1

Ẏ0Reset

Ẏi>>8–

+

–

–

110

<<6×

Yi (N+2)

Yi (N+1)

Yi (N)

Clk Clk Clk

Clk

2+Nbit

Reg

3+Nbit

Reg

1+Nbit

Reg

1+Nbit

Reg

Fig. 5. The block diagram of the FDNR chaotic generator.

A.A. Rezk et al. / Int. J. Electron. Commun. (AEÜ) 113 (2020) 152947 5

The ranges of the system’s variables are �2.62 � X � 2.62,�1.74 � _X � 1.74, and �1.2 � €X � 1.2; therefore, the sizes of theloadable accumulators are (3 + N), (2 + N), and (2 + N)-bits respec-tively. The block diagram of this PRNG is shown in Fig. 6. The partof the circuit that computes (X–sgn(X)) is optimized by taking intoconsideration that the integer part of X has three bits only. There-fore, only a 3-bit subtractor is used to calculate (X–sgn(X)). The out-put of sgn(X) has three integer bits where the LSB is always equal tologic ‘10 while the two most significant bits are equal to the sign bitof X. The critical path of the circuit includes two (3 + N)-bits addersin addition to the (2 + N)-bits loadable accumulator.

2.6. PRNG6: simple equation modelling for the Rössler system

The dynamics of Rössler system can be captured with a simpledifferential equation as shown in (8) where a1 and a2 are theparameters [11]. In this paper, (a1, a2, h) are set to (23, 0, 2�4)respectively.

Xv¼ €X þ B _X þ X

� �ð8-aÞ

+>>6

+

— sgn+>>1

— 01

Ẋ0Ẍ0

>>6

Reset

Ẍi Ẋi+1Ẍi+1

ResetClk Clk

2+Nbit

Reg

Fig. 6. The block diagram of a simp

B ¼ a1; X � 1a2; X < 1

�ð8-bÞ

The ranges of the variables are �2.75 � X � 2.94,�3.54 � _X � 3.93, and �10.56 � €X � 6.67; hence, the sizes of theloadable accumulators are (3 + N), (3 + N), and (5 + N)-bits respec-tively. The hardware realization of the system is presented in Fig. 7.The comparison in (8-b) is realized as explained previously inPRNG4 using three logic gates only. Then, (8-b) is computed bymultiplying the comparator’s output with a1 _Xi using AND gatesonly. Accordingly, the critical path of the circuit includes threelogic gates, two (7 + N)-bit adders, and the (5 + N) loadableaccumulator.

3. Performance analysis and comparison of the PRNGs

The proposed PRNGs have been implemented using VHDL andsynthesized using Xilinx 13.1 ISE where the target FPGA isXC5VLX50T. The number of utilized LUTs and registers, and themaximum operating frequency are summarized in Table 1 wherethe proposed PRNGs have been realized using 20 fractional bits.

+>>6 01

01

X0

XiẊi Xi+1

ResetClk

3+Nbit

Reg

2+Nbit

Reg

le double scroll chaotic system.

+>>4 01

+>>4 01

— 01

Ẋ0Ẍ0 X0

>>4

Reset

XiẊiẌi Xi+1Ẋi+1Ẍi+1

Reset Reset

<<3

× ++Xi(N+2)

Xi(N+1)

Xi(N)

Clk Clk Clk

3+Nbit

Reg

3+Nbit

Reg

5+Nbit

Reg

Fig. 7. The block diagram of a simple chaotic system that captures the dynamics of the Rössler system.

Table 1FPGA synthesis results of the chaotic PRNGs.

System PRNG1 PRNG2 PRNG3 PRNG4 PRNG5 PRNG6 [9] [10]

FPGA XC5VLX50T Zynq 7000Slice LUTs 200 224 178 246 175 191 433 868Slice Registers 67 68 65 87 67 71 96 96DSP blocks 0 0 0 0 0 0 12 8Frequency/MHz 233.672 295.508 298.597 219.214 271.209 215.785 70.9 36.31

Fig. 8. Post synthesis simulation of the modified Lorenz system while operating at maximum speed.

6 A.A. Rezk et al. / Int. J. Electron. Commun. (AEÜ) 113 (2020) 152947

Furthermore, Table 1 includes the performance of other two chao-tic PRNGs that were presented in [9] and [10]. As shown in Table 1,the 3rd PRNG, which is based on the modified Lorenz system, hasthe best performance as it can operate at 298.597 MHz and utilizeonly 65 out of 28,800 and 178 out of 28,800 slice registers and LUTsrespectively. According to XILINX XPOWER analyzer, the powerconsumption of all the PRNGs is approximately 0.5 W. Fig. 8 shows

Table 2NIST statistical results for the PRNGs.

System PRNG1 PRNG2

Frequency 0.98U 0 ✗

Block Frequency 1 U 0 ✗

Cumulative Sums 0.98U 0 ✗

Runs 1 U 0.01✗Longest Run 1 U 1 U

Rank 0.98U 0.98UFFT 0.99U 1 U

Nonoverlapping Template 0.95✗ 0 ✗

Overlapping Template 0.99U 0.99UUniversal 0.99U 0.16✗Approximate Entropy 1 U 0.08✗Random Excursions 0.957U 0.875✗Random Excursions variant 0.957U 0.875✗Serial 1 U 0.74✗Linear Complexity 1 U 0.99U

the post synthesis simulation results of the modified Lorenz sys-tem while operating at maximum speed.

Furthermore, a VHDL test bench has been designed to simulatethe proposed PRNGs and generate 24 random bits per clock cycle,which is suitable for image stream ciphering applications whereeach image pixel consists of 24-bits. In case the PRNG has threevariables, as in PRNG1,2,3,5 and 6, the 24 bits are captured from the

PRNG3 PRNG4 PRNG5 PRNG6

0.97U 0.97U 0.97U 0.98U0.99U 0.82✗ 1 U 1 U

0.97U 0.94✗ 0.97U 0.98U1 U 0.99U 1 U 0.98U0.98U 0.98U 0.97U 1 U

0.98U 0.99U 1 U 0.99U0.99U 0.67✗ 0.98U 0.98U0.96U 0.95✗ 0.94✗ 0.95✗0.99U 0.99U 0.97U 1 U

1 U 1 U 0.98U 0.99U1 U 1 U 0.98U 0.99U0.963U 0.964U 0.984U 0.965U0.981U 0.947✗ 0.983U 0.966U0.98U 0.99U 0.99U 0.98U1 U 1 U 1 U 0.98U

(a) (b)

(c) (d)

(e) (f)

-0.7

0

0.7

-3 0 3-2.2

0

2.2

-1.7 0 1.7

-0.7

0

0.7

-0.5 0 0.5-1.8

0

1.8

-1.5 0 1.5

-1.8

0

1.8

-2.7 0 2.7-3.6

-1.8

0

1.8

3.6

-3 0 3

Fig. 9. The X-Y chaotic attractors of the chaotic PRNGs. (a)–(f): PRNGs (1)–(6).

A.A. Rezk et al. / Int. J. Electron. Commun. (AEÜ) 113 (2020) 152947 7

8 LSBs of each chaotic variable. On the other hand, in case thePRNG has four variables, as in PRNG4, the 24-bits are captured fromthe 6 LSBs of each chaotic variable. For each PRNG, the NIST testsare applied on a stream of 100 million random bits that is dividedinto 100 sequences. The NIST suite includes 15 major tests wheresome of these tests includes several subtests. In case there aremore than one subtest, as in the case of the non-overlapping tem-plate, only the worst subtest result will be taken intoconsideration.

The NIST statistical results are summarized in Table 2 for all thePRNGs. These results show the percentage of sequences that havepassed the tests. The passing criteria for each test is approximately96%. As shown in Table 2, only the 3rd PRNG can pass all the NISTtests. Thus, the 3rd PRNG (Modified Lorenz) is the most efficientPRNG as it has the best hardware performance and the best statis-tical randomness quality.

Finally, another VHDL test bench has been implemented to plotthe chaotic attractors of the proposed PRNGs as shown in Fig. 9.

4. Conclusion

A design methodology for implementing multiplierless chaoticPRNGs on FPGAs has been presented in this paper. The proposedmethodology has been used to implement six different chaoticPRNGs. It has been found that the modified Lorenz PRNG has thebest hardware performance, because it requires a small numberof additions and subtractions that can be performed in parallel.Furthermore, the modified Lorenz has the smallest number of inte-ger bits; therefore, the implementation area and delay of the

adders and subtractors are lower than the other PRNGs. The sixPRNGs have been realized using VHDL, with the same number offractional bits, and implemented on XC5VLX50T. The synthesisand NIST statistical results have showed that only the modifiedLorenz can pass all the NIST tests and achieve the best hardwareperformance compared to the other PRNGs.

Declaration of Competing Interest

The authors of this paper declare that there is no conflict ofinterest.

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