Computer Organization Computer Organization and Architectureand Architecture

Lecture 3Lecture 3

Multiple InterruptsMultiple InterruptsDisable interruptsDisable interrupts•• Processor will ignore further interrupts while Processor will ignore further interrupts while

processing one interruptprocessing one interrupt•• Interrupts remain pending and are checked Interrupts remain pending and are checked

after first interrupt has been processedafter first interrupt has been processed•• Interrupts handled in sequence as they occurInterrupts handled in sequence as they occurDefine prioritiesDefine priorities•• Low priority interrupts can be interrupted by Low priority interrupts can be interrupted by

higher priority interruptshigher priority interrupts•• When higher priority interrupt has been When higher priority interrupt has been

processed, processor returns to previous processed, processor returns to previous interruptinterrupt

Multiple Interrupts Multiple Interrupts -- SequentialSequential

Time Sequence of Multiple Time Sequence of Multiple InterruptsInterrupts

ConnectingConnecting

All the units must be connectedAll the units must be connectedDifferent type of connection for Different type of connection for different type of unitdifferent type of unit•• MemoryMemory•• Input/OutputInput/Output•• CPUCPU

Computer ModulesComputer Modules

What is a busWhat is a bus

A communication pathway A communication pathway connecting two or more devicesconnecting two or more devicesUsually broadcast Usually broadcast Often groupedOften grouped•• A number of channels in one busA number of channels in one bus•• e.g. 32 bit data bus is 32 separate e.g. 32 bit data bus is 32 separate

single bit channelssingle bit channels

Power lines may not be shownPower lines may not be shown

Data BusData Bus

Carries dataCarries data•• Remember that there is no difference Remember that there is no difference

between between ““datadata”” and and ““instructioninstruction”” at this at this levellevel

Width is a key determinant of Width is a key determinant of performanceperformance•• 8, 16, 32, 64 bit8, 16, 32, 64 bit

Address busAddress bus

Identify the source or destination of Identify the source or destination of datadatae.g. CPU needs to read an instruction e.g. CPU needs to read an instruction (data) from a given location in (data) from a given location in memorymemoryBus width determines maximum Bus width determines maximum memory capacity of systemmemory capacity of system•• e.g. 8080 has 16 bit address bus giving e.g. 8080 has 16 bit address bus giving

64k address space64k address space

Control busControl bus

Control and timing informationControl and timing information•• Memory read/write signalMemory read/write signal•• Interrupt requestInterrupt request•• Clock signalsClock signals

Bus Interconnection SchemeBus Interconnection Scheme

Single Bus ProblemsSingle Bus Problems

Lots of devices on one bus leads to:Lots of devices on one bus leads to:•• Propagation delaysPropagation delays

Long data paths mean that coLong data paths mean that co--ordination of ordination of bus use can adversely affect performancebus use can adversely affect performance

Most systems use multiple buses to Most systems use multiple buses to overcome these problemsovercome these problems

Traditional bus architectureTraditional bus architecture

Bus TypesBus Types

DedicatedDedicated•• Separate data & address linesSeparate data & address lines

MultiplexedMultiplexed•• Shared linesShared lines•• Address valid or data valid control lineAddress valid or data valid control line•• Advantage Advantage -- fewer linesfewer lines•• DisadvantagesDisadvantages

More complex controlMore complex controlSlower systemSlower system

Bus ArbitrationBus Arbitration

More than one module controlling the More than one module controlling the busbuse.g. CPU and DMA controllere.g. CPU and DMA controllerOnly one module may control bus at Only one module may control bus at one timeone timeArbitration may be centralised or Arbitration may be centralised or distributeddistributed

TimingTiming

CoCo--ordination of events on busordination of events on busSynchronousSynchronous•• Events determined by clock signalsEvents determined by clock signals•• Control Bus includes clock lineControl Bus includes clock line•• A single 1A single 1--0 is a bus cycle0 is a bus cycle•• All devices can read clock lineAll devices can read clock line•• Usually sync on leading edgeUsually sync on leading edge•• Usually a single cycle for an eventUsually a single cycle for an event