Fusion Engineering and Design 43 (1999) 401–405

Multiple DSP system for real time parallel processing andfeedback control on fusion experiments

A.P. Rodrigues a,*, C.M.B Correia a, C.A.F. Varandas a, F. Schneider b

a Associacao EURATOM/IST, Centro de Fusao Nuclear Instituto Superior Tecnico, 1096 Lisboa Codex, Portugalb Association EURATOM/IPP, Max-Planck-Institut fuer Plasmaphysik, D-85748 Garching, Germany

Abstract

This paper describes a specially designed system for real time parallel processing and feedback control on fusionexperiments. The system is being implemented in PCI and VME modules, based on an array of four synchronizableDSPs, with 1 Mbyte of global RAM, 12 bits resolution, four analog inputs with sampling frequency up to 40 MSPS,two analog or waveform generator outputs with an update rate up to 100 MSPS, eight digital opto-coupledinputs/outputs and one external global trigger optical input. The user interface appears as a virtual instrument fromLabView for Windows. © 1999 Elsevier Science S.A. All rights reserved.

Keywords: Synchronizable DSP; Waveform generator outputs; Virtual instrument

1. Introduction

Future plasma experiments will put even morestringent requirements on real time data process-ing than present ones do. The increased plasmaduration, together with higher time resolution,require sophisticated data pre-selection and com-pression. Detailed plasma parameter control de-mands optimum feedback procedures usingadaptive methods. The real time compensation forthe system’s inherent noise requires feed forwardcontrol using convolution methods.

The usual data acquisition process in the timedomain will lead to a very large increase in theamount of data to be stored, particularly if the

correlation of many MHD signals has to be stud-ied. The amount of data can be reduced in thiscase if, for instance, real time complex FFT isapplied and only the peaks of the spectra arestored. FFT can also be applied to analyse thestability of feedback loops during the operation ofthe experiment.

The control and data acquisition systems of thenext generation fusion devices must be based onintelligent instrumentation. Commercial DSPbased systems most probably cannot be used be-cause they have been designed for audio andvideo processing and the plasma diagnostic andfeedback control requirements are much different.The signal range, speed and number of channelshave to be increased.

This paper describes a specially designed systemfor real time parallel processing and feedback

* Corresponding author. Fax: +351 1 8417814; e-mail:cvarandas@cfn.ist.utl.pt

0920-3796/99/$ - see front matter © 1999 Elsevier Science S.A. All rights reserved.

PII S0920-3796(98)00410-4

A.P. Rodrigues et al. / Fusion Engineering and Design 43 (1999) 401–405402

Fig. 1. The architecture.

control on fusion experiments, based on an arrayof four synchronizable DSPs. Section 2 presentsthe main technical characteristics of the system aswell as a brief description of its architecture.Section 3 describes the hardware implementationand Section 4 suggests some applications of thissystem.

2. Main characteristics and architecture

The hardware, implemented in PCI and VMEmodules, has four DSPs (TI TMS320C44) thatcan deliver up to 40 MIPS/80 MFLOPS each, 1Mbyte of global RAM, 12 bits resolution, four910 V analog inputs with anti-aliasing filters andsampling frequency up to 40 MSPS, two 910 Vanalog or two waveform generator outputs withan update rate up to 100 MSPS, eight digitalopto-coupled inputs/outputs and one externalglobal trigger optical input.

The architecture (Fig. 1) is based on an array of

four synchronisable DSPs, communicating amongthem by the global bus and the three parallelports that link a DSP to the other three. TwoDSPs are mainly dedicated to data processing.The others are mainly affected to running controlalgorithms. The acquisition and waveform genera-tor blocks can operate in stand-alone mode, con-trolled by high density PLD devices. Theconfiguration of the module and communicationswith the host PC are performed by one DSP.

The user interface appears as a virtual instru-ment from LabView for Windows, allowing easyremote operation.

3. The hardware

The first version of the hardware is being imple-mented in a personal computer (PC) embeddedmodule with PCI bus interface as target. All thecommunication between the module and the PC ismade through a FIFO memory.

A.P. Rodrigues et al. / Fusion Engineering and Design 43 (1999) 401–405 403

Fig. 2. Main schematic.

The overall configuration of the module as wellas all the communication with the PC is per-formed by the DSP0. This component is responsi-ble for the program download for each DSP,including itself. This DSP is the only one that canaccess the DAC1 block (Fig. 2).

All the DSPs can communicate [1] betweenthem in two ways. The first one is through theglobal bus, because they share the global RAM,and the second one is through the three parallelcommunication ports that link each DSP to theother three, as shown in Fig. 2. This featureenables the module to execute, if necessary, realparallel processing [2,3].

Each DSP has an additional not shared 128 kBof SRAM for its own operation (data, program,and stack purposes, in what concerns DSP1).

DSP0 has an additional 64 kB of EPROM forstart up module purposes.

Each ADC channel can deliver the data in acontinuous mode to a biport RAM which can beaccessed simultaneously with the acquisition by aspecific DSP (depending on the biport RAM,Figs. 1 and 2). This feature gives the possibility ofprocessing the acquired data (with digital signalprocessing algorithms [4]) while acquiring, with-out the need of data transfer to another RAM.Between each ADC channel and the biport RAMthere is a configurable PLD that enables the datato be delivered where and how needed. For in-stance, it is possible to deliver the data of ADC0as a 32 bit word in the biport RAM belonging tothe DSP2 block, or in another way, the data ofADC0 and ADC1 can be delivered at the same

A.P. Rodrigues et al. / Fusion Engineering and Design 43 (1999) 401–405404

Fig. 3. Real time suppression of noise from thyristor power amplifiers in W7AS diagnostics.

time in the biport RAM of DSP2 block. Thelower significant 16 bits belong to ADC0 and theupper significant 16 bits belong to the ADC1.This feature is very useful when calculating FFTand cross-correlation algorithms [5].

Alternatively, each ADC channel can be readby any of the four DSPs in an asynchronousmode through the global data bus and the PLDthat manages the acquisition.

The direct connection to the DAC0 channelenables the DSP1 to run high speed feedbackcontrol algorithms [6,7]. DSP0 is also able to runcontrol algorithms, because it has a direct connec-tion to the DAC1 channel, but since this DSP isalso the module manager it may not be able torun control algorithms as fast as the DSP1.

Both DAC channels have FIFO memory sothey can perform the function of complex wave-

form generation, and can run in stand alonemode.

There are two bi-directional external ports asso-ciated with each DSP for general purposes, forinstance, to receive or send external triggersignals.

There is one external optical input port tosynchronise all the DSPs if needed.

The global bus arbiter, the interrupt controller,the acquisition controller and the function genera-tor controller, as well all the registers thatconfigure the module are implemented on PLDdevices.

4. Applications

This system will be firstly tested on the real time

A.P. Rodrigues et al. / Fusion Engineering and Design 43 (1999) 401–405 405

suppression of noise due to thyristor power suppliesin the W7AS diamagnetic loop diagnostic (Fig. 3).

In the first step the linear transfer function fromthe thyristor power converter-voltage or coil-cur-rent to the diamagnetic loop has to be determinedby frequency response measurements (Fig. 3 upperpart). This transfer function influenced and delayedby the magnetic field penetration into the compli-cated mechanical structure and vacuum vessel hasto be analyzed in detail via the DSP circuits. Theinverse Fourier-transform of the frequency re-sponse is the dirac-pulse-response which can becalculated afterwards in the PC by a high levellanguage (LabView).

In a second step (Fig. 3 lower part) the DSP’s cando real-time convolution of the signals Sn(t) withthe related dirac-pulse-responses and add them inopposite polarity to the diagnostic signal. If thisoperation is applied to every thyristor power con-verter, the resulting signal D(t) is cleaned of thissort of noise. The correct operation can be testedby another DSP for cross-correlation D(t) to Sn(t),which should be zero.

Other applications could be related with adaptivehigh speed PID control, feed forward control,controlled waveform generation, event detectionwith trigger generation and other real-time cross-correlation measurements.

Acknowledgements

This work has been carried out in the frame ofthe Contract of Association between the EuropeanAtomic Energy Community and ‘Instituto SuperiorTecnico’ and has also received financial supportfrom ‘Junta Nacional de Investigacao Cientıfica eTecnologica’ (JNICT).

References

[1] TMS320C4X General Purpose Applications User’s Guide(Literature number from Texas Instruments SPRU159).

[2] TMS320C4X Parallel Processing Development SystemTechnical Reference (Literature number from Texas In-struments SPRU075).

[3] Parallel Processing with the TMS320C4X (Literature num-ber from Texas Instruments SPRU031).

[4] A.V. Oppenheim, R.W. Schafer, Digital Signal Processing,Prentice-Hall, Eaglewood Cliffs, NJ, 1988.

[5] P.E. Papamichalis, C.S. Burrus, Conversion of digit-re-versed to bit-reversed order in FFT algorithms, Proceed-ings of ICASSO 89, USA, May 1989, pp. 984–987.

[6] I. Ahmed, Implementation of Self Tuning Regulators withTMS320 Family of Digital Signal Processors, MOTOR-CON’88, September 1988, pp. 248–262.

[7] I. Ahmed, S. Lindquist, Digital signal processors: simplify-ing high-performance control, Mach. Des., September1987.

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