Multilayered Architecture for PCI Express...
Transcript of Multilayered Architecture for PCI Express...
Multilayered Multilayered ArchitectureArchitecture for for
PCI Express PCI Express eeVCVC
IntroductionIntroductionLayering is the new buzzword in eVCmethodologyThis presentation aims to explain why layering is importantWill use examples drawn from Paradigm Works eVCs
Traditional approach to Traditional approach to data generationdata generation
High level data structure with control fields for low level behaviour:
struct my_packet {header : my_header_s;payload : my_payload_s;parity_error_positions : list of uint;
};
TL Packet FormatTL Packet Format
DLL Packet FormatsDLL Packet Formats
PHY Layer Data ViewPHY Layer Data View
That’s a whole big bunch of fields
… and I didn’t even show much of the complexity
Single layer approach Single layer approach breaks downbreaks down
Difficult to control lower layer behaviour from high layer data structuresOften want to concentrate on lower-layer testingOften need control of behaviour between ‘packets’Often need to co-ordinate low and high level behaviour
Enter layeringEnter layeringLayering allows separation of control and observabilityShould break layers at natural boundaries for protocolLayering has only become viable as a result of introduction of eRMUse of eRM very important to get full advantages of layered approach
Requirements for Requirements for lowest layerlowest layer
Sequence driverhigher layers provide connector sequence(s)
Monitor (with scoreboard hooks)higher layers extend scoreboard hooks
In other words...Just a normal eRM compatible eVC
Requirements for Requirements for higher layershigher layers
Connector sequenceSequence kind of lower layer eVC
E.g. PW_ATM_ATM pw_utop_sequenceUsually extends pre_do() method of sequence to grab data from higher layerConstrain default lower layer sequence
Extension to lower layer scoreboard hook(s)
Used to extract data from lower layer eVC
More on higher layersMore on higher layersImportant distinction
Higher layer eVCs usually don’t have a physical (signal based) interfaceInstead, they provide a method based interface
Possible to have optional physical interface
Simple layering Simple layering exampleexample
atm_over_xserial_env
atm_env
agent
BFM
sequencedriver
seq
Tx MonRx Mon
xserial_env
agent
BFM
sequencedriver
seq
Tx MonRx Mon
connectorseq
Full Full Example:Example:
PCI PCI ExpressExpress
eeVCVC
SeqDriver
DUT (remote device)
eVC
Tx_0
Rx_n
TLPredictor
BFM
LocalTL
Monitor
RemoteTL
Monitor
SeqDriver
DLLPredictor
BFM
LocalDLL
Monitor
RemoteDLL
Monitor
TL Agent
DLL Agent
SeqDriver
LinkPredictor
BFM
LocalLink
Monitor
RemoteLink
Monitor
PHY_MAC AgentLink to Lane Mapping Interface
SeqDriver
LanePredictor
BFM
LocalLane
Monitor
RemoteLane
Monitor
Lane_Unit_0Lane_Unit_n
Signal Interface
Rx_0
Tx_n
Tx_0
Rx_0
SeqDriver
BFM
LocalDev
Monitor
RemoteDev
MonitorDev Agent(TLP gen/
mon)
LocalConfigAgent
RemoteConfigAgent
CoCo--ordinated testing ordinated testing ––Virtual sequencesVirtual sequences
Can build virtual sequences to control simultaneous behaviour across multiple layers.E.g. A stream of 100 TL packets with an LCRC error on 43rd packet.
ACTIVE SLAVE XSBI EnveVC
Signal interface
Monitor
TX XSBIAgent
BFM Monitor
RX XSBIAgentseq
driverseq
Monitor
TX XGMIIAgent
BFM Monitor
RX XGMIIAgentseq
driverseq
DUT
XSBI Master Ethernet Device(e.g. PCS layer device)
TxRx
BFM Monitor
RX PACKETAgentseq
driverseq
Monitor
TX PACKETAgent
Virtualsequencedriver
seq
More on Virtual More on Virtual SequencesSequences
Can also co-ordinate behaviour across multiple layers AND multiple eVCs.E.g.: Set up DMA transfer on PCI interface to receive Ethernet packet that has error in last XSBI block.
Agents for the Protocol Agents for the Protocol LayersLayers
PCIE eVC encapsulates each protocol layer as an “Agent”An Agent is a UnitAgent units are instantiated inside the envThe user has control over instantiation of agents via constraints on the envThere are standard components within each Agent
Sequence Drivers, Monitors, BFMs, Predictors
Contents of a PCIE Contents of a PCIE Protocol Layer AgentProtocol Layer Agent
Sequence DriverAPISupplied sequence library
PredictorBFM drives signals
Extensible for unique DUT interfaceMonitor
ProtocolScoreboard interfaceCoverageCompliance
ScoreboardSupplied for TL, Interfaces for other layers
Config AgentConfig AgentEvery bit of every PCIE spec registerTwo roles, instantiated twice by default
Provides eVC’s config regs (active: completions)Shadows DUT’s config regs (active & passive)
Auto shadowing on in-band config space accessUser must update for conditions detected by DUT & DUT back-side access
Method interface providedCan compare to DUT registersMACRO provided for adding user-defined regs
A Note on the Device A Note on the Device LayerLayer
Not a PCIE protocol layerModels the behavior of a PCIE device
Think of it as the Software LayerResponds to:
Memory reads/writesI/O reads/writes
Configurable Address spaceOther characteristics
Anatomy of a Single Anatomy of a Single PCIE Protocol LayerPCIE Protocol Layer
Seq Driver
TLPredictor
BFM
LocalTL
Monitor
RemoteTL
Monitor
TL Agent
Tx Rx Tx Rx
Rx
PHY_MAC AgentPHY_MAC Agent
…is a little different
Tx_0Rx_n
Seq Driver
LinkPredictor
BFM
LocalLink
Monitor
RemoteLink
Monitor
PHY_MAC Agent
Link to Lane Mapping Interface
Seq Driver
LanePredictor
BFM
LocalLane
Monitor
RemoteLane
Monitor
Lane_Unit_0
Lane_Unit_n
Signal Interface
Rx_0 Tx_n
Tx_0 Rx_0
Tx Rx Tx Rx
Tx Rx Tx Rx
Rx
Rx
The EnvThe EnvTop level unit of the eVC, inherits from any_envAgents within are created based on user configuration options
Default 3 agents: Transaction, Data Link and Physical layer agents
Each can be disabled with constraintsOther main fields:
Active/Passive modesLocal/Remote
Upstream/Downstream & Root/EndpointDevice layer presentBus & device identifiers
Ways to Use PCIE eVCWays to Use PCIE eVCActive or PassiveRoot Complex or EndpointComplete PCIE entity
PHY_MAC in PCIE mode1 bit or 10 bit
PHY_MAC in PIPE modeMaster or Slave (for PHY or MAC DUTs)8 bit or 16 bit
DLLTL2 config Agents – provide completions, verify DUT regs Device
Any subset
Passive Passive ModeMode
DUT
eVCLocal
TLMonitor
RemoteTL
Monitor
LocalDLL
Monitor
Remote DLLMonitor
TLAgent
DLLAgent
LocalLink
Monitor
RemoteLink
Monitor
PHY_MACAgent
Link to Lane Mapping Interface
LocalLane
Monitor
RemoteLane
Monitor
Lane_Unit_0
Lane_Unit_n
Signal InterfaceRx_0Tx_0
Root Complex(local device)
Endpoint(remote device)
Tx
Tx
Rx
Rx
Tx TxRx Rx
Tx Rx Tx Rx
Tx Rx Tx Rx
LocalConfigAgent
RemoteConfigAgent
Tx Rx Tx Rx
Tx Rx
Tx Rx
Tx Rx
Active Active Mode, Mode,
Full Full eeVCVC
SeqDriver
DUT (remote device)
eVC
Tx_0
Rx_n
TLPredictor
BFM
LocalTL
Monitor
RemoteTL
Monitor
SeqDriver
DLLPredictor
BFM
LocalDLL
Monitor
RemoteDLL
Monitor
TL Agent
DLL Agent
SeqDriver
LinkPredictor
BFM
LocalLink
Monitor
RemoteLink
Monitor
PHY_MAC AgentLink to Lane Mapping Interface
SeqDriver
LanePredictor
BFM
LocalLane
Monitor
RemoteLane
Monitor
Lane_Unit_0Lane_Unit_n
Signal Interface
Rx_0
Tx_n
Tx_0
Rx_0
SeqDriver
BFM
LocalDev
Monitor
RemoteDev
MonitorDev Agent(TLP gen/
mon)
LocalConfigAgent
RemoteConfigAgent
Active Mode, Module Test ExamplesActive Mode, Module Test Examples
TL/DLL DUT
DLLTL
DEV
eVC
DEV
PHY_MAC DUT
DLLTL
DEV
DLLTL
(Pipe)
PHY_MAC eVC
eVC
(Pipe)
(PCIE)
eVCDEV
Compliance UnitCompliance UnitRobust protocol checking in monitorsMapped to compliance checklist items
Hundreds implemented so far, more in progressBlack Box checksUser can extend for white box checksAll compliance checks are also coverage itemsCompliance reporting can be turned offPossible check result values:
YesNOT_EXERCISED
ERRORNOT_APPLICABLE
Log FilesLog Files3 built-in formats for different verbosity levels
Low, medium, highUser can add new formats, extend existing
Constraints on logfile name will control how messages are split up among filesextend INST_A DEV pw_pcie_monitor_u { keep
log_filename == appendf("PW_PCIE_%s_%s_DEV.log", name, monitor_kind);keep file_formatter.log_level == LOW;
};
SummarySummaryLayering solves complex test scenario problemsLayering will be necessary to solve tomorrows verification problems.Paradigm Works PCI Express eVC is the state-of-the-art layered eVCIt is easy to add functionality to a verification component if well designedIt is impossible to add usability and reusability to a verification component if it is not well designed!