Multi

--- What should processor P0 see?--- When?

--- What should memory hold?

--- Ordering of events is unknown.

--- Write-through? Write-back?

--- Bus contention, L2, L3?

READ MISS

WRITE MISS

WRITE HIT

NOT OWNED

http://www.icsa.inf.ed.ac.uk/research/groups/hase/models/dir-cache/