MTLE-6120: Advanced Electronic Properties of Materials

Semiconductor transistors for logic and memory

Reading:

I Kasap 6.6 - 6.8

1

Vacuum tube diodes

I Thermionic emission from cathode

I Electrons collected at anode with positive bias

I Anode not heated: cannot emit electrons ⇒ no reverse current

I Nominally similar characteristics to pn-junction diode

Images: Wiki: Vacuum tubes

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Vacuum tube triodes

I Control plate / grid between cathode and anode

I Negative bias repels electrons; reduces current

I Small changes in voltage ⇒ large changes in current

I Acts as a switch or amplifier

Images: Wiki: Vacuum tubes

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Vacuum tube computers

I Each triode in own separate tube

I ENIAC computer in 1946: 17468 such tubes

I Key characteristic required: three terminal device where third terminalcontrols current between first two

I In principle: computer made entirely of hydrualically orpneumatically-controlled valves!

Images: Wiki: Vacuum tubes

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Bipolar Junction Transistor (BJT)

I Heavily doped emitter E (like cathode in triode)

I Thin lightly-doped base B (like control plate / grid)

I Lightly-doped collector C (like anode)

I Either pnp (shown above) or npn (polarities reversed)

I Which one does the vacuum tube triode correspond to?

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BJT: junction potentials

I Two pn-junctions: E-B and C-B

I Normal (active) operation: forward-bias E-B and reverse-bias C-B

I E-B junction: depletion region mostly in base

I C-B junction: comparitively symmetrical

I Potential drop across depletion regions; negligible field in interiors

I Hole concentration at B-end of E-B junction: pn(0) =n2i

Ndexp eVEB

kBT

I Hole concentration at B-end of C-B junction: pn(WB) ≈ 0

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BJT: current flow

I Diffusion current across base: IE ≈ IC = eADhpn0

WB=

eADhn2i

NdWBexp eVEB

kBT

I Current out of n-type base has to be electrons: two factors in α ≡ IC/IEI Electron current in E-B: small due to asymmetric doping γ = 1

1+NdWBµeNaWEµh

I Recombination: small for thin lightly-doped base αT = 1− W 2B/(2Dh)τh

I Current transfer ratio α = γαT & 0.99 for typical BJTs

I Current gain β ≡ IC/IB = α1−α ∼ 102 − 103

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BJT: IV characteristics

I Ideal characteristic: IC = IE independent of VCBI Leakage current in reverse-biased C-B junction, ICB0

I At high VCB , IC = αIE + ICB0 and IB = (1− α)IE − ICB0

I But slope of IC vs VCB increases for finite IE (beyond ICB0)

I Early effect: C-B depletion width increases with VCBI This reduces WB , making hole diffusion easier, and therefore IE ↑

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BJT: common base amplifier

I Small changes in E-B potential strongly affect IC ≈ IE = IE0 expeVEBkBT

I Convert ‘amplified’ current to voltage using resistor

I Collector potential VCB = −VCC +RCICI Voltage gain (controlled by selecting IE and RC):

∂VCB∂VEB

= RC∂IC∂VEB

=IERCkBT

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BJT: common emitter amplifier

I Note npn-transistor: polarities reversed

I Current amplifier: input IB amplified by β to output ICI With leakage current, IB = (1− α)IE − ICB0 and

IC = IE − IB = βIB +ICB0

1− α︸ ︷︷ ︸ICE0

I Operate at VCE > VBE , else saturation: IC limited by IE

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Junction Field-effect Transistor (JFET)

I n-JFET: narrow n channel between p+ gates (reversed for p-JFET)

I Width of n channel determined by depletion regions

I Basic idea: control channel width and conduction using gates

I Always operate with channel potential > gate ⇒ reverse bias

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JFET: channel IV characteristics

I First consider applied VDS with VGS = 0

I Voltage of channel-gate junction increases from S to D

I Correspondingly increasing depletion width narrows channel

I Increase VDS , current ID increases, but channel narrows

I At V satDS , channel pinches off at D end, ID saturates

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JFET: gate effects

I Apply negative gate potential: VDG increases

I Narrower depletion region, earlier pinch off

I V satDS = VP + VGS , where pinchoff voltage VP = V sat

DS at VGS = 0

I Therefore, gate potential controls channel current and effective resistance

I Strong-enough VGS shuts off channel completely ⇒ V offGS

I Empirical behaviour: IDS = IDSS[1− VGS/V off

GS

]2

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JFET amplifier

I Amplifier: gate voltage controls channelcurrent

I Convert channel current to voltage throughresistor RD

I Vaguely similar to common-emitteramplifier

I Set operating ‘quiescent’ point at center ofoperating range

I Signal amplitudes small enough to stay inrange

I Voltage gain

∂VDS∂VGS

=RD∂IDS∂VGS

=2IDSSRDV offGS

[1− VGS

V offGS

]

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Metal-oxide-semiconductor (MOS) capacitor

Metal Oxide Semiconductor Metal Oxide Semiconductor Metal Oxide Semiconductor

I Metal and SC separated by an insulating oxide: why don’t the bands bend?

I Apply potential: linear variation in oxide, typical bending in SC

I Vacuum level (potential) continuous, D⊥ continuous

I For p-SC and positive Vmetal, CB bends towards EFI For Vmetal > Vth (threshold), CB closer than VB to EFI Inversion region: n > p in p-type semiconductor

I Analogous case with reversed potentials for n-type semiconductors

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Metal-Oxide-SC Field-effect Transistor (MOSFET)

I Enhancement n-channel MOSFET: metal-p capacitor surrounded by n+

I MOS inversion: generates an n channel at surface

I Comparison with n-JFET: existing channel suppressed by gate junction

I Analogous depletion n-MOSFET: replace p above with light n

I Flip n↔ p and polarities ⇒ enhancement and depletion p-MOSFETs

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MOSFET: gate response

I For VGS < Vth, n+ contacts separated by depletion layer

I No channel ⇒ ID = 0 irrespective of VDS

I One VGS > Vth, inversion layer forms an n-channel

I For low VDS , channel behaves like an Ohmic resistor

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MOSFET: drain response

I Increasing VDS causes reduction in VGDI Channel begins to narrow near drain; current starts to level off

I At VDS = V satDS = VGS − Vth, channel pinches off at drain end

I Beyond this potential, ID does not increase with increasing VDS

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MOSFET: IV characteristics

I Saturation drain voltage V satDS = VGS − Vth

I Saturation drain current IDS = K(VGS − Vth)2(1 + λVDS)

I Coefficient K ∼ Cµe2L2 , where C = MOS capacitance, L = channel length

I Coefficient λ due to Early effect (exactly like in BJT, JFET)

I Similar characteristics to JFET ⇒ similar amplifier circuits

I Switching: VGS > Vth ⇒ RDS small (on) vs VGS < Vth ⇒ RDS large (off)

I On-off ratio RoffDS/R

onDS , switching time ∼ RC

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Complementary MOS (CMOS) logic

I Complementary MOS: combine p and n-MOS transistors

I Inverter / NOT gate: Vin < Vth ⇒ Vout = Vdd, Vin > Vth ⇒ Vout = VssI Digital logic: for input 0 and 1, output 1 and 0 respectively

I NOR (NOT OR) gate: output 0 (NOT 1) if any input 1

I NAND (NOT AND) gate: output 0 (NOT 1) if all inputs 1

I Any logic or arithmetic operation using just three gates!

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Arithmetic circuits

I XOR (exclusive OR) gate: output 1 if exactly one input 1

I 1-bit adder: sum bit = XOR, carry bit = AND

I 8-bit adder: chain bit additions together

I N -bit adder: requires ∝ N log2N gates

I N -bit multiplier: adder of N numbers with N -bits each

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Example: Xeon Phi 7210

I 64 compute cores

I Each core: 8× 64-bit multipliers

I Net: 1012 64-bit math operations per second

I 8× 109 CMOS transistors in 8 cm2 of Si!

22

Bistable latches (flip-flops)

I When R = S = 0: latch stores previous value

I Feedback loop between two inverters

I S = 1 sets value to 1, R = 1 resets it to 0

I Volatile memory: data lost when circuit powered off

I Mechanism used in registers and static RAM

I Minimum 8 transistors / bit as shown above (low-density, high power)

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Dynamic RAM

I Bit = whether capacitor is charged

I Transistor in off state: capacitor isolated; retains charge

I To read, transistor in specific row and column switched on

I Reading destroys state; must be written back

I State lost due to leakage ⇒ refresh circuitry

I Volatile: charge retention only ∼ 100 ms

I 1 transistor / bit: high-density, low power

I 8GB DDR4 memory: 8× 109 transistors in < 10 cm2 Si

24

Flash memory / SSD: floating-gate transistors

I Floating gate transistor: bit = whether floating gate is charged

I Charge on floating gate affects VthI Read bit by checking if transistor is on at specified VGSI Write bit by hot-electron injection from channel

I Erase bit by Fowler-Nordheim tunneling to upper gate

I NOR-flash: closer to random-access; erase only in large blocks

I NAND-flash: all access in large pages / blocks (eg. SSD)

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