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Proceedings of MTECS-2008, AMU Aligarh

SUBTHRESHOLD OPERATION OF FIELDPROGRAMMABLE GATE ARRAY

A.K. Kureshi 1, Naushad Alam 2, and Mohd. Hasan 3

Department of Electronics Engineering, AMU, Aligarh,

akkureshi@rediffmail.com 1 , m_hasan786@rediffmail.com 2,itsnaushad@rediffmail.com 3

Abstract FPGA architectures are well suited for wirelessapplications since they provide high performance computationtogether with the capability to adapt to changing communicationprotocols, but as the process technology approaches sub-100nm, theleakage current poses serious design challenges in FPGA.

Furthermore, the fraction of total delay due to routing is increasingwith each process generation; hence these two parameters become abig obstacle in the use of FPGA in wireless low power portableapplication. This paper analyses the operation of FPGA basicBuilding Blocks in subthreshold region. HSPICE simulation basedon BPTM (Berkeley Predictive Technology Model) at 30 C for32nm channel length device shows that with proper sizing of (W/L)ratio for the routing switches and LUT the FPGA worksatisfactorily at a supply voltage of 0.3V with a marginalimprovement in power delay products (PDP), as compared toconventional FPGA.

Index terms -- Ultra-low Power, Subthreshold, FPGA, Switches,LUT, SRAM.

I. INTRODUCTION

Subthreshold logic has emerged as a technology that can delivertheoretical minimum energy per computation which is very lowas compare to (conventional) super-threshold CMOS.Subthreshold circuit operates with a supply voltage less than thethreshold voltage of the MOS transistor [1], where the transistoressentially operates on leakage current. Conventional digitalcircuit either work in saturation or cut-off but subthresholdcircuit operates either in an off state or an almost in on statewhich is the weak inversion region [2]. As power is relatedquadratically on the supply voltage, reducing the voltage to ultra-low level results in a dramatic reduction in both power andenergy consumption [3]. Minimizing the power consumption ofFPGA is a vital design objective for portable devices such asmobile communication and bio-medical appliances where the

power lowering is as important as the performance [4]. One

approach for achieving ultra-low power consumption of FPGA isto operate all the MOS transistors in sub- threshold region [5],where supply voltage (V dd ) is less than transistors thresholdvoltage (V th) [6]. This paper simulates several FPGA routingswitches and LUT (look-up table) at operating frequency of 2.5MHz with supply voltages of 0.9V(>V th) and 0.3V(

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REFRENCES

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[6] Hendrawan Soleleman and Kaushik Roy, Robust subthreshold logic forultra-low power operation, IEEE J. VLSI, vol. 9, no. 1, pp.90-98.

[7] Betz, V., Rose, J. Cluster-based logic blocks for FPGAs: area-efficiency vs.input sharing and size in Proceedings of the IEEE 1997 Custom IntegratedCir-cuits Conference, May 1997, pp.551-554.

[8] Faith Hamzaoglu, Mircea R.Stan, Circuit level techniques to control gateleakage for sub-100nm CMOS, ISLPED 2002, pp.61-63

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