MSP432 SimpleLink Microcontrollers Hardware Tools User's ...
Transcript of MSP432 SimpleLink Microcontrollers Hardware Tools User's ...
MSP432™ SimpleLink™ MicrocontrollersHardware Tools
User's Guide
Literature Number: SLAU571DMarch 2015–Revised June 2018
2 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Contents
Contents
Preface ........................................................................................................................................ 41 Hardware ............................................................................................................................ 5
1.1 MSP-FET-432ADPTR ....................................................................................................... 61.1.1 Introduction .......................................................................................................... 61.1.2 Key Features ........................................................................................................ 61.1.3 Kit Contents.......................................................................................................... 61.1.4 Configuration and Usage .......................................................................................... 61.1.5 Hardware Design ................................................................................................... 7
1.2 MSP-TS432PZ100........................................................................................................... 81.2.1 Introduction .......................................................................................................... 81.2.2 Key Features ........................................................................................................ 81.2.3 Kit Contents.......................................................................................................... 81.2.4 Configuration and Usage .......................................................................................... 81.2.5 Hardware Design .................................................................................................. 15
1.3 MSP-FET .................................................................................................................... 24
Revision History.......................................................................................................................... 25
www.ti.com
3SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
List of Figures
List of Figures1-1. MSP-FET-432ADPTR Schematic ......................................................................................... 71-2. Board Configuration For External Target Power Supply................................................................ 91-3. Board Configuration For Debugger-Supplied Target Power.......................................................... 111-4. Board Configuration When Using Cortex-M Debug Probes With Target Power Supply Capability ............. 121-5. Board Configuration for Debug Probe Does Not Supply Logic Level on Pin 19 ................................... 131-6. Board Configuration for Debug Probe Does Supply Logic Level on Pin 19 ........................................ 141-7. MSP-TS432PZ100 Rev 1.1 Target Socket Board, Schematic ....................................................... 151-8. MSP-TS432PZ100 Rev 1.1 Target Socket Board, PCB .............................................................. 161-9. MSP-TS432PZ100 Rev 1.3 Target Socket Board, Schematic ....................................................... 191-10. MSP-TS432PZ100 Rev 1.3 Target Socket Board, PCB .............................................................. 20
List of Tables1-1. Matrix of S1 Switch Orientation Compared to ARM Connector Option............................................... 61-2. MSP-FET-432ADPTR Bill of Materials.................................................................................... 71-3. Device Compatibility......................................................................................................... 81-4. Jumper Settings for External Target Power Supply ..................................................................... 91-5. Jumper Settings to Use Onboard LDO .................................................................................. 101-6. Jumpers for Debug Probe Does Not Supply Logic Level on Pin 19................................................. 101-7. Jumpers for Debug Probe Does Supply Logic Level on Pin 19...................................................... 101-8. Jumper Settings ............................................................................................................ 121-9. Jumper Settings to Use LDO ............................................................................................. 131-10. Jumper Settings for Debug Probe Does Not Supply Logic Level on Pin 19 ....................................... 131-11. Jumper Settings for Debug Probe Does Supply Logic Level on Pin 19 ............................................ 141-12. MSP-TS432PZ100 Rev 1.1 Important Board Components........................................................... 161-13. MSP-TS432PZ100 Rev 1.1 Bill Of Materials ........................................................................... 171-14. MSP-TS432PZ100 Rev 1.3 Important Board Components........................................................... 211-15. MSP-TS432PZ100 Rev 1.3 Bill Of Materials ........................................................................... 22
4 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Read This First
PrefaceSLAU571D–March 2015–Revised June 2018
Read This First
About This ManualThis manual describes the hardware tools that support the Texas Instruments SimpleLink™ MSP432™device family of ARM® Cortex®-M based microcontrollers.
How to Use This ManualThis manual describes the setup and operation of the hardware tools. It does not fully describe theMSP432 microcontrollers or the development software systems. For details of these items, see theappropriate TI documents listed in Important MSP432 Documents on the Web.
Important MSP432 Documents on the WebThe primary sources of MSP432 information are the device-specific data sheets and user's guides. TheMSP432 web site contains the most recent versions of these documents.
Documents that describe the Code Composer Studio™ tools (Code Composer Studio IDE, assembler, Ccompiler, linker, and librarian) are available on the Code Composer Studio page. A Wiki page (FAQ) thatis specific to the Code Composer Studio tools is available atprocessors.wiki.ti.com/index.php/Category:CCS. The TI E2E™ Community support forums provideadditional help.
Documentation for third-party tools, such as the IAR Embedded Workbench® for ARM IDE or the SeggerJ-Link debug probe, can be found on the respective third-party website.
If You Need AssistanceSupport for the MSP432 devices and the hardware development tools is provided by the TexasInstruments Product Information Center (PIC). Contact information for the PIC can be found on the TI website. The TI E2E™ Community support forums for the MSP432 provide open interaction with peerengineers, TI engineers, and other experts. Additional device-specific information can be found on theMSP432 web site.
TrademarksSimpleLink™ MSP432, SimpleLink, Code Composer Studio, TI E2E are trademarks of Texas Instruments.ARM, Cortex are registered trademarks of ARM Limited.IAR Embedded Workbench is a registered trademark of IAR Systems.
5SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
Chapter 1SLAU571D–March 2015–Revised June 2018
Hardware
This chapter contains information relating to the hardware tools and includes schematics, PCB pictorials,and bills of materials. Other tools such as EVMs and LaunchPad development kits are described inseparate product-specific user's guides. Information about the TI XDS100 and XDS200 debug probes isnot included in this document and can be found at www.ti.com/tool/xds100 and www.ti.com/tool/xds200,respectively.
Topic ........................................................................................................................... Page
1.1 MSP-FET-432ADPTR ............................................................................................ 61.2 MSP-TS432PZ100................................................................................................. 81.3 MSP-FET ........................................................................................................... 24
MSP-FET-432ADPTR www.ti.com
6 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.1 MSP-FET-432ADPTR
1.1.1 IntroductionThe MSP-FET-432ADPTR is an adapter to convert the 14-pin JTAG connector to either standard ARM 10-pin or ARM 20-pin connectors. This allows for use of the MSP-FET debug probe with MSP432 Cortex-Mdevices.
1.1.2 Key Features• Use MSP-FET to debug MSP432 Cortex-M Devices• 10-pin ARM support• 20-pin ARM support
1.1.3 Kit Contents• 1x MSP-FET-432ADPTR 14-pin JTAG to ARM adapter
1.1.4 Configuration and UsageThe MSP-FET-432ADPTR allows the use of the MSP-FET debug probe with the MSP432 Cortex-M familyof devices. Operation is straight-forward, with only one selection for how the power is sourced. Thisselection is required because of the difference in the power source and sense behavior of the MSP-FETand the ARM debug standard.
The MSP-FET debug probe has two power states:1. VCC Output
• MSP-FET outputs a voltage to the target.• Output voltage is configurable in the IDE.• In VCC output state, the MSP-FET voltage sense functionality is not enabled.
2. VCC Sense• MSP-FET senses an existing external voltage (not from the MSP-FET itself).• The JTAG signals are level shifted accordingly to match this voltage.• In VCC Sense state, the MSP-FET output voltage is not provided.
The Cortex-M debug standard works a bit differently. In this standard, the VCC Sense is always active, nomatter where the external voltage is coming from. Some debug probes, such as the IAR I-jet and SeggerJ-Link have a voltage output, all while still sensing the VCC Sense.
Table 1-1. Matrix of S1 Switch Orientation Compared to ARM Connector Option
VCC Sense (S1 Left) VCC Output (S1 Right)
ARM 20-pin connector• External power is sensed through ARM pin 1• External power needs to be connected to
debug target
• Power is provided by the MSP-FET throughARM pin 19.
• Alternatively, power can be wired to the targetusing connector J4.
• This output matches other ARM debug probeslike IAR i-Jet and SEGGER J-Link
• Note that the IAR i-Jet outputs 3.3 V, andSEGGER J-Link outputs 5 V on this pin.Ensure the target accounts for the specificvoltage output by MSP-FET.
ARM 10-pin connector• External power is sensed through ARM pin 1• External power needs to be connected to
debug target
• There is no pin to connect the power outputon the 10 pin connector
• Power output is provided on connector J4.This can be wired to the target board.
1 23 45 67 89 10
1 23 45 67 89 10
11 1213 1415 1617 1819 20
C12L1 1
L2 3
C25L3 4
L4 6
135
246
79
810
1113
1214
123
A
B
C
D
1 2 3 4
A
B
C
D
1 2 3 4
Copyright © 2016, Texas Instruments Incorporated
www.ti.com MSP-FET-432ADPTR
7SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.1.5 Hardware DesignFigure 1-1 shows the schematic of the MSP-FET-432ADPTR.
Figure 1-1. MSP-FET-432ADPTR Schematic
Table 1-2 lists the bill of materials for the MSP-FET-432ADPTR.
Table 1-2. MSP-FET-432ADPTR Bill of Materials
Qty Reference Manufacturer Description Part NumberAlternate
PartNumber
PCB Decal,Package Supplier Digi-Key Number
1 J1 Standard Conn Header 14POS 0.100" TH,RA, Gold, Digikey S9203-ND 2 x 7 0.100" Digikey S9203-ND
1 J2 SamtecCONN HEADER 10POS DUALVERT, Digikey FTSH-105-01-F-D-K-ND
FTSH-105-01-F-D-K 2 x 5 0.050" Digikey FTSH-105-01-F-D-K-ND
1 J3 StandardCONN HEADER LOW-PRO20POS GOLD, DigikeyHRP20H-ND
2 x 10 0.100" Digikey HRP20H-ND
1 J4 StandardCONN HEADER .100 SINGLSTR 3POS, Digikey S1012E-03-ND
1 x 3 0.100" Digikey S1012E-03-ND
1 S1 Standard SW SLIDE DPDT 2POS,Digikey 401-2001-ND M096V Digikey 401-2001-ND
1 MH1 Standard Standoff Nylon 4-40 8mm/0.375" CM
1 MH2 Standard Standoff Nylon 4-40 8mm/0.375" CM
MSP-TS432PZ100 www.ti.com
8 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.2 MSP-TS432PZ100
1.2.1 Introduction
NOTE: This kit does not include MSP432 microcontroller samples. To sample the compatibledevices, visit the product page or select the related MCU after adding the tool to the TI Storecart: MSP432P401R.
The MSP-TS432PZ100 is a stand-alone ZIF socket target board used to program and debug the MSP432MCU in-system through the JTAG interface or the Serial Wire Debug (SWD 2-wire JTAG) protocol. Twostandard ARM Cortex-M debug connectors provide connectivity to a large number of debug probes fromTexas Instruments and third parties.
All device pins are readily accessible through dedicated headers, which makes the board the ideal centerof a prototype setup.
1.2.2 Key Features• ZIF socket for 100-pin QFP (PZ) packages• Access to all 100 device pins• LEDs and buttons• 2 x Cortex-M JTAG connectors supporting all 10- or 20-pin compatible debug probes
1.2.3 Kit Contents• One READ ME FIRST document• One MSP-TS432PZ100 target socket board• One TI Terms and Conditions for Evaluation Modules• One 32.768-kHz crystal from Micro Crystal• Four SAM1029-25-ND 25-pin 100-mil through-hole male headers• Four SAM1213-25-ND 25-pin 100-mil through-hole female headers
1.2.4 Configuration and UsageTable 1-3 lists the devices that are compatible with the MSP-TS432PZ100 target socket board.
Table 1-3. Device Compatibility
Board Socket Type Supported Devices
MSP-TS432PZ100 100-pin QFP (PZ100)
MSP432P401RIPZMSP432P401MIPZMSP432P4111TPZMSP432P4111IPZMSP432P411YTPZMSP432P411YIPZMSP432P411VTPZMSP432P411VIPZ
Feed external
GND here
Feed external
VCC here
www.ti.com MSP-TS432PZ100
9SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.2.4.1 MSP-TS432PZ100 Rev 1.1
1.2.4.1.1 Board Configuration For External Target Power SupplyIf the application needs to operate in stand-alone mode (for example, to measure current consumptionwithout debug overhead) or when using ARM Cortex-M debug probes that do not provide power for thetarget device (for example, TI XDS100, XDS200, Keil ULINK2, or Keil ULINK Pro), power must besupplied externally to the target socket board.
Always follow the voltage limits defined in the device data sheet. Set the jumpers according to Table 1-4before connecting the debug probe and power supply (see Figure 1-2).
Table 1-4. Jumper Settings for External Target Power Supply
Jumper State DescriptionJ1 Close 2-3 Connect EXTERNAL VCC to board VCC
J2 Connect external VCC to J2-1, and external GND to J2-2 or J2-3, per the labelling on the PCBsilkscreen.
JP1 Closed Current-measurement header (closed unless measuring ICC)JP2 Closed Current-measurement header (closed unless measuring IDVCC)
JP16 Closed Current-measurement header (closed unless measuring IAVCC)JP8 Open Disconnect Pin 19 from LDO input
JP12 Open Disconnect LDO output from internal VCC (INTVCC)JP15 Open Do not short LDO input to output
Figure 1-2. Board Configuration For External Target Power Supply
MSP-TS432PZ100 www.ti.com
10 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.2.4.1.2 Board Configuration When Using ARM Cortex-M Debug Probes With Target Power SupplyCapability
Some third-party ARM Cortex-M debuggers (for example, Segger J-Link and IAR i-Jet) can optionallysupply a 5-V voltage to the target system through pin 19 of the debug connector. The LDO IC2 uses thisvoltage to generate the 3.3-V target supply voltage. To use the LDO, set the jumpers according toTable 1-5 before connecting the debug probe (see Figure 1-3).
Table 1-5. Jumper Settings to Use Onboard LDO
Jumper State DescriptionJ1 Close 1-2 Connect Internal VCC (INTVCC) to board VCC
JP1 Closed Current-measurement header (closed unless measuring ICC)JP2 Closed Current-measurement header (closed unless measuring IDVCC)
JP16 Closed Current-measurement header (closed unless measuring IAVCC)
If the debug probe does not supply a logic level through pin 19 on the 20-pin connector, follow the jumpersetting in Table 1-5.
Table 1-6. Jumpers for Debug Probe Does Not Supply Logic Level on Pin 19
Jumper State DescriptionJP8 Closed Connect pin 19 to LDO input
JP12 Closed Connect LDO output to the internal VCC (INTVCC)JP15 Open Do not short LDO input to output
If the debug probe does supply a logic level through pin 19 on the 20-pin connector, follow the jumpersettings in Table 1-7.
Table 1-7. Jumpers for Debug Probe Does Supply Logic Level on Pin 19
Jumper State DescriptionJP8 Open Disconnect pin 19 from LDO input
JP12 Open Disconnect LDO output from internal VCC (INTVCC)JP15 Closed Bypasses the LDO by connecting pin 19 directly to onboard VCC (INTVCC)
www.ti.com MSP-TS432PZ100
11SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
Figure 1-3. Board Configuration For Debugger-Supplied Target Power
MSP-TS432PZ100 www.ti.com
12 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.2.4.2 MSP-TS432PZ100 Rev 1.3 and Newer
1.2.4.2.1 Board Configuration For External Target Power SupplyIf the applications needs to operate in stand-alone mode (for example, to measure current consumptionwithout debug overhead) or when using ARM Cortex-M debug probes that do not provide power for thetarget device (for example, TI XDS100, XDS200, Keil ULINK2, or Keil ULINK Pro), power must besupplied externally to the target socket board.
Always follow the voltage limits defined in the device data sheet. Set the jumpers according to Table 1-8before connecting the debug probe and power supply (see Figure 1-4).
Table 1-8. Jumper Settings
Jumper State Description
J2
Connect external VCC to J2-1, and external GND to J2-2 or J2-3, per the labelling on the PCBsilkscreen.NOTE: Some V1.3 boards have incorrect silkscreen labeling. Make sure to follow the figuresshown in this user's guide.
JP1 Closed Current-measurement header (closed unless measuring ICC)JP2 Closed Current-measurement header (closed unless measuring IDVCC)JP3 Closed Current-measurement header (closed unless measuring IAVCC)JP6 Open Disconnects input of LDO to allow VCC to be driven externally
Figure 1-4. Board Configuration When Using Cortex-M Debug Probes With Target Power SupplyCapability
www.ti.com MSP-TS432PZ100
13SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
Some third-party ARM Cortex-M debuggers (for example, Segger J-Link and IAR i-Jet) can optionallysupply a 5-V voltage to the target system through pin 19 of the debug connector. The LDO IC2 uses thisvoltage to generate the 3.3-V target supply voltage. To use the LDO, set the jumpers according toTable 1-9 before connecting the debug probe (see Figure 1-5 or Figure 1-6):
Table 1-9. Jumper Settings to Use LDO
Jumper State DescriptionJP1 Closed Current-measurement header (closed unless measuring ICC)JP2 Closed Current-measurement header (closed unless measuring IDVCC)JP3 Closed Current-measurement header (closed unless measuring IAVCC)
If the debug probe does not supply a logic level through pin 19 on the 20-pin connector, also close pins1‑2 on JP6 (see Figure 1-5):
Table 1-10. Jumper Settings for Debug Probe Does Not Supply Logic Level on Pin 19
Jumper State DescriptionJP6 Close 1-2 Connect board VCC to LDO output
Figure 1-5. Board Configuration for Debug Probe Does Not Supply Logic Level on Pin 19
MSP-TS432PZ100 www.ti.com
14 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
If the debug probe does supply a logic level through pin 19 on the 20-pin connector, also close pins 2-3 onJP6 (see Figure 1-6):
Table 1-11. Jumper Settings for Debug Probe Does Supply Logic Level on Pin 19
Jumper State DescriptionJP6 Close 2-3 Connect board VCC to pin 19, bypassing LDO
Figure 1-6. Board Configuration for Debug Probe Does Supply Logic Level on Pin 19
DN
P
DN
P
So
cke
t:Y
am
aic
hi IC
35
7-1
00
4-0
53
N
LQ
M2
MP
N4
R7
NG
0
DN
P
DN
P
GN
D
GN
D
100nF
330R
GN
D
1.1
nF
47k
GN
D
0R0R
QU
AR
Z5
10uF
/10V
100
nF
1u
F/1
0V
gre
en
DN
P
ye
llow
DN
P
red
0R
22
pF
22
pF
0R0R
QUARZ5
EV
Q11
0R
EVQ-11L05R
DN
P
FE
25
-1A
1
FE25-1A2
FE
25
-1A
3
FE25-1A4
100nF
4u7
MS
P4
32
P4
01
RIP
Z
100nF ML
20
GNDF
TS
H-1
05
-01
-F-D
-KGN
D
1uF/10V
4.7
uH
DN
P0R
91kO
hm
, 0.1
%, 2
5ppm
/C
GN
D
AV
SS
AV
SS
AV
SS
100nF
AV
SS
AV
SS
27R
27R
27R
27R
27R
27R
27
R
TLV
70
03
3D
DC
IC2
1u
F1
uF
GN
DG
ND
GN
D
JP
2X
2JP
2X
2
4k7
4k7
GND
Ext_
PW
R
MS
P-T
S4
32
PZ
10
0
Vcc
int
ext
Ta
rge
t So
cke
t Bo
ard
for M
SP
43
2P
40
1xIP
Z d
evic
e
DN
PD
NP
co
nn
ectio
n b
y v
ia
DN
P
DN
P
1.1
DN
P
DN
P
co
nn
ectio
n b
y v
ia
C2
C1
C4
R1
12
34
56
78
910
BS
L
123
J2
1 2 3
J1
1 2
JP
2
12J
P9
C5
R4
R5R6
Q1
C3
C6
C7
D1
R2
12J
P1
0
D2
R3
12J
P11
D3
R12
C8
C9
R8R9
Q2
SW
1
R13
TP2TP1
SW2
R14
12345678910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J3
26272829303132333435363738394041424344454647484950
J4
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
J5
767778798081828384858687888990919293949596979899
100
J6
C10
C12
AVCC145
AVCC2 87
AVSS143AVSS2 84
AVSS340
DCOR44
DV
CC
11
3
DV
CC
27
3
DV
SS
115
DV
SS
27
2
NC 82
P1.0
/UC
A0
ST
E4
P1.1
/UC
A0
CL
K5
P1.2
/UC
A0
RX
D/U
CA
0S
OM
I6
P1.3
/UC
A0
TX
D/U
CA
0S
IMO
7
P1.4
/UC
B0
ST
E8
P1.5
/UC
B0
CL
K9
P1.6
/UC
B0
SIM
O/U
CB
0S
DA
10
P1.7
/UC
B0
SO
MI/U
CB
0S
CL
11
P2.0
/PM
_U
CA
1S
TE
16
P2.1
/PM
_U
CA
1C
LK
17
P2.2
/PM
_U
CA
1R
XD
/PM
_U
CA
1S
OM
I1
8
P2.3
/PM
_U
CA
1T
XD
/PM
_U
CA
1S
IMO
19
P2.4
/PM
_TA
0.1
20
P2.5
/PM
_TA
0.2
21
P2.6
/PM
_TA
0.3
22
P2.7
/PM
_TA
0.4
23
P3.0/PM_UCA2STE32
P3.1/PM_UCA2CLK33
P3.2/PM_UCA2RXD/PM_UCA2SOMI34
P3.3/PM_UCA2TXD/PM_UCA2SIMO35
P3.4/PM_UCB2STE36
P3.5/PM_UCB2CLK37
P3.6/PM_UCB2SIMO/PM_UCB2SDA38
P3.7/PM_UCB2SOMI/PM_UCB2SCL39
P4.0
/A13
56
P4.1
/A12
57
P4.2
/AC
LK
/TA
2C
LK
/A11
58
P4.3
/MC
LK
/RT
CC
LK
/A10
59
P4.4
/HS
MC
LK
/SV
MH
OU
T/A
960
P4.5
/A8
61
P4.6
/A7
62
P4.7
/A6
63
P5.0
/A5
64
P5.1
/A4
65
P5.2
/A3
66
P5.3
/A2
67
P5.4
/A1
68
P5.5
/A0
69
P5.6
/TA
2.1
/VR
EF
+/V
ER
EF
+/C
1.7
70
P5.7
/TA
2.2
/VR
EF
-/VE
RE
F-/C
1.6
71
P6.0
/A15
54
P6.1
/A14
55
P6.2/UCB1STE/C1.5 76P6.3/UCB1CLK/C1.4 77
P6.4/UCB1SIMO/UCB1SDA/C1.3 78P6.5/UCB1SOMI/UCB1SCL/C1.2 79
P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1 80P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0 81
P7.0/PM_SMCLK/PM_DMAE0 88P7.1/PM_C0OUT/PM_TA0CLK 89P7.2/PM_C1OUT/PM_TA1CLK 90
P7.3/PM_TA0.0 91
P7.4/PM_TA1.4/C0.526
P7.5/PM_TA1.3/C0.427
P7.6/PM_TA1.2/C0.328
P7.7/PM_TA1.1/C0.229
P8.0/UCB3STE/TA1.0/C0.130
P8.1/UCB3CLK/TA2.0/C0.031
P8.2/TA3.2/A2346
P8.3/TA3CLK/A2247
P8.4/A2148
P8.5/A2049
P8.6/A1950
P8.7
/A18
51
P9.0
/A17
52
P9.1
/A16
53
P9.2
/TA
3.3
74
P9.3
/TA
3.4
75
P9.4/UCA3STE 96P9.5/UCA3CLK 97
P9.6/UCA3RXD/UCA3SOMI 98P9.7/UCA3TXD/UCA3SIMO 99
P10.0/UCB3STE 100
P10.1
/UC
B3C
LK
1
P10.2
/UC
B3S
IMO
/UC
B3S
DA
2
P10.3
/UC
B3S
OM
I/UC
B3S
CL
3
P10.4
/TA
3.0
/C0.7
24
P10.5
/TA
3.1
/C0.6
25
PJ.0/LFXIN41
PJ.1/LFXOUT42PJ.2/HFXOUT 85
PJ.3/HFXIN 86
PJ.4/TDI/ADC14CLK 92PJ.5/TDO/SWO 93
RSTN/NMI 83
SWCLKTCK 95
SWDIOTMS 94
VC
OR
E1
2
VS
W1
4
IC1
C13
12
34
56
78
910
11
12
13
14
JA
15
16
17
18
19
20
12
34
56
78
910
JB
C11 L1
R7
R15
Q3
KX-7
31
R16
C14
1 2
JP
16
R17
R18
R19
R20
R21
R22
R2
3
12
JP
7
IN1
EN
3
GND2
OU
T5
C1
5C
16
12
JP
8
12J
P1
2
1A2A
JP
3A
1B2B
JP
3B
1A2A
JP
4A
1B2B
JP
4B
1A2A
JP
5A
1B2B
JP
5B
1A2A
JP
6A
1B2B
JP
6B
1A
2A
JP
14
A1B
2B
JP
14
B
R10
R11
12 J
P1
5
123 J7
1 2
JP
1
P1
.0
P1
.0 RS
TN
/NM
I
RS
TN
/NM
I
RS
TN
/NM
I
RSTN/NMI
RS
TN
/NM
I
RS
TN
/NM
I
SW
DIO
TM
S
SW
DIO
TM
S
SW
DIO
TM
S
SWDIOTMS
TD
I
TD
I
TD
I
TDI
VC
C
VC
C
VC
C
VC
C
VC
C
INT
VC
C
INT
VC
C
INT
VC
C
EX
TV
CC
EX
TV
CC
P1
.1
P1
.1 SW
CL
KT
CK
SW
CL
KT
CK
SW
CL
KT
CK
SWCLKTCK
TD
O
TD
O
TD
O
TD
O
P1
.2
P1
.2
BS
LT
X
BS
LT
X
BS
LR
X
BS
LR
X
P1
.3
P1.3
AV
SS
AVSSAVSS
AVSS
LF
XO
UT
LF
XIN
LF
GN
D
HF
GN
D
HF
XIN
HF
XO
UT
DV
CC
DVCC
DV
CC
DV
CC
DV
CC
DV
CC
DV
SS
DV
SS
DV
SS
DV
SS
DV
SS
DV
SS
DV
SS
P1
.4
P1.4
P1
.5
P1.5
VC
OR
E
VC
OR
E
VS
W
VS
W
P3.6
P3
.6
P3
.6
P3.7P
3.7
P3
.7
DCOR
DC
OR
P6.7
P6
.7
P2
.0
P2
.0
P1
.7P
1.7
P1
.6
P1
.6
BS
L.1
0
BS
L.1
0B
SL
.9
BS
L.9
AV
CC
AVCC
AVCC
AV
CC
VU
SB
UART
I2C
SPI
1 2 3 4 5 6
1 2 3 4 5 6
Title
:
Da
te:
Pa
ge
1/1
MS
P-T
S4
32
PZ
10
0
3/3
/20
15
3:3
2:5
2 P
MA
3
IH
GF
ED
CB
A AB
CD
EF
GH
I
File
:
Re
v.:
Copyright © 2016, Texas Instruments Incorporated
www.ti.com MSP-TS432PZ100
15SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.2.5 Hardware Design
1.2.5.1 MSP-TS432PZ100 Rev 1.1Figure 1-7 shows the MSP-TS432PZ100 Rev 1.1 schematic.
Figure 1-7. MSP-TS432PZ100 Rev 1.1 Target Socket Board, Schematic
1
Vcc
ext
int
Vcc
GND
GND
RESET
Ext. Pwr.
PWR
DVCC
AVCC
GND
GND
P6.7
UA
RT
I2C
SP
I
BS
LS
ele
ctio
n
VC
C
GN
D
GN
D
101
2
1
12
55
10
15
20
26 5030 35 40 45
51
75
55
60
65
70
76100 80859095
201
2
1
2
9
10
MS
P-T
S4
32
PZ
10
0
Re
v. 1
.1R
oH
S
Q2
Q1
P1
.0
P1
.1
P1
.2
C2
C1
C4
R1
BSL
J2J1
JP2
JP9
C5R4
R5
R6
C3
C6C7
D1
R2
JP10
D2
R3
JP11
D3
R1
2
C8
C9
R8
R9
SW
1
R13
TP2
TP1
SW2
R14
J3
J4
J5
J6
C10
C1
2
IC1
C1
3
JA
JB
C11
L1
R7
R1
5
Q3
R16
C14
JP16
R17
R18
R1
9
R2
0R
21R
22
R23
JP
7
IC2
C1
5
C1
6JP
8
JP12
JP3
JP4
JP5 JP6
JP14R10
R11
JP15
J7
JP
1
Kle
bp
kt
MSP-TS432PZ100 www.ti.com
16 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
Figure 1-8 shows the MSP-TS432PZ100 Rev 1.1 assembly drawing.
Figure 1-8. MSP-TS432PZ100 Rev 1.1 Target Socket Board, PCB
Table 1-12 lists the key components of the MSP-TS432PZ100 Rev 1.1 board.
Table 1-12. MSP-TS432PZ100 Rev 1.1 Important Board Components
Reference Description CommentIC1 Socket for PZ100 package
J1 Selector between internal and external power supply. J1-J2 = InternalJ2-J3 = External
J2 Header to feed external voltage to device. If used, connect a 2-wirecable to J1-1, J1-2 (Vcc,Gnd).
J7 VCC header. Can be used to observe device VCC when supplied bythe debug probe or to feed in external power.
JA 20-pin Cortex-M debug connectorJB 10-pin Cortex-M debug connector
JP1 Header to measure current flowing into AVCC and DVCC powerdomains.
Jumper = Normal operationOpen = Measure current from pin 2 to 1
JP2 Header to disconnect DVCC from VCC supply. Connect an ammeterto measure current flowing into the digital domain.
Jumper = Normal operationOpen = Measure current from pin 2 to 1
www.ti.com MSP-TS432PZ100
17SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
Table 1-12. MSP-TS432PZ100 Rev 1.1 Important Board Components (continued)Reference Description Comment
JP8
Header to disconnect 3.3-V LDO voltage input from pin 19 of headerJA. Pin 19 of header JA is used by some third party ARM Cortex-Mdebuggers (for example, Segger J-Link and IAR i-Jet) to supply a 5-V voltage to the target system.
JP12Header to disconnect 3.3-V LDO voltage output from INTVCC.Remove this header if your debugger does not supply power toavoid current draw by the unpowered LDO.
JP15 Header to bypass 3V3 LDO in case a debug probe supplies a logiclevel voltage through pin 19 of header JA.
JP16 Header to disconnect AVCC from VCC supply. Connect an ammeterto measure current flowing into the analog domain.
Jumper = Normal operationOpen = Measure current from pin 2 to 1
1.2.5.1.1 Bill Of MaterialsTable 1-13 lists the bill of materials for the MSP-TS432PZ100 Rev 1.1.
Table 1-13. MSP-TS432PZ100 Rev 1.1 Bill Of Materials
Pos. Ref Des. No. No. PerBoard Description Digi-Key Part No. Comment
1 PCB 1 95.0 x 100.0 mm "MSP-TS432PZ100" Rev.1.1 2 layers, green solder mask
2 C1, C2 2 12pF, CSMD0805 1276-1120-1-ND DNP3 C8, C9 2 22pF, CSMD0805 490-3608-1-ND4 C3 1 10uF/10V, CSMD0805 490-1709-2-ND
5 C4, C6, C10, C13,C14 5 100nF, CSMD0805 490-1666-1-ND
6 C5 1 1.1nF, CSMD0805 490-1623-2-ND7 C7, C11, C15, C16 4 1uF/10V, CSMD0805 490-1702-2-ND8 C12 1 4u7, CSMD0805 445-1370-1-ND
9 D1 1 green LED, HSMG-C170,DIODE0805 516-1434-1-ND
10 D2 1 yellow LED, DIODE0805 DNP11 D3 1 red LED, DIODE0805 DNP12 R1 1 330R, 0805 541-330ATR-ND13 R2, R3, 2 330R, 0805 541-330ATR-ND DNP14 R5, R6, R7, R8, R9 5 0R, 0805 541-0.0ATR-ND DNP15 L1 1 4.7uH, 0806 490-4044-1-ND Murata16 R12, R13, R15 3 0R, 0805 541-0.0ATR-ND17 R4 1 47k, 0805 541-47KATR-ND18 R10, R11 2 4k7, 0805 541-4.7KATR-ND19 R14 1 47k, 0805 541-47KATR-ND DNP
20 R16 1 91kOhm, 0.1%, 25ppm/°C ,0805 P91KDACT-ND
21 R17, R18, R19,R20, R21, R22, R23 7 27R, 0805 541-27ATR-ND
22 JP1, JP2, JP9, JP7,JP16 4 2-pin header, male, TH SAM1035-02-ND Place jumper on header
23 JP8, JP12, JP15 3 2-pin header, male, TH SAM1035-02-ND Not jumpered
24 JP10, JP11 2 2-pin header, male, TH SAM1035-02-ND DNP, keep pads free ofsolder
25 J1 1 3-pin header, male, TH SAM1035-03-ND Place jumpers on pins 1-2
MSP-TS432PZ100 www.ti.com
18 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
Table 1-13. MSP-TS432PZ100 Rev 1.1 Bill Of Materials (continued)
Pos. Ref Des. No. No. PerBoard Description Digi-Key Part No. Comment
26 JP3, JP4, JP5, JP6,JP14 5 2x2-pin header, male, TH SAM1034-02-ND
27 J2, J7 2 3-pin header, male, TH SAM1035-03-ND
28 J3, J4, J5, J6 4 25-pin header, TH SAM1029-25-NDDNP: Headers are enclosedin kit. Keep vias free ofsolder.
29 J3, J4, J5, J6 4 25-pin receptacle, TH SAM1213-25-NDDNP: Receptacles areenclosed in kit. Keep viasfree of solder.
30 JA 1 20-pin connector, male, TH HRP20H-ND
31 JB 1 10-pin connector FTSH-105-01-F-D-K Samtec: FTSH-105-01-F-D-K
32 BSL 1 10-pin connector, male, TH HRP10H-ND
33 IC1 1 Socket: IC357-1004-053N,LQFP100 Manuf. Yamaichi
34 IC1 2 MSP432P401RIPZ Not enclosed in kit
35 Q1 1 MS3V-TR1 (32,768kHz/20ppm/12,5pF) depends on application
DNP, Micro Crystal,enclosed in kit, keep viasfree of solder
36 Q2 1 DNP, Crystal depends on application DNP, keep vias free ofsolder
37 Q3 1 KX-7T 48MHz 12pF30/30/50ppm Geyer Electronic - 12.88710
38 SW2 1 EVQ-11L05R P8079STB-ND39 SW1 1 EVQ-11L05R P8079STB-ND40 IC2 1 TLV70033DDC, TSOT23-5 296-25276-2-ND
1 1
2 2
3 3
4 4
5 5
6 6
DD
CC
BB
AA
12
2/1
0/2
01
7
Sch
em
atic
.Sch
Do
c
Sh
ee
tT
itle:
Siz
e:
Mo
d.
Da
te:
File
:S
he
et:
ofB
http
://ww
w.ti.c
om
Co
nta
ct:
http
://ww
w.ti.c
om
/su
pp
ort
MS
P-T
S4
32
PZ
10
0P
roje
ctT
itle:
De
sig
ne
dfo
r:Pu
blic
Re
lea
se
Asse
mb
lyV
aria
nt:[N
oV
aria
tion
s]
©T
exa
sIn
stru
me
nts
20
16
Dra
wn
By:
En
gin
ee
r:M
ike
Prid
ge
n
Te
xa
sIn
stru
me
nts
an
d/o
rits
lice
nso
rsd
on
ot
wa
rran
tth
ea
cc
ura
cy
or
co
mp
lete
ne
ss
of
this
sp
ecific
atio
no
ra
ny
info
rma
tion
co
nta
ine
dth
ere
in.Te
xa
sIn
stru
me
nts
an
d/o
rits
lice
nso
rsd
on
ot
wa
rran
tth
at
this
de
sig
nw
illm
ee
tth
esp
ecific
atio
ns,
will
be
su
itab
lefo
ryo
ur
ap
plic
atio
no
rfit
for
an
yp
artic
ula
rp
urp
ose
,o
rw
illo
pe
rate
ina
nim
ple
me
nta
tion
.Te
xa
sIn
stru
me
nts
an
d/o
rits
lice
nso
rsd
on
ot
wa
rran
tth
at
the
de
sig
nis
pro
du
ctio
nw
orth
y.Y
ou
sh
ou
ldco
mp
lete
lyva
lida
tea
nd
test
yo
ur
de
sig
nim
ple
me
nta
tion
toco
nfirm
the
syste
mfu
nctio
na
lityfo
ryo
ur
ap
pl
ica
tio
Ve
rsio
nco
ntro
ld
isa
ble
dS
VN
Re
v:
Nu
mb
er:
Re
v:
1.3
TID
#:
N/A
Ord
era
ble
:E
VM
_o
rde
rab
le
5 4 123678910
1112
13
14
15
16
17
18
19
20
21
22
23
24
25
J3
TS
W-1
25
-07
-G-S
5
4
1
2
3
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J4
TS
W-1
25
-07
-G-S
541 2 3 6 7 8 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J5
TS
W-1
25
-07
-G-S
P1
.0P
1.1
P1
.2
P1
.3P
1.4
P1
.5P
1.6
P1
.7V
CO
RE
DV
CC
VS
W
DV
SS
P2
.0
P3.6P3.7AVSS
AVSSDCORAVCC
1
2
JP
4H
MT
SW
-10
2-0
7-G
-S-2
40
1
2
JP
5H
MT
SW
-10
2-0
7-G
-S-2
40
33
0
R1
P1
.0
P2
.0
Gre
en
12
D1
0 R1
2
DV
SS
AV
SS
AV
SS
0.1
µF
C1
4
AV
CC
AV
SS
AV
SS
DC
OR
0.1
µF
C1
01
µF
C11
DV
CC
DV
SS
0.1
µF
C1
34
.7µ
FC
12
4.7
µH
L1
VS
W
VC
OR
E
DV
SS
P1
.1
DVCC
1 2
JP
3
HM
TS
W-1
02
-07
-G-S
-24
0
1 2
JP
2
HM
TS
W-1
02
-07
-G-S
-24
0
1 2
JP
1
HM
TS
W-1
02
-07
-G-S
-24
0
10µ
FC
30
.1µ
FC
4
AV
SS
AV
CC
DV
CC
12
34
56
78
91
0
111
2
13
14
15
17
19
16
18
20
JA
51
03
30
9-5
GN
D
VC
C
27
R1
7
27
R1
8
27
R1
9
RS
Tn
/NM
I
27
R2
0
27
R2
1
27
R2
2
12
34
56
78
91
0
JB
FT
SH
-10
5-0
1-F
-D-K
SW
DIO
TM
ST
DI
SW
CL
KT
CK
TD
O
GN
DV
CC
1µ
FC
15
1µ
FC
16
IN1
2
EN
3N
C4
OU
T5
GN
D
IC2
TL
V7
00
33
DD
CR
GN
D
GN
D
GN
D
VC
C GN
D 123
J2
TS
W-1
03
-07
-T-S
VC
CR
ST
n/N
MI
BS
LS
TE
VC
CG
ND
0.1
µF
C6
1µ
FC
7
DV
SS
DV
CC
DN
P
R5
DN
P
R6
DN
P
C1
DN
P
C2
LF
GN
D
AV
SS
48
MH
z
Q3
Q2
2F
A2
38
01
85
21
4
DN
P
R8
DN
P
R9
22
pF
C9
22
pF
C8
HF
GN
D
AV
SS
co
nn
ectio
nb
yvia
co
nn
ectio
nb
yvia
1 2 3
JP
6
TS
W-1
03
-07
-T-S
Use
Byp
ass
BS
LS
OM
I
47
k
R4
11
00
pF
C5
SW
2
EV
Q-1
1L
05
R
RS
Tn
/NM
I
DV
CC
91
.0k
R1
6
Q1
MS
3V
-T1
R
Q2
MS
3V
-T1
R
SW
1
EV
Q-1
1L
05
R
DN
PR
14
BS
LR
XB
SLT
XB
SL
SD
AB
SL
SIM
O
BS
LC
LK
BS
LS
CL
UA
RT
BS
LC
onnectio
n
I2C
BS
LC
onnectio
n
SP
IB
SL
Connectio
n
BS
LT
XB
SL
RX
P1
.3P
1.2
BS
LS
DA
BS
LS
CL
P3
.6P
3.7
P1
.7P
1.6
P1
.5P
1.4
BS
LS
OM
IB
SL
SIM
OB
SL
CL
KB
SL
ST
E
TP
3T
P4
TP
5T
P6
TP
7T
P8
TP
9T
P1
0
TP
1
4.7
k
R1
0
4.7
k
R11
I2C
Pullu
ps
VC
CP
3.6
P3
.7
DV
SS
0 R1
3
TP
2
GN
D
0 R2
40 R2
5
BS
LT
X
BS
LR
X34
56 710
JP
1:
1-2
SH
-JP
1
JP
2:
1-2
SH
-JP
2
JP
3:1
-2
SH
-JP
3
JP
4:
1-2
SH
-JP
4
JP
5:
1-2
SH
-JP
5
JP
6:
2-3
SH
-JP
6
Blu
e
21
D2
20
0
R2
DN
PR
70 R
15
HF
XO
UT
HF
XIN
_e
xt
HF
XO
UT
_e
xt
HF
XIN
0 R3
DV
SS
LFXOUT
LF
XO
UT
LF
XIN
LFXIN
LF
XO
UT
_e
xt
LF
XIN
_e
xt
LFXIN_ext
DV
CC
DV
SS
P9
.3/T
A3
.4P
9.2
/TA
3.3
DV
CC
2D
VS
S2
P5
.7/T
A2
.2/V
RE
F-/V
eR
EF
-/C1
.6P
5.6
/TA
2.1
/VR
EF
+/V
eR
EF
+/C
1.7
P5
.5/A
0P
5.4
/A1
P5
.3/A
2P
5.2
/A3
P5
.1/A
4P
5.0
/A5
P4
.7/A
6P
4.6
/A7
P4
.5/A
8P
4.4
/HS
MC
LK
/SV
MH
OU
T/A
9P
4.3
/MC
LK
/RT
CC
LK
/A1
0P
4.2
/AC
LK
/TA
2C
LK
/A11
P4
.1/A
12
P4
.0/A
13
P6
.1/A
14
P6
.0/A
15
P9
.2/A
16
P9
.0/A
17
P8
.7/A
18
P3.2/PM_UCA2RXD/PM_UCA2SOMI
P3.3/PM_UCA2TXD/PM_UCA2SIMOP3.4/PM_UCB2STEP3.5/PM_UCB2CLK
LFXOUT_ext
P3.6/PM_UCB2SIMO/PM_UCB2SDAP3.7/PM_UCB2SOMI/PM_UCB2SCLAVSS3
PJ.0/LFXINPJ.1/LFXOUT
AVSS1DCORAVCC1P8.2/TA3.2/A23P8.3/TA3CLK/A22P8.4/A21P8.5/A20P8.6/A19
P3.1/PM_UCA2CLKPM3.0/PM_UCA2STEP8.1/UCB3CLK/TA2.0/C0.0P8.0/UCB3STE/TA1.0/C0.1P7.7/PM_TA1.1/C0.2P7.6/PM_TA1.2/C0.3P7.5/PM_TA1.3/C0.4
P7.4/PM_TA1.5/C0.5
P1
.7/U
CB
0S
OM
I/UC
B0
SC
LP
1.6
/UC
B0
SIM
O/U
CB
0S
DA
P1
.5/U
CB
0C
LK
P1
.4/U
CB
0S
TE
P1
.3/U
CA
0T
XD
/UC
A0
SIM
O
P1
.2/U
CA
0R
XD
/UC
A0
SO
MI
P1
.1/U
CA
0C
LK
P1
.0/U
CA
0S
TE
P1
0.3
/UC
B3
SO
MI/U
CB
3S
CL
P1
0.2
/UC
B3
SIM
O/U
CB
3S
DA
P1
0.1
/UC
B3
CL
K
VC
OR
ED
VC
C1
VS
W
DV
SS
1P
2.0
/PM
_U
CA
1S
TE
P2
.1/P
M_
UC
A1
CL
KP
2.2
/PM
_U
CA
1R
XD
/PM
_U
CA
1S
OM
IP
2.3
/PM
_U
CA
1T
XD
/PM
_U
CA
1S
IMO
P2
.4/P
M_
TA
0.1
P2
.5/P
M_
TA
0.2
P2
.6/P
M_
TA
0.3
P2
.7/P
M_
TA
0.4
P1
0.4
/TA
3.0
/C0
.7P
10
.5/T
A3
.1/C
0.6
23456789
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
1
100
EP 101
IC1
5
4
1
2
3
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J6
TS
W-1
25
-07
-G-S
AVSS
HFXINHFXOUT HFXOUT_ext
HFXIN_ext
SWDIOTMSTDO_DevTDI
AVCC
RSTn/NMI
P6.7
SWCLKTCK
P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1P6.5/UCB1SOMI/UCB1SCL/C1.2P6.4/UCB1SIMO/UCB1SDA/C1.3P6.3/UCB1CLK/C1.4P6.2/UCB1STE/C1.5
RSTn/NMI
P10.0/UCB3STe
P9.7/UCA3TXD/UCA3SIMOP9.6/UCA3RXD/UCA3SOMIP9.5/UCA3CLKP9.4/UCA3STESWCLKTCKSWDIOTMSPJ.5/TDO/SWOPJ.4/TDI/ADC14CLK
P7.3/PM_TA0.0P7.2/PM_C1OUT/PM_TA1CLKP7.1/PM_COUT/PM_TA0CLKP7.0/PM_SMCLK/PM_DMAE0AVCC2
27
R2
3T
DO
TD
O_
De
v
12
34
SW
4
12
34
SW
5
12
34
SW
6
12
34
56
78
SW
3
DVSS3
AVSS
DV
SS
3
12
34
56
78
91
0
BS
L
AW
HW
-10
G-0
20
2-T
Exte
rna
l(N
C)
www.ti.com MSP-TS432PZ100
19SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.2.5.2 MSP-TS432PZ100 Rev 1.3Figure 1-9 shows the MSP-TS432PZ100 schematic.
Figure 1-9. MSP-TS432PZ100 Rev 1.3 Target Socket Board, Schematic
MSP-TS432PZ100 www.ti.com
20 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
Figure 1-10 shows the MSP-TS432PZ100 assembly drawing.
Figure 1-10. MSP-TS432PZ100 Rev 1.3 Target Socket Board, PCB
www.ti.com MSP-TS432PZ100
21SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
Table 1-14 lists the key components of the MSP-TS432PZ100 Rev 1.3 board.
Table 1-14. MSP-TS432PZ100 Rev 1.3 Important Board Components
Reference Description CommentIC1 Socket for PZ100 package
J2 Header to feed external voltage to device. If used, connect a2-wire cable to J1-1, J1-2 (VCC, GND).
JA 20-pin Cortex-M debug connectorJB 10-pin Cortex-M debug connector
JP1 Header to measure current flowing into AVCC and DVCCpower domains.
Jumper = normal operationOpen = measure current from pin 2 to 1
JP2 Header to disconnect DVCC from VCC supply. Connect anammeter to measure current flowing into the digital domain.
Jumper = normal operationOpen = measure current from pin 2 to 1
JP3 Header to disconnect AVCC from VCC supply. Connect anammeter to measure current flowing into the analog domain.
Jumper = normal operationOpen = measure current from pin 2 to 1
JP6 Header to select how VCC is supplied to the target.No Jumper = externally sourced VCCJumper pins 1-2 = VCC sourced from JTAG directlyJumper pins 2-3 = VCC sourced from LDO output
SW3 Switch to connect SPI BSL connections between targetdevice and BSL header Switch ON to enable, SW4 and SW5 should be OFF
SW4 Switch to connect UART BSL connections between targetdevice and BSL header Switch ON to enable, SW3 and SW5 should be OFF
SW5 Switch to connect I2C BSL connections between targetdevice and BSL header Switch ON to enable, SW3 and SW4 should be OFF
SW6 Switch to connect 4.7kOhm pullup resistors to target devicepins 38 and 39, which are also the I2C BSL connections
Switch ON to connect pullup resistorsSwitch OFF to disconnect pullup resistors
MSP-TS432PZ100 www.ti.com
22 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.2.5.2.1 Bill Of MaterialsTable 1-15 lists the bill of materials for the MSP-TS432PZ100 Rev 1.3.
Table 1-15. MSP-TS432PZ100 Rev 1.3 Bill Of Materials
Item Designator Quantity Description Supplier Part Number Note
1 !PCB1 1 PCB, 3.20" x 4.50" 2 layers, green soldermask
2 BSL 1 Header (shrouded), 100mil, 5x2,Gold, TH A33159-ND
3 C1, C2 0 CAP, CERM, 12 pF, 50 V, +/- 5%,C0G/NP0, 0805 311-1100-1-ND DNP
4 C3 1 CAP, CERM, 10 µF, 10 V, +/- 10%,X5R, 0805 490-1709-1-ND
5 C4, C6, C10,C13, C14 5 CAP, CERM, 0.1 µF, 50 V, +/- 10%,
X7R, 0805 490-1666-1-ND
6 C5 1 CAP, CERM, 1100 pF, 50 V, +/-5%, C0G/NP0, 0805 490-1623-1-ND
7 C7, C11,C15, C16 4 CAP, CERM, 1 µF, 10 V, +/- 10%,
X5R, 0805 490-1702-1-ND
8 C8, C9 2 CAP, CERM, 22 pF, 50 V, +/- 5%,C0G/NP0, 0805 490-3608-1-ND
9 C12 1 CAP, CERM, 4.7 µF, 10 V, +80/-20%, Y5V, 0805 311-1371-2-ND
10 D1 1 LED, Green, SMD 754-1939-1-ND11 D2 1 LED, Blue, SMD 732-4982-1-ND
12 H1, H2, H3,H4 4 125mil Mounting Hole
13 IC1 1 MSP432P401RIPZ Socket 945-IC357-1004-053N
14 IC2 1
Single Output LDO, 200 mA, Fixed3.3 V Output, 2 to 5.5 V Input, withLow IQ, 5-pin SOT (DDC), -40 to125 degC, Green (RoHS & noSb/Br)
296-27937-2-ND
15 J2, JP6 2 Header, 2.54 mm, 3x1, Tin, TH SAM1035-03-ND16 J3, J4, J5, J6 4 Header, 100mil, 25x1, Gold, TH SAM1029-25-ND
17 JA 1 Header (shrouded), 100mil, 10x2,Gold, TH A33166-ND
18 JB 1 Header, 1.27 mm, 5x2, Gold, TH FTSH-105-01-F-D-K-ND
19JP1, JP2,JP3, JP4,
JP55 Header, 100mil, 2x1, Gold, TH HMTSW-102-07-G-S-240-ND
20 L1 1 Inductor, Wirewound, Ferrite, 4.7µH, 0.3 A, 0.8 ohm, SMD 490-4044-1-ND
21 Q1, Q2 0 32.768KHz +/-20ppm 12.5pF 94M8466 DNP22 Q3 1 SMD Crystal FA-238 48.0000MB-W0-ND23 R1 1 RES, 330, 5%, 0.125 W, 0805 541-330ACT-ND24 R2 1 RES, 200, 5%, 0.125 W, 0805 541-200ACT-ND
25R3, R12,R13, R15,R24, R25
6 RES, 0, 5%, 0.125 W, 0805 541-0.0ACT-ND
26 R4 1 RES, 47 k, 5%, 0.125 W, 0805 541-47KACT-ND
27 R5, R6, R7,R8, R9 0 RES, 0, 5%, 0.125 W, 0805 541-0.0ACT-ND DNP
28 R10, R11 2 RES, 4.7 k, 5%, 0.125 W, 0805 541-4.7KACT-ND29 R14 0 RES, 47 k, 5%, 0.125 W, 0805 541-47KACT-ND DNP
30 R16 1 RES, 91.0 k, 0.1%, 0.125 W, AEC-Q200 Grade 0, 0805 P91KDACT-ND
www.ti.com MSP-TS432PZ100
23SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
Table 1-15. MSP-TS432PZ100 Rev 1.3 Bill Of Materials (continued)Item Designator Quantity Description Supplier Part Number Note
31
R17, R18,R19, R20,R21, R22,
R23
7 RES, 27, 5%, 0.125 W, 0805 541-27ACT-ND
32
SH-JP1, SH-JP2, SH-JP3,SH-JP4, SH-JP5, SH-JP6
6 Shunt, 100mil, Gold plated, Black 3M9580-NDJP1: 1-2, JP2: 1-2,JP3:1-2, JP4: 1-2,JP5: 1-2, JP6: 2-3
33 SW1, SW2 2 Switch Tactile SPST-NO 0.02A 15V P8079STB-ND
34 SW3 1 Quad Pole Single Throw TH DIPSwitch GH7198-ND
35 SW4, SW5,SW6 3 Double Pole Single Throw TH DIP
Switch GH7727-ND
36
TP1, TP2,TP3, TP4,TP5, TP6,TP7, TP8,TP9, TP10
0 Test Point, Miniature, Black, TH 36-5001-ND DNP
1.2.5.3 MSP-TS432PZ100 Revision History
Revision Date CommentsRev 1.1 March 2015 First released revisionRev 1.3 September 2016 Changed LDO configuration jumpers. Replaced BSL selection jumpers with switches.
MSP-FET www.ti.com
24 SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Hardware
1.3 MSP-FETSee the MSP Debuggers User’s Guide.
www.ti.com Revision History
25SLAU571D–March 2015–Revised June 2018Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Revision History
Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from July 20, 2017 to June 8, 2018 ................................................................................................................... Page
• Added note to description of jumper J2 in Table 1-8, Jumper Settings .......................................................... 12• Changed Figure 1-4, Board Configuration When Using Cortex-M Debug Probes With Target Power Supply Capability . 12• Changed "close pins 2-3 on JP6" to "close pins 1-2 on JP6" in the paragraph before Table 1-10, Jumper Settings for
Debug Probe Does Not Supply Logic Level on Pin 19 ............................................................................. 13• Changed the State column from "Close 2-3" to "Close 1-2" in Table 1-10, Jumper Settings for Debug Probe Does Not
Supply Logic Level on Pin 19 .......................................................................................................... 13• Changed Figure 1-5, Board Configuration for Debug Probe Does Not Supply Logic Level on Pin 19 ....................... 13• Changed "close pins 1-2 on JP6" to "close pins 2-3 on JP6" in the paragraph before Table 1-11, Jumper Settings for
Debug Probe Does Supply Logic Level on Pin 19 .................................................................................. 14• Changed the State column from "Close 1-2" to "Close 2-3" in Table 1-11, Jumper Settings for Debug Probe Does Supply
Logic Level on Pin 19 ................................................................................................................... 14• Changed Figure 1-6, Board Configuration for Debug Probe Does Supply Logic Level on Pin 19 ............................ 14• Changed Figure 1-10, MSP-TS432PZ100 Rev 1.3 Target Socket Board, PCB................................................. 20
STANDARD TERMS FOR EVALUATION MODULES1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordancewith the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are notfinished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. Forclarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditionsset forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or productionsystem.
2 Limited Warranty and Related Remedies/Disclaimers:2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused byneglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that havebeen altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specificationsor instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality controltechniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or creditUser's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warrantyperiod to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair orreplace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall bewarranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) daywarranty period.
3 Regulatory Notices:3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or softwareassociated with the kit to determine whether to incorporate such items in a finished product and software developers to writesoftware applications for use with the end product. This kit is not a finished product and when assembled may not be resold orotherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the conditionthat this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit mustoperate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTIONThis device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may notcause harmful interference, and (2) this device must accept any interference received, including interference that may causeundesired operation.Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority tooperate the equipment.
FCC Interference Statement for Class A EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment isoperated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if notinstalled and used in accordance with the instruction manual, may cause harmful interference to radio communications.Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required tocorrect the interference at his own expense.
FCC Interference Statement for Class B EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residentialinstallation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordancewith the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interferencewill not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, whichcan be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or moreof the following measures:
• Reorient or relocate the receiving antenna.• Increase the separation between the equipment and receiver.• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.• Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:(1) this device may not cause interference, and (2) this device must accept any interference, including interference that maycause undesired operation of the device.
Concernant les EVMs avec appareils radio:Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitationest autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doitaccepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna typeand its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary forsuccessful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna typeslisted in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibitedfor use with this device.
Concernant les EVMs avec antennes détachablesConformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type etd'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillageradioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotroperayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Leprésent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans lemanuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antennenon inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation del'émetteur
3.3 Japan3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certifiedby TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow theinstructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule forEnforcement of Radio Law of Japan,
2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect toEVMs, or
3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japanwith respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please notethat if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けていないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。2. 実験局の免許を取得後ご使用いただく。3. 技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社東京都新宿区西新宿6丁目24番1号西新宿三井ビル
3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to alow-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment thisproduct may cause radio interference in which case the user may be required to take adequate measures.
4 EVM Use Restrictions and Warnings:4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety informationrelated to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable andcustomary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to inputand output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, orproperty damage. If there are questions concerning performance ratings and specifications, User should contact a TIfield representative prior to connecting interface electronics including input power and intended loads. Any loads appliedoutside of the specified output range may also result in unintended and/or inaccurate operation and/or possiblepermanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting anyload to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuitcomponents may have elevated case temperatures. These components include but are not limited to linear regulators,switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using theinformation in the associated documentation. When working with the EVM, please be aware that the EVM may becomevery warm.
4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with thedangers and application risks associated with handling electrical mechanical components, systems, and subsystems.User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronicand/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safelylimit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility andliability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors ordesignees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes allresponsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility andliability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and localrequirements.
5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurateas possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites asaccurate, complete, reliable, current, or error-free.
6. Disclaimers:6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALLFAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUTNOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESSFOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADESECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BECONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL ORINTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THEEVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY ORIMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITSLICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANYHANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLYWHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGALTHEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8. Limitations on Damages and Liability:8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESETERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OFSUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL ORREINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OFUSE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TIMORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HASOCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDEDHEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR INCONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAREVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARECLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not ina resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicableorder, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating tothese terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive reliefin any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2018, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who aredeveloping applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms ofthis Notice.TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TIproducts, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,enhancements, improvements and other changes to its TI Resources.You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing yourapplications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. Yourepresent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures thatmight cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, youwill thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted anytesting other than that specifically described in the published documentation for a particular TI Resource.You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that includethe TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TOANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTYRIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationregarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty orendorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES ORREPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TOACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OFMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUALPROPERTY RIGHTS.TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOTLIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IFDESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH ORARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THEPOSSIBILITY OF SUCH DAMAGES.You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your non-compliance with the terms and provisions of this Notice.This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluationmodules, and samples (http://www.ti.com/sc/docs/sampterms.htm).
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2018, Texas Instruments Incorporated