M.Sc. ELECTRONICS (ELECTIVE)-Ilnmuacin.in/studentnotice/ddelnmu/2020/M.SC_PHYSICS_Electronic… ·...

M.Sc.

ELECTRONICS (ELECTIVE)-I

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CONTENTS

Chapters Page No.

1. OperationalAmplifiers 12. Modulation 343. Digital Electronics 514. Intel 8085 Microprocessor 1115. Optical Fiber Waveguides 149

NOTES

Operational Amplifiers

Self-Instructional Material 1

CHAPTER – 1

OPERATIONAL AMPLIFIERSSTRUCTURE

1.1 Learning Objectives 1.2 Introduction 1.3 DifferentialAmplifier 1.4 Operationalamplifier 1.5 Properties of practical op-amp 1.6 Effect of Negative Feed Back on Closed Loop op-amp 1.7 Applications of op-amp 1.8 Summary 1.9 Keywords 1.10 Review Questions 1.11 Further Readings

1.1 LEARNING OBJECTIVESAfter studying the chapter, students will be able to:

zz Toexplainthebasicdifferentialamplifier.zz Introducingtheoperationalamplifier.zz Todiscussthepropertiesofoperationalamplifier.zz To discuss the effect of negative feed back on(i) closed loop voltage gain(ii) input resistance(iii) output resistance and(iv) band-width of op-amp.zz To discuss the applications of op-amp

1.2 INTRODUCTIONTheoperationalamplifierisaversatiledevicethatcanbeusedtoamplifydcaswellasacinputsignals and was originally designed for computing such mathematical functions as addition, subtraction,multiplicationandintegration.Thusthenameoperationalamplifierstemsfromitsoriginal use for doing these mathematical operations and so is abbreviated to op-amp. With the additionofsuitableexternalfeedbackcomponentthemoderndayoperationalamplifiercanbeused for a variety of applications.

NOTES

Electronics-1

Self-Instructional Material2

Differential i/p resistance Ri (often referred to as i/p resistance) is the equivalent resistance that can be measured at either the inverting or non-inverting i/p terminal with the other terminal grounded. For the 741C the i/p resistance is relatively high 2 MW.

As the open loop gain of op-amp is very high, only very small signals (of the order ofmicro-voltsor less)havingverylowfrequencymaybeamplifiedaccuratelywithoutdistortion. However, signals this small are very susceptible to noise. Besides being large the open loop gain of the op-amp is not constant. The voltage gain varies with changes in temperature and power supply as well as with mass production techniques. The variations in voltage gain are relatively large in open-loop op-amp, in particular, which makes the open-loop op-amp unsuitable for many linear applications. In most linear applications the output is proportional to the input and is of the same type. Further the bandwidth (band of frequencies for which the gain remains constant) of most openloop op-amps is negligibly small - almost a zero. For this reason, the open-loop op-amp is impractical in ac applications. For instance the open loop bandwidth of the 741C is approximately 5Hz. However, in almost all ac applications a bandwidth larger than 5 Hz is needed.

Because of the above stated reasons, the open loop op-amp is generally not used in linear applications. Never the less in certain applications the open-loop op-amp is purposely used as a nonlinear device; that is a square ware output is obtained by deliberately applying a relatively largeinputsignal.Open-loopop-ampconfigurationsaremostsuitableinsuchapplications.

We will be able to select as well as control the gain of the op-amp, if we introduce a modificationinthebasiccircuit.Thismodificationinvolvestheuseoffeedback,thatis,anoutput signal is fed back to the input either directly or via another network. If the signal fed back is of opposite polarity or out of phase by 1800 with respect to input signal, the feedback is calledofnegativefeedback.Anamplifierwithnegativefeedbackhasaself-correctingabilityagainst any change in output voltage caused by changes in environmental conditions. Negative feedback is also known as degenerative feedback because when used it degenerates (reduces) the output voltage amplitude and in turn reduces the output gain.

Suppose the signal fed back is in phase with the input signal, the feedback is called positive feedback. In positive feedback, the feed back signal aids the input signal. For this reason it is also known as regenerative feedback. Positive feedback is necessary in oscillator circuits.

Therefore negative fed back stabilizes the gain, increases the bandwidth and changes the inputandoutputresistances,whenusedinamplifiers.Thepricepaidfortheseimprovementsisreducedvoltagegain.Otherbenefitsofnegativefeedbackincludeadecreaseinharmonicdistortion and reduction in effect of input offset voltage at the output. Negative feed back also reduces the effect of variation in temperature and supply voltages on the output of the op-amp.

1.3 DIFFERENTIAL AMPLIFIERThedifferentialamplifier,alsocalledadifferenceamplifier,asthenameimplies,amplifiesthedifference between two signals. Because of its balanced nature and symmetry, it can amplify very small signals. It usually requires a minimum number of capacitors and can operate without bypassandcouplingcapacitors.Itisthebasicbuildingblockofoperationalamplifiers,whichare most widely used in integrated circuits.

NOTES



Acharya Nagarjuna University 1 Centre for Distance Education

UNIT I:

LESSON 1

OPERATIONAL AMPLIFIERS I

Objectives:

to explain the basic differential amplifier

Introducing the operational amplifier

To discuss the properties of operational amplifier.

Structure of the lesson :

1.1 Differential Amplifier

1.2 Operational amplifier

1.3 Properties of practical op-amp

1.4 Summary of the Lesson

1.5 Key terminology

1.6 Self-assessment questions

1.7 Reference Books

1.1 Differential Amplifier

The differential amplifier, also called a difference amplifier, as the name implies, amplifies the

difference between two signals. Because of its balanced nature and symmetry, it can amplify very small

signals. It usually requires a minimum number of capacitors and can operate without bypass and coupling

capacitors. It is the basic building block of operational amplifiers, which are most widely used in

integrated circuits.

For a linear active device with two input signals v1 and v2 and the out put signals v0

each measured with respect to ground, we have

v0 = A (v1-v2)------(1.1)

where A is the voltage gain of the differential amplifier. In actual practice, the output depends not only

upon the difference of the two input signals but also upon the average level. In symmetrical circuits we

Linear activedevice

v1

v2v0

Fig 1.1 Schematic diagram of a differential amplifier.Fig. 1.1. Schematic diagram of a differential amplifier

For a linear active device with two input signals v1 and v2 and the out put signals v0 each measured with respect to ground, we have

v0 = A (v1 – v2) ...(1.1)

whereAisthevoltagegainofthedifferentialamplifier.Inactualpractice,theoutputdepends not only upon the difference of the two input signals but also upon the average level. In symmetrical circuits we talk about the in-phase signals (called common mode (CM) Signals vc) and the difference or anti-phase signals (called differential mode (DM) signals vd).Theyaredefinedas

vc = 12

(v1 + v2), and vd = (v1 – v2) ...(1.2)

The output v0 can be expressed as linear combination of the two input voltages, as v0 = A1 v1 + A2 v2 ...(1.3)Where A1 and A2arethevoltageamplificationsfrominput1and2respectively.From

equations (1.2) and (1.3) we get

vo = A1 (vc + 12

vd) + A2 (vc – 12

vd) = (A1 + A2) vc + 12

(A1 – A2) vd = Ac vc + Ad vd

...(1.4)where Ac = A1 + A2 and Ad =

12

( A1 – A2), are voltage gains for the signals in common

mode and differential modesrespectively.Theymaybedefinedas

M. Sc. Physics 2 Opamp I

talk about the in-phase signals (called common mode (CM) Signals vc) and the difference or anti-phase

signals (called differential mode (DM) signals vd). They are defined as

vc =21 (v1+v2), and vd = (v1 - v2)---------(1.2)

The output v0 can be expressed as linear combination of the two input voltages, as

v0=A1 v1 +A2 v2--------- (1.3)

Where A1 and A2 are the voltage amplifications from input 1and 2 respectively. From equations (1.2)

and (1.3) we get

vo = A1(vc +21 vd) + A2(vc -

21 vd) = (A1 + A2)vc +

21 (A1 - A2) vd = Ac vc + Ad vd--------------(1.4)

where Ac = A1 + A2 and Ad =21 ( A1 - A2), are voltage gains for the signals in common mode and

differential modes respectively. They may be defined as

Ad =0V

0

Cvv

d

and Ac =0Vc

0

dvv

------------(1.5)

Thus Ad can be measured directly by setting vc = 0, or v2 = - v1.

The Ac can be measured by setting vd = 0, or v2 = v1, generally the desired signals in differential amplifier

are DM and undesired signals are CM. The figure of merit for differential amplifier in defined as

= c

dAA ------------(1.6)

This is called the common-mode rejection ratio (CMRR) and is also some times referred to as the

discrimination factor of a differential amplifier. Ideally Ac=0, and CMRR= . In practice, A/c is non-

zero but very small, where as Ad is very large. The combination of equations (1.4) and (1.6) gives

Vo = Ad vd

dd

cc

vAvA

1 = Ad vd

CMRR1.

vv

1d

c

V0 = Ad vd (since CMRR = ) ---------------(1.7)

A basic differential amplifier circuit (ckt), consisting of two interlocked common emitter

amplifier stages is shown in fig (1.2). The two stages are linked by having both emitters

connected to a constant current generator. As current through one emitter increases, current

through the other decreases.

...(1.5)

Thus Ac can be measured directly by setting vd = 0, or v2 = – v1.The Ac can be measured by setting vd = 0, or v2 = v1, generally the desired signals in

differentialamplifierareDMandundesiredsignalsareCM.Thefigureofmeritfordifferentialamplifierindefinedas




vc =21 (v1+v2), and vd = (v1 - v2)---------(1.2)


v0=A1 v1 +A2 v2--------- (1.3)


and (1.3) we get

vo = A1(vc +21 vd) + A2(vc -

21 vd) = (A1 + A2)vc +

21 (A1 - A2) vd = Ac vc + Ad vd--------------(1.4)



Ad =0V

0

Cvv

d

and Ac =0Vc

0

dvv

------------(1.5)




= c

dAA ------------(1.6)




Vo = Ad vd

dd

cc

vAvA

1 = Ad vd

CMRR1.

vv

1d

c

V0 = Ad vd (since CMRR = ) ---------------(1.7)





...(1.6)

This is called the common-mode rejection ratio (CMRR) and is also some times referred toasthediscriminationfactorofadifferentialamplifier.IdeallyAc = 0, and CMRR= . In practice, A/c is nonzero but very small, where as Ad is very large. The combination of equations (1.4) and (1.6) gives




vc =21 (v1+v2), and vd = (v1 - v2)---------(1.2)


v0=A1 v1 +A2 v2--------- (1.3)


and (1.3) we get

vo = A1(vc +21 vd) + A2(vc -

21 vd) = (A1 + A2)vc +

21 (A1 - A2) vd = Ac vc + Ad vd--------------(1.4)



Ad =0V

0

Cvv

d

and Ac =0Vc

0

dvv

------------(1.5)




= c

dAA ------------(1.6)




Vo = Ad vd

dd

cc

vAvA

1 = Ad vd

CMRR1.

vv

1d

c

V0 = Ad vd (since CMRR = ) ---------------(1.7)





NOTES

Electronics-1


V0 = Ad vd (since CMRR = ) ...(1.7)Abasicdifferentialamplifiercircuit(ckt),consistingoftwointerlockedcommonemitter

amplifierstagesisshowninfig(1.2).Thetwostagesarelinkedbyhavingbothemittersconnected to a constant current generator. As current through one emitter increases, current through the other decreases.

The circuit is symmetric about the vertical dashed line and the two transistors and resistors Rc form a bridge circuit that is balanced under zero input signal. The resistors and the transistors are simultaneously fabricated in adjacent areas on a small chip. They will be at the same temperature. A simultaneous change in hFE or vBE will produce equal changes in the voltages at a and b and v0 will not be affected.


The circuit is symmetric about the vertical dashed line and the two transistors and resistors Rc

form a bridge circuit that is balanced under zero input signal. The resistors and the transistors

are simultaneously fabricated in adjacent areas on a small chip. They will be at the same

temperature. A simultaneous change in hFE or vBE will produce equal changes in the voltages at

a and b and v0 will not be affected.

Consider the circuit operation with no input signals. For v1=v2=0, an emitter current IE flows

in each BJT. Therefore IC = IE and

V01 = V02 = V CC – IC RC -----------------(1.8)

thus the base current IB =FE

E

hI

------------------(1.9)

and VE = -IB R1- VBE ----------------(1.10)

If vCE is chosen large enough to bias each BJT in the center or the linear operating region, then

VCC = VEE +2 IE RE +V CE + IC RC ----------------(1.11)

The ac equivalent circuit for use differential amplifier is shown in fig (1.3). Here it is

assumed

+VCC

V01 V02

C CA B

E

BB Q1

IC

RC

IC

RC

Q2

EVE

IE IE

2IE RE

-VEE

R1R2

V1 ~~ V2

Fig (1.2) Basic differential amplifier circuit diagramFig. (1.2). Basic differential amplifier circuit diagram

Consider the circuit operation with no input signals. For v1= v2 = 0, an emitter current IEflowsineachBJT.ThereforeIC = IE and

V01 = V02 = V CC – IC RC ...(1.8)

thus the base current


The circuit is symmetric about the vertical dashed line and the two transistors and resistors Rc

form a bridge circuit that is balanced under zero input signal. The resistors and the transistors

are simultaneously fabricated in adjacent areas on a small chip. They will be at the same

temperature. A simultaneous change in hFE or vBE will produce equal changes in the voltages at

a and b and v0 will not be affected.

Consider the circuit operation with no input signals. For v1=v2=0, an emitter current IE flows

in each BJT. Therefore IC = IE and

V01 = V02 = V CC – IC RC -----------------(1.8)

thus the base current IB =FE

E

hI

------------------(1.9)

and VE = -IB R1- VBE ----------------(1.10)


VCC = VEE +2 IE RE +V CE + IC RC ----------------(1.11)

The ac equivalent circuit for use differential amplifier is shown in fig (1.3). Here it is

assumed

+VCC

V01 V02

C CA B

E

BB Q1

IC

RC

IC

RC

Q2

EVE

IE IE

2IE RE

-VEE

R1R2

V1 ~~ V2

Fig (1.2) Basic differential amplifier circuit diagram

...(1.9)

and VE = –IB R1 – VBE ...(1.10)


VCC = VEE + 2 IE RE + VCE + IC RC ...(1.11)

Theacequivalentcircuitforusedifferentialamplifierisshowninfig(1.3).Hereitis assumed hoe RC <<1 or hoe <<1/RC andthushoeisomittedinthisfigure.Thecollectorcurrent Ic = hfe Ib. The voltage hre vc is neglected in comparison with the hib Ib drop across hie

NOTES




hoe RC <<1 or hoe <<1/RC and thus hoe is omitted in this figure. The collector current Ic = hfe Ib.

The voltage hre vc is neglected in comparison with the hib Ib drop across hie

Common mode voltage gain :

Let v1 = v2 = vs , user Ac =s

o

c

o

vv

vv

.

Due to symmetry, each input at the base, sees a common emitter circuit, with an un bypassed

emitter resister of 2RE (the emitter resistor is effectively doubled, as it carries the emitter current

for both transistors). Thus we have

Zi=R1+hie +2RE (1+hfe) and Z0 = Rc -----------(1.12)

Current gain = Ai =b

bfe

b

c

IIh-

II-

= - hfe ------------(1.13)

Voltage gain Av = feEie1

cfe

i

0i

h1R2hRRh-

ZZA

------------(1.14)

Since usually (1+hfe) 2RE >> hie and 1+hfe = hfe. The source resistance Ri << hie. Therefore

Av =E

C

2RR-

= common mode voltage gain Ac.

Differential mode voltage gain:-

Let –v2 = v1 =2vs ;

V01 V02

hfe Ibhfe Ib

hiehie

R1 R2

V1 ~ ~ V1RCRC

2IE

Fig (1.3) AC equivalent circuit of basic differential amplifier

A B

Fig. (1.3). AC equivalent circuit of basic differential amplifier

Common mode voltage gain:

Let v1 = v2 = vs , user Ac =






o

c

o

vv

vv

.






bfe

b

c

IIh-

II-

= - hfe ------------(1.13)


cfe

i

0i

h1R2hRRh-

ZZA

------------(1.14)


Av =E

C

2RR-



Let –v2 = v1 =2vs ;

V01 V02

hfe Ibhfe Ib

hiehie

R1 R2

V1 ~ ~ V1RCRC

2IE


A B

Due to symmetry, each input at the base, sees a common emitter circuit, with an un bypassed emitter resister of 2RE (the emitter resistor is effectively doubled, as it carries the emitter current for both transistors). Thus we have

Zi = R1 + hie +2RE (1 + hfe) and Z0 = Rc ...(1.12)

Current gain = Ai = –Ic

Ib =

–HfeIb

Ib = –hfe ...(1.13)

Voltage gain






o

c

o

vv

vv

.






bfe

b

c

IIh-

II-

= - hfe ------------(1.13)


cfe

i

0i

h1R2hRRh-

ZZA

------------(1.14)


Av =E

C

2RR-



Let –v2 = v1 =2vs ;

V01 V02

hfe Ibhfe Ib

hiehie

R1 R2

V1 ~ ~ V1RCRC

2IE


A B

...(1.14)

Since usually (1 + hfe) 2RE >> hie and 1 + hfe = hfe. The source resistance Ri << hie. Therefore

Av = –RC

2RE = common mode voltage gain Ac

Differential mode voltage gain:

Let






o

c

o

vv

vv

.






bfe

b

c

IIh-

II-

= - hfe ------------(1.13)


cfe

i

0i

h1R2hRRh-

ZZA

------------(1.14)


Av =E

C

2RR-



Let –v2 = v1 =2vs ;

V01 V02

hfe Ibhfe Ib

hiehie

R1 R2

V1 ~ ~ V1RCRC

2IE


A B

Therefore vd = v1, –v2 = vs and


Therefore vd = v1, -v2 = vs and Ad =d

0

vv

=s

0

vv

. From the symmetry of fig(1.2) for v1= -v2,

the emitter of each transistor is grounded for small signal operation i.e RE=0 and

Zi = 2(Ri +hie ), Zo Rc, Ai -hfe. ------------------(1.15)

Av = iei

cfe

i

0i

hR2Rh-

ZZA

------------------(1.16)

= differential mode voltage gain Ad.

Common mode rejection ratio:-

CMRR=c

d

AA

=

E

c

iei

cfe

2RR

hR2Rh-

= ie1

efe

hRRh-

---------(1.17)

Thus we see that CMRR increases with RE as desirable.

Constant current generators:

Instead of resistor RE, a constant current generator is used. It may be a JFET with its gate tied to

its source. A BJT can be used in a similar way with voltage divider bias. In both cases the

output current is approximately constant as long as the voltage across the device is sufficient.

Constant current bias:-

In the differential amplifier discussed so far, the combination of RE & VEE is used to set up the dc

emitter current. We can also use constant bias to set up the dc emitter current if desired. In fact

the constant current bias is better because it provides current stabilization and in turn, assures a

stable operating point for the differential amplifier. Fig(1.4). shows the dual input balanced

output differential amplifier using a resistive constant current bias. Notice that the resistor RE is

replaced by a constant current source transistor (Q3) circuit. The dc collector current in the

transistor Q3 is established by resisters R1 ,R2 and RE and can be determined as follows.

Applying the voltage divider rule, the voltage at the base of transistor Q3 (neglecting base

loading effect) is

VB3 = R2R

VR-

1

EE2

--------------(1.18)

VE3 = VB3 – VBE3 =

R2RVR-

1

EE2 – VBE3 --------------(1.19)

IE3 = IC3 =E

EEE3

R))(-V-(V

--------------(1.20)

Fromthesymmetryoffig(1.2)for

v1= -v2, the emitter of each transistor is grounded for small signal operation i.e RE = 0 andZi = 2(Ri + hie ), Zo Rc, Ai –hfe. ...(1.15)



0

vv

=s

0

vv




Av = iei

cfe

i

0i

hR2Rh-

ZZA

------------------(1.16)



CMRR=c

d

AA

=

E

c

iei

cfe

2RR

hR2Rh-

= ie1

efe

hRRh-

---------(1.17)















loading effect) is

VB3 = R2R

VR-

1

EE2

--------------(1.18)

VE3 = VB3 – VBE3 =

R2RVR-

1

EE2 – VBE3 --------------(1.19)

IE3 = IC3 =E

EEE3

R))(-V-(V

--------------(1.20)

= –HfeRc

2(Ri + hie) ...(1.16)

differential mode voltage gain Ad.

NOTES

Electronics-1





0

vv

=s

0

vv




Av = iei

cfe

i

0i

hR2Rh-

ZZA

------------------(1.16)



CMRR=c

d

AA

=

E

c

iei

cfe

2RR

hR2Rh-

= ie1

efe

hRRh-

---------(1.17)















loading effect) is

VB3 = R2R

VR-

1

EE2

--------------(1.18)

VE3 = VB3 – VBE3 =

R2RVR-

1

EE2 – VBE3 --------------(1.19)

IE3 = IC3 =E

EEE3

R))(-V-(V

--------------(1.20)

– – ...1.17)


Constant Current GeneratorsInstead of resistor RE, a constant current generator is used. It may be a JFET with its gate tied to its source. A BJT can be used in a similar way with voltage divider bias. In both cases the outputcurrentisapproximatelyconstantaslongasthevoltageacrossthedeviceissufficient.

Constant Current BiasInthedifferentialamplifierdiscussedsofar,thecombinationofRE & VEE is used to set up the dc emitter current. We can also use constant bias to set up the dc emitter current if desired. In fact the constant current bias is better because it provides current stabilization andinturn,assuresastableoperatingpointforthedifferentialamplifier.Fig(1.4).showsthedualinputbalancedoutputdifferentialamplifierusingaresistiveconstantcurrentbias.Notice that the resistor RE is replaced by a constant current source transistor (Q3) circuit. The dc collector current in the transistor Q3 is established by resisters R1, R2 and RE and can be determined as follows.

Applying the voltage divider rule, the voltage at the base of transistor Q3 (neglecting base loading effect) is



0

vv

=s

0

vv




Av = iei

cfe

i

0i

hR2Rh-

ZZA

------------------(1.16)



CMRR=c

d

AA

=

E

c

iei

cfe

2RR

hR2Rh-

= ie1

efe

hRRh-

---------(1.17)















loading effect) is

VB3 = R2R

VR-

1

EE2

--------------(1.18)

VE3 = VB3 – VBE3 =

R2RVR-

1

EE2 – VBE3 --------------(1.19)

IE3 = IC3 =E

EEE3

R))(-V-(V

--------------(1.20)

–

...(1.18)


IC3 = vEE -

R2RVR-

1

EE2 .E

BE3

RV

---------------(1.21)

Because two halves of the differential amplifier are symmetrical, each has half of current Ice3.

That is

IE1 = IE2 =2

IC3 = VEE -

R2RVR

1

EE2 .E

BE3

2RV

---------------(1.22)

The collector current Ic3 in transistor Q3 is fixed and must be invariant because no signal is

injected into either the emitter or the base of Q3. Thus the transistor Q3 is a source of constant

emitter current for transistors Q1 and Q2 of the differential amplifier. Besides supplying constant

emitter current, the constant current bias also provides a very high source resistance since the ac

equivalent of the dc current source is ideally an open circuit.

1.2 Operational amplifier:

An operational amplifier is a direct-coupled high gain amplifier usually consists of one or more

differential amplifiers and usually followed by a level translator and an output stage. The output

Rin2

V0– +

Ic3

VB3

Q2

Rc

+VCC

Rc

Q1

Rin1

+RE VE3

–

R2+ –+

R1–

Q3

– VEE

Fig (1.4) Differential amplifier using constant current bias.

Vin1 ~ ~Vin

2

Fig. (1.4). Differential amplifier using constant current bias.

NOTES





0

vv

=s

0

vv




Av = iei

cfe

i

0i

hR2Rh-

ZZA

------------------(1.16)



CMRR=c

d

AA

=

E

c

iei

cfe

2RR

hR2Rh-

= ie1

efe

hRRh-

---------(1.17)















loading effect) is

VB3 = R2R

VR-

1

EE2

--------------(1.18)

VE3 = VB3 – VBE3 =

R2RVR-

1

EE2 – VBE3 --------------(1.19)

IE3 = IC3 =E

EEE3

R))(-V-(V

--------------(1.20)

–

...(1.19)



0

vv

=s

0

vv




Av = iei

cfe

i

0i

hR2Rh-

ZZA

------------------(1.16)



CMRR=c

d

AA

=

E

c

iei

cfe

2RR

hR2Rh-

= ie1

efe

hRRh-

---------(1.17)















loading effect) is

VB3 = R2R

VR-

1

EE2

--------------(1.18)

VE3 = VB3 – VBE3 =

R2RVR-

1

EE2 – VBE3 --------------(1.19)

IE3 = IC3 =E

EEE3

R))(-V-(V

--------------(1.20)– –

...(1.20)M. Sc. Physics 6 Opamp I

IC3 = vEE -

R2RVR-

1

EE2 .E

BE3

RV

---------------(1.21)


That is

IE1 = IE2 =2

IC3 = VEE -

R2RVR

1

EE2 .E

BE3

2RV

---------------(1.22)









Rin2

V0– +

Ic3

VB3

Q2

Rc

+VCC

Rc

Q1

Rin1

+RE VE3

–

R2+ –+

R1–

Q3

– VEE


Vin1 ~ ~Vin

2

–– ...(1.21)

Because twohalvesof thedifferential amplifier are symmetrical, eachhashalf ofcurrent Ice3.

That is


IC3 = vEE -

R2RVR-

1

EE2 .E

BE3

RV

---------------(1.21)


That is

IE1 = IE2 =2

IC3 = VEE -

R2RVR

1

EE2 .E

BE3

2RV

---------------(1.22)









Rin2

V0– +

Ic3

VB3

Q2

Rc

+VCC

Rc

Q1

Rin1

+RE VE3

–

R2+ –+

R1–

Q3

– VEE


Vin1 ~ ~Vin

2

– ...(1.22)

The collector current Ic3 in transistor Q3 isfixedandmustbeinvariantbecausenosignal is injected into either the emitter or the base of Q3. Thus the transistor Q3 is a source of constant emitter current for transistors Q1 and Q2ofthedifferentialamplifier.Besidessupplying constant emitter current, the constant current bias also provides a very high source resistance since the ac equivalent of the dc current source is ideally an open circuit.

1.4 OPERATIONAL AMPLIFIERAnoperationalamplifierisadirect-coupledhighgainamplifierusuallyconsistsofoneormoredifferentialamplifiersandusuallyfollowedbyaleveltranslatorandanoutputstage.The output stage is generally a push pull or push pull complementary symmetry pair. An operationalamplifier isavailableasa single integratedcircuitpackage.Theoperationalamplifierisaversatiledevicethatcanbeusedtoamplifydcaswellasacinputsignalsandwas originally designed for computing such mathematical functions as addition, subtraction, multiplicationandintegration.Thusthenameoperationalamplifierstemsfromitsoriginaluse for doing these mathematical operations and so is abbreviated to op-amp. With the additionofsuitableexternalfeedbackcomponentthemoderndayoperationalamplifiercanbeusedforavarietyofapplications.Suchasacanddcsignalamplification,activefilters,oscillators, comparators, regulators and others.

Block Diagram Representation of a Typical op-amp Sinceanop-ampisamultistageamplifier.Itcanberepresentedbyablockdiagramshowninfigure(1.5).

The input stage is thedual inputbalancedoutputdifferential amplifier.This stagegenerallyprovidesmostofthevoltagegainoftheamplifierandalsoestablishestheinputresistanceoftheop-amp.Theintermediatestageisusuallyanotherdifferentialamplifier,whichisdrivenbytheoutputofthefirststage.Inmostamplifiers,theintermediatestageisdual input unbalanced (single ended) output. Because direct coupling is used, the dc voltage

NOTES

Electronics-1


at the output of the intermediate stage is well above ground potential. Therefore, the level translator circuit is used after the intermediate stage to shift the dc level at the output of theintermediatestagedownwardtozerovoltagewithrespecttoground.Thefinalstageisusuallyapushpullcomplementaryamplifieroutputstage.Theoutputstageincreasestheoutput voltage swing and raises the current supplying capabilities of the op-amp. The well designed output stage also provides low output resistance.


stage is generally a push pull or push pull complementary symmetry pair. An operational

amplifier is available as a single integrated circuit package. The operational amplifier is a

versatile device that can be used to amplify dc as well as ac input signals and was originally

designed for computing such mathematical functions as addition, subtraction, multiplication and

integration. Thus the name operational amplifier stems from its original use for doing these

mathematical operations and so is abbreviated to op-amp. With the addition of suitable external

feed back component the modern day operational amplifier can be used for a variety of

applications. Such as ac and dc signal amplification, active filters, oscillators, comparators,

regulators and others.

Block diagram representation of a typical op-amp:

Since an op-amp is a multistage amplifier. It can be represented by a block diagram shown in

figure (1.5)

The input stage is the dual input balanced output differential amplifier. This stage generally

provides most of the voltage gain of the amplifier and also establishes the input resistance of the

op-amp. The intermediate stage is usually another differential amplifier, which is driven by the

output of the first stage. In most amplifiers, the intermediate stage is dual input unbalanced

(single ended) output. Because direct coupling is used, the dc voltage at the output of the

intermediate stage is well above ground potential. Therefore, the level translator circuit is used

after the intermediate stage to shift the dc level at the output of the intermediate stage downward

to zero voltage with respect to ground. The final stage is usually a push pull complementary

amplifier output stage. The output stage increases the output voltage swing and raises the current

supplying capabilities of the op-amp. The well designed output stage also provides low output

resistance.

Input

stage

Intermediate stage

Levelshifting

stage

Out putstage Output

InvertingInput

Non-InvertingInput

Fig (1.5) Block diagram of a typical op-amp

Dual input Dual input complementaryBalanced output unbalanced output emitter follower symmetryDifferential Differential using constant push pull amplifierAmplifier amplifier current source

Fig. (1.5). Block diagram of a typical op-amp

Schematic SymbolThemostwidelyusedsymbolforacircuitwithtwoinputsandoneoutputisshowninfig(1.6)


Schematic symbol:

The most widely used symbol for a circuit with two inputs and one out put is shown in fig

(1.6)

In fig (1.6)

v1 = voltage at the non-inverting input (volts)

v2 = voltage at the inverting input (volts)

vo = output voltage (voltage)

All these are measured w.r.t. ground

A = large signal voltage gain that is specified on the data sheets for an op-amp

For amplifier, power supply and other pin connections are omitted. Since the input differential

amplifier stage of the op-amp is designed to be operated in the differential mode, the differential

inputs are designated by the (+) and (-) notations, the (+) input is used for non-inverting input.

An ac signal (or dc voltage) applied to this input produces an in-phase (or same polarity) signal

at the output. On the other hand the (-) input is the inverting input because an ac signal (or dc

voltage) applied to this input produces an 180 out of phase (or opposite polarity) signal at the

output.

Ideal op-amp:

An ideal op-amp exhibits the following electrical characteristics.

(1) Infinite voltage gain AV.

(2) Infinite input resistance Ri, so that, almost any signal source can drive it and there is no

loading of the preceding stage.

(3) Zero output resistance Ro, so that, output can drive an infinite number of other devices

(4) Zero output voltage when the input voltage is zero.

(5) Infinite bandwidth, so that, any frequency signal from 0 to Hz can be amplified with

out attenuation.

(6) Infinite common mode rejection ratio so that output common mode noise voltage is zero.

Fig (1.6) Schematic symbol of op-amp

V0 outputNon-inverting input V1

Inverting input V2

+

A

–

Fig. (1.6). Schematic symbol of op-amp

Infig(1.6)v1 = voltage at the non-inverting input (volts)v2 = voltage at the inverting input (volts)vo = output voltage (voltage)All these are measured w.r.t. groundA=largesignalvoltagegainthatisspecifiedonthedatasheetsforanop-ampForamplifier,powersupplyandotherpinconnectionsareomitted.Sincetheinput

differentialamplifierstageoftheop-ampisdesignedtobeoperatedinthedifferentialmode,the differential inputs are designated by the (+) and (-) notations, the (+) input is used for non-inverting input.

An ac signal (or dc voltage) applied to this input produces an in-phase (or same polarity) signal at the output. On the other hand the (-) input is the inverting input because an ac signal (or dc voltage) applied to this input produces an 180 out of phase (or opposite polarity) signal at the output.

Ideal op-ampAn ideal op-amp exhibits the following electrical characteristics.

(1) InfinitevoltagegainAV.

NOTES



(2) InfiniteinputresistanceRi, so that, almost any signal source can drive it and there is no loading of the preceding stage.

(3) Zero output resistance Ro,sothat,outputcandriveaninfinitenumberofotherdevices

(4) Zero output voltage when the input voltage is zero.

(5) Infinitebandwidth,sothat,anyfrequencysignalfrom0toHzcanbeamplifiedwith out attenuation.

(6) Infinitecommonmoderejectionratiosothatoutputcommonmodenoisevoltageis zero.

(7) Infiniteslewratesothatvoltagechangesoccursimultaneouslywithinputvoltagechanges.

There are practical op-amps that can be made to achieve some of these characteristic using a negative feedback arrangement. In particular, the input resistance, the output resistance, and bandwidth can be brought close to ideal values by this method.

Equivalent circuit of an op-amp: Fig (1.7) shows an equivalent circuit of an op-amp. The circuit includes important values from the data sheets: A , Ri and Ro.

Note that A vid is an equivalent Thevenin voltage source, and Ro is the Thevenin equivalent resistance looking back into the output terminal of an op-amp.


(7) Infinite slew rate so that voltage changes occur simultaneously with input voltage

changes.

There are practical op-amps that can be made to achieve some of these characteristic using a

negative feedback arrangement. In particular, the input resistance, the output resistance, and

bandwidth can be brought close to ideal values by this method.

Equivalent circuit of an op-amp: Fig (1.7) shows an equivalent circuit of an op-amp. The

circuit includes important values from the data sheets: A , Ri and Ro.

Note that A vid is an equivalent Thevenin voltage source, and Ro is the Thevenin equivalent

resistance looking back into the output terminal of an op-amp.

The equivalent circuit is useful in analyzing the basic operating principles of op-amps and in

observing the effectiveness of feed back arrangement. For the circuit shown in fig (1.7), the

output voltage is

v0 = Avid = A (v1-v2) ---------------(1.23)

Where A = large- signal voltage gain

vid = difference input voltage

v1 = voltage at the non-inverting input terminal w.r.t. ground.

v2 = voltage at the inverting input terminal w.r.t. ground.

Eqn.(1.23) indicates that the output voltage v0 is directly proportional to the algebraic difference

between the two input voltages. In other words the op-amp amplifies the difference between

the two input voltages; it does not amplify the input signal voltages themselves. For this reason

the polarity of the output voltage depends upon the polarity of the difference voltage.

R0

Fig (1.7) Equivalent circuit of op-amp

Inverting input V2

Non-inverting input V1

Vid

– VEE

+VCC

+AVid

–

out putV0 = AVid

Rii–

+

Fig. (1.7). Equivalent circuit of op-amp

The equivalent circuit is useful in analyzing the basic operating principles of op-amps andinobservingtheeffectivenessoffeedbackarrangement.Forthecircuitshowninfig(1.7), the output voltage is

v0 = Avid = A (v1 – v2) ...(1.23)

Where A = large- signal voltage gain

vid = difference input voltage

v1 = voltage at the non-inverting input terminal w.r.t. ground.

v2 = voltage at the inverting input terminal w.r.t. ground.

Eqn.(1.23) indicates that the output voltage v0 is directly proportional to the algebraic differencebetweenthetwoinputvoltages.Inotherwordstheop-ampamplifiesthedifferencebetween the two input voltages; it does not amplify the input signal voltages themselves. For this reason the polarity of the output voltage depends upon the polarity of the difference voltage.

NOTES

Electronics-1


1.5 PROPERTIES OF PRACTICAL OP-AMPToenhanceourunderstandingofop-amps,weneedtodefinesomeparametersthatappearon data sheet of practical op-amp.

(1) Voltage gain:

Fig (1.8) shows an idealized transfer characteristic

In the active region the slope of the curve is the differential mode voltage gain Ad is definedas

Ad =


1.3 Properties of practical op-amp:

To enhance our understanding of op-amps, we need to define some parameters that appear on

data sheet of practical op-amp.

(1) Voltage gain:


In the active region the slope of the curve is the differential mode voltage gain Ad is defined as

Ad =d

0

vv

, where vd = v1-v2, the differential mode input. Ad is very large ~ 106.

To stabilize the voltage gain, negative feedback is always used. Fig (1.8) shows that the

voltage gain is virtually zero when the output is at saturation level.

(2) Input impedance Ri:

It is the open loop incremental impedance looking into the two input terminals. It is large

(~M )

(3) Output impedance Ro:

It is the open loop impedance across the output. It is low (~ 100 )

(4) ): Common mode rejection ratio (CMRR):

The op-amp should ideally respond to a difference mode only. There will also be an

output for the common mode input, because of the nature of the input circuit any (differential

amplifier). The common mode gain Ac =cv

v0

The ratio of these two gains is defined as common mode rejection ratio

V1 – V2

Active region

Positive saturation

NegativeSaturation

– VEE

+ VCC

V0

Fig (1.8) Idealized transfer characteristic of op-amp

, where vd = v1 – v2, the differential mode input. Ad is very large ~ 106.





(1) Voltage gain:



Ad =d

0

vv






(~M )







v0


V1 – V2

Active region

Positive saturation

NegativeSaturation

– VEE

+ VCC

V0

Fig (1.8) Idealized transfer characteristic of op-ampFig. (1.8). Idealized transfer characteristic of op-amp





(~M )





output for the common mode input, because of the nature of the input circuit any

(differentialamplifier).Thecommonmodegain Ac =





(1) Voltage gain:



Ad =d

0

vv






(~M )







v0


V1 – V2

Active region

Positive saturation

NegativeSaturation

– VEE

+ VCC

V0

Fig (1.8) Idealized transfer characteristic of op-amp

The ratioofthesetwogainsisdefinedascommonmoderejectionratio


CMRR =c

d

AA

---------------- (1.24)

It is usually expressed in decibels, as 20 log 10 (CMRR) = 20 log 10 | Ad | - 20 log 10 |Ac|

It is having a value 70 dB to 100 dB

Op-amps are further classified into two groups: general- purpose and special purpose.

General- purpose op-amps may be used for a variety of applications such as integrator,

differentiator, summing amplifier and others. An example of a widely used general-purpose

op-amp is the 741/351. On the other hand, special purpose op-amps are used only for the

specific applications they are designed for. For example the LM 380 op-amp can be used

only for audio power applications;

The pin configuration of most widely used 741 op-amp is given below

It is the most commonly used general-purpose op-amp. It has an integrated 30pF MOS

capacitor. It has high input impedance (> M ), low output impedance (750 ) and large

voltage gain (200,000). From here onwards all the discussions are confined to A741 op-amp.

The electrical parameters of op-amp are defined in the following paragraphs.

Input offset voltage: Input offset voltage is the voltage that must be applied between the two

input terminals of an op-amp to null the output as shown in fig (1.10). In fig (1.10) Vdc1 and

Vdc2 are dc voltages and Rs represents the source resistance. We denote input offset voltage

by Vi0. This voltage Vi0 could be positive or negative;

5 OFF SET NULL

6 OUTPUT

7 +VCCInverting I/P 2

– VEE 4

8 NCOFF SET NULL 1

Non-inverting I/P 3

5

Fig (1.9) pin configuration of A-741 op-amp

–A

+

...(1.24)

NOTES



It is usually expressed in decibels, as 20 log 10 (CMRR) = 20 log 10 | Ad | – 20 log 10 |Ac|


Op-ampsarefurtherclassifiedintotwogroups:general-purposeandspecialpurpose.

General purpose op-amps may be used for a variety of applications such as integrator, differentiator,summingamplifierandothers.Anexampleofawidelyusedgeneral-purposeop-amp is the 741/351. On the other hand, special purpose op-amps are used only for the specificapplicationstheyaredesignedfor.ForexampletheLM380op-ampcanbeusedonly for audio power applications;

Thepinconfigurationofmostwidelyused741op-ampisgivenbelow


capacitor. It has high input impedance (> M), low output impedance (750 ) and large

voltagegain(200,000).FromhereonwardsallthediscussionsareconfinedtoA741 op-

amp.Theelectricalparametersofop-amparedefinedinthefollowingparagraphs.


CMRR =c

d

AA

---------------- (1.24)

It is usually expressed in decibels, as 20 log 10 (CMRR) = 20 log 10 | Ad | - 20 log 10 |Ac|


Op-amps are further classified into two groups: general- purpose and special purpose.

General- purpose op-amps may be used for a variety of applications such as integrator,

differentiator, summing amplifier and others. An example of a widely used general-purpose

op-amp is the 741/351. On the other hand, special purpose op-amps are used only for the

specific applications they are designed for. For example the LM 380 op-amp can be used

only for audio power applications;

The pin configuration of most widely used 741 op-amp is given below


capacitor. It has high input impedance (> M ), low output impedance (750 ) and large

voltage gain (200,000). From here onwards all the discussions are confined to A741 op-amp.

The electrical parameters of op-amp are defined in the following paragraphs.

Input offset voltage: Input offset voltage is the voltage that must be applied between the two

input terminals of an op-amp to null the output as shown in fig (1.10). In fig (1.10) Vdc1 and

Vdc2 are dc voltages and Rs represents the source resistance. We denote input offset voltage

by Vi0. This voltage Vi0 could be positive or negative;

5 OFF SET NULL

6 OUTPUT

7 +VCCInverting I/P 2

– VEE 4

8 NCOFF SET NULL 1

Non-inverting I/P 3

5

Fig (1.9) pin configuration of A-741 op-amp

–A

+

Fig. (1.9). pin configuration of A-741 op-amp

Input offset voltage: Input offset voltage is the voltage that must be applied between thetwoinputterminalsofanop-amptonulltheoutputasshowninfig(1.10).Infig(1.10)Vdc1 and Vdc2 are dc voltages and Rs represents the source resistance. We denote input offset voltage by Vi0. This voltage Vi0 could be positive or negative;


For 741C, the maximum value of Vi0 is 6 mV DC. The smaller the value of vi0, the better the

input terminals are matched.

Input offset Current:

The algebraic difference between the currents into the inverting and non-inverting terminals

is referred to as input offset current Ii0 (see fig.1.11). In the form of an equation.

Ii0 = |IB1-IB2|

Where Ib1is the current into the non-inverting input Ib2 is the current into the inverting input

The input offset current for the 741C is 200 nA maximum. As the matching between the

two input terminals is improved, the difference between IB1 and IB2 becomes smaller; that is,

the Ii0 value decreases further.

Input Bias current:

Input bias current IB is the average of the currents that flow into the inverting and non-

inverting input terminals of the op-amp. In equation form

IB =2

II B2B1

IB = 500 nA maximum for the 741C, where as IB for the precision 741C is 7 nA

Fig (1.10) Defining input offset voltage Vi0

Rs 10k

+VCCVdc1 Rs 10k

Vio = (Vdc1 – Vdc2)

VEE

2

output

Vo = 0V

Vdc2

7Vio

+741 C

– 4

36

– +

– +

Fig (1.11) defining input offset current Ii0

+VCC

OUTPUT

IB1

IB2

3

4

67

Ii0 = |IB1-IB2|-VEE

2

+741

–

Fig. (1.10). Defining input offset voltage Vi0

For 741C, the maximum value of Vi0 is 6 mV DC. The smaller the value of vi0, the better the input terminals are matched.

NOTES

Electronics-1


Input offset CurrentThe algebraic difference between the currents into the inverting and non-inverting terminals

is referred to as input offset current Ii0(seefig.1.11).Intheformofanequation.

Ii0 = |IB1 – IB2|

Where Ib1 is the current into the non-inverting input Ib2 is the current into the inverting input The input offset current for the 741C is 200 nA maximum. As the matching between the two input terminals is improved, the difference between IB1 and IB2 becomes smaller; that is, the Ii0 value decreases further.







Ii0 = |IB1-IB2|





Input Bias current:



IB =2

II B2B1



Rs 10k

+VCCVdc1 Rs 10k


VEE

2

output

Vo = 0V

Vdc2

7Vio

+741 C

– 4

36

– +

– +


+VCC

OUTPUT

IB1

IB2

3

4

67

Ii0 = |IB1-IB2|-VEE

2

+741

–

Fig. (1.11). Defining input offset current Ii0

Input Bias CurrentInputbiascurrentIBistheaverageofthecurrentsthatflowintotheinvertingandnoninvertinginput terminals of the op-amp. In equation form







Ii0 = |IB1-IB2|





Input Bias current:



IB =2

II B2B1



Rs 10k

+VCCVdc1 Rs 10k


VEE

2

output

Vo = 0V

Vdc2

7Vio

+741 C

– 4

36

– +

– +


+VCC

OUTPUT

IB1

IB2

3

4

67

Ii0 = |IB1-IB2|-VEE

2

+741

–

IB = 500 nA maximum for the 741C, where as IB for the precision 741C is 7 nANote: that the input currents IB1 and IB2 areactually thebasecurrentsof thefirst

differentialamplifierstage.

Differential Input Resistance Differential i/p resistance Ri (often referred to as i/p resistance) is the equivalent resistance that can be measured at either the inverting or non-inverting i/p terminal with the other terminal grounded. For the 741C the i/p resistance is relatively high 2 M.

Input capacitance: Input capacitance Ci is the equivalent capacitance that can be measured at either the inverting or non-inverting terminal with the other terminal grounded. A typical value of ci is 1.4 pf for the 741C. This parameter is not listed in all op-amp-data sheets.

Offset voltage adjustment ratio: One of the features of the 741 family op-amps is an offset voltage null capability. The 741 op-amps pins 1 and 5 marked as offset null are forthispurpose.Asshowninfigure1.11a10k potentiometer can be connected between

NOTES



offset null pins 1 and 5, and the wiper of the potentiometer can be connected to the negative supply –VEE. By varying the potentiometer the output offset voltage can be reduced to zero volts. Thus the offset voltage adjustment range is the range through which the i/p offset voltage can be adjusted by varying the 10k potentiometer. For the 741C is the offset voltage adjustment range is 15mV. Very few op-amps have the offset voltage null capability. This means that for most op-amps , we have to design an offset voltage compensating net work in order to reduce the o/p offset voltage to zero.

Common mode rejection ratio: The common-mode rejection ratio (CMRR) is definedinseveralessentiallyequivalentwaysbythevariousmanufactures.GenerallyitcanbedefinedastheratioofthedifferentialvoltagegainAd to the common mode voltage gain Acm. That is

CMRR =


Note: that the input currents IB1 and IB2 are actually the base currents of the first differential

amplifier stage.

Differential input resistance:

Differential i/p resistance Ri (often referred to as i/p resistance) is the equivalent resistance

that can be measured at either the inverting or non-inverting i/p terminal with the other

terminal grounded. For the 741C the i/p resistance is relatively high 2 M.

Input capacitance: Input capacitance Ci is the equivalent capacitance that can be measured

at either the inverting or non-inverting terminal with the other terminal grounded. A typical

value of ci is 1.4 pf for the 741C. This parameter is not listed in all op-amp-data sheets.

Offset voltage adjustment ratio: One of the features of the 741 family op-amps is an offset

voltage null capability. The 741 op-amps pins 1 and 5 marked as offset null are for this

purpose. As shown in figure 1.11 a 10k potentiometer can be connected between offset

null pins 1 and 5, and the wiper of the potentiometer can be connected to the negative supply

-VEE.. By varying the potentiometer the output offset voltage can be reduced to zero volts.

Thus the offset voltage adjustment range is the range through which the i/p offset voltage can

be adjusted by varying the 10k potentiometer. For the 741C is the offset voltage adjustment

range is 15mV. Very few op-amps have the offset voltage null capability. This means that

for most op-amps , we have to design an offset voltage compensating net work in order to

reduce the o/p offset voltage to zero.

Common mode rejection ratio: The common-mode rejection ratio (CMRR) is defined in

several essentially equivalent ways by the various manufactures. Generally it can be defined

as the ratio of the differential voltage gain Ad to the common mode voltage gain Acm. That is

CMRR =cm

d

AA

The differential voltage gain Ad is the same as the large signal voltage gain A, which is

specified on the data sheets; The common mode voltage gain can be determined from the

circuit.

Acm =cm

ocm

vv

.

v0cm = o/p common mode voltage.

vcm = i/p common mode voltage.

The differential voltage gain Ad is the same as the large signal voltage gain A, which

is specifiedonthedatasheets;Thecommonmodevoltagegaincanbedeterminedfromthecircuit.


Note: that the input currents IB1 and IB2 are actually the base currents of the first differential

amplifier stage.

Differential input resistance:

Differential i/p resistance Ri (often referred to as i/p resistance) is the equivalent resistance

that can be measured at either the inverting or non-inverting i/p terminal with the other

terminal grounded. For the 741C the i/p resistance is relatively high 2 M.

Input capacitance: Input capacitance Ci is the equivalent capacitance that can be measured

at either the inverting or non-inverting terminal with the other terminal grounded. A typical

value of ci is 1.4 pf for the 741C. This parameter is not listed in all op-amp-data sheets.

Offset voltage adjustment ratio: One of the features of the 741 family op-amps is an offset

voltage null capability. The 741 op-amps pins 1 and 5 marked as offset null are for this

purpose. As shown in figure 1.11 a 10k potentiometer can be connected between offset

null pins 1 and 5, and the wiper of the potentiometer can be connected to the negative supply

-VEE.. By varying the potentiometer the output offset voltage can be reduced to zero volts.

Thus the offset voltage adjustment range is the range through which the i/p offset voltage can

be adjusted by varying the 10k potentiometer. For the 741C is the offset voltage adjustment

range is 15mV. Very few op-amps have the offset voltage null capability. This means that

for most op-amps , we have to design an offset voltage compensating net work in order to

reduce the o/p offset voltage to zero.

Common mode rejection ratio: The common-mode rejection ratio (CMRR) is defined in

several essentially equivalent ways by the various manufactures. Generally it can be defined

as the ratio of the differential voltage gain Ad to the common mode voltage gain Acm. That is

CMRR =cm

d

AA

The differential voltage gain Ad is the same as the large signal voltage gain A, which is

specified on the data sheets; The common mode voltage gain can be determined from the

circuit.

Acm =cm

ocm

vv

.

v0cm = o/p common mode voltage.

vcm = i/p common mode voltage.

v0cm = o/p common mode voltage.vcm = i/p common mode voltage.Acm = common mode voltage gain.Generally the Acm is very small and Ad = A is very large; therefore the CMRR is very

large,being a large value, CMRR is most often expressed is decibels (dB) for the 741C,

CMRR is 90 dB typically.Slew rate (S.R):Slewrateisdefinedasthemaximumrateofchangeofoutputvoltage

per unit of time and is expressed in volts per microseconds. In equation form


Acm = common mode voltage gain.

Generally the Acm is very small and Ad = A is very large; therefore the CMRR is very large,

being a large value, CMRR is most often expressed is decibels (dB) for the 741C, CMRR is

90 dB typically.

Slew rate (S.R): Slew rate is defined as the maximum rate of change of output voltage per

unit of time and is expressed in volts per microseconds. In equation form

S.R =dt

dvo / maximum V/s

Slew rate indicates, how rapidly the output of an op-amp can change in response to changes

in the input frequency with input amplitude constant. The slew rate changes with change in

voltage gain and is normally specified at unity (+1) gain. The slew rate of an op-amp is

fixed, therefore if the slope requirements of the o/p signal are greater than the slew rate,

distortion occurs. The slew rate is one of the important factors in selecting the op-amp for an

application, particularly at relatively high frequencies. One of the drawback of the 741C is its

low slew rate (0.5 V/s).

Open-loop op-amp configurations:

In the case of amplifiers, the term “open-loop” indicates that no connections, either direct

or via another network exists between the o/p and i/p terminals. That is, the o/p signal is not

fed-back in any form as part of the input signal and the “loop” that would have been formed

with feedback is open.

When connected in open loop configuration the op-amp simply functions as a high gain

amplifier. There are three open loop op-amp configurations:

1. The differential amplifier.

2. The inverting amplifier.

3. The non-inverting amplifier.

The differential amplifier:

Fig 1. 12 shows the open loop differential amplifier in which input signals vis1 and vis2 are

applied to the positive and negative input terminals. Since the op-amp amplifies the

difference between the two input signals, this configuration is called the differential

amplifier.

maximum V/s

Slew rate indicates, how rapidly the output of an op-amp can change in response to changes in the input frequency with input amplitude constant. The slew rate changes with changeinvoltagegainandisnormallyspecifiedatunity(+1)gain.Theslewrateofanop-ampisfixed,thereforeifthesloperequirementsoftheo/psignalaregreaterthantheslewrate, distortion occurs. The slew rate is one of the important factors in selecting the op-amp for an application, particularly at relatively high frequencies. One of the drawback of the 741C is its low slew rate (0.5 V/s).

Open-loop op-amp ConfigurationsInthecaseofamplifiers,theterm“open-loop”indicatesthatnoconnections,eitherdirector via another network exists between the o/p and i/p terminals. That is, the o/p signal is

NOTES

Electronics-1


not fed-back in any form as part of the input signal and the “loop” that would have been formed with feedback is open.

Whenconnectedinopenloopconfigurationtheop-ampsimplyfunctionsasahighgainamplifier.Therearethreeopenloopop-ampconfigurations:

1.Thedifferentialamplifier.

2.Theinvertingamplifier.

3.Thenon-invertingamplifier.

The Differential AmplifierFig1.12showstheopenloopdifferentialamplifierinwhichinputsignalsvis1 and vis2 are appliedtothepositiveandnegativeinputterminals.Sincetheop-ampamplifiesthedifferencebetweenthetwoinputsignals,thisconfigurationiscalledthedifferentialamplifier.

Theop-ampisaversatiledevicebecauseitamplifiesbothacanddcinputsignals.This means that vis1 and vis2 could be either ac or dc voltages. The source resistance Rin1 and Rin2 are normally negligible compared to the input resistance Ri. Therefore, the voltage drops across the resistors can be assumed to be zero, which then implies that v1 = vis1, and v2 = vis2. Substituting these values of v1 and v2 in equation for output voltage, we get v0 = A( vin1 – vin2).Acharya Nagarjuna University 15 Centre for Distance Education

The op-amp is a versatile device because it amplifies both ac and dc input signals. This

means that vis1 and vis2 could be either ac or dc voltages. The source resistance Rin1 and

Rin2 are normally negligible compared to the input resistance Ri. Therefore, the voltage

drops across the resistors can be assumed to be zero, which then implies that v1 = vis1, and

v2 = vis2 . Substituting these values of v1 and v2 in equation for output voltage, we get

v0 = A( vin1-vin2)

Thus, as expected the output voltage is equal to voltage gain A times the difference

between the two input voltages. Also notice that the polarity of the output voltage is

dependent on the polarity of the input difference voltage (vin1-vin2). In open loop

configurations gain A is commonly referred to as open loop gain.

The inverting amplifier:

In the inverting amplifier only one input is applied and that, to the inverting input

terminal.

The non-inverting input terminal is grounded. Since v1 = 0 and v2 = vin.

+VCC

V0 = A(Vin1 – Vin2)

RL 2k-VEE

Vid

+Vin1 ~

–+

~ Vin2_

Rin2Rin1

V2

V1

+A

–

Fig 1.12 Open loop differential amplifier

RL 2kRin -VEE

V0 = - AVin

V2

Vid

+VCC

+A

–

V1

+Vin ~

–

Fig 1.13 Inverting amplifier

V0 = - AVin

Fig. 1.12. Open loop differential amplifier

Thus, as expected the output voltage is equal to voltage gain A times the difference between the two input voltages. Also notice that the polarity of the output voltage is dependent on the polarity of the input difference voltage (vin1 – vin2).InopenloopconfigurationsgainA is commonly referred to as open loop gain.

The Inverting AmplifierIntheinvertingamplifieronlyoneinputisappliedandthat,totheinvertinginputterminal.

The non-inverting input terminal is grounded. Since v1 = 0 and v2 = vin.V0 = – AVin

NOTES




The op-amp is a versatile device because it amplifies both ac and dc input signals. This

means that vis1 and vis2 could be either ac or dc voltages. The source resistance Rin1 and

Rin2 are normally negligible compared to the input resistance Ri. Therefore, the voltage

drops across the resistors can be assumed to be zero, which then implies that v1 = vis1, and

v2 = vis2 . Substituting these values of v1 and v2 in equation for output voltage, we get

v0 = A( vin1-vin2)

Thus, as expected the output voltage is equal to voltage gain A times the difference

between the two input voltages. Also notice that the polarity of the output voltage is

dependent on the polarity of the input difference voltage (vin1-vin2). In open loop

configurations gain A is commonly referred to as open loop gain.

The inverting amplifier:

In the inverting amplifier only one input is applied and that, to the inverting input

terminal.

The non-inverting input terminal is grounded. Since v1 = 0 and v2 = vin.

+VCC

V0 = A(Vin1 – Vin2)

RL 2k-VEE

Vid

+Vin1 ~

–+

~ Vin2_

Rin2Rin1

V2

V1

+A

–

Fig 1.12 Open loop differential amplifier

RL 2kRin -VEE

V0 = - AVin

V2

Vid

+VCC

+A

–

V1

+Vin ~

–

Fig 1.13 Inverting amplifier

V0 = - AVin

Fig 1.13. Inverting amplifier

The negative sign indicates that the output voltage is out of phase with respect to input by 1800orisofoppositepolarity.Thusintheinvertingamplifiertheinputsignalisamplifiedby gain A and is also inverted at the output.

The Non-inverting AmplifierFig1.14showstheopenloopconfigurationsofnoninvertingamplifierinthisconfigurationthe input is applied to the non inverting input terminal and the inverting input terminal is grounded.

In the circuit shown below v1 = vin and v2 = 0v. Therefore according to equation v0 = Avin. This means that the output voltage is larger than the input voltage. By gain A and is in phase with input signal.


The negative sign indicates that the output voltage is out of phase with respect to input by

1800

or is of opposite polarity. Thus in the inverting amplifier the input signal is amplified by

gain A and is also inverted at the output.

The non-inverting amplifier:

Fig 1.14 shows the open loop configurations of non inverting amplifier in this

configuration the input is applied to the non inverting input terminal and the inverting

input terminal is grounded.

In the circuit shown below v1=vin and v2=0v. Therefore according to equation v0 = Avin.

This means that the output voltage is larger than the input voltage. By gain A and is in

phase with input signal.

In all the three open loop configurations any input signal that is only slightly greater than

zero drives the output to saturation level. This results from the very high gain A of the op-amp.

Thus when operated in open loop, the output of the op-amp is either at negative saturation or

positive saturation or switches between positive and negative saturation levels. For this reason

the open loop configurations are not used in linear applications.

1.4 Summary of the Lesson:

A differential amplifier consists of two symmetrical common emitter stages and is capable of

amplifying the difference between two input signals. Differential amplifier is capable of

amplifying ac as well as dc input signals because it employs direct coupling. For proper

operation of the differential amplifier, a transistor array and matched components must be used.

The differential amplifier can be biased by using emitter bias (a combination of RE and VEE), a

V0 = AVin

+VCC

-VEE

RL 2kRin

Vid

V2

+A

–

+Vin ~

–

V1

Fig 1.14 Non-inverting amplifierFig. 1.14. Non-inverting amplifier

Inallthethreeopenloopconfigurationsanyinputsignalthatisonlyslightlygreaterthan zero drives the output to saturation level. This results from the very high gain A of the op-amp. Thus when operated in open loop, the output of the op-amp is either at negative saturation or positive saturation or switches between positive and negative saturation levels. Forthisreasontheopenloopconfigurationsarenotusedinlinearapplications.

NOTES

Electronics-1


1.6 EFFECT OF NEGATIVE FEED BACK ON CLOSED LOOPOP-AMPAmplifierperformancecanbealteredconsiderablybysamplingtheoutputsignalandsendinga part of it to a mixer circuit where the feedback signal mixes with the input. Depending upon the phase relation ship between the input and feedback signals the resultant input can be less than the source voltage or more than that. If the effective input is less than source voltage it is called negative feed back. In this lesson you will learn the effect of negative feed back on various op amp parameters.

Block Diagram representation of feeDBack configurations

Anop-ampthatusesthefeedbackiscalledafeedbackamplifier.Afeedbackamplifierissometimesreferredtoasaclosedloopamplifierbecausethefeedbackformsaclosedloopbetweentheinputandoutput.Afeedbackamplifieressentiallyconsistsoftwoparts:anop-amp and a feed back circuit. The feedback circuit can take any form what so ever, depending ontheintendedapplicationoftheamplifier.Itmeans,thefeedbackcircuitmaybemadeupof either passive components, active components, or combinations of both. This chapter, in order to develop the basic feedback concepts presents only purely resistive feedback circuits.

Aclosedloopamplifiercanberepresentedbyusingtwoblocks,oneforop-ampandanother for a feedback circuit. There are four ways to connect these two blocks. These connectionsareclassifiedaccordingtowhetherthevoltageorcurrentisfedbacktotheinputin series or parallel as follows:

1. Voltage- series feedback.

2. Voltage- shunt feedback

3. Current - series feedback

4. Current – shunt feedback

Thefourtypesofconfigurationsareillustratedinfig(1.1).Infig(1.15)(a)and(b)thevoltage across load resistor RL is the input voltage to the feed back circuit. The feedback quantity (either voltage or current) is the output of the feedback circuit and is proportional to the output voltage. On the other hand in the current series and current shunt feedback circuits. [1.15 (c) and (d)] the load current iLflowsintothefeedbackcircuit.Theoutputofthe feedback circuit is the feedback quantity which is proportional to the load current iL.

Acharya Nagarjuna University 3 Center for Distance Education

2.2.1 Block diagram representation of feedback configurations:

An op-amp that uses the feedback is called a feedback amplifier. A feedback amplifier is

sometimes referred to as a closed loop amplifier because the feedback forms a closed loop between

the input and output. A feedback amplifier essentially consists of two parts: an op-amp and a feed

back circuit. The feedback circuit can take any form what so ever, depending on the intended

application of the amplifier. It means, the feedback circuit may be made up of either passive

components, active components, or combinations of both. This chapter, in order to develop the basic

feedback concepts presents only purely resistive feedback circuits.

A closed loop amplifier can be represented by using two blocks, one for op-amp and another for

a feedback circuit. There are four ways to connect these two blocks. These connections are

classified according to whether the voltage or current is fed back to the input in series or parallel as

follows:

1. Voltage- series feedback.

2. Voltage- shunt feedback

3. Current - series feedback

4. Current – shunt feedback

The four types of configurations are illustrated in fig (2.1). In fig (2.1)(a) and (b) the voltage

across load resistor RL is the input voltage to the feed back circuit. The feedback quantity (either

voltage or current) is the output of the feedback circuit and is proportional to the output voltage. On

the other hand in the current series and current shunt feedback circuits. [2.1 (c) and (d)] the load

current iL flows into the feedback circuit. The output of the feedback circuit is the feedback quantity

which is proportional to the load current iL.

Fig (a): Voltage series feed back Fig (b): Voltage shunt feedback

Op-amp

Feed backcircuit

+vin ~

– v0

v0

IF

Iin IB

RL

Op-amp

Feed backcircuit

+vin ~

–

v0

v0vF

RL

(a) Voltage series feed back (b) Voltage shunt feedback

NOTES



M. Sc. Physics 4 OpampII

Note that in all four of these configurations, the signal direction through the op-amp is from

the input to output. On the other hand, in the ideal case, the signal direction through the feedback

circuit is exactly opposite, from output to input.

The voltage-series and voltage - shunt feedback configurations are important because they are

most commonly used. In the present chapter the analysis of voltage series feedback is discussed,

through computing voltage gain, input resistance, output resistance and bandwidth.

2.2.2 Voltage series feedback amplifier:

The schematic diagram of the voltage series feed back amplifier is shown in fig (2.2). The op-

amp is represented by its schematic symbol including the large signal voltage gain A, and the

feedback circuit is composed of two resistances R1 and RF.

Fig (2.2): voltage series feed back amplifier.Feed back circuit

+ VCCv1

Rm 0 VEE

Vid

RL+vin ~

–

+VF–

RFR1

v2

+

v0

–

+A

–

Fig (c): current series feed back Fig (d): Current shunt feedback

Fig 2.1. Block diagram represent to that of configurations.

Feedback

Op -amp

+vin ~

–

RL

IL Op-amp

Feedback

+vin ~

– RL

ILIF

Iin IB

(c) current series feed back (d) Current shunt feedback

Fig. 1.15. Block diagram represent to that of configurations

Notethatinallfouroftheseconfigurations,thesignaldirectionthroughtheop-ampis from the input to output. On the other hand, in the ideal case, the signal direction through the feedback circuit is exactly opposite, from output to input.

Thevoltage-seriesandvoltage–shuntfeedbackconfigurationsareimportantbecausethey are most commonly used. In the present chapter the analysis of voltage series feedback is discussed, through computing voltage gain, input resistance, output resistance and bandwidth.

Voltage series feeDBack amplifier

Theschematicdiagramofthevoltageseriesfeedbackamplifierisshowninfig(1.16).Theopamp is represented by its schematic symbol including the large signal voltage gain A, and the feedback circuit is composed of two resistances R1 and RF.


Note that in all four of these configurations, the signal direction through the op-amp is from

the input to output. On the other hand, in the ideal case, the signal direction through the feedback

circuit is exactly opposite, from output to input.

The voltage-series and voltage - shunt feedback configurations are important because they are

most commonly used. In the present chapter the analysis of voltage series feedback is discussed,

through computing voltage gain, input resistance, output resistance and bandwidth.

2.2.2 Voltage series feedback amplifier:

The schematic diagram of the voltage series feed back amplifier is shown in fig (2.2). The op-

amp is represented by its schematic symbol including the large signal voltage gain A, and the

feedback circuit is composed of two resistances R1 and RF.

Fig (2.2): voltage series feed back amplifier.Feed back circuit

+ VCCv1

Rm 0 VEE

Vid

RL+vin ~

–

+VF–

RFR1

v2

+

v0

–

+A

–

Fig (c): current series feed back Fig (d): Current shunt feedback

Fig 2.1. Block diagram represent to that of configurations.

Feedback

Op -amp

+vin ~

–

RL

IL Op-amp

Feedback

+vin ~

– RL

ILIF

Iin IB

Fig (1.16). Voltage series feed back amplifier.

Thecircuitshowninfig(1.16)iscommonlyknownasanon-invertingamplifierwithfeedback(orclosedloopnon-invertingamplifier)becauseitusesfeedback,andtheinputsignal is applied to the non-inverting input terminal of the op-amp.

Beforeproceeding,itisnecessarytodefinesomeimportanttermsforthevoltageseriesfeedbackamplifieroffig(1.16).Speciallythevoltagegainwithandwithoutfeedback,andthegainofthefeedbackcircuitaredefinedasfollows.

NOTES

Electronics-1


Open loop voltage gain (or gain without feedback)


The circuit shown in fig (2.2) is commonly known as a non- inverting amplifier with feedback (or

closed loop non-inverting amplifier) because it uses feedback, and the input signal is applied to the

non-inverting input terminal of the op-amp.

Before proceeding, it is necessary to define some important terms for the voltage series feed back

amplifier of fig (2.2). Specially the voltage gain with and without feedback, and the gain of the

feedback circuit are defined as follows.

Open loop voltage gain (or gain without feedback) A =id

o

vv

.

Closed –loop voltage gain (or gain with feedback) Af =in

o

vv

Gain of the feedback current B=o

f

vv

2.2.3 Negative feedback:

Returning to the circuit of fig (2) Kirchoff’s voltage equation for the input loop is

vid = vin- vf --------(2.1)

Where vin = input voltage

Vf = feedback voltage

Vid =difference voltage

However, recall that an op-amp always amplifies the difference input voltage vid. From eqn (2.1)the difference voltage is equal to input voltage vin minus the feedback voltage vf, in other words thefeedback voltage opposes the input voltage (or is out of phase by 1800 with respect to the inputvoltage). Hence the feedback is said to be negative. Returning to the analysis of voltage seriesfeedback amplifier we should note that, it is performed by computing closed loop voltage gain, inputresistance, output resistance, and the bandwidth.2.2.4 Closed loop voltage gain:

As defined previously, the closed loop voltage gain

Af =in

o

vv

,

However by equation v0 = A (v1-v2),

Referring to fig (2.2) we see that

v1= vin

Closed –loop voltage gain (or gain with feedback)









o

vv

.


o

vv


f

vv



vid = vin- vf --------(2.1)






Af =in

o

vv

,



v1= vin

Gain of the feedback current









o

vv

.


o

vv


f

vv



vid = vin- vf --------(2.1)






Af =in

o

vv

,



v1= vin

negatiVe feeDBack

Returningtothecircuitoffig(2)Kirchoff’svoltageequationfortheinputloopis

vid = vin– vf ...(1.25)



Vid = difference voltage

However,recallthatanop-ampalwaysamplifiesthedifferenceinputvoltagevid.Fromeqn (2.1) the difference voltage is equal to input voltage vin minus the feedback voltage vf, in other words the feedback voltage opposes the input voltage (or is out of phase by 1800 with respect to the input voltage). Hence the feedback is said to be negative. Returning to theanalysisofvoltageseriesfeedbackamplifierweshouldnotethat, it isperformedbycomputing closed loop voltage gain, input resistance, output resistance, and the bandwidth.

closeD loop Voltage gain

Asdefinedpreviously,theclosedloopvoltagegain









o

vv

.


o

vv


f

vv



vid = vin- vf --------(2.1)






Af =in

o

vv

,



v1= vin

However by equation v0 = A (v1 – v2),

Referringtofig(1.16)weseethatM. Sc. Physics 6 OpampII

v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv

Rearranging the above equation, we get

vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)

Generally, A is very large (typically 105), therefore,

AR1 >> R1+RF and R1+RF+AR1 AR1

Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)

Equation (2.3) is important because, it shows that the gain of a voltage series feed back

amplifier is determined by the ratio of the two resistors, R1 and RF. For instance , if a gain of

11 is desired, we can then choose R1 = 1k and RF = 10k or R1 = 100 and RF = 1k.

Another interesting result can be obtained from equation (2.3). As defined previously the

gain or the feed back circuit (B) is the ratio of vf to v0. Referring to fig (2.2), the gain is

B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)

Comparing equations (2.3) and (2.4) we can conclude that

AF =B1 (ideal) ---------- (2.5)

This means that gain of the feed back circuit is the reciprocal of the closed loop voltage gain.

In other words for given R1 and RF the values of AF and B are fixed. Besides that equation

(2.5) is an alternative to equation (2.3)

Finally the closed loop voltage gain AF can be expressed in terms or open loop gain A and

feedback circuit gain B by rearranging equation (2.2) in the following manner we get



v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)







v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)






...(1.26)

NOTES




v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)






Therefore vo = A


v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)








v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)






Thus


v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)






(exact) ...(1.27)



Thus


v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)






(ideal) ...(1.28)

Equation (1.28) is important because, it shows that the gain of a voltage series feed back amplifierisdeterminedbytheratioofthetworesistors,R1 and RF. For instance , if a gain of 11 is desired, we can then choose R1 = 1k and RF = 10k or R1 = 100 and RF = 1k.

Anotherinterestingresultcanbeobtainedfromequation(1.28).Asdefinedpreviouslythe gain or the feed back circuit (B) is the ratio of vf to v0.Referringtofig(1.16),thegainis


v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)







v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)






...(1.29)Comparing equations (1.29) and (1.30) we can conclude that


v2 = vf =F1

01

RRvR

since Ri >> R1

Therefore v0 = A

F1

01in RR

vRv


vo =1F1

inF1

ARRRv)R(RA

Thus AF =in

o

vv

=1F1

F1

ARRR)R(RA

(exact) ---------- (2.2)



Thus AF =in

o

vv

=1

F

RR

1 (ideal) --------- (2.3)






B =o

f

vv

B = 0F1

01

vRRvR

=

F1

1

RRR

---------- (2.4)


AF =B1 (ideal) ---------- (2.5)






(ideal) ...(1.30)

This means that gain of the feed back circuit is the reciprocal of the closed loop voltage gain. In other words for given R1 and RF the values of AFandBarefixed.Besidesthatequation (1.31) is an alternative to equation (1.28)

Finally the closed loop voltage gain AF can be expressed in terms or open loop gain A and feedback circuit gain B by rearranging equation (1.27) in the following manner we getAcharya Nagarjuna University 7 Center for Distance Education

AF =

F1

1

F1

F1

F1

F1

RRAR

RRRR

RRRR

A---------- (2.6)

Using equation (2.4) yields

AF =AB1

A

---------- (2.7)

Where AF = closed loop gain

A = open loop gain

B = gain of the feed back circuit

AB = “loop gain”

2.2.5 Input resistance with feedback:

A voltage series feed back amplifier with the op-amp equivalent circuit is shown in fig (2.3).

In this circuit Ri is the input resistance (open-loop) of the op-amp, and RiF is the input

resistance of the feed back amplifier. The input resistance with feedback is defined as

Rif =in

in

iv

=iid

in

R/vv

---------- (2.8)

However,

Vid =Av0 and v0 =

AB1A

vin ---------- (2.9)

Rm 0

Fig 2.3 Derivation of input resistance with feedback.

+Ri

Avid~–

+VCC

–VEE

v1

vid

v2

Iin

R1

RF RL

+

v0

–

+vin ~

– +vF–

RiF

R0

...(1.31)

NOTES

Electronics-1




AF =

F1

1

F1

F1

F1

F1

RRAR

RRRR

RRRR

A---------- (2.6)


AF =AB1

A

---------- (2.7)


A = open loop gain







Rif =in

in

iv

=iid

in

R/vv

---------- (2.8)

However,

Vid =Av0 and v0 =

AB1A

vin ---------- (2.9)

Rm 0


+Ri

Avid~–

+VCC

–VEE

v1

vid

v2

Iin

R1

RF RL

+

v0

–

+vin ~

– +vF–

RiF

R0

...(1.32)


A = open loop gain



input resistance with feeDBack

Avoltage series feedbackamplifierwith theop-ampequivalent circuit is shown infig(1.17). In this circuit Ri is the input resistance (open-loop) of the op-amp, and RiF is the inputresistanceofthefeedbackamplifier.Theinputresistancewithfeedbackisdefinedas


AF =

F1

1

F1

F1

F1

F1

RRAR

RRRR

RRRR

A---------- (2.6)


AF =AB1

A

---------- (2.7)


A = open loop gain







Rif =in

in

iv

=iid

in

R/vv

---------- (2.8)

However,

Vid =Av0 and v0 =

AB1A

vin ---------- (2.9)

Rm 0


+Ri

Avid~–

+VCC

–VEE

v1

vid

v2

Iin

R1

RF RL

+

v0

–

+vin ~

– +vF–

RiF

R0

...(1.33)


AF =

F1

1

F1

F1

F1

F1

RRAR

RRRR

RRRR

A---------- (2.6)


AF =AB1

A

---------- (2.7)


A = open loop gain







Rif =in

in

iv

=iid

in

R/vv

---------- (2.8)

However,

Vid =Av0 and v0 =

AB1A

vin ---------- (2.9)

Rm 0


+Ri

Avid~–

+VCC

–VEE

v1

vid

v2

Iin

R1

RF RL

+

v0

–

+vin ~

– +vF–

RiF

R0

Fig. 1.17. Derivation of input resistance with feedback

However,


AF =

F1

1

F1

F1

F1

F1

RRAR

RRRR

RRRR

A---------- (2.6)


AF =AB1

A

---------- (2.7)


A = open loop gain







Rif =in

in

iv

=iid

in

R/vv

---------- (2.8)

However,

Vid =Av0 and v0 =

AB1A

vin ---------- (2.9)

Rm 0


+Ri

Avid~–

+VCC

–VEE

v1

vid

v2

Iin

R1

RF RL

+

v0

–

+vin ~

– +vF–

RiF

R0

...(1.34)M. Sc. Physics 8 OpampII

Rif = Ri .A/v

v

0

in ---------- (2.10)

Rif = ARi

AB1Avv

in

in

= Ri (1+AB) ---------- (2.11)

It means, the input resistance of the op-amp with feedback is (1+AB) times that without

feedback.

2.2.6 Output resistance with feedback:

Output resistance is the resistance determined looking back into the feedback amplifier from

the output terminal, as shown in fig 2.4. This resistance can be obtained by using Thevenin’s

theorem for dependent sources. Specifically, to find output resistance with feed back RoF,

reduce the independent source vin to zero, apply an external voltage v0 and then calculate the

resulting current io in short , the RoF is defined as follows:

RoF =o

o

iv

.

Writing Kirchoff currents equation at the output node N, we get

io =ia+ib ---------------(2.12)

Since RF+R1 || Ri >> R0, ia >> ib therefore

io ia ------------(13)

The current io can be found by writing Kirchoff’s voltage equation for the output loop

v0 - R0i0 - Avid = 0 ---------- (2.14)

i0 =R

Av-v

0

id0

vid = v1-v2 = -vf =F1

01

RRvR

= -Bvo

therefore i0 =0

00 A.BvvR

substituting the value of io in equation, we get

RoF =R/)ABv(v

v

000

0

=

AB1R 0

---------- (15)

...(1.35)


Rif = Ri .A/v

v

0

in ---------- (2.10)

Rif = ARi

AB1Avv

in

in

= Ri (1+AB) ---------- (2.11)


feedback.







RoF =o

o

iv

.


io =ia+ib ---------------(2.12)


io ia ------------(13)


v0 - R0i0 - Avid = 0 ---------- (2.14)

i0 =R

Av-v

0

id0

vid = v1-v2 = -vf =F1

01

RRvR

= -Bvo

therefore i0 =0

00 A.BvvR


RoF =R/)ABv(v

v

000

0

=

AB1R 0

---------- (15)

...(1.36)

It means, the input resistance of the op-amp with feedback is (1+AB) times that withoutfeedback.

NOTES



output resistance with feeDBack

Outputresistanceistheresistancedeterminedlookingbackintothefeedbackamplifierfromtheoutputterminal,asshowninfig1.18.ThisresistancecanbeobtainedbyusingThevenin’stheoremfordependentsources.Specifically,tofindoutputresistancewithfeedbackRoF, reduce the independent source vin to zero, apply an external voltage v0 and then calculate the resulting current io in short , the RoFisdefinedasfollows:


Rif = Ri .A/v

v

0

in ---------- (2.10)

Rif = ARi

AB1Avv

in

in

= Ri (1+AB) ---------- (2.11)


feedback.







RoF =o

o

iv

.


io =ia+ib ---------------(2.12)


io ia ------------(13)


v0 - R0i0 - Avid = 0 ---------- (2.14)

i0 =R

Av-v

0

id0

vid = v1-v2 = -vf =F1

01

RRvR

= -Bvo

therefore i0 =0

00 A.BvvR


RoF =R/)ABv(v

v

000

0

=

AB1R 0

---------- (15)


io = ia+ib ...(1.37)


io ia ...(1.38)


v0 – R0i0 – Avid = 0 ...(1.39)


Rif = Ri .A/v

v

0

in ---------- (2.10)

Rif = ARi

AB1Avv

in

in

= Ri (1+AB) ---------- (2.11)


feedback.







RoF =o

o

iv

.


io =ia+ib ---------------(2.12)


io ia ------------(13)


v0 - R0i0 - Avid = 0 ---------- (2.14)

i0 =R

Av-v

0

id0

vid = v1-v2 = -vf =F1

01

RRvR

= -Bvo

therefore i0 =0

00 A.BvvR


RoF =R/)ABv(v

v

000

0

=

AB1R 0

---------- (15)

–


Rif = Ri .A/v

v

0

in ---------- (2.10)

Rif = ARi

AB1Avv

in

in

= Ri (1+AB) ---------- (2.11)


feedback.







RoF =o

o

iv

.


io =ia+ib ---------------(2.12)


io ia ------------(13)


v0 - R0i0 - Avid = 0 ---------- (2.14)

i0 =R

Av-v

0

id0

vid = v1-v2 = -vf =F1

01

RRvR

= -Bvo

therefore i0 =0

00 A.BvvR


RoF =R/)ABv(v

v

000

0

=

AB1R 0

---------- (15)

––

therefore


Rif = Ri .A/v

v

0

in ---------- (2.10)

Rif = ARi

AB1Avv

in

in

= Ri (1+AB) ---------- (2.11)


feedback.







RoF =o

o

iv

.


io =ia+ib ---------------(2.12)


io ia ------------(13)


v0 - R0i0 - Avid = 0 ---------- (2.14)

i0 =R

Av-v

0

id0

vid = v1-v2 = -vf =F1

01

RRvR

= -Bvo

therefore i0 =0

00 A.BvvR


RoF =R/)ABv(v

v

000

0

=

AB1R 0

---------- (15)



Rif = Ri .A/v

v

0

in ---------- (2.10)

Rif = ARi

AB1Avv

in

in

= Ri (1+AB) ---------- (2.11)


feedback.







RoF =o

o

iv

.


io =ia+ib ---------------(2.12)


io ia ------------(13)


v0 - R0i0 - Avid = 0 ---------- (2.14)

i0 =R

Av-v

0

id0

vid = v1-v2 = -vf =F1

01

RRvR

= -Bvo

therefore i0 =0

00 A.BvvR


RoF =R/)ABv(v

v

000

0

=

AB1R 0

---------- (15) ...(1.40)


This result shows that the output resistance of the voltage series feedback amplifier is

1/(1+AB) times the output resistance Ro of the op-amp. That is, the output resistance of the

op-amp with feedback is much smaller than the output resistance without feedback.

2.2.7 Bandwidth with feed back:

The bandwidth of an amplifier is defined as the band (range) of frequencies for which the

gain remains constant. Manufacturers generally specify either the gain bandwidth product or

supply open loop gain versus frequency curve for the op-amp. For the 741 op-amp the latter

is typical.

The open loop gain versus frequency curve of the 741C op-amp is shown in Fig 2.5. From

this curve for a gain of 200,000 the bandwidth is approximately 5Hz. In other extreme, the

bandwidth is approximately 1MHz when the gain is unity. The frequency at which gain

equals 1 is known as unity gain-band width. It is the maximum frequency the op-amps can

be used for. Further more the gain bandwidth product obtained from the open loop gain

versus frequency curve of fig 2.5 is equal to the unity gain bandwidth of an op-amp.

However this holds true only for those op-amps like 741,which have just one break frequency

below unity gain bandwidth.

Since the gain bandwidth product is constant, obviously the higher the gain the smaller the

bandwidth and vice versa. As we have seen if negative feedback is used gain A decreases to

A/1+AB. Therefore to obtain the closed loop bandwidth, the open loop bandwidth must be

Fig 2.4 Derivation of output resistance with feedback

+vin ~

–

+

Ri ~–

+Avid

–

v1+

vid–

v2

+VCC

–VEE

+

vf

–

RF

+~ v0

–

i0

ib

ia

R1

RoF

NR0

Fig. 1.18. Derivation of output resistance with feedback

NOTES

Electronics-1


Thisresultshowsthattheoutputresistanceofthevoltageseriesfeedbackamplifieris1/(1+AB) times the output resistance Ro of the op-amp. That is, the output resistance of the op-amp with feedback is much smaller than the output resistance without feedback.

BanDwiDth with feeD Back

Thebandwidthofanamplifierisdefinedastheband(range)offrequenciesforwhichthegain remains constant. Manufacturers generally specify either the gain bandwidth product or supply open loop gain versus frequency curve for the op-amp. For the 741 op-amp the latter is typical.

The open loop gain versus frequency curve of the 741C op-amp is shown in Fig 2.5. From this curve for a gain of 200,000 the bandwidth is approximately 5Hz. In other extreme, the bandwidth is approximately 1MHz when the gain is unity. The frequency at which gain equals 1 is known as unity gain-band width. It is the maximum frequency the op-amps can be used for. Further more the gain bandwidth product obtained from the open loop gain versus frequencycurveoffig2.5isequaltotheunitygainbandwidthofanop-amp.Howeverthisholds true only for those op-amps like 741,which have just one break frequency below unity gain bandwidth.

Since the gain bandwidth product is constant, obviously the higher the gain the smaller the bandwidth and vice versa. As we have seen if negative feedback is used gain A decreases to A/1+AB. Therefore to obtain the closed loop bandwidth, the open loop bandwidth must be multiplied by the same factor, by which the gain is divided, that is, by the factor (1 + AB). In short.


multiplied by the same factor, by which the gain is divided, that is, by the factor (1+AB). In

short.

Band width with feed back = (band width without feedback) (1+AB)

fF = f0 (1+AB) ---------- (16)

or alternatively,

fF = unity gain band width/closed loop gain = U.G.B.W /AF ------------(17)

The closed loop bandwidth can also be determined from the open loop gain versus

frequency plot. To do this we locate the closed loop voltage gain value on the gain axis and

draw a parallel line through this value to the frequency axis. Then we project the point of

inter section of the line with the curve on the frequency axis and read the value of the closed

loop bandwidth. Using this procedure in figure 2.5. The bandwidth is approximately 100

KHz. for a closed loop gain of 10.

2.2.8 Voltage follower:

The lowest gain that can be obtained from a non-inverting amplifier with feedback is 1.

When the non-inverting amplifier is configured for unity gain, it is called a voltage follower

Fig 2.5 Open loop gain versus frequency curve of 741c.

1 10 100 1K 10K 100K 1M 10M

frequency (Hz).

Vs = 15vTA = 250C

Voltagegain

106

105

104

103

102

10

1

10-1

Fig. 1.19. Open loop gain versus frequency curve of 741c

NOTES



Band width with feed back = (band width without feedback) (1 + AB)

fF = f0 (1 + AB) ...(1.41)

or alternatively,

fF = unity gain band width/closed loop gain = U.G.B.W /AF ...(1.42)

The closed loop bandwidth can also be determined from the open loop gain versus frequency plot. To do this we locate the closed loop voltage gain value on the gain axis and draw a parallel line through this value to the frequency axis. Then we project the point of inter section of the line with the curve on the frequency axis and read the value of the closed loopbandwidth.Usingthisprocedureinfigure2.5.Thebandwidthisapproximately100

KHz. for a closed loop gain of 10.

Voltage follower

Thelowestgainthatcanbeobtainedfromanon-invertingamplifierwithfeedbackis1.

Whenthenon-invertingamplifierisconfiguredforunitygain,itiscalledavoltagefollower because the output voltage is equal to and in phase with the input. In other words, in the voltage follower, the output follows the input.

Although it is similar to the discrete emitter follower, the voltage follower is preferred because it has much higher input resistance, and the output amplitude is exactly equal to the input.


because the output voltage is equal to and in phase with the input. In other words, in the

voltage follower, the output follows the input.

Although it is similar to the discrete emitter follower, the voltage follower is preferred

because it has much higher input resistance, and the output amplitude is exactly equal to the

input.

To obtain the voltage follower from the non-inverting amplifier of figure (2.2), simply

open R1 and short RF. The resulting circuit is shown in figure 2.6. In this figure all the

output voltage is feedback into the inverting terminal of the op-amp; consequently the gain of

the feedback circuit is 1. (B = AF = 1).

Since the voltage follower is a special case of the non-inverting amplifier all the formulae

developed for the latter are indeed applicable to the former except that the gain of the

feedback circuit is 1 (B=1) the applicable formulae are:-

AF = 1

RiF = A Ri

RoF = Ro/A

f F= Afo

vooT =Avsat

Since (1+A) A

The voltage follower is also called a non-inverting buffer because when placed between two

networks, it removes the loading on the first network.

+vin ~–

+A

–

Figure 2.6. Voltage follower.

+VCC

–VEE

v0 = vin

RL

Fig. 1.20. Voltage follower

Toobtainthevoltagefollowerfromthenon-invertingamplifieroffigure(1.16),simplyopen R1 and short RF.Theresultingcircuitisshowninfigure2.6.Inthisfigurealltheoutputvoltage is feedback into the inverting terminal of the op-amp; consequently the gain of the feedback circuit is 1. (B = AF = 1).

Since the voltage follower is a special case of the non-inverting amplifier all theformulae developed for the latter are indeed applicable to the former except that the gain of the feedback circuit is 1 (B=1) the applicable formulae are:

NOTES

Electronics-1


AF = 1

RiF = A Ri

RoF = Ro/A

f F= Afo

vooT =


because the output voltage is equal to and in phase with the input. In other words, in the

voltage follower, the output follows the input.

Although it is similar to the discrete emitter follower, the voltage follower is preferred

because it has much higher input resistance, and the output amplitude is exactly equal to the

input.

To obtain the voltage follower from the non-inverting amplifier of figure (2.2), simply

open R1 and short RF. The resulting circuit is shown in figure 2.6. In this figure all the

output voltage is feedback into the inverting terminal of the op-amp; consequently the gain of

the feedback circuit is 1. (B = AF = 1).

Since the voltage follower is a special case of the non-inverting amplifier all the formulae

developed for the latter are indeed applicable to the former except that the gain of the

feedback circuit is 1 (B=1) the applicable formulae are:-

AF = 1

RiF = A Ri

RoF = Ro/A

f F= Afo

vooT =Avsat

Since (1+A) A

The voltage follower is also called a non-inverting buffer because when placed between two

networks, it removes the loading on the first network.

+vin ~–

+A

–

Figure 2.6. Voltage follower.

+VCC

–VEE

v0 = vin

RL

Since (1+A) AThe voltage follower is also called a non-inverting buffer because when placed between

twonetworks,itremovestheloadingonthefirstnetwork.

1.7 APPLICATIONS OF OP-AMPOp-amps have many applications. Some are described below

inVerting amplifier ThebasicinvertingamplifierwithaninputresistorR1 and feed back resistor RF is shown infig2.7.


2.3 Applications of op-amp:

Op-amps have many applications. Some are described below

2.3.1 Inverting amplifier: The basic inverting amplifier with an input resistor R1 and feed back

resistor RF is shown in fig 2.7.

The non-inverting input terminal is grounded and the input voltage is v1 and the output

voltage is v0. Since the gain ‘A’ of the operational amplifier is very large, the voltage v at the

inverting input terminal is very small. In fact, the voltage v is very close to the ground potential.

That is, although the point G is not actually connected to the ground, it is held virtually at ground

potential irrespective of magnitudes or the potentials v1 and v0, the current i. is flowing through

resistor R1 is given by i =1

1

Rv-v

. Assuming that the operational amplifier is ideal, having an infinite

input impedance the current i will flow through RF and not into the op-amp. Applying the Kirchoff’s

current law at the point G. We can have

1

1

Rv-v

=F

0

Rv-v

---------- (2.18)

Since the point ‘G’ is virtually ground i.e.v 0

From eqn.2.18. we get1

1

Rv

=F

0

Rv-

Fig 2.7 An inverting amplifier.

+v1 ~

–

RF

i

–A

+

+VCC

–VEE

R1

Gv

Outputv0

Fig. 1.21. An inverting amplifier

The non-inverting input terminal is grounded and the input voltage is v1 and the output voltage is v0.Sincethegain‘A’oftheoperationalamplifierisverylarge,thevoltagevatthe inverting input terminal is very small. In fact, the voltage v is very close to the ground potential. That is, although the point G is not actually connected to the ground, it is held virtually at ground potential irrespective of magnitudes or the potentials v1 and v0, the current

i. isflowing through resistorR1 is given by i =












1

Rv-v




1

1

Rv-v

=F

0

Rv-v

---------- (2.18)



1

Rv

=F

0

Rv-


+v1 ~

–

RF

i

–A

+

+VCC

–VEE

R1

Gv

Outputv0

– Assuming that the operational

amplifieris ideal,havinganinfiniteinputimpedance thecurrentiwillflowthroughRF and not into the op-amp. Applying the Kirchoff’s current law at the point G. We can have












1

Rv-v




1

1

Rv-v

=F

0

Rv-v

---------- (2.18)



1

Rv

=F

0

Rv-


+v1 ~

–

RF

i

–A

+

+VCC

–VEE

R1

Gv

Outputv0

––

(1.43)

NOTES




From eqn.2.18. we get












1

Rv-v




1

1

Rv-v

=F

0

Rv-v

---------- (2.18)



1

Rv

=F

0

Rv-


+v1 ~

–

RF

i

–A

+

+VCC

–VEE

R1

Gv

Outputv0

–

Rearranging equation 2.18.

We have



We have1

0

vv

= -1

F

RR

---------- (2.19)

The ratio of the output voltage to the input voltage is the gain of the amplifier. Hence the voltage

gain is the ratio of feedback resistor RF to the input resistance R1. The negative sign indicates that

the output voltage is inverted w.r.t. the input voltage. The input resistance (Rin) of the whole

amplifier is given by the ratio of voltage v1and the input current1

1

Rv-v

that is

Rin =

1

1

1

Rv-v

v R1 ---------- (2.20)

since v 0, note that Rin refers to the whole of the amplifier not to the op-amp which has an infinite

input resistance

2.3.2 Scale changer:

If use ratio1

F

RR

is denoted by k, a real constant, we get v0 = -kv1. That is, input voltage has been

multiplied by the factor ‘- k’ to give the output voltage scale. The circuit shown in fig 2.7 acts as

scale changer. For such applications precision resistors are used to get accurate values for the scale

factor ‘k’

2.3.3 Phase shifter:

If the resistance RF and R1 in the circuit are replaced respectively by impedances zF an z1 which

are equal in magnitude but differ in phase angle, we can write

1

0

vv

= -1

F

zz

= -|z||z|

1

F .)j(exp)(exp

1

Fj=

|z||z|

1

F ej [ + F - 1 ]

1

0

vv

= exp j [ + F - 1] ---------- (2.21)

Since | z F | = | z1 | and ej = -1, the angles F and 1 represent respectively, phase angles of the

independents zF and z1. The circuit is capable of shifting the phase of a sinusoidal input signal

– (1.44)

The ratiooftheoutputvoltagetotheinputvoltageisthegainoftheamplifier.Hencethevoltage gain is the ratio of feedback resistor RF to the input resistance R1. The negative sign indicates that the output voltage is inverted w.r.t. the input voltage. The input resistance (Rin)

ofthewholeamplifierisgivenbytheratioofvoltagev1and the input current



We have1

0

vv

= -1

F

RR

---------- (2.19)





1

Rv-v

that is

Rin =

1

1

1

Rv-v

v R1 ---------- (2.20)


input resistance


If use ratio1

F

RR




factor ‘k’




1

0

vv

= -1

F

zz

= -|z||z|

1

F .)j(exp)(exp

1

Fj=

|z||z|

1

F ej [ + F - 1 ]

1

0

vv

= exp j [ + F - 1] ---------- (2.21)



– that is



We have1

0

vv

= -1

F

RR

---------- (2.19)





1

Rv-v

that is

Rin =

1

1

1

Rv-v

v R1 ---------- (2.20)


input resistance


If use ratio1

F

RR




factor ‘k’




1

0

vv

= -1

F

zz

= -|z||z|

1

F .)j(exp)(exp

1

Fj=

|z||z|

1

F ej [ + F - 1 ]

1

0

vv

= exp j [ + F - 1] ---------- (2.21)



–

(1.45)since v 0, note that Rinreferstothewholeoftheamplifiernottotheop-ampwhich

hasaninfiniteinputresistance

scale changer

If use ratio



We have1

0

vv

= -1

F

RR

---------- (2.19)





1

Rv-v

that is

Rin =

1

1

1

Rv-v

v R1 ---------- (2.20)


input resistance


If use ratio1

F

RR




factor ‘k’




1

0

vv

= -1

F

zz

= -|z||z|

1

F .)j(exp)(exp

1

Fj=

|z||z|

1

F ej [ + F - 1 ]

1

0

vv

= exp j [ + F - 1] ---------- (2.21)



is denoted by k, a real constant, we get v0 = –kv1. That is, input voltage has

been multipliedbythefactor‘–k’togivetheoutputvoltagescale.Thecircuitshowninfig2.7 acts as scale changer. For such applications precision resistors are used to get accurate values for the scale factor ‘k’

phase shifter:If the resistance RF and R1 in the circuit are replaced respectively by impedances zF an z1 which are equal in magnitude but differ in phase angle, we can write



We have1

0

vv

= -1

F

RR

---------- (2.19)





1

Rv-v

that is

Rin =

1

1

1

Rv-v

v R1 ---------- (2.20)


input resistance


If use ratio1

F

RR




factor ‘k’




1

0

vv

= -1

F

zz

= -|z||z|

1

F .)j(exp)(exp

1

Fj=

|z||z|

1

F ej [ + F - 1 ]

1

0

vv

= exp j [ + F - 1] ---------- (2.21)



– – – .



We have1

0

vv

= -1

F

RR

---------- (2.19)





1

Rv-v

that is

Rin =

1

1

1

Rv-v

v R1 ---------- (2.20)


input resistance


If use ratio1

F

RR




factor ‘k’




1

0

vv

= -1

F

zz

= -|z||z|

1

F .)j(exp)(exp

1

Fj=

|z||z|

1

F ej [ + F - 1 ]

1

0

vv

= exp j [ + F - 1] ---------- (2.21)



– (1.46)

Since | z F | = | z1 | and ej = –1, the angles F and 1 represent respectively, phase angles of the independents zF and z1. The circuit is capable of shifting the phase of a sinusoidal input signal voltage with out changing its magnitude. The amount of phase shift can be any thing between 0 and 3600.

non-inVerting amplifier

Thecircuitdiagramofnon-invertingamplifierisshowninfigure1.22.In this case the input voltage v1 is applied to the non-inverting input terminal. The

potential of the point G is also v1,sincetheop-ampgainisinfinite.Then,asmentionedbefore, since the input current to the op-amp is negligible, we can write using Kirchoff’s current law at the point G.

NOTES

Electronics-1



voltage with out changing its magnitude. The amount of phase shift can be any thing between 0 and

3600.

2.3.4 Non- inverting amplifier:

The circuit diagram of non-inverting amplifier is shown in figure 2.8.

In this case the input voltage v1 is applied to the non-inverting input terminal. The potential of the

point G is also v1, since the op-amp gain is infinite. Then, as mentioned before, since the input

current to the op-amp is negligible, we can write using Kirchoff’s current law at the point G.

F

10

Rvv

=1

1

Rv

---------- (2.22)

Therefore, the gain of the amplifier is

1

0

vv

= 1 +1

F

RR

---------- (2.23)

Since the gain of the op-amp is 1 plus the ratio of the two resistors RF and R1. And also note that the

output voltage is in phase with the input voltage.

2.3.5 Summing amplifier:

An adder or summing amplifier using op-amp is shown fig2.7. Here the point G is a virtual ground.

Since the current flowing into the ground is equal to that flowing out of it we can write

Fig 2.8 Circuit of non-inverting amplifier.

–A

+

+v1 ~

–

v0 output

– VEE

+VCC

RF

R1

v1G

Fig 2.9 an adder or summing amplifier.

–

+

R2v2 i2

R1v1

i1

Rn

vn in

RF i0

G

–VEE

+VCC

v0

Fig. 1.22. Circuit of non-inverting amplifier



3600.






F

10

Rvv

=1

1

Rv

---------- (2.22)


1

0

vv

= 1 +1

F

RR

---------- (2.23)







–A

+

+v1 ~

–

v0 output

– VEE

+VCC

RF

R1

v1G


–

+

R2v2 i2

R1v1

i1

Rn

vn in

RF i0

G

–VEE

+VCC

v0

...(1.47)

Therefore,thegainoftheamplifieris



3600.






F

10

Rvv

=1

1

Rv

---------- (2.22)


1

0

vv

= 1 +1

F

RR

---------- (2.23)







–A

+

+v1 ~

–

v0 output

– VEE

+VCC

RF

R1

v1G


–

+

R2v2 i2

R1v1

i1

Rn

vn in

RF i0

G

–VEE

+VCC

v0

...(1.48)

Since the gain of the op-amp is 1 plus the ratio of the two resistors RF and R1. And also note that the output voltage is in phase with the input voltage.

summing amplifier

Anadderorsummingamplifierusingop-ampisshownfig1.23.HerethepointGisavirtual

ground.Sincethecurrentflowingintothegroundisequaltothatflowingoutofitwecanwrite



3600.






F

10

Rvv

=1

1

Rv

---------- (2.22)


1

0

vv

= 1 +1

F

RR

---------- (2.23)







–A

+

+v1 ~

–

v0 output

– VEE

+VCC

RF

R1

v1G


–

+

R2v2 i2

R1v1

i1

Rn

vn in

RF i0

G

–VEE

+VCC

v0

Fig. 1.23. an adder or summing amplifier

i1 + i2 +……… + in = i0 ...(1.49)


i1 + i2 + ……… + in = i0 ---------- (2.24)

1

1

Rv

+2

2

Rv

+ …….. +n

n

Rv

= -F

0

Rv

---------- (2.25)

Solving equation. (2.25) for v0, we get

v0 = - RF

n

n

2

2

1

1

Rv

..........Rv

Rv

---------- (2.26)

If R1 = R2 ….. = Rn = R, we obtain v0 = -R

R F [ v1+v2+….+vn ] ---------(2.27)

Again if RF = R we get

v0 = -[ v1+v2+…..+vn] --------(2.28)

Equation 2.28 shows that the output voltage v0 is numerically equal to the negative sum of all input

voltages v1 through vn. Hence it was named as adder or summing amplifier.

2.3.6 Integrator:

A circuit in which the output voltage waveform is the integral of the input waveform is the integrator

or the integration amplifier. Such a circuit obtained by using a basic inverting amplifier

configuration, if the feedback resistor RF is replaced by a capacitor CF and the relevant circuit is

shown fig 2.10.

Fig 2.10 (b, c) input and ideal output waveforms using sine wave and square wave respectively

R1 CF = 1 second and voo = 0V assumed.

The expression for the output voltage v0 can be obtained by writing Kirchoff ‘s current equation at

node v2:

– ...(1.50)

NOTES




v0 = – RF


i1 + i2 + ……… + in = i0 ---------- (2.24)

1

1

Rv

+2

2

Rv

+ …….. +n

n

Rv

= -F

0

Rv

---------- (2.25)


v0 = - RF

n

n

2

2

1

1

Rv

..........Rv

Rv

---------- (2.26)


R F [ v1+v2+….+vn ] ---------(2.27)


v0 = -[ v1+v2+…..+vn] --------(2.28)



2.3.6 Integrator:




shown fig 2.10.




node v2:

...(1.51)

If R1 = R2 ….. = Rn = R, we obtain v0 =


i1 + i2 + ……… + in = i0 ---------- (2.24)

1

1

Rv

+2

2

Rv

+ …….. +n

n

Rv

= -F

0

Rv

---------- (2.25)


v0 = - RF

n

n

2

2

1

1

Rv

..........Rv

Rv

---------- (2.26)


R F [ v1+v2+….+vn ] ---------(2.27)


v0 = -[ v1+v2+…..+vn] --------(2.28)



2.3.6 Integrator:




shown fig 2.10.




node v2:

[ v1+v2+….+vn ] ...(1.52)


v0 = –[ v1+v2+…..+vn] ...(1.53)

Equation 1.52 shows that the output voltage v0 is numerically equal to the negative sumofallinputvoltagesv1throughvn.Henceitwasnamedasadderorsummingamplifier.

integrator

A circuit in which the output voltage waveform is the integral of the input waveform is the integratorortheintegrationamplifier.Suchacircuitobtainedbyusingabasicinvertingamplifierconfiguration,ifthefeedbackresistorRFisreplacedbyacapacitorCFandtherelevantcircuitisshownfig1.24.


i1 = IB+iF

Since IB is negligibly small, i1 = iF

Recall that the relationship between current through and voltage across the capacitor

ic = C .dt

dvc

Therefore

1

2in

Rv-v

= CF

dtd (v2-v0)

However, v1 = v2 0 because A is very large. Therefore

1

in

Rv

= CF dtd (-v0)

3T/2 2TT/2 T t

vin

IV

IV

Fig 2.10(b)

T/2 T 3T/2 2T

t0V–1/V–2/V

v0

t (s)

vin

IV

IV

Fig 2.10(c)|slope| = IV/S

t (s)0V

v0

–0 .5V

Fig 2.10(a) Integrator circuit.

V0 = t

inF

dtVCR 0

1

1

R1 V2 CF

ROM = R1

+VCC

– VEE

+Vin ~

–

–

A

+

IB iF

IB RL

V1

i1


i1 = IB+iF



ic = C .dt

dvc

Therefore

1

2in

Rv-v

= CF

dtd (v2-v0)


1

in

Rv

= CF dtd (-v0)

3T/2 2TT/2 T t

vin

IV

IV

Fig 2.10(b)

T/2 T 3T/2 2T

t0V–1/V–2/V

v0

t (s)

vin

IV

IV


t (s)0V

v0

–0 .5V


V0 = t

inF

dtVCR 0

1

1

R1 V2 CF

ROM = R1

+VCC

– VEE

+Vin ~

–

–

A

+

IB iF

IB RL

V1

i1

Fig. 1.24. (a) Integrator circuit.

NOTES

Electronics-1


Fig 1.24 (b, c) input and ideal output waveforms using sine wave and square wave respectively R1 CF = 1 second and v∞ = 0V assumed.

The expression for the output voltage v0 can be obtained by writing Kirchoff ‘s current equation at node v2:



ic = C


i1 = IB+iF



ic = C .dt

dvc

Therefore

1

2in

Rv-v

= CF

dtd (v2-v0)


1

in

Rv

= CF dtd (-v0)

3T/2 2TT/2 T t

vin

IV

IV

Fig 2.10(b)

T/2 T 3T/2 2T

t0V–1/V–2/V

v0

t (s)

vin

IV

IV


t (s)0V

v0

–0 .5V


V0 = t

inF

dtVCR 0

1

1

R1 V2 CF

ROM = R1

+VCC

– VEE

+Vin ~

–

–

A

+

IB iF

IB RL

V1

i1

Therefore


i1 = IB+iF



ic = C .dt

dvc

Therefore

1

2in

Rv-v

= CF

dtd (v2-v0)


1

in

Rv

= CF dtd (-v0)

3T/2 2TT/2 T t

vin

IV

IV

Fig 2.10(b)

T/2 T 3T/2 2T

t0V–1/V–2/V

v0

t (s)

vin

IV

IV


t (s)0V

v0

–0 .5V


V0 = t

inF

dtVCR 0

1

1

R1 V2 CF

ROM = R1

+VCC

– VEE

+Vin ~

–

–

A

+

IB iF

IB RL

V1

i1

– (v2 – v0)



i1 = IB+iF



ic = C .dt

dvc

Therefore

1

2in

Rv-v

= CF

dtd (v2-v0)


1

in

Rv

= CF dtd (-v0)

3T/2 2TT/2 T t

vin

IV

IV

Fig 2.10(b)

T/2 T 3T/2 2T

t0V–1/V–2/V

v0

t (s)

vin

IV

IV


t (s)0V

v0

–0 .5V


V0 = t

inF

dtVCR 0

1

1

R1 V2 CF

ROM = R1

+VCC

– VEE

+Vin ~

–

–

A

+

IB iF

IB RL

V1

i1

(–v0)

The out put voltage can be obtained by integrating both sides w. r. t. timeAcharya Nagarjuna University 17 Center for Distance Education

The out put voltage can be obtained by integrating both sides w. r. t. time

t

0 1

in

Rv

. dt = t

FC0 dt

d (-v0) . dt = CF (-v0) +0t0v

There fore

v0 = -F1CR

10

t vin dt --------(2.29)

Equation 2.29 says that the output voltage is directly proportional to the negative integral of the input

and inversely proportional to the time constant R1CF. For example if the input is a sine wave, the

output will be a cosine wave of if input is a square wave, the output will be a triangular wave as

shown as fig 2.10 (b) and (c) respectively. Note that the wave forms are drawn on the assumption

that R1CF = 1second and v00 = 0v.

For accurate integration of the input waveform, the time period of the input signal T must be

longer than or equal to R1CF. Again, the Rom is used to minimize the effect or input bias current and

the output offset voltage. The input offset voltage vi0 and the part of the input current charging the

capacitor produce the error voltage at the output of the integrator. Therefore in the practical

integrator shown in fig 2.10(a), a resistor RF is connected across the feed back capacitor CF to

produce DC stabilization. In other words RF limits the low frequency gain and hence minimizes the

variations is the output voltage. Generally, RF 10R1. The integrator is most commonly used in

analog computers and analog to digital converters (ADC) and signal wave shaping circuits.

2.3.7 The differentiator:

Fig 2.11 shows a differentiator or differentiating amplifier. As the name implies, the circuit performs

the mathematical operation of differentiation: that is the output waveform is the derivative of the

input waveform. The differentiator may be constructed form a basic inverting amplifier of an input

resistor R1 is replaced by a capacitor C1

The expression for the output voltage can be obtained from Kirchoff’s current equation

written at node v2 as follows:

ic = IB+iF

since IB 0,

– –

There fore

v0 = –


The out put voltage can be obtained by integrating both sides w. r. t. time

t

0 1

in

Rv

. dt = t

FC0 dt

d (-v0) . dt = CF (-v0) +0t0v

There fore

v0 = -F1CR

10

t vin dt --------(2.29)

Equation 2.29 says that the output voltage is directly proportional to the negative integral of the input

and inversely proportional to the time constant R1CF. For example if the input is a sine wave, the

output will be a cosine wave of if input is a square wave, the output will be a triangular wave as

shown as fig 2.10 (b) and (c) respectively. Note that the wave forms are drawn on the assumption

that R1CF = 1second and v00 = 0v.

For accurate integration of the input waveform, the time period of the input signal T must be

longer than or equal to R1CF. Again, the Rom is used to minimize the effect or input bias current and

the output offset voltage. The input offset voltage vi0 and the part of the input current charging the

capacitor produce the error voltage at the output of the integrator. Therefore in the practical

integrator shown in fig 2.10(a), a resistor RF is connected across the feed back capacitor CF to

produce DC stabilization. In other words RF limits the low frequency gain and hence minimizes the

variations is the output voltage. Generally, RF 10R1. The integrator is most commonly used in

analog computers and analog to digital converters (ADC) and signal wave shaping circuits.

2.3.7 The differentiator:

Fig 2.11 shows a differentiator or differentiating amplifier. As the name implies, the circuit performs

the mathematical operation of differentiation: that is the output waveform is the derivative of the

input waveform. The differentiator may be constructed form a basic inverting amplifier of an input

resistor R1 is replaced by a capacitor C1

The expression for the output voltage can be obtained from Kirchoff’s current equation

written at node v2 as follows:

ic = IB+iF

since IB 0,

– ...(1.54)

Equation 1.54 says that the output voltage is directly proportional to the negative integral of the input and inversely proportional to the time constant R1CF. For example if the input is a sine wave, the output will be a cosine wave of if input is a square wave, the output will beatriangularwaveasshownasfig1.24(b)and(c)respectively.Notethatthewaveformsare drawn on the assumption that R1CF = 1second and v00 = 0v.

For accurate integration of the input waveform, the time period of the input signal T must be longer than or equal to R1CF. Again, the Rom is used to minimize the effect or input bias current and the output offset voltage. The input offset voltage vi0 and the part of the input current charging the capacitor produce the error voltage at the output of the integrator. Thereforeinthepracticalintegratorshowninfig1.24(a),aresistorRF is connected across the feed back capacitor CF to produce DC stabilization. In other words RF limits the low frequency gain and hence minimizes the variations is the output voltage. Generally, RF 10R1. The integrator is most commonly used in analog computers and analog to digital converters (ADC) and signal wave shaping circuits.

NOTES



the Differentiator

Fig1.25showsadifferentiatorordifferentiatingamplifier.Asthenameimplies,thecircuitperforms the mathematical operation of differentiation: that is the output waveform is the derivative of the input waveform. The differentiator may be constructed form a basic inverting amplifierofaninputresistorR1 is replaced by a capacitor C1.

The expression for the output voltage can be obtained from Kirchoff’s current equation written at node v2 as follows:

ic = IB + iFsince IB 0,


Ic = IF

C1 dt)vd(v 2in =

F

02

Rv-v

But v1 = v2 0v, because A is very large, therefore

C1 dtdvin = -

F

0

Rv

or

v0 = -RFC1 dtdvin ---------- (2.30)

Thus the output v0 is equal to the RFC1 times the negative instantaneous rate of change of the

input voltage vin with time. Since the differentiator performs the reverse operation of the

integrators function a cosine wave input will produce a sine wave output or triangular input

will produce a square wave output. However, the differentiator of fig 2.11 will not do this

because it has some practical problems. The gain of the circuit (RF | Xc1) increases with

increase in frequency at a rate of 20 dB/decade. This makes the circuit unstable. Also, the

input impedance Xc1 decreases with increase in the frequency, which makes the circuit very

susceptible to high frequency noise. When amplified, the noise can completely over ride the

differentiated output signal.

Fig 2.11 Basic differentiator circuit.

v0 = RFC1dt

dvin

C1 v2 RF

ROM = RF

+Vin ~

–

iCiFIB0

v1

–

+

+VCC

– VEE

Fig. 1.25. Basic differentiator circuit.

Ic = IF


Ic = IF

C1 dt)vd(v 2in =

F

02

Rv-v


C1 dtdvin = -

F

0

Rv

or

v0 = -RFC1 dtdvin ---------- (2.30)











v0 = RFC1dt

dvin

C1 v2 RF

ROM = RF

+Vin ~

–

iCiFIB0

v1

–

+

+VCC

– VEE

–



Ic = IF

C1 dt)vd(v 2in =

F

02

Rv-v


C1 dtdvin = -

F

0

Rv

or

v0 = -RFC1 dtdvin ---------- (2.30)











v0 = RFC1dt

dvin

C1 v2 RF

ROM = RF

+Vin ~

–

iCiFIB0

v1

–

+

+VCC

– VEE

–

or


Ic = IF

C1 dt)vd(v 2in =

F

02

Rv-v


C1 dtdvin = -

F

0

Rv

or

v0 = -RFC1 dtdvin ---------- (2.30)











v0 = RFC1dt

dvin

C1 v2 RF

ROM = RF

+Vin ~

–

iCiFIB0

v1

–

+

+VCC

– VEE

– ...(1.55)

Thus the output v0 is equal to the RFC1 times the negative instantaneous rate of change of the input voltage vin with time. Since the differentiator performs the reverse operation of the integrators function a cosine wave input will produce a sine wave output or triangular inputwillproduceasquarewaveoutput.However,thedifferentiatoroffig1.25willnotdo this because it has some practical problems. The gain of the circuit (RF | Xc1) increases with increase in frequency at a rate of 20 dB/decade. This makes the circuit unstable. Also, the input impedance Xc1 decreases with increase in the frequency, which makes the circuit verysusceptibletohighfrequencynoise.Whenamplified,thenoisecancompletelyoverride the differentiated output signal.

NOTES

Electronics-1


Both the stability and the high frequency noise problems can be corrected by an additionof two components; R1 and CFasshowninfig1.25thiscircuitisapracticaldifferentiator

(fig1.26)


Both the stability and the high frequency noise problems can be corrected by an addition

of two components; R1 and CF as shown in fig 2.11 this circuit is a practical differentiator (fig

2.12)


Open loop op amp configuration is unsuitable for linear applications because of its very high

voltage gain as well as its variation with temperature, power supply etc.

Therefore, we can select, as well as, control the gain of the op-amp, if we introduce a

modification in the basic circuit This modification involves the use of fed-back, that is, the output

signal is fed back to the input either directly or via another network. If the signal feed-back is 1800

out of phase w.r.t. the input signal. Such a type of feedback is called negative feed back. Negative

feedback is also known as degenerative feedback, because when used, it reduces the output voltage

and in turn reduces the voltage gain and stabilizes the gain.

On the other hand if the signal fed-back is in phase with the input signal such type of feedback is

called positive feed back. Positive feedback is also known as regenerative feedback, because the

feedback signals aid the input signal. Positive feedback is needed in the oscillator circuits.

Fig 2.12(A) Practical differentiator.

v0 = - RFC1dt

dvin

CF

R1 C1

RF

ROM

VEE

+VCC

RLvin ~

–

+

if RF C1 > R1 C1 or RF CF

Fig 2.12(B) sine wave input and resulting cosine wave output.1 ms

2 4 t 3 (ms)

Vin

+IV

0V–IV

1 ms

V0

+ 0.94V

0V– 0.94V

2 4 t 3 (ms)

Fig. 1.26(A) Practical differentiator


Both the stability and the high frequency noise problems can be corrected by an addition

of two components; R1 and CF as shown in fig 2.11 this circuit is a practical differentiator (fig

2.12)


Open loop op amp configuration is unsuitable for linear applications because of its very high

voltage gain as well as its variation with temperature, power supply etc.

Therefore, we can select, as well as, control the gain of the op-amp, if we introduce a

modification in the basic circuit This modification involves the use of fed-back, that is, the output

signal is fed back to the input either directly or via another network. If the signal feed-back is 1800

out of phase w.r.t. the input signal. Such a type of feedback is called negative feed back. Negative

feedback is also known as degenerative feedback, because when used, it reduces the output voltage

and in turn reduces the voltage gain and stabilizes the gain.

On the other hand if the signal fed-back is in phase with the input signal such type of feedback is

called positive feed back. Positive feedback is also known as regenerative feedback, because the

feedback signals aid the input signal. Positive feedback is needed in the oscillator circuits.

Fig 2.12(A) Practical differentiator.

v0 = - RFC1dt

dvin

CF

R1 C1

RF

ROM

VEE

+VCC

RLvin ~

–

+

if RF C1 > R1 C1 or RF CF

Fig 2.12(B) sine wave input and resulting cosine wave output.1 ms

2 4 t 3 (ms)

Vin

+IV

0V–IV

1 ms

V0

+ 0.94V

0V– 0.94V

2 4 t 3 (ms)

Fig. 1.26(B). sine wave input and resulting cosine wave output

1.8 SUMMARYAdifferentialamplifierconsistsoftwosymmetricalcommonemitterstagesandiscapableofamplifyingthedifferencebetweentwoinputsignals.Differentialamplifieriscapableofamplifying ac as well as dc input signals because it employs direct coupling. For proper operationofthedifferentialamplifier,atransistorarrayandmatchedcomponentsmustbeused.Thedifferentialamplifiercanbebiasedbyusingemitterbias(acombinationofRE and VEE), a constant current bias. The constant current bias is more preferable in differential amplifiersbecauseitmaintainstheinfiniteinputimpedanceforall thedesiredvaluesofemitter currents IE.

Anidealop-amphasinfinitevoltagegain,inputresistance,CMRRandslewratetogetherwith zero output resistance and output offset voltage. The equivalent circuit of op-amp is useful in analyzing the basic operating principles of an op-amp and in observing the effects of feedback arrangements. The voltage transfer characteristic curve of an op-amp is the graph of output voltage versus the differential input voltage. Differential, inverting and non-inverting amplifiersarethethreeopenloopop-ampconfigurationsinwhichtheoutputsignalisnot

NOTES



fed back in any form as part of the input signal. When operated in the open loop; generally the op-amp’s output is either at positive or negative saturation or switches between positive and negative saturation levels. This action is undesirable in linear applications, hence the op-amp’sarerarelyusedinopenloopconfigurationforthelinearapplications.

Openloopopampconfigurationisunsuitableforlinearapplicationsbecauseofitsveryhigh voltage gain as well as its variation with temperature, power supply etc.

Therefore, we can select, as well as, control the gain of the op-amp, if we introduce a modificationinthebasiccircuitThismodificationinvolvestheuseoffed-back,thatis,theoutput signal is fed back to the input either directly or via another network. If the signal feed-back is 1800 out of phase w.r.t. the input signal. Such a type of feedback is called negative feed back. Negative feedback is also known as degenerative feedback, because when used, it reduces the output voltage and in turn reduces the voltage gain and stabilizes the gain.

On the other hand if the signal fed-back is in phase with the input signal such type of feedback is called positive feed back. Positive feedback is also known as regenerative feedback, because the feedback signals aid the input signal. Positive feedback is needed in the oscillator circuits.

Therearefourtypesofclosedloopconfigurationsusingnegativefeedback:voltageseries,voltageshunt,currentseriesandcurrentshunt.Furthertheseconfigurationsarelabeledaccording to whether the voltage or current is fed-back to the input in series or in parallel. Thevoltageseriesnegative feedbackconfiguration isgenerallyknownasnon invertingamplifierifthefeedbackandtheidealclosedloopvoltagegainoftheconfigurationdependsonly on the feedback network (components) and is independent of the internal or open loop gain A of the op-amp.

Introductionofthenegativefeedbackinnon-invertingamplifierincreasestheinputimpedance and bandwidth and decreases the output resistance; total output- offset voltage and the effect of varying environmental conditions on the gain. The voltage follower is the specialcaseofnoninvertingamplifier.

Summing, scaling amplifiers can be constructed byusing inverting, non-invertinganddifferentialconfigurations.Theintegratoranddifferentiatoraremostwidelyusedinsignal wave shaping applications. Besides the integrator is used in analog computers and the differentiator is used as a rate of change detector in FM modulators.

1.9 KEYWORDSzz Configuration: Design of the circuit by employing the various possible networks iscalledconfiguration.

zz Decibel (dB); 1/ tenth of a Bell; Bell is unit of power ratio

zz Milli volts (mV); 1/1000 of a volts

zz Nano Ampere (nA); 1nA = 10-9 ampere

NOTES

Electronics-1


zz Pico Farad (pF); 1pF = 10-12 Farad

zz Saturation; when input voltage in the circuit exceeds a certain value, the output goes to the maximum value is called saturation

zz Pot (Potentiometer); variable wire wound resistor

zz Active components: Active components can generate voltage or current or power

zz Example: Battery, signal generator.

zz Passive components: The components only dissipate power Example: Resistor, capacitor.

zz Degenerative feedback: The output voltage is fed back to the input such that this voltage is 1800 out of phase w.r.t. the source voltage. As a result, the effective input voltage decreases (degenerates) and this is called degenerative feedback or negative feedback.

1.10 REVIEW QUESTIONS1. Explaintheworkingofdifferentialamplifierwithadiagram.

2. Whatarecommonmodeanddifferentialmodegainofadifferentialamplifier?

3. Derive expressions for the common mode voltage gain and differential mode voltagegain.ofatransistordifferentialamplifierandshowthatthecommonmoderejection ratio increases with emitter resistance.

4. Whatismeantbyconstantcurrentbias?Explainitsuse.

5. Whataretheimportantstagesofatypicaloperationalamplifier?

6. Mention the important electrical characteristics of an ideal op-amp.

7. How far IC 741 electrical characteristics are nearer to the ideal characteristic of op-amp.

8. Explain the terms input offset voltage, input offset current, input bias current.

9. Explainwhyop-ampisnotusedinopenloopconfigurationforlinearapplications.

10. Mention two reasons why an open loop op-amp is unsuitable for linear applications.

11. Whatdoyoumeanbyfeedback?Listtwotypesoffeedback.Whichtypeisusedinlinearapplications?

12. Describethefournegativefeedbackconfigurations.Whichconfigurationismostwidelyused?

13. Explainbrieflywhynegativefeedbackisdesirableinamplifierapplications.

14. How does negative feedback affect the close loop voltage gain, input resistance, outputresistanceandbandwidthofvoltageseriesfeedbackamplifier(closedloopnon-invertingamplifier)

NOTES



15. Inwhatwayisthevoltagefolloweraspecialcaseofthenon-invertingamplifier?

16. Explaintheinvertingandnon-invertingamplifiers?

17. Explain the difference between the integrator and differentiator and give one application of each.

1.11 FURTHER READINGSzz OperationalAmplifiersandLinearIntegratedCircuitTechnologybyRamakanth

A. Gaykwad Prentice Hall Inc.,

zz Basic Electronics by DC Tayal, Himalaya Publish Co.,

zz Semi Conductor Electronics by A K. Sharma New Age International Publishers

zz Foundations of Electronics By D. Chattopadhyay, PC Rakshit, B. Saha, M.N. Purkait Second Edition, Wiley Eastern Ltd.,

zz Integrated Electronics By Millman & Halkias (MH)

NOTES

Electronics-1


CHAPTER – 2

MODULATIONSTRUCTURE

2.1 Learning Objectives

2.2 Introduction

2.3 Need for Modulation

2.4 Amplitude Modulation

2.5 Mathematical analysis of Wave

2.6 Generation of A.M. waves

2.7 Demodulation of A.M. Waves

2.8 Super heterodyne receiver Frequency modulation and detection

2.9 Summary

2.10 Keywords

2.11 Review Questions

2.12 Further Readings


zz In this chapter, we study about thez (i) Processes of amplitude and frequency modulationz (ii) Types of amplitude modulationz (iii) Process of detection of AM and FM waves

AMPLITUDE MODULATION AND A.M. DETECTION

2.2 INTRODUCTIONFor successful transmission and reception of intelligence (code, voice, music etc) by the use of radio waves, two processes are essential. They are ( i ) Modulation ( ii ) De-Modulation or detection. To modulate means to regulate or adjust. Speech and music etc. are sent thousands of kilometers away by a radio transmitter. Similarly, a scene in front of a television camera is also sent many kilometers away to viewers. In such cases the carrier is the high frequency radio wave. The intelligence i.e. video, sound and other data is impressed on the carrier wave and is carried along with it to the destination.

NOTES

Modulation


Modulation is the process of combining the low frequency signal with a very high frequency radio wave called carrier wave ( c.w.). The resultant wave is called modulated carrier wave. This job is done at the transmitting station.

During modulation some characteristic of the carrier wave is varied in time with the modulating signal. Accordingly there are three types of sine wave modulations known as amplitude Modulation, Frequency Modulation and Phase Modulation.

The A.M. wave contains three frequency components, a carrier frequency (fc), one component above the carrier frequency (fc + fs) and the other component ‘below’ the carrier frequency (fc - fs) where ‘fc’ and ‘fs’ are the carrier and signal frequencies respectively. At the receiver the signal is extracted from the modulated carrier. This process is called A.M. detection or de-modulation.

Amplitude modulated signals are influenced by noise. Most noise appears as additional amplitude modulation on the signal. The effect of noise is minimized in frequency modulation.

Def: When the frequency of carrier wave is changed in accordance with the instantaneous value of signal, it is called frequency modulation.


LESSON – 7

SECTION II

Frequency modulation and detection

Introduction:- Amplitude modulated signals are influenced by noise. Most noise appears as additional

amplitude modulation on the signal. The effect of noise is minimized in frequency modulation.

Def: When the frequency of carrier wave is changed in accordance with the instantaneous value of signal, it is

called frequency modulation.

In frequency modulation, only the frequency of the carrier wave is changed in accordance with the signal.

However, the amplitude of the modulated wave remains the same i.e. carrier wave amplitude. The amount of

change in frequency is determined by the amplitude of the modulating signal where as rate of change is

determined by the frequency of the modulating signal as shown in fig.

In F.M., information or intelligence is carried as variations in carrier frequency.

Carrier – f0

H f0 L f0 H f0 L

HighHigh

Center CenterCenter

Low Low

Fig 7.2.1

Modulating signal

0.50

t

Fig. 2.1

NOTES

Electronics-1


In frequency modulation, only the frequency of the carrier wave is changed in accordance with the signal. However, the amplitude of the modulated wave remains the same i.e. carrier wave amplitude. The amount of change in frequency is determined by the amplitude of the modulating signal where as rate of change is determined by the frequency of the modulating signal as shown in fig. 2.1.

In F.M., information or intelligence is carried as variations in carrier frequency.

2.3 NEED FOR MODULATIONSometimes, beginners question the necessity of modulation is using a carrier wave to carry the low frequency signal from one place to another. Why not transmit the signals directly and save lot of difficulty? Unfortunately there are the many hurdles in the process of such direct transmission of audio frequency signals. These are:

(i) Voice, data and video signals have low frequencies. These waves have relatively short range.

(ii) If everybody transmits these low frequency signals directly, mutual interference will render all of them ineffective.

(iii) Size of antennas required for their efficient radiation would be large, i.e., about 75Km!

Hence, the solution lies in modulation, which enables a low frequency signal to travel very large distances through space with the help of a high frequency carrier wave (fc). These carrier waves need reasonably sized antennas and care is taken to select the carrier frequencies to avoid interference with other transmitters operating in the same area.

2.4 AMPLITUDE MODULATIONDefinition: When the amplitude of high frequency carrier wave is changed in

accordance with the instantaneous value of the amplitude of the signal, it is called amplitude modulation. However the frequency of the modulated wave remains the same i.e at carrier frequency. The following fig (2.2) shows the principle of amplitude modulation. Fig 2.2(a) shows the audio electrical signal where as fig 2.2(b) shows a carrier wave.

Fig. 2.2(c) shows the amplitude modulated (AM) wave.

Note that the amplitudes of both positive and negative half cycles of carrier wave are changed in accordance with the signal. Amplitude modulation is done by, an electronic circuit called modulator.

Modulation factor: An important consideration in A.M. is to describe the depth of modulation, i.e the extent to which the Amplitude of carrier wave is changed by the signal. This is described by a factor called modulation index, which may be defined as under.

Definition of Modulation index / factor: The ratio of change of carrier wave amplitude due to modulation to the amplitude of unmodulated carrier wave is called the modulation factor m.

NOTES

Modulation



Hence, the solution lies in modulation, which enables a low frequency signal to travel very large distances

through space with the help of a high frequency carrier wave (fc). These carrier waves need reasonably sized

antennas and care is taken to select the carrier frequencies to avoid interference with other transmitters

operating in the same area.

7.3 Amplitude Modulation:

Definition: When the amplitude of high frequency carrier wave is changed in accordance with the

instantaneous value of the amplitude of the signal, it is called amplitude modulation. However the frequency

of the modulated wave remains the same i.e at carrier frequency. The following fig (1) shows the principle of

amplitude modulation. Fig 1(a) shows the audio electrical signal where as fig 1(b) shows a carrier wave.

Fig 1(c) shows the amplitude modulated (AM) wave.

Note that the amplitudes of both positive and negative half cycles of carrier wave are changed in

accordance with the signal. Amplitude modulation is done by, an electronic circuit called modulator.

Ec

Ec

m Ec

Ec

CARRIER A M WAVE

Fig 7.1.1 Amplitude Modulation

SIGNAL

Fig. 2.2. Amplitude Modulation

2.5 MATHEMATICAL ANALYSIS OF WAVEA carrier wave may be represented by ec = Ec cos ct , where

ec = instantaneous voltage of carrier

Ec = amplitude of carrier

c = 2fc = angular velocity of carrier of frequency ‘fc’.

The modulating signal can be represented by

es = Es cos st

where es is the instantaneous value of modulating signal. Es is its amplitude.

s = 2fs = angular frequency ‘fs’.

In amplitude modulation the amplitude Ec of the carrier wave is varied in accordance with the instantaneous value of the signal as shown in fig (2.2). The amplitude of modulated signal can be represented by

E = Ec + ka E m cos st

Where ka is called coefficient of modulation

The carrier wave amplitude is varied at signal frequency fs. Therefore

e = Ec. (1 + m cos st ) cos ct.

Where m = kaEs/Ec is called modulation index or modulation factor

NOTES

Electronics-1


The expression for A.M. wave can be expanded as

= Ec . cos ct + m .Ec . cos st . cos ct.

= Ec . cos ct + m . Ec

2 2 cos st . cos c t

= Ec . cos ct + m . Ec

2 cos (c + s)t + cos (c – s)t

= Ec . cos ct + . mEc

2 . cos (c + s).t +

mEc

2 . cos (c – s) t.

The following points may be noted from the equation of Amplitude modulated wave.

The A.M. wave is equivalent to the summation of three sinusoidal waves: one having

amplitude Ec and frequency ‘fc’, the second having amplitude mEc

2 and frequency (fc + fs)

and the third having amplitude mEc

2 and frequency (fc - fs).

The A.M. wave contains three frequencies. They are fc, fc + fs and (fc – fs). Thus, the process of amplitude modulation does not change the original carrier frequency but produces two new frequencies (fc + fs) and (fc – fs), which are called side band frequencies. The sum of carrier frequency and signal frequency i.e.,(fc + fs) is called upper side band frequency. The lower side band frequency is (fc – fs) i.e., the difference between carrier and signal frequencies. The amplitudes of the side bands are equal and proportional to depth of modulation. It can be shown that the maximum power in each side band occurs when m = 1 and is equal to one fourth of carrier power.

Upper and Lower SidebandsIn the above discussion, it was assumed that the modulating signal was composed of one frequency component only. However, in a broadcasting station, the modulating signal is the human voice (or music), which contains waves with a frequency range of 20-4000 Hz. Each of these waves have its own LSF and USF. When combined together, they give rise to an Upper-side band (USB) and a Lower-side band (LSB) as Shown in fig.2.3.

The USB, in fact, contains all sum components of the signal and carrier frequency whereas LSB contains their difference components. The channel width (or bandwidth) is given by the difference between extreme frequencies i.e., between maximum frequency of USB and minimum frequency of LSB. As seen

Channel width = 2x maximum frequency of modulating signal = 2x fs(max).

Example: An audio signal given by 15 sin 2 (2000 t) amplitude-modulates a sinusoidal carrier wave 60 sin 2 (100,000) t.. Assuming ka =1 determine (a) modulation index, (b) percent modulation, (c) frequencies of signal and carrier, (d) frequency spectrum of the modulated wave.

NOTES

Modulation



The following points may be noted from the equation of Amplitude modulated wave.

The A.M. wave is equivalent to the summation of three sinusoidal waves: one having amplitude Ec and

frequency ‘fc’, the second having amplitude2

mEc and frequency (fc + fs) and the third having amplitude

2mEc and frequency (fc - fs).

The A.M. wave contains three frequencies. They are fc, fc + fs and (fc-fs). Thus, the process of amplitude

modulation does not change the original carrier frequency but produces two new frequencies (fc + fs) and (fc -

fs), which are called side band frequencies. The sum of carrier frequency and signal frequency i.e.,(fc +fs) is

called upper side band frequency. The lower side band frequency is (fc - fs) i.e., the difference between carrier

and signal frequencies. The amplitudes of the side bands are equal and proportional to depth of modulation. It

can be shown that the maximum power in each side band occurs when m = 1 and is equal to one fourth of

carrier power .

Upper and Lower Sidebands:

In the above discussion, it was assumed that the modulating signal was composed of one frequency

component only. However, in a broadcasting station, the modulating signal is the

human voice (or music), which contains waves with a frequency range of 20-4000 Hz. Each of these waves

have its own LSF and USF. When combined together, they give rise to an Upper-side band (USB) and a

Lower-side band (LSB) as Shown in fig.7.1.2

Channel width

fc – fs (max) fc + fs (max)fc + fs (min)fc – fs (min)

LSB USB

CW

Fig 7.1.2

fc

Fig. 2.3

Solution. Here carrier amplitude, A = 60 and modulating signal amplitude B = 15. Therefore

(a) Modulation index, m = BA

= 1560

= 0.25

(b) Percent modulation, M = m x 100 = 0.25 x 100 = 25%

(c) fs = 2000 Hz --------by inspection of the given equation

fc = 100,000 Hz --------by inspection of the given equation

(d) The three frequencies present in the modulated carrier wave are

( i ) 100,000 Hz = 100 kHz, (ii) 120,000 or 120 kHz, (iii) 80,000 or 80kHz

Experimentally by measuring the maximum and minimum value of the modulated carrier amplitude one can determine the depth of modulation from the relation

m = (Emax – Emin) / (Emax + Emin)

From this relation we see that , when Emax = Emin , m = 0 or there is no modulation and when

Emin = 0 there is 100% modulation. In commercial radio broadcasting the depth of modulation is maintained around 40%.

2.6 GENERATION OF A.M. WAVESAmplitude modulation is produced by combining the carrier and the signal frequencies using a non-linear device. Diodes are non-linear devices but they are not used as they do not offer any gain. Transistors behave as non-linear elements and offer gain as such they are suitable for this applications. Fig. 2.3 shows a simple amplitude – modulated amplifier.

NOTES

Electronics-1


The supply VCC in combination with the resistors R1, R2, RC & RE sets the quiescent point for the transistor. The carrier eC is the input to the CE amplifier. The circuit amplifies the carrier by a factor AV where AV is the voltage gain, so that the amplifier output is AV eC. The modulating signal em is applied in emitter circuit and hence forms a part of the biasing. It produces variations in emitter current at modulating frequency, which in turn produces variations in base emitter resistance and gain AV. Thus, the amplitude of the carrier varies in accordance with the strength of the signal there by producing Amplitude modulated output across ‘RL’.


Forms of amplitude modulation:

We know now that one carrier and two side bands are produced in A.M. generation. It is not necessary to

transmit all these signals to enable the receiver to reconstruct the original signal. Accordingly, we may

attenuate or altogether remove the carrier or any one of the side bands with out affecting the communication

process. The advantages are,

(1) Less transmitted power and

(2) Small bandwidth required.

The different suppressed component systems are: (a) DSB-SC (b) SSB-TC (C) SSB-SC,

(a)DSB-SC: It stands for double side band suppressed carrier system. Here carrier component is suppressed

there by saving enormous amount of power.

(b)SSB-TC: It stands for single side band transmitted carrier system. In this case one sideband is suppressed

but the other sideband and carrier are transmitted.

(c) SSB-SC: It stands for single side band suppressed carrier system. It suppresses one side band and the

carrier and transmits only the remaining side bond.

Out of the above three systems, the SSB-SC (or simply SSB) is more preferable because of its advantage over

other.

Generation of SSB-SC or SSB systems:

The SSB-SC or simply SSB is generated mainly through the following three methods:

~

~

+VCC

RC

CoutR1

R2

RERL

em

ec

(ec) AM

CE

Cin

Carrier

Signal

Fig 7.1.3 An amplitude-modulated amplifier.Fig. 2.3. An amplitude-modulated amplifier.

Forms of Amplitude ModulationWe know now that one carrier and two side bands are produced in A.M. generation. It is not necessary to transmit all these signals to enable the receiver to reconstruct the original signal. Accordingly, we may attenuate or altogether remove the carrier or any one of the side bands with out affecting the communication process. The advantages are,

(1) Less transmitted power and

(2) Small bandwidth required.

The different suppressed component systems are: (a) DSB-SC (b) SSB-TC (C) SSB-SC,

(a) DSB-SC: It stands for double side band suppressed carrier system. Here carrier component is suppressed there by saving enormous amount of power.

(b) SSB-TC: It stands for single side band transmitted carrier system. In this case one sideband is suppressed but the other sideband and carrier are transmitted.

(c) SSB-SC: It stands for single side band suppressed carrier system. It suppresses one side band and the carrier and transmits only the remaining side bond.

Out of the above three systems, the SSB-SC (or simply SSB) is more preferable because of its advantage over other.

NOTES

Modulation


Generation of SSB-SC or SSB SystemsThe SSB-SC or simply SSB is generated mainly through the following three methods:

(1) Filter method.

(2) Phase cancellation (shift) method.

(3) The third method.

1. Filter method: In this method, DSB-SC signal is generated by, the balanced modulator. This signal is allowed to pass through side band filters, which are narrow band pass filters that only allow to pass the desired side band of frequencies. The filter may be a LC, mechanical or a crystal filter. All these filters have the disadvantage that their operating frequency is below the usual transmitting frequencies. Thus a balanced mixer and crystal oscillator are used to provide up conversion to the final transmitter frequency.

2. Phase shift method: In this method, two balanced modulators and two phase shifting networks are used. One of the balanced modulator receives the carrier voltage shifted by 900 and the modulating voltage signal while the other balanced modulator receives the carrier voltage and the modulating voltage shifted by 90°. The output of both modulators consists of sidebands only. The signal is applied directly to the modulator M1, therefore the modulator puts out two side bands, each one is shifted in phase by 90°. The signal is shifted 90° before it is applied to the modulator, therefore, the modulator also puts two side bands, but in this case the upper and lower side bands and shifted by +90° and –90° respectively. The two lower side bands, which are out of phase, when combined in the adder cancel each other. The upper side hands, which are in phase add directly in the adder. Thus SSB in which lower sideband is removed is produced. The block diagram of this method is shown in the fig. 2.4.

M.Sc. Physics 8 Modulation

(1) Filter method.

(2) Phase cancellation (shift) method.

(3) The third method.

1. Filter method: In this method, DSB-SC signal is generated by, the balanced modulator. This signal is

allowed to pass through side band filters, which are narrow band pass filters that only allow to pass the desired

side band of frequencies. The filter may be a LC, mechanical or a crystal filter. All these filters have the

disadvantage that their operating frequency is below the usual transmitting frequencies. Thus a balanced

mixer and crystal oscillator are used to provide up conversion to the final transmitter frequency.

2. Phase shift method: In this method, two balanced modulators and two phase shifting networks are used.

One of the balanced modulator receives the carrier voltage shifted by 900 and the modulating voltage signal

while the other balanced modulator receives the carrier voltage and the modulating voltage shifted by 900.

The output of both modulators consists of sidebands only. The signal is applied directly to the modulator M1,

therefore the modulator puts out two side bands, each one is shifted in phase by 900. The signal is shifted 900

before it is applied to the modulator, therefore, the modulator also puts two side bands, but in this case the

upper and lower side bands and shifted by +900 and -900 respectively. The two lower side bands, which are

out of phase, when combined in the adder cancel each other. The upper side hands, which are in phase add

directly in the adder. Thus SSB in which lower sideband is removed is produced. The block diagram of this

method is shown in the fig.

The output of first balanced modulator M1

v1 = 2 vc. ma cos ct . sin m .t . ----------- (1)

The output from the balanced modulator M2

v2 = 2 vc ma co sin ct . cos m . t --------------(2)

Balancedmodulator

M1

Balancedmodulator

M2

Carriersource

A.F.900 Phase

shifter

Adder

Audio input

SSBOutput

Carrier900 Phase

shifter

Fig 7.1.4 SSB – SC transmitter using phase shift.Fig. 2.4. SSB – SC transmitter using phase shift

The output of first balanced modulator M1

v1 = 2 vc. ma cos ct . sin m .t . ...(1)

NOTES

Electronics-1


The output from the balanced modulator M2

v2 = 2 vc ma co sin ct . cos m . t ...(2)The summing amplifier, the resultant outputv = v1 + v2 = 2 vc . ma sin (c + m )t ...(3)(By adding (1) & (2))Thus the output contains only upper sideband, similarly, the output with lower side

band can be obtained by passing the signal carrier directly to balanced modulator M1 and each through 90° phase shifting networks to the modulator M2.

(iii) The third method:


The summing amplifier, the resultant output

v = v1 + v2 = 2 vc . ma sin (c + m )t ------------ (3)

(By adding (1) & (2))

Thus the output contains only upper sideband, similarly, the output with lower side band can be obtained by

passing the signal carrier directly to balanced modulator M1 and each through 900 phase shifting networks to

the modulator M2.

(iii) The third method:-

This method has the ability to generate SSB at any frequency and the low audio frequencies. It neither

refuses a filter circuit nor a wide band, audio phase shift network. The circuit is identical to that of the phase

shift method, but the way in which voltages are fed to the two balanced modulators has been changed. Due to

this reason, this method is called modified phase shift method the block diagram of the method is shown in the

following fig.7.1.4.

7.6 Demodulation of A.M. Waves:

Definition of Demodulation:

The process of recovering the audio signal from the modulated wave is known as demodulation of

detection.

At the broadcasting station, modulation is done to transmit the audio signal over larger distances to a

receiver. When the modulated wave is picked up by the radio receiver, it is necessary to recover the audio

signal from it. This process is accomplished in the radio receiver and is called demodulation.

Necessity of Demodulation:

We know, that an A.M. wave consists of carrier and side band frequencies. The audio signal is in side

band frequencies, which are radio frequencies. If the modulated wave after amplification is directly fed to the

900 Phaseshifter

900 Phaseshifter

A.F.Carrier

R.F.Carrier

Adder

Balancedmodulator

M1

Balancedmodulator

M2

Low-passfilter

Balancedmodulator

M4

Balancedmodulator

M3

Low-passfilter

SSBOutput

Audio

input

Fig 7.1.5 Third method for SSB generation.Fig. 2.5. Third method for SSB generation

This method has the ability to generate SSB at any frequency and the low audio frequencies. It neither refuses a filter circuit nor a wide band, audio phase shift network. The circuit is identical to that of the phase shift method, but the way in which voltages are fed to the two balanced modulators has been changed. Due to this reason, this method is called modified phase shift method the block diagram of the method is shown in the following fig.2.5.

2.7 DEMODULATION OF A.M. WAVES

Definition of DemoDulation

The process of recovering the audio signal from the modulated wave is known as demodulation of detection.

At the broadcasting station, modulation is done to transmit the audio signal over larger distances to a receiver. When the modulated wave is picked up by the radio receiver, it is necessary to recover the audio signal from it. This process is accomplished in the radio receiver and is called demodulation.

Necessity of DemodulationWe know, that an A.M. wave consists of carrier and side band frequencies. The audio signal is in side band frequencies, which are radio frequencies. If the modulated wave after

NOTES

Modulation


amplification is directly fed to the speaker, no sound will be heard because of the inertia of the diaphragm as it is not able to respond to such high frequencies.

Essentials of DemodulationFor a modulated wave to be audible, it is necessary to change the nature of modulated wave. This is done by a circuit called detector. A detector circuit performs the following two functions

It rectifies the modulated wave.

It separates the audio signal from the carrier.

The demodulation can be accomplished with the help of a diode detector.

A.M. Diode DetectorDiode detection is also known as envelope detection or linear detection.

In appearance it looks like an ordinary half wave rectifier circuit with capacitor input. As shown in the below fig. 2.6.

It is called envelope detection because it recovers the A.F. signal envelope from the composite signal. Similarly, diode detector is called linear detector because its output is proportional to the voltage of the input signal.


speaker, no sound will be heard because of the inertia of the diaphragm as it is not able to respond to such

high frequencies.

Essentials of demodulation:

For a modulated wave to be audible, it is necessary to change the nature of modulated wave. This is done

by a circuit called detector. A detector circuit performs the following two functions

It rectifies the modulated wave.

It separates the audio signal from the carrier.

The demodulation can be accomplished with the help of a diode detector.

A.M. Diode detector:

Diode detection is also known as envelope detection or linear detection.

In appearance it looks like an ordinary half wave rectifier circuit with capacitor input. As shown in the below

fig--

It is called envelope detection because it recovers the A.F. signal envelope from the composite signal.

Similarly, diode detector is called linear detector because its output is proportional to the voltage of the input

signal.

Circuit Action:

This circuit involves the rectification of the signal, and filtering the r.f. and dc components. The signal is

rectified by diode ‘D’. The rectified wave is shown at A in the fig. The combination C1 – R1 removes the

high frequency component and provide the signal super posed over a dc component. The dc component is

eliminated by capacitor ‘C2’ to give the output shown in the figure 7.1.5

AM

A B O

D

R1 C1

Fig 7.1.6 Simple detectorAM – Amplitude Modulated Wave

C2

Fig 2.6. Simple detector AM – Amplitude Modulated Wave

Circuit ActionThis circuit involves the rectification of the signal, and filtering the r.f. and dc components. The signal is rectified by diode ‘D’. The rectified wave is shown at A in the fig. The combination C1 – R1 removes the high frequency component and provide the signal super posed over a dc component. The dc component is eliminated by capacitor ‘C2’ to give the output shown in the figure 2.6.

2.8 SUPER HETERODYNE RECEIVERThe shortcomings of a radio receiver were overcome by the invention of super heterodyne receiver.

NOTES

Electronics-1


Principle of super – heterodyning: In this type of radio receiver the selected radio frequency is converted to a fixed lower value called intermediate frequency (IF). This is achieved by a special electronic circuit called mixer circuit. There is a local oscillator in the radio receiver itself. This oscillator produces high frequency waves. The selected radio frequency is mixed with the high frequency wave by the mixer circuit. In this process, beats are produced and the mixer produces a frequency equal to the difference between local oscillator and radio wave frequency. The circuit is so designed that oscillator always produces a frequency 455KHz above the selected & R.F. Therefore the mixer always produces an IF of 455KHz regardless of the station to which the receiver is tuned. The production of mixed IF is the salient feature of a super heterodyne circuit. At this fixed IF, the amplifier circuit operates with a maximum stability, selectivity and sensitivity. As the conversion of incoming RF to IF is achieved by heterodyning or beating the local oscillator against R.F., therefore this circuit is called super heterodyne circuit.

Stages of Super Heterodyne ReceiverThe following fig 2.7 shows the block diagram of a super hetero dyne receiver. It consists of 5 stages. There are (1) RF amplifier stage (2) Mixer stage (3) IF amplifier stage (4) Detector stage (5) AF amplifier stage


7.7 Super heterodyne receiver:

The shortcomings of a radio receiver were overcome by the invention of super heterodyne receiver.

Principle of super - heterodyning: In this type of radio receiver the selected radio frequency is

converted to a fixed lower value called intermediate frequency (IF). This is achieved by a special

electronic circuit called mixer circuit. There is a local oscillator in the radio receiver itself. This

oscillator produces high frequency waves. The selected radio frequency is mixed with the high

frequency wave by the mixer circuit. In this process, beats are produced and the mixer produces a

frequency equal to the difference between local oscillator and radio wave frequency. The circuit is

so designed that oscillator always produces a frequency 455KHz above the selected & R.F.

Therefore the mixer always produces an IF of 455KHz regardless of the station to which the

receiver is tuned. The production of mixed IF is the salient feature of a super heterodyne circuit. At

this fixed IF, the amplifier circuit operates with a maximum stability, selectivity and sensitivity. As

the conversion of incoming RF to IF is achieved by heterodyning or beating the local oscillator

against R.F., therefore this circuit is called super heterodyne circuit.

Stages of super heterodyne receiver

The following fig 7.1.6 shows the block diagram of a super hetero dyne receiver. It consists of 5

stages. There are 1) RF amplifier stage 2) Mixer stage 3) IF amplifier stage 4) Detector stage 5)AF

amplifier stage

C3 L3

OSCILLATOR

C1 L1

R.F.AMPLIFIE

C2 L2

MIXER

I.F.AMPLIFIER

DETECTOR A.F.AMPLIFIER

Fig 7.1.7

455kHz

Receiving aerial

Fig. 2.7

RF amplifier stage: This stage uses a tuned parallel circuit L1 C1 with a variable capacitor ‘C1’. The radio waves from various broadcasting stations are intercepted by the receiving aerial and are coupled to this stage.

This stage selects the desired radio wave and raises the strength of the wave to the desired level.

Mixer stage: The amplified output of RF amplifier is fed to the mixer stage. Hence it is combined with the output of local oscillator. The two frequencies beat together and produce an intermediate frequency (IF).

IF = Oscillator frequency – Radio frequency.

= 455 KHz (always)

NOTES

Modulation


IF amplifier stage: The output of mixer is always 455KHz and is fed to fixed tuned IF amplifiers. These amplifiers are tuned to one frequency and give nice amplification.

Detector stage: The output from the last IF amplifier stage is coupled to the input of the detector stage. Here, the audio signal is extracted from the input.

AM amplifier stage: The audio signal output of the detector stage is fed to multistage audio amplifier. Here, the signal is amplified until it is sufficiently strong to drive the speaker. The speaker converts the audio signal into sound waves corresponding to the original sound of the broadcasting station.

Advantages of Super Heterodyne CircuitThe super heterodyne principle has the following advantages.

High RF Amplification.

Improved selectivity.

Low cost.

FREQUENCY MODULATION AND DETECTIONMathematical expression for F.M. wave:

The unmodulated carrier is given by

ec = A sin 2 f0 t ...(4)

The modulating signal frequency is given by

em = B sin 2 fm t ...(5)

The modulated carrier frequency ‘f’ swings around the resting frequency f0. Thus

f = f0 + f sin 2 fm t ...(6)

Hence equation for the frequency-modulated wave becomes

e = A sin 2 f t ...(7)

= A sin 2 (f0 + f .sin 2 fm t) t

(Substituting (3) in (4) );

=


Mathematical expression for F.M. wave:

The unmodulated carrier is given by

ec = A sin 2 f0 t --------(1)

The modulating signal frequency is given by

em = B sin 2 fm t --------(2)

The modulated carrier frequency ‘f’ swings around the resting frequency f0. Thus

f = f0 + f sin 2 fm t --------(3)

Hence equation for the frequency-modulated wave becomes

e = A sin 2 f t --------(4)

= A sin 2 (f0 + f .sin 2 fm t) t

(Substituting (3) in (4) );

= A sin (2 f0 t +mff

.cos 2 fm t)

e = A sin (2 f0 t + mf .cos 2 fm t)

e= A sin(0t + mf cosmt) since = 2f

e= A sin(0t) cos(mf cosmt) + cos(0t) sin(mf cosmt)

The cos(mf cosmt) and sin(mf cosmt) terms have to be expanded into infinite trigonometric series

involving sine and cosine terms of harmonics of m. When the relevant series are substituted in equation x it

can be shown that an FM wave comprises of an infinite number of side frequencies on both sides of the carrier

frequency. The frequencies of these components are fc +fm, fc+2fm, fc+3fm, etc. The amplitudes of these

components depend on the modulation index. The amplitudes are negligible when the separation between the

carrier frequency and the side-band frequencies becomes sufficiently large. Therefore, in practice only a

limited number of side frequency pairs are present. Also, as in AM the information is carried by side-

frequency components. Hence the bandwidth needed for transmission or reception in case of FM is 2nfm

where n is the number of pairs of side frequencies. The total power in an FM wave remains constant and does

not depend on the depth of modulation.

Thus, analysis of FM wave shows that unlike the AM wave, which has two side frequencies for each

modulating frequency, it has an infinite number of side frequencies.

Generation of F.M. waves:-

The methods used for FM generation can be grouped into two types. They are

e = A sin (2 f0 t + mf .cos 2 fm t)

e = A sin(0t + mf cos mt) since = 2f

e = A sin(0t) cos(mf cos mt) + cos(0t) sin(mf cosmt)

The cos (mf cosmt) and sin(mf cos mt) terms have to be expanded into infinite trigonometric series involving sine and cosine terms of harmonics of m. When the relevant series are substituted in equation x it can be shown that an FM wave comprises of an infinite number of side frequencies on both sides of the carrier frequency. The frequencies of these components are fc + fm, fc + 2fm, fc + 3fm, etc. The amplitudes of these components

NOTES

Electronics-1


depend on the modulation index. The amplitudes are negligible when the separation between the carrier frequency and the side-band frequencies becomes sufficiently large. Therefore, in practice only a limited number of side frequency pairs are present. Also, as in AM the information is carried by sidefrequency components. Hence the bandwidth needed for transmission or reception in case of FM is 2nfm where n is the number of pairs of side frequencies. The total power in an FM wave remains constant and does not depend on the depth of modulation.

Thus, analysis of FM wave shows that unlike the AM wave, which has two side frequencies for each modulating frequency, it has an infinite number of side frequencies.

Generation of F.M. wavesThe methods used for FM generation can be grouped into two types. They are:

(i) Direct method (ii) Indirect method

Direct method: In this method, the carrier frequency is directly modulated or varies in accordance with the input modulating signal such as (a) reactance modulator and (b) varactor diode.

Indirect method: The modulating signal is first integrated and then allowed to phase modulate a carrier. It is called indirect method because phase modulator is used for frequency modulation.

Reactance Modulator: In frequency modulation, the frequency deviation must be made proportional to the amplitude of the modulating signal. In the earlier methods, it was done by varying capacitance or inductance in the oscillator tuned circuits. A more modern technique is to insert a reactance circuit across the tuned oscillator circuit. In general series RC and RL circuits are used as reactance circuits. Phase technique can be used for the determination whether the particular circuit acts as capacitive or inductive. A typical reactance modulator.



Direct method: In this method, the carrier frequency is directly modulated or varies in accordance with the

input modulating signal such as (a) reactance modulator and (b) varactor diode.

Indirect method: The modulating signal is first integrated and then allowed to phase modulate a carrier. It is

called indirect method because phase modulator is used for frequency modulation.

Reactance Modulator:- In frequency modulation, the frequency deviation must be made proportional to the

amplitude of the modulating signal. In the earlier methods, it was done by varying capacitance or inductance

in the oscillator tuned circuits. A more modern technique is to insert a reactance circuit across the tuned

oscillator circuit. In general series RC and RL circuits are used as reactance circuits. Phase technique can be

used for the determination whether the particular circuit acts as capacitive or inductive. Fig.7.2.2 shows a

typical reactance modulator.

Here RF oscillator is connected to produce carrier waves. The capacitance C is chosen so that its reactance

at the oscillator frequency is much greater than R2 in parallel with ‘R1’. Thus the current flowing through ‘C’

leads the voltage applied between C and ground by 900. The base current therefore leads the carrier voltage

by 900. The collector current is in phase with the base current and therefore in phase with the current which

passes through ‘C’. The total current is leading the carrier voltage by 900. Thus the entire circuit appears as a

capacitor.

The effective or equivalent capacitance of the reactance modulator is given by

Ceq =2ie

2fe

RhCRh

-------------- (1)

Carrierinput RFC - 1

VCC

RFC - 2

Modulatinginput

ModulatedOutputR1

R2RE CE

C

Fig 7.2.2 Transistor reactance FM ModulatorFig. 2.8. Transistor reactance FM Modulator

Here RF oscillator is connected to produce carrier waves. The capacitance C is chosen so that its reactance at the oscillator frequency is much greater than R2 in parallel with ‘R1’.

NOTES

Modulation


Thus the current flowing through ‘C’ leads the voltage applied between C and ground by 90°. The base current therefore leads the carrier voltage by 90°. The collector current is in phase with the base current and therefore in phase with the current which passes through ‘C’. The total current is leading the carrier voltage by 90°. Thus the entire circuit appears as a capacitor.




Direct method: In this method, the carrier frequency is directly modulated or varies in accordance with the

input modulating signal such as (a) reactance modulator and (b) varactor diode.

Indirect method: The modulating signal is first integrated and then allowed to phase modulate a carrier. It is

called indirect method because phase modulator is used for frequency modulation.

Reactance Modulator:- In frequency modulation, the frequency deviation must be made proportional to the

amplitude of the modulating signal. In the earlier methods, it was done by varying capacitance or inductance

in the oscillator tuned circuits. A more modern technique is to insert a reactance circuit across the tuned

oscillator circuit. In general series RC and RL circuits are used as reactance circuits. Phase technique can be

used for the determination whether the particular circuit acts as capacitive or inductive. Fig.7.2.2 shows a

typical reactance modulator.

Here RF oscillator is connected to produce carrier waves. The capacitance C is chosen so that its reactance

at the oscillator frequency is much greater than R2 in parallel with ‘R1’. Thus the current flowing through ‘C’

leads the voltage applied between C and ground by 900. The base current therefore leads the carrier voltage

by 900. The collector current is in phase with the base current and therefore in phase with the current which

passes through ‘C’. The total current is leading the carrier voltage by 900. Thus the entire circuit appears as a

capacitor.


Ceq =2ie

2fe

RhCRh

-------------- (1)

Carrierinput RFC - 1

VCC

RFC - 2

Modulatinginput

ModulatedOutputR1

R2RE CE

C

Fig 7.2.2 Transistor reactance FM Modulator

...(8)

The audio signal varies the operating point, which varies hfe of the transistor, and thus the equivalent capacitance of the transistor reactor modulator according to the eqn.(1). The effective capacitance C eq is controlled by hfe. Then the oscillator frequency across the tuned circuit


The audio signal varies the operating point, which varies hfe of the transistor, and thus the equivalent

capacitance of the transistor reactor modulator according to the eqn.(1). The effective capacitance C eq is

controlled by hfe. Then the oscillator frequency across the tuned circuit

f = CeqCL 21

------------ (2) where

L = Inductance and

C = capacitance

F.M. Detection:

We know that an F.M. signal contains information in the form of frequency variation of the carrier signal.

A simple method of converting frequency variations to voltage variations depends on the principle that

reactance of the inductor or capacitor varies with the frequency. Thus the amplitude of current in the inductor

or capacitor varies with the frequency of FM signal. As the frequency variations of FM signal depend on the

amplitude of the AF signal, the current variations in the inductor or capacitor correspond to the AF signal.

These amplitude variations in current, when made to flow through a resistor they will produce corresponding

voltage variations across the resistor.

There are various types of circuits used for FM demodulations. They are

Phase discriminator or frequency discriminator

Ratio detector and

Quadrature detector.

A circuit that gives an output voltage whose amplitude is proportional to the frequency of the input

signal can be used to decode or detect FM signals. Such circuits are called frequency discriminators.

Now, let us discuss in detail about the functioning of Foster-Seeley discriminator.

Foster - Seeley discriminator:

The phase shift between Primary and Secondary voltages of a tuned transformer is a function of frequency

and the Foster-Seeley discriminator utilizes this frequency phase dependence for the recovery of the

modulating signal. The following fig.7.2.3 shows the basic arrangement for the Foster-Seeley discriminator.

Ceq ...(2) where

L = Inductance and

C = capacitance

F.M. DetectionWe know that an F.M. signal contains information in the form of frequency variation of the carrier signal. A simple method of converting frequency variations to voltage variations depends on the principle that reactance of the inductor or capacitor varies with the frequency. Thus the amplitude of current in the inductor or capacitor varies with the frequency of FM signal. As the frequency variations of FM signal depend on the amplitude of the AF signal, the current variations in the inductor or capacitor correspond to the AF signal. These amplitude variations in current, when made to flow through a resistor they will produce corresponding voltage variations across the resistor.

There are various types of circuits used for FM demodulations. They are:

zz Phase discriminator or frequency discriminator

zz Ratio detector and

zz Quadrature detector.

A circuit that gives an output voltage whose amplitude is proportional to the frequency of the input signal can be used to decode or detect FM signals. Such circuits are called frequency discriminators.

Now, let us discuss in detail about the functioning of Foster-Seeley discriminator.

Foster – Seeley DiscriminatorThe phase shift between Primary and Secondary voltages of a tuned transformer is a function of frequency and the Foster-Seeley discriminator utilizes this frequency phase dependence

NOTES

Electronics-1


for the recovery of the modulating signal. The following fig.2.9 shows the basic arrangement for the Foster-Seeley discriminator.


The primary voltage is tightly coupled through capacitor ‘C3’ and the RFC to the center cap on the

secondary. The coupling is tight enough that practically all the primary voltage appears between the centre

top and ground.

SUMMARY OF SECTION – I

1. Amplitude modulation is a process of modulating a signal for efficient transmission. Carrier wave can be

filtered using the process of demodulation by rectifying the modulated signal.

2. Frequency modulated signal does not consist of noise as in A.M. signal.

3. Modulated Broadcasting signals are received by a radio receiver with the help of antenna and resonant

circuit. It is amplified, demodulated and fed to a speaker.

4. The important characteristics of a receiver are sensitivity, selectivity, fidelity, and noise figure.

C3 RFC

+

–

V0V121

V2

21

V2

+

–+

–

+

–

D1

D2

Fig 7.2.3(a) Basic Foster – Seeley Discriminator.

V1

D1

– +

V1

21

V2

21

V2

+–

+–

+

V01

–

+

V02

–

+

V0

–D2

Fig 7.2.3(b) Voltage generator equivalent circuit

~

~

~

Fig. 2.9/(a). Basic Foster – Seeley Discriminator.


The primary voltage is tightly coupled through capacitor ‘C3’ and the RFC to the center cap on the

secondary. The coupling is tight enough that practically all the primary voltage appears between the centre

top and ground.

SUMMARY OF SECTION – I

1. Amplitude modulation is a process of modulating a signal for efficient transmission. Carrier wave can be

filtered using the process of demodulation by rectifying the modulated signal.

2. Frequency modulated signal does not consist of noise as in A.M. signal.

3. Modulated Broadcasting signals are received by a radio receiver with the help of antenna and resonant

circuit. It is amplified, demodulated and fed to a speaker.

4. The important characteristics of a receiver are sensitivity, selectivity, fidelity, and noise figure.

C3 RFC

+

–

V0V121

V2

21

V2

+

–+

–

+

–

D1

D2

Fig 7.2.3(a) Basic Foster – Seeley Discriminator.

V1

D1

– +

V1

21

V2

21

V2

+–

+–

+

V01

–

+

V02

–

+

V0

–D2

Fig 7.2.3(b) Voltage generator equivalent circuit

~

~

~

Fig. 2.9(b). Voltage generator equivalent circuit

The primary voltage is tightly coupled through capacitor ‘C3’ and the RFC to the center cap on the secondary. The coupling is tight enough that practically all the primary voltage appears between the centre top and ground.

2.9 SUMMARYAmplitude modulation is a process of modulating a signal for efficient transmission. Carrier wave can be filtered using the process of demodulation by rectifying the modulated signal. 2. Frequency modulated signal does not consist of noise as in A.M. signal.

Modulated Broadcasting signals are received by a radio receiver with the help of antenna and resonant circuit. It is amplified, demodulated and fed to a speaker. The important characteristics of a receiver are sensitivity, selectivity, fidelity, and noise figure.

NOTES

Modulation


In frequency modulation the frequency of the carrier wave is modulated as a function of the instantaneous value of the modulating signal. Un like amplitude modulation there will be infinite number of sideband in the spectrum of F.M.wave. However, the bandwidth converges to 150kHz.

Several direct and indirect methods are available to produce FM waves. F.M waves are detected by using Foster-Seeley discriminator circuit.

2.10 KEYWORDSzz Modulation: Process of combining low frequency signal with a high frequency

radio wave (carrier wave).

zz Balanced modulator: A modulation circuit which cancels but the product term does not cancel

2.11 REVIEW QUESTIONS1. Draw the circuit diagram of amplitude modulator and explain its working.

2. Define modulation, define amplitude and frequency modulations and explains about them.

3. Explain how the Amplitude modulated waves are generated. Give the necessary diagrams.

4. With neat diagram and waveform, explain how the Amplitude modulated waves are detected.

5. Give the analysis of an AM wave. What are side bands? Explain Them.

6. Derive an expression for a Frequency modulated wave.

7. Discuss the principles involved in the production and detection of FM wave.

8. Give the block diagram of a super heterodyne receiver and explain the function of each block.

9. Explain a method for the generation of SSB modulation.

10. How can we detect an FM wave using Foster- Seeley discriminator? Explain with neat diagrams.

11. Discuss the need for modulation in radio and TV Transmissions.

12. What are sidebands produced in AM Wave. Explain them.

13. Distinguish between Amplitude and frequency modulation.

14. Write in detail about AM diode detector.

15. Explain the principle of super heterodyne reception.

16. Explain now a SSB modulated system can be detected.

NOTES

Electronics-1


2.12 FURTHER READINGSzz Operational Amplifiers and Linear Integrated Circuit Technology by Ramakanth

A. Gaykwad Prentice Hall Inc.,

zz Basic Electronics by DC Tayal, Himalaya Publish Co.,

zz Semi Conductor Electronics by A K. Sharma New Age International Publishers

zz Foundations of Electronics By D. Chattopadhyay, PC Rakshit, B. Saha, M.N. Purkait Second Edition, Wiley Eastern Ltd.,

zz Integrated Electronics By Millman & Halkias (MH)

NOTES

Digital Electronics


CHAPTER – 3

DIGITAL ELECTRONICSSTRUCTURE

3.1 Learning Objectives 3.2 Introduction 3.3 Boolean Algebra 3.4 Basic logic gates 3.5 De Morgan’s theorems 3.6 Universal logic gates 3.7 Binary addition 3.8 Half Adder 3.9 Full adder 3.10 Binary four bit parallel Adder 3.11 Decoder 3.12 Demultiplexer 3.13 Encoder 3.14 Multiplexers / Data selector 3.15 Flip-flop 3.16 S-R Latch3.17 Clocked R-S Flip – Flop 3.18 D Flip – Flop 3.19 11.5 J-K Flip – Flop 3.20 Master – Slave JK Flip – Flop (Solution to the Race-Around Problem) 3.21 Applications of JK Flip – Flop 3.22 Shift Register 3.23 Serial In – Serial out Shift Register: 3.24 Serial In, Parallel – out Shift Register 3.25 Parallel In, Serial – Out Shift Register 3.26 Parallel In, Parallel – out Shift Register 3.27 Bi-directional Shifter 3.28 Universal Shift Register 3.29 Counters 3.30 Asynchronous counters

Contd....

NOTES

Electronics-1


3.31 Synchronous Counters 3.32 Digital – to – Analog Converter [D/A] 3.33 Analog – to – Digital Converter 3.34 A/DConverterSpecifications 3.35 Sample & Hold Circuit 3.36 Summary 3.37 Keywords 3.38 Review questions 3.39 Further Readings


zz To understand the digital electronics

zz To learn Boolean algebra

zz To understand various basic logic gates

zz To understand De Morgan’s theorems

zz To know about universal gates

zz To understand binary addition

zz To understand the working of various combinational logic circuits like adders, decoders, demultiplexers, data selectors, multiplexers.

zz This lesson explains you the concept of

z (i) Flip – Flops

z (ii) Different types of Flip Flops

z (iii) Shift Registers

z (iv) Synchronous and asynchronous counters

zz This lesson gives an idea of

z (i) Digital to Analog converters

z (ii) Analog to Digital converters

zz After going through this lesson you will be in a position to explain

z (i) The working of weighted-Resistor type digital to Analog converter

z (ii) The working of successive approximation Analog – to – Digital Converter

z (iii) The sample and Hold Circuits.

NOTES

Digital Electronics


3.2 INTRODUCTIONThetermdigitalreferstoanyprocessthatisaccomplishedusingdiscreteunits,e.g.fingers,toes,digits etc. Each of these can be used as a unit or group of units to express a whole number. On the other-hand, analog numbers are represented as directly measurable quantities such as volts, distances, and rotations etc. Thus, in analog method, a number can be represented as an angle (in degrees) rotation of the needle on a meter. This method has been used widely in electronics to represent intensity, frequency, and time etc. The two factors namely accuracy and economy made the people to prefer digital readout devices. As examples we can quote: Digital multi-meters, Digital frequency counters, Screw gauges, Vernier calipers with digital readout facility.

Though there are many number systems, in digital electronics, binary system is used extensively. Good amount of accuracy and reliability that can be achieved with digital electronics. Because of this reason conventional electronic circuits are being replaced with digital circuits. Already we see present day communication is based on digital techniques. Digital electronics is also extensively used in computers.

In computers information and data are processed in terms of only zeros and ones (0 and 1) which are called binary digits. In binary system those are only two digits 0 and 1. The Binary digits are called Bits. The programmer feeds instructions and data in a form that looks like English. For example ADD for addition, SUB for subtraction etc. Later computer converts these instructions and data into binary digits before processing. Processing of data in computers is performed by digital circuits. Because the data in computers is in the form of 0’s and 1’s, a special logic is developed by George Boole to perform the arithmetic and logic operations. Hence the algebra developed for binary systems is known as Boolean algebra.

In a digital system, we will consider inputs and outputs, as either 0’s or 1’s. In order to express the input and output relationship, an algebra known as switching algebra is useful. Shannon developed this in 1938 for use in telecommunication switching circuits. It is based on a more general algebra that was developed earlier by Boole. This algebra uses a limited number of operators to connect variables together to form expressions. Further, it is also easy to build electronic circuits to implement these operators. Boolean Algebra is the algebra of binary variables. Any system, which has only two states, can be expressed in terms of Boolean logic. For example a statement can be either true or false, if it is true we can represent it as logic 1 and if is false we represent it by 0. This is called positive logic.

Existence of positive voltage at a point may be taken as logic 1. Zero voltage can be representedaslogiczero.Aglowingbulb,acurrentflow,ahappeningofanincidentcanberepresented by logic 1 or TRUE state. The complementary actions can be represented by a 0 or FALSE state. In fact we may represent actions that were represented by 1 by logic 0 also. It all depends on one’s choice. The electronic circuits used to perform Boolean operations are called gates. The gate is a circuit with one or more input signals but only one output signal. These gates are constructed by using diodes and transistors (known as DTL logic) or using transistors only (known as TTL) Technical standards were evolved in electronics depending

NOTES

Electronics-1


on the implementation of integrated circuits using various semiconductor technologies viz DTL,TTL,ECL etc. The most important and popular semiconductor logic is Transistor-Transistor Logic (TTL), in which a +5V DC is taken as logic 1 and zero volts is taken as logic 0 .

This chapter introduces the fundamentals of Boolean operations, corresponding logic circuits and gates and integrated circuits related to these circuits are discussed.

Basic logic gates are the building blocks of logic systems like digital computers. In digital computers arithmetical operations are performed using binary number system. Further any arithmetic operations like subtraction, multiplication and division can be expressed in the terms of binary addition. In this lesson we learn basic concepts of binary additions using logic gates. Varies logic gates are combined to generate a complex logical operation and if these circuits are made to work independent of time. Such circuits are called simply combinational logic circuits. If these logic circuits are made to work with time as a parameter these circuits are called sequential logic circuits. A general logic circuits may be combinational and sequential logic circuits. In this lesson learn about some combinational logic circuits.

Binary codes are used to specify instructions, addresses and coded data. One binary digit (bit) can stand for two codes 0 or 1. with two bits we can have four codes namely 00, 01, 10, 11. Similarly with n bits we can form 2n codes. Circuits, that generate these codes are called encoders. It become necessary not only the code information but also to decode the codes whenever necessary. Circuits with decode are called decoders.

Information coming on several channels may have to be rooted on a single channel this is called multiplexing and circuits with do this multiplexers. Multiplexer information coming on a single channel have to be separated and sent and varies channels and this is called demultiplexers. In this lesson we learn about these combinational logic circuits also.

The logic circuits whose present output depends on the past inputs are known as sequential logic circuits.

These circuits store and remember information. The sequential circuits unlike combinational circuits are time dependent. Normally the current output of a sequential circuit depends on the previous state of the circuit and on the current input to the circuit. It isaconnectionofflip-flopsandgates.Whatisaflip-flop?

Youwillfindtheanswerinthissection.Therecanbetwotypesofsequentialcircuits.

(i) Synchronous, (ii) Asynchronous

Synchronouscircuitsuseflip-flopsandtheirstatuscanchangeonlyatdiscreteinstants.The Asynchronous sequential circuits may be regarded as combinational circuits with feedback path. Since the propagation delays of output to input are small they may tend to become unstable at times.

The synchronization in sequential circuits can be achieved using a clock pulse generators. A clock synchronizes the effect of input over output. It presents a signal of the following form:

NOTES

Digital Electronics


M. Sc. Physics 2 Sequential Logic Circuits

INTRODUCTION:

The logic circuits whose present output depends on the past inputs are known as sequential logic circuits.

These circuits store and remember information. The sequential circuits unlike combinational circuits are

time dependent. Normally the current output of a sequential circuit depends on the previous state of the

circuit and on the current input to the circuit. It is a connection of flip-flops and gates. What is a flip-flop?

You will find the answer in this section. There can be two types of sequential circuits.

Synchronous

Asynchronous

Synchronous circuits use flip-flops and their status can change only at discrete instants. The

Asynchronous sequential circuits may be regarded as combinational circuits with feedback path. Since the

propagation delays of output to input are small they may tend to become unstable at times.

The synchronization in sequential circuits can be achieved using a clock pulse generators. A clock

synchronizes the effect of input over output. It presents a signal of the following form:

The signal produced by clock generator is in the form of clock pulse or clock signal. These clock pulses

are distributed throughout the computer system for synchronization.

A clock can have two states, an enable or active state, otherwise a disable or inactive state. Both of these

states can be related to zero or one levels of clock signals. Normally, the flip-flops change their state only at

the active state of the clock pulse. In certain designs the active state of the clock is triggered, when

transition from 0 to 1 or 1 to 0 is taking place in clock signal.

11.1 Flip-flop

A flip-flop is a binary cell, which can store a bit of information. It itself is a sequential circuit. A flip-

flop maintains any one of the two stable states that can be treated as 1 or 0 depending on the presence or

absence of output signal. The state of flip-flop can only change when clock pulse has arrived. Let us first

see the basic flip – flop or a latch .

CLOCK CYCLE

Fig 11.1 Clock signal of a Clock Pulse Generator

Rising edge falling edge

Fig. 3.1. Clock signal of a Clock Pulse Generator

The signal produced by clock generator is in the form of clock pulse or clock signal. These clock pulses are distributed throughout the computer system for synchronization.

A clock can have two states, an enable or active state, otherwise a disable or inactive state. Both of these states can be related to zero or one levels of clock signals. Normally, theflip-flopschangetheirstateonlyattheactivestateoftheclockpulse.Incertaindesignsthe active state of the clock is triggered, when transition from 0 to 1 or 1 to 0 is taking place in clock signal.

The physical quantities such as voltage, current, temperature, pressure and time etc., areavailableinanalogform.Itisdifficulttoprocess,storeortransmittheanalogsignal,even though, an analog signal represents a real physical parameter with accuracy. Therefore, for processing transmission and storage purposes, it is often convenient to express these variables in digital form. It gives better accuracy and reduces noise. The operation of any digital communication system is based upon analog signals to digital (A/D) and digital to analog (D/A) conversion.

Fig. 3.2 highlights a typical application within which A/D and D/A conversion is used. This is used either in full or in part in applications such as digital audio recording and play back, computer, music and video synthesis, data acquisition, digital signal processing, microprocessor based instrumentation. Both A/D and D/A conversions are also known as dataconverters.WeshallfirstdiscussD/AfollowedbyA/D,becauseA/Dconversionusuallymakes use of a D/A conversion.

M.Sc. Physics 2 D/A and A/D Converters

12.1 Introduction:-

The physical quantities such as voltage, current, temperature, pressure and time etc., are

available in analog form. It is difficult to process, store or transmit the analog signal, even though,

an analog signal represents a real physical parameter with accuracy. Therefore, for processing

transmission and storage purposes, it is often convenient to express these variables in digital form.

It gives better accuracy and reduces noise. The operation of any digital communication system is

based upon analog signals to digital (A/D) and digital to analog (D/A) conversion.

Fig 12.1 highlights a typical application within which A/D and D/A conversion is used. This is

used either in full or in part in applications such as digital audio recording and play back, computer,

music and video synthesis, data acquisition, digital signal processing, microprocessor based

instrumentation. Both A/D and D/A conversions are also known as data converters. We shall first

discuss D/A followed by A/D, because A/D conversion usually makes use of a D/A conversion.

12.2 Digital – to – Analog Converter [D/A] :

The Digital to Analog converter accepts data in digital form and converts it to a voltage or current which

is proportional to the digital value.

The black diagram of a n-bit D/A converter is shown in fig 12.2. It has n-logic inputs and a single analog

output, whose value varies discretely in response to the 2n possible input bit patterns. The internal circuit

can be all electronically switched ladder network.

Normally two types of networks are used:

i) Weighted resistor network ii) R – 2R ladder network.

Sensor ortransducer

Antialiasingfilter

Sample andhold

Analog todigital

converter

PLANTComputeror digital

signalprocessor

Analogsignal

Bandlimitedanalogsignal

Discreteanalog

Discretedigital

Analog signal Staircase signal Digital binary signalSmoothing

filterD/A

converter

Fig 12.1 Applications of A/D and D/A converter.Fig. 3.2. Applications of A/D and D/A converter

NOTES

Electronics-1


3.3 BOOLEAN ALGEBRAThe fundamental operations in Boolean algebra are OR, AND and NOT, with symbols + (plus),. (dot) and bubble or bar over Boolean variable respectively.

In real life applications, one combined several logic gates and the combined effect determines a system behavior depending on the states of individual logic variables. This is usually expressed in terms of a truth table. In truth table, various inputs are listed and various combinations are worked out to determine the system behavior. As a simple example, see the OR gate truth table given in table 3.3a. Here A and B are the input variables. These two variables can have 22 = 4 combinations of 1s and 0s. As per the Boolean equation y = A + B (A + B to be red as A or B), output is true for 3 input combinations and false for one combination.

The following are the laws of Boolean algebra and complicated laws can be proved using simpleBooleanlaws.TheselawscanbeverifiedbywritingtruthtablesforL.H.SandR.H.Sexpressions.


In real life applications, one combined several logic gates and the combined effect determines a system

behavior depending on the states of individual logic variables. This is usually expressed in terms of a truth

table. In truth table, various inputs are listed and various combinations are worked out to determine the system

behavior. As a simple example, see the OR gate truth table given in table 9.3a. Here A and B are the input

variables. These two variables can have 22=4 combinations of 1s and 0s. As per the Boolean equation y = A +

B (A+B to be red as A or B), output is true for 3 input combinations and false for one combination.

The following are the laws of Boolean algebra and complicated laws can be proved using simple Boolean

laws. These laws can be verified by writing truth tables for L.H.S and R.H.S expressions.

1. A + 0 = A

2. A + 1 = 1 Laws of ‘OR’

3. A + A = A

4. A + A = 1

5. A . 0 = 0

6. A . 1 = A Laws of ‘AND’

7. A . A = A

8. A . A = 0

9. 0 = 1

10. 1 = 0

11. of A = 0 then A = 1 Laws of complementation (NOT Laws)

12. of A = 1 then A = 0

13. A = A

14. A + B = B + A Commutative Laws

15. A . B = B . A

16. A + (B + C) = (A + B) + C Associative Laws

17. A .(B . C) = (A . B) . C

18. A . (B + C) = (A + B) . C Distributive Laws

19. A + B . C = (A + B).(A + C)

20. A + A B = A + B

21. A + AB = A

22. A (A + B) = A

NOTES

Digital Electronics


M. Sc Physics 4 Digital Electronics

23. A ( A + B) = AB

24. AB + A B = A

25. (A + B) (A + B ) = A

26. AB + A C = (A + C) ( A + B)

27. (A + B) ( A + C) = AC + A B

28. AB + A C + BC = AB + A C

29. (A + B) ( A + C) . (B + C) = (A + B) ( A + C)

30. --CBA = A . B . C . ---- De Morgan’s Laws

31. --.C.B.A = A + B + C + ----

9.3 Basic logic gates:

Basically, a logic gate is a circuit with one or more logic input signals (each input is either 0 or 1), but with

only one output signal (logically related to inputs). Logic circuits are analyzed with the help of Boolean laws.

The basic logic gates are: OR, AND and NOT

9.3.1 OR Gate:

An OR gate has two or more input signals but only one output signal. If one or more input signals are high,

the output signal is high.

Boolean expression for two input OR gate is Y = A + B

(read as Y equals A OR B).

The circuit to implement the OR function, logic symbol and its truth table(which depicts the output condition

to given input is shown in fig 9.3(a).

Any one or both of the inputs A,B are high (+5V) makes the corresponding diode to forward bias and the

current flows through load resistor RL to have an output at Y.

A

B

D1

D2 RL

Y

Circuit of OR gate

3.4 BASIC LOGIC GATES

Basically, a logic gate is a circuit with one or more logic input signals (each input is either 0 or 1), but with only one output signal (logically related to inputs). Logic circuits are analyzed with the help of Boolean laws.


OR Gate

An OR gate has two or more input signals but only one output signal. If one or more input signals are high, the output signal is high.

Boolean expression for two input OR gate is Y = A + B (read as Y equals A OR B).

The circuit to implement the OR function, logic symbol and its truth table(which depicts the output condition to given input is shown in Fig. 3.3(a).

Any one or both of the inputs A,B are high (+5V) makes the corresponding diode to forwardbiasandthecurrentflowsthroughloadresistorRLtohaveanoutputatY.


23. A ( A + B) = AB

24. AB + A B = A

25. (A + B) (A + B ) = A

26. AB + A C = (A + C) ( A + B)

27. (A + B) ( A + C) = AC + A B

28. AB + A C + BC = AB + A C

29. (A + B) ( A + C) . (B + C) = (A + B) ( A + C)

30. --CBA = A . B . C . ---- De Morgan’s Laws

31. --.C.B.A = A + B + C + ----

9.3 Basic logic gates:

Basically, a logic gate is a circuit with one or more logic input signals (each input is either 0 or 1), but with

only one output signal (logically related to inputs). Logic circuits are analyzed with the help of Boolean laws.


9.3.1 OR Gate:

An OR gate has two or more input signals but only one output signal. If one or more input signals are high,

the output signal is high.

Boolean expression for two input OR gate is Y = A + B

(read as Y equals A OR B).

The circuit to implement the OR function, logic symbol and its truth table(which depicts the output condition

to given input is shown in fig 9.3(a).

Any one or both of the inputs A,B are high (+5V) makes the corresponding diode to forward bias and the

current flows through load resistor RL to have an output at Y.

A

B

D1

D2 RL

Y

Circuit of OR gate

NOTES

Electronics-1



An OR gate can have any number of inputs 1 to n. For example two input OR-gates can be used to form a 3

input OR gate as shown in fig 9.3(b)

.

Fig 3b: Two two input OR gates connected to form a 3 input OR gate.

The OR gate circuit of Fig 9.3(a) constructed by using diodes and resistors . But the same OR gate can also be

constructed by using transistors only (TTL circuit). The logic gates are available in the form of integrated

circuits(ICs) to offer advantages in terms of size, cost and power. The

IC 7432 is a quad (four), two input OR gate using TTL logic and 74LS32 and 74HS32 are the low power

and high speed versions of the same OR gate.

9.3.2 AND gate:

The AND gate has two or more inputs but has only one output. If all the inputs are simultaneously high,

the output is high. Boolean expression for two input AND gate is

Y = A . B (read as Y equals A AND B). The circuit to implement AND function, corresponding logic

diagram and its truth table is shown in Fig 9.3(c).

C

A

B

=ABC

Y = A+ B + C

Input Output

A B Y0

0

1

1

0

1

0

1

0

1

1

1

TURTH TABLE

A

BY

INPUT1

INPUT2

OUTPUT

Logic Symbol of OR gate

Fig 9.3(a)

Fig. 3.3(a)

An OR gate can have any number of inputs 1 to n. For example two input OR-gates

can be used to form a 3 input OR gate as shown in Fig. 3.3(b)


An OR gate can have any number of inputs 1 to n. For example two input OR-gates can be used to form a 3

input OR gate as shown in fig 9.3(b)

.

Fig 3b: Two two input OR gates connected to form a 3 input OR gate.

The OR gate circuit of Fig 9.3(a) constructed by using diodes and resistors . But the same OR gate can also be

constructed by using transistors only (TTL circuit). The logic gates are available in the form of integrated

circuits(ICs) to offer advantages in terms of size, cost and power. The

IC 7432 is a quad (four), two input OR gate using TTL logic and 74LS32 and 74HS32 are the low power

and high speed versions of the same OR gate.

9.3.2 AND gate:

The AND gate has two or more inputs but has only one output. If all the inputs are simultaneously high,

the output is high. Boolean expression for two input AND gate is

Y = A . B (read as Y equals A AND B). The circuit to implement AND function, corresponding logic

diagram and its truth table is shown in Fig 9.3(c).

C

A

B

=ABC

Y = A+ B + C

Input Output

A B Y0

0

1

1

0

1

0

1

0

1

1

1

TURTH TABLE

A

BY

INPUT1

INPUT2

OUTPUT

Logic Symbol of OR gate

Fig 9.3(a)

Fig. 3b: Two two input OR gates connected to form a 3 input OR gate.

The OR gate circuit of Fig. 3.3(a) constructed by using diodes and resistors . But the

same OR gate can also be constructed by using transistors only (TTL circuit). The logic gates

are available in the form of integrated circuits(ICs) to offer advantages in terms of size, cost

and power. The IC 7432 is a quad (four), two input OR gate using TTL logic and 74LS32

and 74HS32 are the low power and high speed versions of the same OR gate.

aND Gate:The AND gate has two or more inputs but has only one output. If all the inputs are

simultaneously high, the output is high. Boolean expression for two input AND gate is

Y = A . B (read as Y equals A AND B). The circuit to implement AND function, corresponding

logic diagram and its truth table is shown in Fig. 3.3(c).

Whenanyoneorbothoftheinputsinabovecircuitarelow,thediodeofthatinput

becomes forward biased, so the level of voltage at output point Y is at 0V i.e low state. On

the other hand, if both Aand B are high, both diodes are now in reverse biased having same

voltages at both ends. So 5V now appears at Y, i.e high state.

NOTES

Digital Electronics



When any one or both of the inputs in above circuit are low, the diode of that input becomes forward biased,

so the level of voltage at output point Y is at 0V i.e low state. On the other hand, if both A and B are high,

both diodes are now in reverse biased having same voltages at both ends. So 5V now appears at Y, i.e high

state.

As in the case of OR gate, the two input AND gates can be used to construct three input or n-input AND gate.

Construction of 3-input AND gate by using two 2-input AND gates is shown in Fig 9.3(d).

IC 7408 / 74LS08 is a Quad two input AND gate whereas IC 7411 is a triple 3 input AND gate IC.

9.3.3 NOT gate: (Inverter gate):

The inverter is a gate with only one input and one output. The output state is always the opposite of the

input state. It is also called as NOT gate. Boolean expression for this gate is Y = A (read as Y equals

complement of A or Y equals NOT of A). The circuit, logic symbol and its truth table is shown in Fig 9.3(e).

Input Output

A B Y0

0

1

1

0

1

0

1

0

0

0

1

TURTH TABLE

A

B Y

INPUT1

INPUT2

OUTPUT

Logic Symbol of AND gateFig 9.3(c)

D1

D2

RL

A

B

Y

Circuit of AND gate

+5V

Y= A.B.CAB

Y C C

BA

Fig 9.3(d)

Fig. 3.3(c)

As in the case of OR gate, the two input AND gates can be used to construct three

input or n-input AND gate. Construction of 3-input AND gate by using two 2-input AND

gates is shown in Fig. 3.3(d).


When any one or both of the inputs in above circuit are low, the diode of that input becomes forward biased,

so the level of voltage at output point Y is at 0V i.e low state. On the other hand, if both A and B are high,

both diodes are now in reverse biased having same voltages at both ends. So 5V now appears at Y, i.e high

state.

As in the case of OR gate, the two input AND gates can be used to construct three input or n-input AND gate.

Construction of 3-input AND gate by using two 2-input AND gates is shown in Fig 9.3(d).

IC 7408 / 74LS08 is a Quad two input AND gate whereas IC 7411 is a triple 3 input AND gate IC.

9.3.3 NOT gate: (Inverter gate):

The inverter is a gate with only one input and one output. The output state is always the opposite of the

input state. It is also called as NOT gate. Boolean expression for this gate is Y = A (read as Y equals

complement of A or Y equals NOT of A). The circuit, logic symbol and its truth table is shown in Fig 9.3(e).

Input Output

A B Y0

0

1

1

0

1

0

1

0

0

0

1

TURTH TABLE

A

B Y

INPUT1

INPUT2

OUTPUT

Logic Symbol of AND gateFig 9.3(c)

D1

D2

RL

A

B

Y

Circuit of AND gate

+5V

Y= A.B.CAB

Y C C

BA

Fig 9.3(d)

Fig. 3.3(d)

IC 7408 / 74LS08 is a Quad two input AND gate whereas IC 7411 is a triple 3 input

AND gate IC.

NOt Gate: (INveRteR Gate)The inverter is a gate with only one input and one output. The output state is always the

opposite of the input state. It is also called as NOT gate. Boolean expression for this gate is

Y = A (read as Y equals complement of A or Y equals NOT of A). The circuit, logic symbol

and its truth table is shown in Fig. 3.3(e).

NOTES

Electronics-1



In the above circuit, the transistor is working either in the conduction or cut-off state. When a high state(+5V)

is presented in input make to conduct transistor to produce 0V or low state at output. On the other hand, a low

state at input A produces a high state at output Y by cut-off the transistor T. Input given to Two NOT gates

connected in cascade results in the original Boolean variable as shown in fig 9.3(f). This is called as a buffer.

Electronically buffers are very useful as they do not alter the nature of original signal but provide boosting of

signal amplitude and power to standard levels. This prevents logic failure due to fall in signal strength. Tri-

state buffers are also available whose output can be 0 or 1 or tri-state. In the tri-state condition the signal path

is disconnected. These tri-state buffers are used in advanced logic circuits like Microprocessors and memories.

9.3.4 NOR gate:

The basic logic circuits are used to construct some more gates to perform more Boolean

functions. For example, consider the NOR gate which has two or more inputs but only one output.

All the inputs must be low to get a high output. Boolean expression for two input NOR gate is

Y = BA .(read as Y equals not of A OR B).

The NOR gate can be constructed by connecting an OR gate with NOT gate as shown in Fig 9.3(g)

InputA

OutputY

0

1

0

1

TRUTH TABLE

Fig 9.3(f) Two NOT gates connected to form a buffer,logic symbol of buffer and truth table

A A =Y =A

A

InputA

OutputY

0

1

1

0

TRUTH TABLE

+5V

TY

RL

R1A

A AY=

Fig 9.3(e)

Fig. 3.3(e)

In the above circuit, the transistor is working either in the conduction or cut-off state. Whenahighstate(+5V)ispresentedininputmaketoconducttransistortoproduce0Vorlow state at output. On the other hand, a low state at input A produces a high state at output Y by cut-off the transistor T. Input given to Two NOT gates connected in cascade results in the original Boolean variable as shown in Fig. 3.3(f). This is called as a buffer.


In the above circuit, the transistor is working either in the conduction or cut-off state. When a high state(+5V)

is presented in input make to conduct transistor to produce 0V or low state at output. On the other hand, a low

state at input A produces a high state at output Y by cut-off the transistor T. Input given to Two NOT gates

connected in cascade results in the original Boolean variable as shown in fig 9.3(f). This is called as a buffer.

Electronically buffers are very useful as they do not alter the nature of original signal but provide boosting of

signal amplitude and power to standard levels. This prevents logic failure due to fall in signal strength. Tri-

state buffers are also available whose output can be 0 or 1 or tri-state. In the tri-state condition the signal path

is disconnected. These tri-state buffers are used in advanced logic circuits like Microprocessors and memories.

9.3.4 NOR gate:

The basic logic circuits are used to construct some more gates to perform more Boolean

functions. For example, consider the NOR gate which has two or more inputs but only one output.

All the inputs must be low to get a high output. Boolean expression for two input NOR gate is

Y = BA .(read as Y equals not of A OR B).

The NOR gate can be constructed by connecting an OR gate with NOT gate as shown in Fig 9.3(g)

InputA

OutputY

0

1

0

1

TRUTH TABLE

Fig 9.3(f) Two NOT gates connected to form a buffer,logic symbol of buffer and truth table

A A =Y =A

A

InputA

OutputY

0

1

1

0

TRUTH TABLE

+5V

TY

RL

R1A

A AY=

Fig 9.3(e)

Fig. 3.3(f) Two NOT gates connected to form a buffer, logic symbol of buffer and truth table

Electronically buffers are very useful as they do not alter the nature of original signal but provide boosting of signal amplitude and power to standard levels. This prevents logic failure due to fall in signal strength. Tristate buffers are also available whose output can be 0 or 1 or tri-state. In the tri-state condition the signal path is disconnected. These tri-state buffers are used in advanced logic circuits like Microprocessors and memories.

NOR Gate

The basic logic circuits are used to construct some more gates to perform more Boolean functions. For example, consider the NOR gate which has two or more inputs but only one output. All the inputs must be low to get a high output. Boolean expression for two input NOR gate is Y = A + B .(read as Y equals not of A OR B).

The NOR gate can be constructed by connecting an OR gate with NOT gate as shown in Fig. 3.3(g)

NOTES

Digital Electronics



The NOR gate may have more than two inputs. Regardless of how many inputs a NOR gate has, it is still

logically equivalent to one OR gate followed by an inverter. For instance, the equation for 3-input NOR gate

is Y= CBA . The 7402 is a quad 2-input NOR gate where as 7427 is a triple 3-input NOR gate.

9.3.5 NAND gate:

A NAND gate has two or more inputs but only one output. All the input are the simultaneously high to get

a low output. Boolean expression for two – input NAND gate is

Y = B.A (read as Y equals Not of A AND B).

Input Output

A B Y0

0

1

1

0

1

0

1

1

0

0

0

TRUTH TABLE

Out putY

INPUT1

A

BINPUT2 Bubble

Fig 9.3(g)

YA

B

Input Output

A B Y0

0

1

1

0

1

0

1

1

1

1

0

TRUTH TABLE

OUTPUTA

BY

INPUT1

INPUT2

Logic Symbol of NAND gate

Fig 9.3(h)

BubbleAB

Y

The NOR gate may have more than two inputs. Regardless of how many inputs a NOR gate has, it is still logically equivalent to one OR gate followed by an inverter. For instance, the equation for 3-input NOR gate is Y= A + B + C. The 7402 is a quad 2-input NOR gate where as 7427 is a triple 3-input NOR gate.

NaND Gate

A NAND gate has two or more inputs but only one output. All the input are the simultaneously high to get a low output. Boolean expression for two – input NAND gate is

Y = A.B (read as Y equals Not of A AND B).


The NOR gate may have more than two inputs. Regardless of how many inputs a NOR gate has, it is still

logically equivalent to one OR gate followed by an inverter. For instance, the equation for 3-input NOR gate

is Y= CBA . The 7402 is a quad 2-input NOR gate where as 7427 is a triple 3-input NOR gate.

9.3.5 NAND gate:

A NAND gate has two or more inputs but only one output. All the input are the simultaneously high to get

a low output. Boolean expression for two – input NAND gate is

Y = B.A (read as Y equals Not of A AND B).

Input Output

A B Y0

0

1

1

0

1

0

1

1

0

0

0

TRUTH TABLE

Out putY

INPUT1

A

BINPUT2 Bubble

Fig 9.3(g)

YA

B

Input Output

A B Y0

0

1

1

0

1

0

1

1

1

1

0

TRUTH TABLE

OUTPUTA

BY

INPUT1

INPUT2

Logic Symbol of NAND gate

Fig 9.3(h)

BubbleAB

Y

The Boolean equations for 3-input and 4-input NAND gates are Y = ABC and Y = ABCD respectively.

The IC 7400 have 4 Nos of 2- input NAND gates, whereas 7410 have three numbers of 3-input NAND gates.

NOTES

Electronics-1


eX – OR Gate

An OR gate recognizes words with one or more 1s, whereas the exclusive – OR gate recognizes only words that have an odd number of 1s. Boolean expression for two – input EX-OR gate is Y = A B + A B = A B. (read as Y equals A EX-OR B). The logic diagram, symbol and its truth table is shown in Fig. 3.3(i).


The Boolean equations for 3-input and 4-input NAND gates are Y = ABC

and Y = ABCD respectively.


9.3.6 EX – OR gate:

An OR gate recognizes words with one or more 1s, whereas the exclusive – OR gate recognizes only words

that have an odd number of 1s. Boolean expression for two – input

EX-OR gate is Y = A B + A B = A B. (read as Y equals A EX-OR B). The logic diagram, symbol and its

truth table is shown in Fig 9.3(i).

When both inputs A & B in the above circuit are high or low both AND gates have low outputs to have the

final output zero. But when any one of the input(A or B) is high, the corresponding AND gate output is high.

So the final output is one as shown in truth table. IC 7486 is the IC version of

EX – OR gate.

9.4 De Morgan’s theorems:

The Boolean algebra developed by George Boole was further extended by De Morgan by his famous theorems

that can be used in the simplification of logic circuits.

9.4.1 De Morgan’s First Theorem:

BA = B.A

+

Input Output

A B Y0

0

1

1

0

1

0

1

0

1

1

0

TRUTH TABLE

A

B Y

INPUT1

INPUT2

OUTPUT

Logic Symbol of EX-ORgate

Fig 9.3(i)

Y

A

B


The Boolean equations for 3-input and 4-input NAND gates are Y = ABC

and Y = ABCD respectively.


9.3.6 EX – OR gate:

An OR gate recognizes words with one or more 1s, whereas the exclusive – OR gate recognizes only words

that have an odd number of 1s. Boolean expression for two – input

EX-OR gate is Y = A B + A B = A B. (read as Y equals A EX-OR B). The logic diagram, symbol and its

truth table is shown in Fig 9.3(i).

When both inputs A & B in the above circuit are high or low both AND gates have low outputs to have the

final output zero. But when any one of the input(A or B) is high, the corresponding AND gate output is high.

So the final output is one as shown in truth table. IC 7486 is the IC version of

EX – OR gate.

9.4 De Morgan’s theorems:

The Boolean algebra developed by George Boole was further extended by De Morgan by his famous theorems

that can be used in the simplification of logic circuits.

9.4.1 De Morgan’s First Theorem:

BA = B.A

+

Input Output

A B Y0

0

1

1

0

1

0

1

0

1

1

0

TRUTH TABLE

A

B Y

INPUT1

INPUT2

OUTPUT

Logic Symbol of EX-ORgate

Fig 9.3(i)

Y

A

B

Fig. 3.3(i)

WhenbothinputsA&BintheabovecircuitarehighorlowbothANDgateshavelowoutputstohavethefinaloutputzero.Butwhenanyoneoftheinput(AorB)ishigh,thecorresponding AND gate output is high.

Sothefinaloutputisoneasshownintruthtable.IC7486istheICversionofEX–OR gate.

3.5 DE MORGAN’S THEOREMSThe Boolean algebra developed by George Boole was further extended by De Morgan by hisfamoustheoremsthatcanbeusedinthesimplificationoflogiccircuits.

De MORGaN’s FIRst theOReM

A + B = A. B

Statement: Complement of sum equals the product of the complements.Proof: The theorem can be proved by taking expressions and writing the truth tables

on both sides.AndfinallyweequateLHStoRHS.

Consider L.H.S i.e A + B It indicates a 2-input OR gate followed by a NOT gate that is a NOR gate as shown in Fig. 3.4(a). Fig. 3.4(a) also shows its truth table. Similarly take the R.H.S of the theorem which is equal to A. B. This equation indicates that the two inputs A and B are inverted before they reach the AND gate as shown in Fig. 3.4(b). Therefore we

NOTES

Digital Electronics


have the truth table as in Fig. 3.4(b) for this circuit. Therefore the comparison of the truth table of Fig. 3.4(a) with the truth table of Fig3.4(b) reveals that these two are equivalent; the circuits of Fig. 3.4(a) and Fig. 3.4(b) are equivalent. Hence the theorem is proved.


Statement: Complement of sum equals the product of the complements.

Proof: The theorem can be proved by taking expressions and writing the truth tables on both sides.

And finally we equate LHS to RHS.

Consider L.H.S i.e BA . It indicates a 2-input OR gate followed by a NOT gate that is a NOR

gate as shown in Fig9.4(a). Fig 9.4(a) also shows its truth table. Similarly take the R.H.S of the

theorem which is equal to B.A . This equation indicates that the two inputs A and B are inverted

before they reach the AND gate as shown in Fig 9.4(b). Therefore we have the truth table as in

Fig 9.4(b) for this circuit. Therefore the comparison of the truth table of Fig 9.4(a) with the truth

table of Fig9.4(b) reveals that these two are equivalent; the circuits of Fig 9.4(a) and Fig 9.4(b)

are equivalent. Hence the theorem is proved.

R.H.S = A . B

NOR gate

AB

Y = BA =

Fig 9.4(a)

A B

0

0

1

1

0

1

0

1

0

1

1

1

A+BA+B

1

0

0

0

A B

0

0

1

1

0

1

0

1

1

1

0

0

1

0

1

0

A B A . B

1

0

0

0

Bubbled AND gate

Y = A . B =AB

A

B

Fig 9.4(b)

Fig. 3.4(a)












R.H.S = A . B

NOR gate

AB

Y = BA =

Fig 9.4(a)

A B

0

0

1

1

0

1

0

1

0

1

1

1

A+BA+B

1

0

0

0

A B

0

0

1

1

0

1

0

1

1

1

0

0

1

0

1

0

A B A . B

1

0

0

0

Bubbled AND gate

Y = A . B =AB

A

B

Fig 9.4(b)

R.H.S = A.B












R.H.S = A . B

NOR gate

AB

Y = BA =

Fig 9.4(a)

A B

0

0

1

1

0

1

0

1

0

1

1

1

A+BA+B

1

0

0

0

A B

0

0

1

1

0

1

0

1

1

1

0

0

1

0

1

0

A B A . B

1

0

0

0

Bubbled AND gate

Y = A . B =AB

A

B

Fig 9.4(b)Fig. 3.4(a)












R.H.S = A . B

NOR gate

AB

Y = BA =

Fig 9.4(a)

A B

0

0

1

1

0

1

0

1

0

1

1

1

A+BA+B

1

0

0

0

A B

0

0

1

1

0

1

0

1

1

1

0

0

1

0

1

0

A B A . B

1

0

0

0

Bubbled AND gate

Y = A . B =AB

A

B

Fig 9.4(b)

De MORGaN’s secOND theOReM

A + B = A + B

Statement: Complement of product equals the sum of the complements.

Proof: Left hand side of the theorem shown is a 2-input AND gate followed by a NOT gate i.e. a NAND gate having the circuit and truth table as shown in Fig. 3.4(c).


9.4.2 De Morgan’s Second Theorem

B.A = A + B


Proof: Left hand side of the theorem shown is a 2-input AND gate followed by a NOT gate i.e. a

NAND gate having the circuit and truth table as shown in Fig 9.4(c).

The right hand side of the equation shows an OR gate with two inverted inputs. The circuit and truth table

is shown in Fig 9.4(d).

A B A . B A . B

0

0

1

1

0

0

0

1

1

1

1

0

0

1

0

1

Fig 9.4(c)

Y = A . B =

NAND gateA . BA

B

Y = A + BA

B

A

B

(Bubbled OR gate)

Fig 9.4(d)

A B

0

0

1

1

1

0

1

0

1

1

1

0

0

1

0

1

A B A + B

1

1

0

0

Fig. 3.4(c)

NOTES

Electronics-1




B.A = A + B






A B A . B A . B

0

0

1

1

0

0

0

1

1

1

1

0

0

1

0

1

Fig 9.4(c)

Y = A . B =

NAND gateA . BA

B

Y = A + BA

B

A

B

(Bubbled OR gate)

Fig 9.4(d)

A B

0

0

1

1

1

0

1

0

1

1

1

0

0

1

0

1

A B A + B

1

1

0

0

The right hand side of the equation shows an OR gate with two inverted inputs. The circuit and truth table is shown in Fig. 3.4(d).



B.A = A + B






A B A . B A . B

0

0

1

1

0

0

0

1

1

1

1

0

0

1

0

1

Fig 9.4(c)

Y = A . B =

NAND gateA . BA

B

Y = A + BA

B

A

B

(Bubbled OR gate)

Fig 9.4(d)

A B

0

0

1

1

1

0

1

0

1

1

1

0

0

1

0

1

A B A + B

1

1

0

0

Fig. 3.4(d)



B.A = A + B






A B A . B A . B

0

0

1

1

0

0

0

1

1

1

1

0

0

1

0

1

Fig 9.4(c)

Y = A . B =

NAND gateA . BA

B

Y = A + BA

B

A

B

(Bubbled OR gate)

Fig 9.4(d)

A B

0

0

1

1

1

0

1

0

1

1

1

0

0

1

0

1

A B A + B

1

1

0

0

Comparison of these two truth tables reveals that they too are identical and equal. Therefore the theorem is proved.

3.6 UNIVERSAL LOGIC GATESThe logic gates NAND and NOR are called Universal Building Blocks or Universal Logic Gates because using either NAND or NOR gates we can construct other logic gates (AND, OR, NOT, EX-OR) as well as we can implement Boolean functions.

FORMING OtheR LOGIc Gates usING ONLy NaND Gates

(i) NOT gate: From the truth table of the NAND gate given in Fig. 3.3(h), we know that the same inputs of the NAND gives its complement output viz if A= B= 0 we have an output of 1 and if A= B= 1, the output is 0. Hence the circuit of Fig. 3.5(a) acts as NOT gate.


Comparison of these two truth tables reveals that they too are identical and equal. Therefore the theorem is

proved.

9.5 Universal logic gates:

The logic gates NAND and NOR are called Universal Building Blocks or Universal Logic Gates because

using either NAND or NOR gates we can construct other logic gates (AND, OR, NOT, EX-OR) as well as we

can implement Boolean functions.

1

9.5.1 Forming other logic gates using only NAND gates:

(i) NOT gate: From the truth table of the NAND gate given in Fig 9.3(h), we know that the same inputs of

the NAND gives its complement output viz if A= B= 0 we have an output of 1 and if A= B= 1, the output is

0. Hence the circuit of Fig 9.5(a) acts as NOT gate.

ii) AND gate: The Boolean expression for NAND is Y= B.A . So, the first NAND gate output in the Fig

9.5(b) is B.A and second NAND gate simply a NOT gate. Now the

circuit is simply an AND gate circuit.

(iii) OR gate: Two NOT gates of Fig 9.5(c) gives output of A and B , which are the inputs of second

NAND gate. Hence, second NAND gives an output of BA. . According to second

De Morgan’s theorem it can be written as BA which can also be written as A+B( A =A

and B = B , refer fig 9.3(c). It is the output of an OR gate.

Y = AA

Fig 9.5(a)

Fig 9.5(b)

Y = A . BA . BA

B

Y = A + BA

A

BB

Fig 9.5(c)

Fig. 3.5(a)

NOTES

Digital Electronics




proved.





1












Y = AA

Fig 9.5(a)

Fig 9.5(b)

Y = A . BA . BA

B

Y = A + BA

A

BB

Fig 9.5(c)

Fig. 3.5(b)

(ii) AND gate: The Boolean expression for NAND is Y = A . B .So,thefirstNANDgate output in the Fig. 3.5(b) is A . B and second NAND gate simply a NOT gate. Now the circuit is simply an AND gate circuit.

(iii) OR gate: Two NOT gates of Fig. 3.5(c) gives output of A and B, which are the inputs of second NAND gate. Hence, second NAND gives an output of



proved.





1












Y = AA

Fig 9.5(a)

Fig 9.5(b)

Y = A . BA . BA

B

Y = A + BA

A

BB

Fig 9.5(c)

.

According to second De Morgan’s theorem it can be written as



proved.





1












Y = AA

Fig 9.5(a)

Fig 9.5(b)

Y = A . BA . BA

B

Y = A + BA

A

BB

Fig 9.5(c)

which

can also be written as



proved.





1












Y = AA

Fig 9.5(a)

Fig 9.5(b)

Y = A . BA . BA

B

Y = A + BA

A

BB

Fig 9.5(c)

+ B ( A =A and



proved.





1












Y = AA

Fig 9.5(a)

Fig 9.5(b)

Y = A . BA . BA

B

Y = A + BA

A

BB

Fig 9.5(c)

= B, refer Fig. 3.3(c). It is the output of an OR gate.



proved.





1












Y = AA

Fig 9.5(a)

Fig 9.5(b)

Y = A . BA . BA

B

Y = A + BA

A

BB

Fig 9.5(c)Fig. 3.5(c)

(iv) NOR gate: Addition of another NOT gate to the circuit for OR gate of Fig. 3.5(c) as shown in Fig. 3.5(d) gives the operation of a NOR gate.


(iv) NOR gate:

Addition of another NOT gate to the circuit for OR gate of Fig 9.5(c) as shown in Fig 9.5(d) gives the

operation of a NOR gate.

(v) EX – OR gate:

9.5.2 Other Logic gates using only NOR gates :

(i) NOT gate :

(ii) OR gate:

(iii) AND gate:

Fig 9.5(d)

A

B

Y = A + B

Y = AA

Fig 9.5(f)

Fig 9.5(g)

Y = A +BA + BA

B

Y = A . BA

B

Fig 9.5(h)

Y = AB +ABA

B

Fig 9.5(e)

Fig. 3.5(d)

(v) EX-OR gate:


(iv) NOR gate:



(v) EX – OR gate:


(i) NOT gate :

(ii) OR gate:

(iii) AND gate:

Fig 9.5(d)

A

B

Y = A + B

Y = AA

Fig 9.5(f)

Fig 9.5(g)

Y = A +BA + BA

B

Y = A . BA

B

Fig 9.5(h)

Y = AB +ABA

B

Fig 9.5(e)Fig. 3.5(e)

NOTES

Electronics-1


OtheR LOGIc Gates usING ONLy NOR Gates (i) NOT gate :


(iv) NOR gate:



(v) EX – OR gate:


(i) NOT gate :

(ii) OR gate:

(iii) AND gate:

Fig 9.5(d)

A

B

Y = A + B

Y = AA

Fig 9.5(f)

Fig 9.5(g)

Y = A +BA + BA

B

Y = A . BA

B

Fig 9.5(h)

Y = AB +ABA

B

Fig 9.5(e)

Fig. 3.5(f)

(ii) OR gate:


(iv) NOR gate:



(v) EX – OR gate:


(i) NOT gate :

(ii) OR gate:

(iii) AND gate:

Fig 9.5(d)

A

B

Y = A + B

Y = AA

Fig 9.5(f)

Fig 9.5(g)

Y = A +BA + BA

B

Y = A . BA

B

Fig 9.5(h)

Y = AB +ABA

B

Fig 9.5(e)

Fig. 3.5(g)

(iii) AND gate:


(iv) NOR gate:



(v) EX – OR gate:


(i) NOT gate :

(ii) OR gate:

(iii) AND gate:

Fig 9.5(d)

A

B

Y = A + B

Y = AA

Fig 9.5(f)

Fig 9.5(g)

Y = A +BA + BA

B

Y = A . BA

B

Fig 9.5(h)

Y = AB +ABA

B

Fig 9.5(e)

Fig. 3.5(h)

(iv) NAND gate:


(iii) NAND gate:

(v) EX - OR gate:

Of the several technologies available Transistor–Transistor Logic is widely used where logic 1 is

represented by +5V DC. And Logic zero by 0V DC. Circuits using other types of logic are provided with TTL

logic compatibility to facilitate easy interfacing of logic circuits.

When a logic gate is connected to another logic gate, depending on the logic status it is supposed to supply or

take currents. Supplying current is called sourcing and taking the current is called sinking. Capability of a

circuit depends on how much current a circuit can sink and source.

This is expressed in terms of how many logic gates can be connected to it (fan-in) and how many circuits can

be driven by it (fan-out). For standard TTL fan – out is 10.

Logic circuits are supposed to change their states from 0 to 1 or 1 to 0 instantaneously, but, electronic

circuits have inherent delays and because of it, there will be some definite rise time, fall time and propagation

delay as a signal passes from input to output. Further there will be signal attenuation and induction effects and

noise, which affect signal amplitude. For a standard TTL circuit if a logic 1 signal amplitude falls below 2.4V

DC it cannot be recognized as Logic1. Like wise, if logic 0 signal amplitude is greater than 0.4V DC it cannot

be identified as logic 0. This results in failure of logic circuits. Crossing the fan-in and fan-out limits also

changes logic voltages. So logic circuits are to be buffered to bring back, the signal levels to TTL levels

Fig 9.5(i)

A

B

Y = A . B

Y = AB +ABAB

Fig 9.5(j)

Fig. 3.5(i)

(v) EX - OR gate:


(iii) NAND gate:

(v) EX - OR gate:

Of the several technologies available Transistor–Transistor Logic is widely used where logic 1 is

represented by +5V DC. And Logic zero by 0V DC. Circuits using other types of logic are provided with TTL

logic compatibility to facilitate easy interfacing of logic circuits.

When a logic gate is connected to another logic gate, depending on the logic status it is supposed to supply or

take currents. Supplying current is called sourcing and taking the current is called sinking. Capability of a

circuit depends on how much current a circuit can sink and source.

This is expressed in terms of how many logic gates can be connected to it (fan-in) and how many circuits can

be driven by it (fan-out). For standard TTL fan – out is 10.

Logic circuits are supposed to change their states from 0 to 1 or 1 to 0 instantaneously, but, electronic

circuits have inherent delays and because of it, there will be some definite rise time, fall time and propagation

delay as a signal passes from input to output. Further there will be signal attenuation and induction effects and

noise, which affect signal amplitude. For a standard TTL circuit if a logic 1 signal amplitude falls below 2.4V

DC it cannot be recognized as Logic1. Like wise, if logic 0 signal amplitude is greater than 0.4V DC it cannot

be identified as logic 0. This results in failure of logic circuits. Crossing the fan-in and fan-out limits also

changes logic voltages. So logic circuits are to be buffered to bring back, the signal levels to TTL levels

Fig 9.5(i)

A

B

Y = A . B

Y = AB +ABAB

Fig 9.5(j)Fig. 3.5(j)

NOTES

Digital Electronics


Of the several technologies available Transistor–Transistor Logic is widely used where logic 1 is represented by +5V DC. And Logic zero by 0V DC. Circuits using other types of logic are provided with TTL logic compatibility to facilitate easy interfacing of logic circuits.

Whenalogicgateisconnectedtoanotherlogicgate,dependingonthelogicstatusitis supposed to supply or take currents. Supplying current is called sourcing and taking the current is called sinking. Capability of a circuit depends on how much current a circuit can sink and source.

This is expressed in terms of how many logic gates can be connected to it (fan-in) and how many circuits can be driven by it (fan-out). For standard TTL fan – out is 10.

Logic circuits are supposed to change their states from 0 to 1 or 1 to 0 instantaneously, but,electroniccircuitshaveinherentdelaysandbecauseofit,therewillbesomedefiniterisetime, fall time and propagation delay as a signal passes from input to output. Further there will be signal attenuation and induction effects and noise, which affect signal amplitude. For a standard TTL circuit if a logic 1 signal amplitude falls below 2.4V. DC it cannot be recognized as Logic1. Like wise, if logic 0 signal amplitude is greater than 0.4V DC it cannotbeidentifiedaslogic0.Thisresultsinfailureoflogiccircuits.Crossingthefan-inand fan-out limits also changes logic voltages. So logic circuits are to be buffered to bring back, the signal levels to TTL levels before they are deteriated. A signal in its transmission path may develop glitches, slopes and other types of distortion. Schmitt trigger circuit is used to produce rectangular wave shape regardless of the input waveform.

3.7 BINARY ADDITIONWhenweperformbinaryadditionandsubtraction,thefollowingrulesmustbefollowed.

Binary addition Binary subtraction

0 + 0 = 0 (1) 0 – 0 = 0 borrow 0

0 + 1 = 1 (2) 0 – 1 = 1 borrow 1

1 + 0 = 1 (3) 1 – 0 = 1 borrow 0

1 + 1 = 10 (4) 1 – 1 = 0 borrow 0

1 + 1 + 1 = 11 (5)

Inbinaryadditionthefirstthreeoperationsproduceasumwithonlyonedigit,butwhen both augend and added bits are equal to 1, the binary sum consists of two digits. The highersignificantbitofthisresultiscalledacarry.

3.8 HALF ADDERA combinational circuit that performs the addition of two – bits is called a Half – adder. The Half – adder has two binary inputs and two binary outputs.

This is 1 – bit adder. This circuit is called half – adder because it cannot accept a carry – in from previous additions. The inputs to the circuits are the addend and augend bits. The

NOTES

Electronics-1


outputs produced by it are sum (s) and carry (c). The half adder can be constructed by using one AND gate and an EX – OR gate. Fig. 3.6(a) shows logic circuit that adds 2 bits namely A and B.

Fig. 3.6(b) shows the truth table of it. The carry output is 0 unless both inputs are 1. TheSoutputrepresentstheleastsignificantbitofthesum.

Boolean equation for sum (s) =

M. Sc Physics 2 Combinational Logic Circuits

Binary codes are used to specify instructions, addresses and coded data. One binary digit (bit) can stand

for two codes 0 or 1. with two bits we can have four codes namely 00, 01, 10, 11. Similarly with n bits we

can form 2n codes. Circuits, that generate these codes are called encoders. It become necessary not only the

code information but also to decode the codes whenever necessary. Circuits with decode are called

decoders.

Information coming on several channels may have to be rooted on a single channel this is called

multiplexing and circuits with do this multiplexers. Multiplexer information coming on a single channel

have to be separated and sent and varies channels and this is called demultiplexers. In this lesson we learn

about these combinational logic circuits also.

10.1 Binary addition:

When we perform binary addition and subtraction, the following rules must be followed.

Binary addition Binary subtraction

0 + 0 = 0 (1) 0 – 0 = 0 borrow 0

0 + 1 = 1 (2) 0 – 1 = 1 borrow 1

1 + 0 = 1 (3) 1 – 0 = 1 borrow 0

1 + 1 = 10 (4) 1 – 1 = 0 borrow 0

1 + 1 + 1 = 11 (5)

In binary addition the first three operations produce a sum with only one digit, but when both augend and

added bits are equal to 1, the binary sum consists of two digits. The higher significant bit of this result is

called a carry.

10.2 Half Adder:

A combinational circuit that performs the addition of two – bits is called a Half – adder. The Half –

adder has two binary inputs and two binary outputs.

This is 1 – bit adder. This circuit is called half – adder because it cannot accept a carry – in from

previous additions. The inputs to the circuits are the addend and augend bits. The outputs produced by it

are sum (s) and carry (c). The half adder can be constructed by using one AND gate and an EX – OR gate.

Fig 10.1(a) shows logic circuit that adds 2 bits namely A and B.

Fig 10.1(b) shows the truth table of it. The carry output is 0 unless both inputs are 1. The S output

represents the least significant bit of the sum.

Boolean equation for sum (s) = = A ĀB. A B+ B +


= A EX – OR B

Carry (c) = A AND B = AB

10.3 Full adder:

A full adder is combinational circuit that forms the arithmetic sum of three input bits. The two

significant bits to be added are denoted as A and B, where as the third input C represents the carry from the

previous lower significant position. The full adder can be constructed from two half adders and one OR gate

as shown in fig 10.2(a). and its symbol is shown in fig 10.2(b).

C(CARRY)

A . B

A

B

INPUT1

INPUT2

S(SUM A B)+

Fig 10.1(a) Half-Adder Logic circuit

A HALFADDERB

C

S

Fig 10.1 (b) Half – adder Logic symbol

Fig 10.1 (c)

CarryC

SumSA B

0

0

1

1

0

1

0

1

0

1

1

0

Half – adder Truth table

0

0

0

1

Fig. 3.6(a). Half-Adder Logic circuit


= A EX – OR B


10.3 Full adder:





C(CARRY)

A . B

A

B

INPUT1

INPUT2

S(SUM A B)+


A HALFADDERB

C

S


Fig 10.1 (c)

CarryC

SumSA B

0

0

1

1

0

1

0

1

0

1

1

0


0

0

0

1

Fig. 3.6(b). Half – adder Logic symbol


= A EX – OR B


10.3 Full adder:





C(CARRY)

A . B

A

B

INPUT1

INPUT2

S(SUM A B)+


A HALFADDERB

C

S


Fig 10.1 (c)

CarryC

SumSA B

0

0

1

1

0

1

0

1

0

1

1

0


0

0

0

1

Fig. 3.6(c)

3.9 FULL ADDERA full adder is combinational circuit that forms the arithmetic sum of three input bits. The two significantbitstobeaddedaredenotedasAandB,whereasthethirdinputCrepresentsthecarryfromthepreviouslowersignificantposition.Thefulladdercanbeconstructedfromtwohalf adders and one OR gate as shown in Fig. 3.7(a). and its symbol is shown in Fig. 3.7(b).

NOTES

Digital Electronics



CCARRY

SSUM

Fig 10.2(a) : Full – adder Logic diagram

ORHA1

EXOR Sum

AND Carry

HA2

AND Carry

EXOR Sum

AHA1

B

CarryC

Fig 10.2 (b): Full – adder Logic Symbol

HA2

C

OR

SumS

Fig 10.2 (c) Full – adder Truth Table

A B C SumCarryINPUTS OUTPUTS

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

Fig. 3.7(a): Full – adder Logic diagram


CCARRY

SSUM


ORHA1

EXOR Sum

AND Carry

HA2

AND Carry

EXOR Sum

AHA1

B

CarryC


HA2

C

OR

SumS



0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

Fig. 3.7(b): Full – adder Logic Symbol


CCARRY

SSUM


ORHA1

EXOR Sum

AND Carry

HA2

AND Carry

EXOR Sum

AHA1

B

CarryC


HA2

C

OR

SumS



0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

Fig. 3.7(c) Full – adder Truth Table

3.10 BINARY FOUR BIT PARALLEL ADDERNote:Inbinary,thecountstartsfromzeroratherthanfrom1.ThefirstbitiscalledS0ratherthan S1. Similarly the nyj bit is Sn-1.

A parallel adder is an m-bi at a time. This produces the arithmetic sum of two n-bit binary numbers in parallel. This can be constructed by using one half adder and several full adders. The full adders are connected in cascade, with the output carry from one full adder connected to the input carry of the next full adder.

NOTES

Electronics-1



10.4 Binary four bit parallel Adder:

Note: In binary, the count starts from zero rather than from 1. The first bit is called S0

rather than S1. Similarly the nyj bit is Sn-1.

A parallel adder is an m-bi at a time. This produces the arithmetic sum of two n-bit binary numbers in

parallel. This can be constructed by using one half adder and several full adders. The

full adders are connected in cascade, with the output carry from one full adder connected to the input carry

of the next full adder.

Fig 10.3 shows the logic diagram for 4-bit parallel adder circuit.

Suppose we want to add 4-bit binary numbers A3 A2 A1 A0 and B3 B2 B1 B0 then we get a sum S4 S3 S2 S1 S0

where S4 indicates overflow bit if the sum exceeds four bits. For adding the above two 4-bit numbers, we

require three full adders and a half adder connected in parallel. The output (carry) of each adder is

connected to next adder to get a parallel adder.

10.5 Decoder:

A decoder is a combinational circuit that converts binary information from ‘n’ input lines to a maximum

of 2n unique output lines. Decoders are available with several output configurations: active low voltage,

high-sink current for direct driving of indicator lamps. Output voltage ratings range from +5V to over

+100V. the decoder is used in conjunction with some code converters such as a BCD – to – 7 segment

decoder, BCD – to – Decimal decoder. The decoder presented here is called n – to 2n line decoders decoder.

Its purpose is to generate the 2n min terms of n input variables. These decoders form a combinational circuit

with n input variables and 2n output variables. For each binary input combination of 1s and 0s, there is one

and only one output line that assumes the value of 1. Figure 10.4(a) shows a 2 by 4 decoder. It has four

AND gates and two inverters.

F.A F.A F.A H.A

A0

A1

A1A2A3

B1B2B3

S2S3 S1S0S4(Over flow bit)

Fig 10.3

Final outputFig. 3.8

Fig. 3.8 shows the logic diagram for 4-bit parallel adder circuit.

Suppose we want to add 4-bit binary numbers A3 A2 A1 A0 and B3 B2 B1 B0 then we get a sum S4 S3 S2 S1 S0 where S4indicatesoverflowbitifthesumexceedsfourbits.Foradding the above two 4-bit numbers, we require three full adders and a half adder connected in parallel. The output (carry) of each adder is connected to next adder to get a parallel adder.

3.11 DECODERA decoder is a combinational circuit that converts binary information from ‘n’ input lines to a maximum of 2n unique output lines. Decoders are available with several output configurations:activelowvoltage,high-sinkcurrentfordirectdrivingofindicatorlamps.Output voltage ratings range from +5V to over +100V. the decoder is used in conjunction with some code converters such as a BCD – to – 7 segment decoder, BCD – to – Decimal decoder. The decoder presented here is called n – to 2n line decoders decoder. Its purpose is to generate the 2n min terms of n input variables. These decoders form a combinational circuit with n input variables and 2n output variables. For each binary input combination of 1s and 0s, there is one and only one output line that assumes the value of 1. Figure 3.9(a) shows a 2 by 4 decoder. It has four AND gates and two inverters.


Some times an enable input may be included with a decoder to control the circuit operation. In this, all

outputs will be equal to 0, if the enable input is zero. When the enable input is 1, the circuit operates as a

conventional decoder. Block diagram of 3 to 8 decoder with enable signal is shown in Fig 10.5.

X Y D0 D1 D2 D3

0

0

1

1

0

1

0

1

0

0

0

1

0

0

1

0

1

0

0

0

0

1

0

0

Fig 10.4(b) 2- bit decoder Truth table

00010203040506

07

ABC

Inputs

Outputs

Enable

Fig 10.5 Block diagram of 3 to 8 bit decoder

X

Y D3 = X Y

D1 = X Y

D2 = X Y

D0 = X Y

FIG 10.4(a) 2 – bit decoderFig. 3.9(a) 2 – bit decoder

NOTES

Digital Electronics






X Y D0 D1 D2 D3

0

0

1

1

0

1

0

1

0

0

0

1

0

0

1

0

1

0

0

0

0

1

0

0


00010203040506

07

ABC

Inputs

Outputs

Enable


X

Y D3 = X Y

D1 = X Y

D2 = X Y

D0 = X Y

FIG 10.4(a) 2 – bit decoder

Fig. 3.9(b) 2- bit decoder Truth table

Some times an enable input may be included with a decoder to control the circuit operation.Inthis,alloutputswillbeequalto0,iftheenableinputiszero.Whentheenableinput is 1, the circuit operates as a conventional decoder. Block diagram of 3 to 8 decoder with enable signal is shown in Fig. 3.10.





X Y D0 D1 D2 D3

0

0

1

1

0

1

0

1

0

0

0

1

0

0

1

0

1

0

0

0

0

1

0

0


00010203040506

07

ABC

Inputs

Outputs

Enable


X

Y D3 = X Y

D1 = X Y

D2 = X Y

D0 = X Y

FIG 10.4(a) 2 – bit decoder

Fig. 3.10. Block diagram of 3 to 8 bit decoder

3.12 DEMULTIPLEXERA demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2npossibleoutput lines.Theselectionofaspecificoutput line iscontrolled by the bit values of n selection lines. Figure 3.11 shows the block diagram of decoder and demultiplixer. The decoder with an enable input can function as a demultiplexer.


10.6 Demultiplexer:

A demultiplexer is a circuit that receives information on a single line and transmits this information on

one of 2n possible output lines. The selection of a specific output line is controlled by the bit values of n

selection lines. Figure 10.6 shows the block diagram of decoder and demultiplixer. The decoder with an

enable input can function as a demultiplexer.

The decoder of Fig 10.6(a) can function as a demultiplexer if the enable line is taken as a data input line and

lines A and B are taken as the selection lines as shown in Fig 10.6(b). Out of 4 output lines, one gets link

with input E depends upon the binary value of two selection lines A and B (i.e), if AB = 01, D1 gets

connected with the input E, so that input is available at D1 output. While all other outputs are maintained

at 1.

10.7 Encoder:

An encoder is a digital circuit, that produces a reverse operation from that of a decoder. An encoder has

2n input lines and n output lines. The output lines generate the binary code for the 2n input variables. One of

OutputD0D1

D2

D3

A

BInput 2 x 4

Decoder

Enable

Fig 10.6(a)

A B

D0D1

D2

D3

EnableInputE

1 x 4De-

multiplexer

Fig 10.6(b)

X

Fig. 3.11(a)

NOTES

Electronics-1



10.6 Demultiplexer:

A demultiplexer is a circuit that receives information on a single line and transmits this information on

one of 2n possible output lines. The selection of a specific output line is controlled by the bit values of n

selection lines. Figure 10.6 shows the block diagram of decoder and demultiplixer. The decoder with an

enable input can function as a demultiplexer.

The decoder of Fig 10.6(a) can function as a demultiplexer if the enable line is taken as a data input line and

lines A and B are taken as the selection lines as shown in Fig 10.6(b). Out of 4 output lines, one gets link

with input E depends upon the binary value of two selection lines A and B (i.e), if AB = 01, D1 gets

connected with the input E, so that input is available at D1 output. While all other outputs are maintained

at 1.

10.7 Encoder:

An encoder is a digital circuit, that produces a reverse operation from that of a decoder. An encoder has

2n input lines and n output lines. The output lines generate the binary code for the 2n input variables. One of

OutputD0D1

D2

D3

A

BInput 2 x 4

Decoder

Enable

Fig 10.6(a)

A B

D0D1

D2

D3

EnableInputE

1 x 4De-

multiplexer

Fig 10.6(b)

X

Fig. 3.11(b)

The decoder of Fig. 3.11 can function as a demultiplexer if the enable line is taken as a data input line and lines A and B are taken as the selection lines as shown in Fig. 3.11(b). Out of 4 output lines, one gets link with input E depends upon the binary value of two selection lines A and B (i.e), if AB = 01, D1 gets connected with the input E, so that input is available at D1output.Whileallotheroutputsaremaintainedat1.

3.13 ENCODERAn encoder is a digital circuit, that produces a reverse operation from that of a decoder. An encoder has 2n input lines and n output lines. The output lines generate the binary code for the 2n input variables. One of the encoders is shown in Fig. 3.12(a). It has eight inputs, one for each of the eight digits and three outputs that generate the corresponding binary outputs that generate the corresponding binary number.


the encoders is shown in fig 10.7(a). It has eight inputs, one for each of the eight digits and three outputs

that generate the corresponding binary outputs that generate the corresponding binary number.

Fig 10.7(a) shows the octal to binary encoder. It is constructed with OR gates. It, has 8 input lines and

could have 28 = 256 possible input combinations. Only eight of these combinations have meaning and

others are don’t care conditions. The output z is 1, if the input digits are odd. Output Y is 1 for octal digits

2, 3, 6 and 7. Output X is 1 for digits 4, 5, 6 or 7. It is 1 at any time. Do is not connected to any OR gate.

It erises that only the highest priority input line is encoded.

D0 D1 D2 D3 D4 D5 D6 D7

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

X Y Z

INPUTS OUTPUTS

Truth table 10.7(b)

D0D1D2

D3

D4D5D6D7

X = D4 + D5 + D6 + D7

Y= D2 + D3 + D6 + D7

Z= D1 + D3 + D5 + D7

Fig. 10.7(a)Fig. 3.12(a)

Fig. 3.12(a) shows the octal to binary encoder. It is constructed with OR gates. It, has 8 input lines and could have 28 = 256 possible input combinations. Only eight of these combinations have meaning and others are don’t care conditions. The output z is 1, if the input digits are odd. Output Y is 1 for octal digits 2, 3, 6 and 7. Output X is 1 for digits 4, 5,

NOTES

Digital Electronics


6 or 7. It is 1 at any time. Do is not connected to any OR gate. It erises that only the highest priority input line is encoded. Truth table 3.12(b).


the encoders is shown in fig 10.7(a). It has eight inputs, one for each of the eight digits and three outputs

that generate the corresponding binary outputs that generate the corresponding binary number.

Fig 10.7(a) shows the octal to binary encoder. It is constructed with OR gates. It, has 8 input lines and

could have 28 = 256 possible input combinations. Only eight of these combinations have meaning and

others are don’t care conditions. The output z is 1, if the input digits are odd. Output Y is 1 for octal digits

2, 3, 6 and 7. Output X is 1 for digits 4, 5, 6 or 7. It is 1 at any time. Do is not connected to any OR gate.

It erises that only the highest priority input line is encoded.

D0 D1 D2 D3 D4 D5 D6 D7

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

X Y Z

INPUTS OUTPUTS

Truth table 10.7(b)

D0D1D2

D3

D4D5D6D7

X = D4 + D5 + D6 + D7

Y= D2 + D3 + D6 + D7

Z= D1 + D3 + D5 + D7

Fig. 10.7(a)

Truth table 3.12(b)

3.14 MULTIPLEXERS / DATA SELECTORIt is a combinational circuit which selects binary information from one of many input lines and directs it to single outputs line. The selection of a particular input line is controlled by a set of selection lines. For ‘n’ bits, there are 2n input lines and n selection lines whose bit combinations determine which inputs is selected.


10.8 Multiplexers / Data selector:

It is a combinational circuit which selects binary information from one of many input lines and directs it

to single outputs line. The selection of a particular input line is controlled by a set of selection lines. For ‘n’

bits, there are 2n input lines and n selection lines whose bit combinations determine which inputs is selected.

This means “many into one”. It is used when a complex logic circuit is to be shaved by a number of input

signals. Fig 10.8 shows the logic diagram, block diagram and function table of a 4 to 1 line multiplexer.

A line to 1 line multiplexer has 4 inputs I0 to I3 and one output line. Each of the four input lines is

applied to one input of a three input AND gate. The remaining two inputs of it is supplied by selection lines

S1 and S0.

I0

I1

I2

S0

I3

S1

Y

1

2

3

4

Fig 10.8(a): 4 to 1 Multiplexer

4 x 1Mux

0

1

2

3

InputOutput

Select

Fit 10.8(c)

0

0

1

1

0

1

0

1

I0

I1

I2

I3

S1 S0 Y

Fig 10.8(b)

Fig. 3.13(a). 4 to 1 Multiplexer

NOTES

Electronics-1


This means “many into one”. It is used when a complex logic circuit is to be shaved by a number of input signals. Fig. 3.10 shows the logic diagram, block diagram and function table of a 4 to 1 line multiplexer. A line to 1 line multiplexer has 4 inputs I0 to I3 and one output line. Each of the four input lines is applied to one input of a three input AND gate. The remaining two inputs of it is supplied by selection lines S1 and S0.










S1 and S0.

I0

I1

I2

S0

I3

S1

Y

1

2

3

4


4 x 1Mux

0

1

2

3

InputOutput

Select

Fit 10.8(c)

0

0

1

1

0

1

0

1

I0

I1

I2

I3

S1 S0 Y

Fig 10.8(b)Fig. 3.13(b)










S1 and S0.

I0

I1

I2

S0

I3

S1

Y

1

2

3

4


4 x 1Mux

0

1

2

3

InputOutput

Select

Fit 10.8(c)

0

0

1

1

0

1

0

1

I0

I1

I2

I3

S1 S0 Y

Fig 10.8(b)

Fig. 3.13(c)

Based on the combination of S1 and S0, the input associated with the selected AND gatefindsoutthepathtoreachtheoutputthroughORgate.Forexample:whenS1S0 = 01, it selects the AND gate 2. So the input I1 is transferred to the output i.e OR gate output is now equal to the value of I1. thus providing a path from the selected input to the output. The remaining AND gates have at least one input equal to 0.

As in decoders, multiplexer IC have an enable input (or) storbe input to control the operation of the unit. It can also be used to expand two or more multiplexers to a digital multiplexer with a large number of inputs.

3.15 FLIP-FLOPAflip-flopisabinarycell,whichcanstoreabitofinformation.Ititselfisasequentialcircuit.Aflipflopmaintainsanyoneofthetwostablestatesthatcanbetreatedas1or0dependingonthepresenceorabsenceofoutputsignal.Thestateofflip-flopcanonlychangewhenclockpulsehasarrived.Letusfirstseethebasicflip–floporalatch.

NOTES

Digital Electronics


3.16 S-R LATCHThemostfundamentalcircuitinthegroupofflip-flopsistheS-R(set-reset)latch.ThebasicS-R latch has two NAND gates connected back – to – back. Fig. 3.14(a) shows, such an S-R latch. The truth table of the S-R latch is given in Table 3.1. It describes the conditions oftheflip-flopsattimest0 and t1. The state at t = t0 is called the present state (PS) and the state at t = t1 is called the next state (NS).


11.2 S-R Latch:-

The most fundamental circuit in the group of flip-flops is the S-R(set-reset) latch . The basic S-R latch

has two NAND gates connected back – to – back. Fig 11.2 shows, such an S-R latch. The truth table of the

S-R latch is given in Table 11.1. It describes the conditions of the flip-flops at times t0 and t1. The state at t

= t0 is called the present state (PS) and the state at t = t1 is called the next state (NS).

The S – R latch has two external inputs S and R, and two feed – back inputs Q and Q . The present states

of the inputs are S0, R0 and Q0. After one clock pulse, the output will change to the next state Q1. This

changed value of the output will be the new present state of the input.

For testing the validity of the circuit, we have to test eight states corresponding to the three inputs. So, R0

and Q0. These states are tested by using fig 11.2 and table 11.1

We shall test the outputs for the conditions: S = R= 0; S=0, R=1; S=R=1. In each of these cases, we test

the state of the latch for the conditions of Q = 0, and Q = 1 respectively.

Fig 11.2 Circuit diagram of the S – R latch.

R

S A1

A2

Q

Q

Table 11.1 Truth Table of S – R latch

Present state (PS) Next state (NS)S0 R0 Q0 Q1

0

0

1

1

0

1

0

1

01010101

Not permitted

Reset to 0

Set to 1

01 Q0

Fig. 3.14(a). Circuit diagram of the S – R latch.

The S – R latch has two external inputs S and R, and two feed – back inputs Q and Q. The present states of the inputs are S0, R0 and Q0. After one clock pulse, the output will change to the next state Q1. This changed value of the output will be the new present state of the input. For testing the validity of the circuit, we have to test eight states corresponding to the three inputs. So, R0 and Q0. These states are tested by using Fig. 3.15 and table 3.1

Table 3.1. Truth Table of S – R latch


11.2 S-R Latch:-

The most fundamental circuit in the group of flip-flops is the S-R(set-reset) latch . The basic S-R latch

has two NAND gates connected back – to – back. Fig 11.2 shows, such an S-R latch. The truth table of the

S-R latch is given in Table 11.1. It describes the conditions of the flip-flops at times t0 and t1. The state at t

= t0 is called the present state (PS) and the state at t = t1 is called the next state (NS).

The S – R latch has two external inputs S and R, and two feed – back inputs Q and Q . The present states

of the inputs are S0, R0 and Q0. After one clock pulse, the output will change to the next state Q1. This

changed value of the output will be the new present state of the input.

For testing the validity of the circuit, we have to test eight states corresponding to the three inputs. So, R0

and Q0. These states are tested by using fig 11.2 and table 11.1

We shall test the outputs for the conditions: S = R= 0; S=0, R=1; S=R=1. In each of these cases, we test

the state of the latch for the conditions of Q = 0, and Q = 1 respectively.

Fig 11.2 Circuit diagram of the S – R latch.

R

S A1

A2

Q

Q

Table 11.1 Truth Table of S – R latch

Present state (PS) Next state (NS)S0 R0 Q0 Q1

0

0

1

1

0

1

0

1

01010101

Not permitted

Reset to 0

Set to 1

01 Q0

Weshalltesttheoutputsfortheconditions:S=R=0;S=0,R=1;S=R=1.Ineachof these cases, we test the state of the latch for the conditions of Q = 0, and Q = 1 respectively.

Case(i): WefindthatwhenS=R=0bothQandQ– become 1. But this is not allowed

because we want Q and Qto be complementary outputs. This state is designated as the forbidden state.

Case (ii): In S = 0, R = 1 case, when S = 0, output of NAND gate A2, i.e., Q– becomes

1. Now the inputs to gate A1. i.e., R and Q– , both become 1, which make its output, Q = 0.

This is called the reset (to 0) state.

NOTES

Electronics-1


Case (iii): In S = 1, R = 0 case, when R = 0, A1 produces an output of 1 i.e., Q = 1. Now, both the inputs to A2 are 1, which makes Q = 0. This state (S = 1) making Q equal to 1 is called the set (to 1) state.

Case (iv): In S = 1, R = 1 case, both the inputs are equal to 1 . It will not produce any change in the output. Hence, for these cases, the outputs will remain as such in their previous states. This means that the present state and the next state are one and the same.

Using Fig. 3.13, we have described the behavior of a bi-stable multi-vibrator using NAND gates for all possible input states. Table 3.1 represents the truth table of the S-R latch. The behavior of the circuit shows that it will remain in one of the two states (i.e. 0 or 1) till an externally applied trigger pulse produces a transition in the output from 0 to 1, or 1 to 0. Thus, the circuit is able to store one bit of information in its memory. Therefore, this flip-flopiscalledamemorycell,weshallnowdiscusstheclockedS-RFlip-Flop.

3.17 CLOCKED R-S FLIP – FLOPThemainfeatureinR-SFlip-Flopsistheadditionofaclockpulseinput.Inthisflip-flopchangeinthevalueofRorSwillchangethestateoftheflip-floponlyiftheclockpulseatthat moment is one. It is shown in Fig. 3.15a.

The excitation or characteristic table basically represents the effect of S and R inputs onthestateoftheflip-flop,irrespectiveofthecurrentstateofflip-flop.TheothertwoinputsP(present)andC(clear)areasynchronousinputsandcanbeusedtosettheflip-floporcleartheflip-floprespectivelyatthestartofoperation,independentoftheclockpulse.


11.4 D Flip – Flop:

D flip-flop is a special type flip-flop and it represents the currently applied input as the state of the flip-

flop. It can store 1 bit of data information and sometimes refers to as Data flip-flop. The state of flip-flop

changes with the applied input. It does not have a condition where the state does not change as the case in

RS flip-flop, the state of R-S flip-flop does not change when S = 0 and R = 0. If we want that for a

particular input state does not change, then either the clock is to be disabled during that period or a feedback

of the output can be embedded with the D- flip-flop is also known as Delay Flip-Flop because it delays the

0 or 1 applied to its input by a single clock pulse.

P11.4(a) Logic Diagram

D Q

Q

Clock

C

R

S

Q

Q

a

bClock Signal

Clear C

P (Preset)

11.3(a) Logic Diagram

Q

QR R

S S P

(Preset)

Clear

C

11.3(b) Symbolic representation

InputS R

State on completionof clock cycle

No change in StateClear the flip – flop (state 0)Set the flip – flop (state 1)Undesirable (Not allowed)

0 00 11 01 1

Fig 11.3(c) Characteristic table.

Fig 11.3: R – S flip – flop

Clock

3.15(a) Logic Diagram 3.15(b) Symbolic representation











D Q

Q

Clock

C

R

S

Q

Q

a

bClock Signal

Clear C

P (Preset)


Q

QR R

S S P

(Preset)

Clear

C


InputS R



0 00 11 01 1



Clock

3.15(c) Characteristic table.

Ffig. 3.15: R – S flip -flop

NOTES

Digital Electronics


3.18 D FLIP – FLOPDflip-flopisaspecialtypeflip-flopanditrepresentsthecurrentlyappliedinputasthestateoftheflipflop.Itcanstore1bitofdatainformationandsometimesreferstoasDataflip-flop.Thestateofflip-flopchangeswiththeappliedinput.ItdoesnothaveaconditionwherethestatedoesnotchangeasthecaseinRSflip-flop,thestateofR-Sflip-flopdoesnotchangewhen S = 0 and R = 0. If we want that for a particular input state does not change, then either the clock is to be disabled during that period or a feedback of the output can be embedded withtheD-flip-flopisalsoknownasDelayFlip-Flopbecauseitdelaysthe0or1appliedto its input by a single clock pulse.











D Q

Q

Clock

C

R

S

Q

Q

a

bClock Signal

Clear C

P (Preset)


Q

QR R

S S P

(Preset)

Clear

C


InputS R



0 00 11 01 1



Clock



11.5 J-K Flip – Flop:

It is not possible to achieve toggling (changing the state of the output wherever the input makes a

transition from 1 to 0) with the simple flip-flops described above. By using NAND gates, one can construct

a flip-flop that toggles. The symbol and truth table of one such circuit, called J-K flip-flop are shown in fig

11.5

J

K Q

Q

Clock

C

P


Q

QK K

JJ P

>Clock

C


InputJ K


No change in StateClear the flip –f lop (state 0)Set the flip – flop (state 1)Complement the state of flip- flop

0 00 11 01 1

Fig 11.5(c) Truth table.

Fig 11.5: J – K flip – flop

Fig 11.4: D flip – flop

Fig 11.4(c) Truth table of D-Flip-Flop.

InputD

State oncompletion of

clock cycle

01

01


S

PD Q

Q>Clock

3.16(b) Symbolic representation Fig. 3.16(c) Truth table of D-Flip-Flop

Fig. 3.16. D flip – flop

3.19 11.5 J-K FLIP – FLOPIt is not possible to achieve toggling (changing the state of the output wherever the input makesatransitionfrom1to0)withthesimpleflip-flopsdescribedabove.ByusingNANDgates,onecanconstructaflip-flopthat toggles.Thesymbolandtruthtableofonesuchcircuit,calledJ-Kflip-flopareshowninFig.3.17.






11.5

J

K Q

Q

Clock

C

P


Q

QK K

JJ P

>Clock

C


InputJ K



0 00 11 01 1





InputD


clock cycle

01

01


S

PD Q

Q>Clock


NOTES

Electronics-1







11.5

J

K Q

Q

Clock

C

P


Q

QK K

JJ P

>Clock

C


InputJ K



0 00 11 01 1





InputD


clock cycle

01

01


S

PD Q

Q>Clock

3.17(b) Symbolic representation Fig. 3.17(c) Truth table

Fig. 3.17. J – K flip – flop

AJKflip-flopisarefinementoftheSRflip-flopinthattheindeterminateconditionoftheSRtypedefinesintheJKtype.AnexaminationofthetruthtablegiveninFig.3.17(a)revealsthefollowingpropertiesoftheJKflip-flop.

(a) It retains its present state if J = 0 and K = 0

(b) If J = 0, K = 1, Q = 0, it resets to zero

(c) If J = 1, K = 0, Q = 1, it sets

(d) If J = 1, K = 1, it Toggles.

IfthefirstclockpulseleavesQ=1andQ– = 0 the second clock pulse make Q = 0 and Q

– =

0. The third clock pulse make Q = 1 and Q– = 0 again and so on as shown


A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate condition of the SR type

defines in the JK type. An examination of the truth table given in fig 11.5(a) reveals the following

properties of the JK flip-flop.

a) It retains its present state if J = 0 and K = 0

b) If J = 0, K = 1, Q = 0, it resets to zero

c) If J = 1, K = 0, Q = 1, it sets

d) If J = 1, K = 1, it Toggles.

If the first clock pulse leaves Q = 1 and Q = 0 the second clock pulse make Q = 0 and Q = 0. The third

clock pulse make Q = 1 and Q = 0 again and so on as shown

Relation between clock pulses and output JK flip-flop. When J = 1 and K = 1.

Please note Q = 1 once in every two clock pulses i.e., the output has half the frequency of the clock pulse.

This property is utilized in binary counters.

Preset and Clear Inputs:

Usually, the J-K flip – flop works on the basis of the clock input. However, we can introduce two inputs

called the PRESET and CLEAR in the last NAND level. As shown in fig 11.6(a) these inputs do not obey

the clock pulses, and override them in action. Hence, they are called the asynchronous inputs. The working

of these inputs is as given below.

Q

T

Q

Q

Q

PR

>Clock

CLR11.6(a) Symbolic representation

PR CLR Q0 Q1

Forbidden operations0/1 10/1 0

Normal operations

0 00 11 01 1

Fig 11.6(b) Truth table.



Please note Q = 1 once in every two clock pulses i.e., the output has half the frequency of the clock pulse. This property is utilized in binary counters.

Preset and Clear InputsUsually,theJ-Kflip–flopworksonthebasisoftheclockinput.However,wecanintroducetwo inputs called the PRESET and CLEAR in the last NAND level. As shown in Fig. 3.18(a) these inputs do not obey the clock pulses, and override them in action. Hence, they are called the asynchronous inputs. The working of these inputs is as given below.

Let PR = 0 and CLR = 1. Then, as and when PR = 1 and CLR = 0, Q will jump to 1 from whatever state it is in. This operation presets Q

–to1.WhenPR=1andCLR=0,the

lower NAND produces 1 at its output, i.e., Q– = 1. This makes Q = 0. Thus whatever be the

state,Qwillfallbackto‘0’.WhenbothPR=CLR=1,theNANDsareenabledandthe

NOTES

Digital Electronics


J-Kflip-flopfunctionsinthenormalway.However,thestatePR=CLR=0isforbidden,since both Q and Q

– will be 1 in this state. The truth table for the PR and CLR terminals is

asshowninTable3.18a.Fig.3.18bshowsthesymbolofJ-Kflip-flop.


A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate condition of the SR type

defines in the JK type. An examination of the truth table given in fig 11.5(a) reveals the following

properties of the JK flip-flop.

a) It retains its present state if J = 0 and K = 0

b) If J = 0, K = 1, Q = 0, it resets to zero

c) If J = 1, K = 0, Q = 1, it sets

d) If J = 1, K = 1, it Toggles.

If the first clock pulse leaves Q = 1 and Q = 0 the second clock pulse make Q = 0 and Q = 0. The third

clock pulse make Q = 1 and Q = 0 again and so on as shown


Please note Q = 1 once in every two clock pulses i.e., the output has half the frequency of the clock pulse.

This property is utilized in binary counters.

Preset and Clear Inputs:

Usually, the J-K flip – flop works on the basis of the clock input. However, we can introduce two inputs

called the PRESET and CLEAR in the last NAND level. As shown in fig 11.6(a) these inputs do not obey

the clock pulses, and override them in action. Hence, they are called the asynchronous inputs. The working

of these inputs is as given below.

Q

T

Q

Q

Q

PR

>Clock

CLR11.6(a) Symbolic representation

PR CLR Q0 Q1

Forbidden operations0/1 10/1 0

Normal operations

0 00 11 01 1

Fig 11.6(b) Truth table.


3.18(a) Symbolic representation Fig. 3.18(b) Truth table

Fig. 3.18. J – K flip – flop

Race – Around ConditionsConsiderthelasttworowsofthetruthtableoftheJ-Kflip-flop,whereboththeJandKinputsareconnectedtologic-1state.WefindthatwhenJ=K=1,Q0 changes to Q0. That is, if Q0 = 0, Q1 = 1, and if Q0 = 1, Q1 = 0. These transitions gives rise to what is called the race-aroundproblem.WhenJ=K=1andCK=1theoutputwilltogglefrom‘0’to‘1’,and1 to 0 continuously, until the clock pulse becomes zero. The result of this toggling action is thatwhentheclockfinallybecomeszero,wewellnotknowinwhatstateQwouldbe.Thisis called race-around problem, as it is generated due to the racing of this signal around the

feedback path, and around the circuit.

3.20 MASTER – SLAVE JK FLIP – FLOP (SOLUTION TO THERACE-AROUND PROBLEM)TheracearoundproblemcanbesolvedusingtwoJ-Kflip-flopsinthemaster-slavemodeofoperation.HeretwoS-Rflip-flopsareintheJ-Kmodeofoperation.Thefirstflip-flopinthe‘master’ and the second one is the ‘slave’. The master is converted into J-K mode of operation.


Let PR = 0 and CLR = 1. Then, as and when PR = 1 and CLR = 0, Q will jump to 1 from whatever state

it is in. This operation presets Q to 1. When PR = 1 and CLR = 0, the lower NAND produces 1 at its

output, i.e., Q = 1. This makes Q = 0. Thus whatever be the state, Q will fall back to ‘0’. When both PR =

CLR = 1, the NANDs are enabled and the J-K flip-flop functions in the normal way. However, the state PR

= CLR = 0 is forbidden, since both Q and Q will be 1 in this state. The truth table for the PR and CLR

terminals is as shown in Table 11.6a. fig 11.6b shows the symbol of J-K flip-flop.

RACE – AROUND CONDITIONS:

Consider the last two rows of the truth table of the J-K flip-flop, where both the J and K inputs are

connected to logic-1 state. We find that when J = K = 1, Q0 changes to Q 0. That is, if Q0 = 0, Q1 = 1, and if

Q0 = 1, Q1 = 0. These transitions gives rise to what is called the race-around problem. When J = K = 1 and

CK = 1 the output will toggle from ‘0’ to ‘1’, and 1 to 0 continuously, until the clock pulse becomes zero.

The result of this toggling action is that when the clock finally becomes zero, we well not know in what state

Q would be. This is called race-around problem, as it is generated due to the racing of this signal around the

feedback path, and around the circuit.

11.6 Master – Slave JK Flip – Flop (Solution to the Race-Around Problem):

The race around problem can be solved using two J-K flip-flops in the master-slave mode of operation.

Here two S-R flip-flops are in the J-K mode of operation. The first flip-flop in the ‘master’ and the second

one is the ‘slave’. The master is converted into J-K mode of operation.

Fig 11.7 J – K master –slave flip – flop.

CK

CK

KM

JM

Master Slave

SM

RM

QM

QMQS

QSSS

RS

Fig. 3.19. J – K master –slave flip – flop.

NOTES

Electronics-1


The slave inputs are connected to the outputs of the master. In this mode, the slave will also act as a J-K Flip – Flop. The Master is driven by clock pulse CK, while the slave is driven by CK , which is obtained by inverting the CK pulses. The feedback connection can be seen to be from the Slave outputs to the master inputs.

(i) Whentheclock is ON, the master gets enabled and the slave gets disabled. So, the inputs appearing at input terminals SM and RM of the master will appear at its outputs QM and Q

– M. respectively, which means that the external inputs now

appear at the inputs Ss and Rs of the slave.

(ii) WhentheCK=0,themasterisdisabled,andtheslaveisenabledbecauseCK = 1. Thus the inputs at Ss and Rs will appear at Qs and Qs, respectively, and hence at the inputs JM and KM of the master. However, as the master is now disabled, these inputs will not appear at Ss and Rs. Hence, no feedback problem occurs. Thus, the race-around problem is eliminated.

3.21 APPLICATIONS OF JK FLIP – FLOP

(a) JK Flip - Flop as D-Flip - FlopThe‘D’flip-flophasonlyoneinput,calledthedelay–orD–input.Thetruthtablewillhaveonly four entries, as shown in Fig. 3.20b. when D is 0, Q will become’0’after the program delay tp. similarly, if D = 1, output will become 1, irrespective of the previous value of the output.Wethusfindthattheflip-flopwillalwaysproduceanoutputequaltotheinput,aftera time – delay equal to tp. By cascading a number of D- Flip - Flops, the delay time can be increased.


The slave inputs are connected to the outputs of the master. In this mode, the slave will also act as a J-K

Flip – Flop. The Master is driven by clock pulse CK, while the slave is driven by CK , which is obtained by

inverting the CK pulses. The feedback connection can be seen to be from the Slave outputs to the master

inputs.

(i) When the clock is ON, the master gets enabled and the slave gets disabled. So, the inputs

appearing at input terminals SM and RM of the master will appear at its outputs QM and Q M.

respectively, which means that the external inputs now appear at the inputs Ss and Rs of the slave.

(ii) When the CK = 0, the master is disabled, and the slave is enabled because CK = 1. Thus the

inputs at Ss and Rs will appear at Qs and Q s, respectively, and hence at the inputs JM and KM of

the master. However, as the master is now disabled, these inputs will not appear at Ss and Rs.

Hence, no feedback problem occurs. Thus, the race-around problem is eliminated.

11.7 Applications of JK Flip – Flop:

a) JK Flip - Flop as D-Flip - Flop

The ‘D’ flip-flop has only one input, called the delay – or D – input. The truth table will have only

four entries, as shown in fig 11.8b. when D is 0, Q will become’0’after the program delay tp. similarly, if D

= 1, output will become 1, irrespective of the previous value of the output. We thus find that the flip-flop

will always produce an output equal to the input, after a time – delay equal to tp. By cascading a number of

D- Flip - Flops, the delay time can be increased.

Since the circuit output is produced after a time-delay, this is called the delay flip-flop. It is also called the

D latch.

b) JK Flip-Flop as T-Flip- Flop :-

By shorting the J and K terminals, we can construct a T Flip-Flop. Usually, the T – input is tied to

logical 1 . Fig 11.9a shows the circuit of the toggle flip-flop and fig 11.9b shows its truth table.

D0 Q0 Q1

0 0 00 1 01 0 11 1 1

Fig 11.8(b) Truth Table of the Dflip – flop.

11.8(a) D flip – flop.

Q

Q

J

K

3.20(a). D flip – flop. Fig. 3.20(b) Truth Table of the D flip – flop

Sincethecircuitoutputisproducedafteratime-delay,thisiscalledthedelayflip-flop.

It is also called the D latch.

(b) JK Flip-Flop as T-Flip- FlopBy shorting the J and K terminals, we can construct a T Flip-Flop. Usually, the T – input is tiedtological1.Fig.3.21ashowsthecircuitofthetoggleflip-flopandFig.3.19bshowsits truth table.

Table shows that, when T = 0, Q1 = Q0. However, if T = 1, Q1 = Q–

0.Tflip–flopsareuseful in the construction of counters.

NOTES

Digital Electronics



Table shows that, when T = 0, Q1 = Q0. However, if T = 1, Q1 = Q 0. T flip – flops are useful in the

construction of counters.

11.8 Shift Register:

Shift registers are very important in applications involving the storage and transfer of data in digital

system. A register, in general, is used solely for storing and shifting data (1s and 0s) entered into it from all

external source and possesses no characteristic internal sequence of states. The storage capability of a

register is one of its two basic functional characteristics and makes it an important type of memory device.

Registers are commonly used for the temporary storage of data within a digital system. The shift

capability of a register permits the movement of data from stage to stage within the register or into or out of

the register upon application of clock pulses.

Fig 11.10 shows symbolically the types of data movement in shift register operations. The block

represents any arbitrary four-bit register, and the arrow indicates the direction and type of data movement.

T0 Q0 Q1

0 0 00 1 01 0 11 1 1

Fig 11.9(b) Truth Table of the Tflip – flop.

T

CK11.9(a) Toggle flip – flop.

Q

Q

J

K

Figure 11.10 Basic data movement in registers.

Data bits

(a) Serial shift right, then out.

Data bits

(b) Serial shift left, then out.

(c) Parallel shift in.

Data bits

Data bits

(d) Parallel shift out. (e) Rotate right (f) Rotate left














T0 Q0 Q1

0 0 00 1 01 0 11 1 1


T


Q

Q

J

K


Data bits


Data bits



Data bits

Data bits


3.21(a) Toggle flip – flop Fig. 3.21(b) Truth Table of the T flip – flop

3.22 SHIFT REGISTERShift registers are very important in applications involving the storage and transfer of data in digital system. A register, in general, is used solely for storing and shifting data (1s and 0s) entered into it from all external source and possesses no characteristic internal sequence of states. The storage capability of a register is one of its two basic functional characteristics and makes it an important type of memory device.














T0 Q0 Q1

0 0 00 1 01 0 11 1 1


T


Q

Q

J

K


Data bits


Data bits



Data bits

Data bits


Fig. 3.22. Basic data movement in registers

Registers are commonly used for the temporary storage of data within a digital system. The shift capability of a register permits the movement of data from stage to stage within the register or into or out of the register upon application of clock pulses.

Fig. 3.22 shows symbolically the types of data movement in shift register operations. The block represents any arbitrary four-bit register, and the arrow indicates the direction and type of data movement.

3.23 SERIAL IN – SERIAL OUT SHIFT REGISTER:This type of shift register accepts data serially, i.e. one bit at a time, and also outputs data serially. The logic diagram of a 4 – bit serial – in, serial – out, shift register is shown in Fig. 3.23.withfourstages,i.e.,fourflip–flops,theregistercanstoreuptofourbitsofdata.

NOTES

Electronics-1



11.9 Serial In – Serial out Shift Register:

This type of shift register accepts data serially, i.e. one bit at a time, and also outputs data serially. The

logic diagram of a 4 – bit serial – in, serial – out, shift register is shown in fig 11.11. with four stages, i.e.,

four flip –flops, the register can store up to four bits of data.

Serial data is applied at the D input of the first Flip-Flop (FF). The Q output of the first FF is connected to

the D input of the second FF, the Q output of the second FF is connected to the D input of the third FF and

the Q output of the third FF is connected to the D input of the fourth FF. The data is outputted from the Q

terminal of the last FF.

When serial data is transferred into a register, each new bit is clocked into the first FF at the positive –

going edge of each clock pulse. The bit that was previously stored by the first FF is transferred to the

second FF. The bit that was stored by the second FF is transferred to the third FF, and so on. The bit that

was stored by the last FF is shifted out.

Fig 11.12 and 11.13a illustrate this process to store the data bits 0101 in the register. Initially all the FFs

are reset, i.e., Q1 = 0, Q2 = 0, Q3 = 0 and Q4 = 0.

The right most bit ‘1’ is applied at the D1 input of FF1. At the positive – going edge of the first clock

pulse, this ‘1’ is shifted into FF1 and all other FFs store their respective bits at the D inputs. Therefore, Q1 =

1, Q2 = 0, Q3 = 0 and Q4 = 0, after the first clock pulse.

Then a ‘0’ is applied at the D1 input of FF1. At the positive – going edge of the second clock pulse, this

‘0’ is shifted to Q1 of FF1 and the D inputs of all other FFs are also shifted to their respective outputs.

Therefore Q1 = 0, Q2 = 1, Q3 = 0 and Q4 = 0, after the second clock pulse.

CLK

Serialinput

Serialoutput

Figure 11.11 4 – bit serial – in, serial – out, shift register

D1 Q1 D2 Q2 D3 Q3 D4 Q4

Figure 3.23. 4 – bit serial – in, serial – out, shift register

SerialdataisappliedattheDinputofthefirstFlip-Flop(FF).TheQoutputofthefirstFF is connected to the D input of the second FF, the Q output of the second FF is connected to the D input of the third FF and the Q output of the third FF is connected to the D input of the fourth FF. The data is outputted from the Q terminal of the last FF.


Then a ‘1’ is applied at the D1 input of FF1. At the positive – going edge of the third clock pulse, this ‘1’

is shifted into Q1 of FF1 and the D inputs of all other FFs are also shifted to their respective outputs.

Therefore, Q1 = 1, Q2 = 0, Q3 = 1 and Q4 = 0, after the third clock pulse.

Then a ‘0’ is applied at the D1 input of FF1. At the positive – going edge of the fourth clock pulse, this

‘0’ is shifted into Q1 of FF1 and the D inputs of all other FFs are also shifted to their respective outputs.

Therefore, Q1 = 0, Q2 = 1, Q3 = 0 and Q4 = 1, after the third clock pulse, this ‘0’ is shifted to Q1 of FF1 and

the D inputs of all other FFS are also shifted to their respective outputs. Therefore, Q1 = 0, Q2 = 1, Q3 = 0

and Q4 = 1, after the fourth clock pulse.

CLK

Serial input Serial outputD1 Q1

FF1

D2 Q2FF3

D3 Q3

FF3

D4 Q4FF4

1 0 0 0 0

(a) Initial states (0000)

CLK


FF1

D2 Q2FF3

D3 Q3

FF3

D4 Q4FF4

0 1 0 0 0

(b) After the first clock pulse (1000)

CLK


FF1

D2 Q2

FF3

D3 Q3

FF3

D4 Q4

FF4

1 0 1 0 0

(c) After the second clock pulse (0100)

CLK


FF1

D2 Q2FF3

D3 Q3

FF3

D4 Q4FF4

0 1 0 1 0

(d) After the third clock pulse (1010)

Fig11.12 Loading of the 4 – bit serial – in, serial – out, shift register

CLK


FF1

D2 Q2FF3

D3 Q3

FF3

D4 Q4FF4

0 0 1 0 1

(e) After the fourth clock pulse (0101)

Fig. 3.24. Loading of the 4 – bit serial – in, serial – out, shift register

NOTES

Digital Electronics


Whenserialdataistransferredintoaregister,eachnewbitisclockedintothefirstFFat

thepositive–goingedgeofeachclockpulse.Thebitthatwaspreviouslystoredbythefirst

FF is transferred to the second FF. The bit that was stored by the second FF is transferred to

the third FF, and so on. The bit that was stored by the last FF is shifted out.

Fig. 3.24 and 3.24a illustrate this process to store the data bits 0101 in the register. Initially all the FFs are reset, i.e., Q1 = 0, Q2 = 0, Q3 = 0 and Q4 = 0.

The right most bit ‘1’ is applied at the D1 input of FF1. At the positive – going edge ofthefirstclockpulse,this‘1’isshiftedintoFF1andallotherFFsstoretheirrespectivebits at the D inputs. Therefore, Q1 = 1, Q2 = 0, Q3 = 0 and Q4=0,afterthefirstclockpulse.

Then a ‘0’ is applied at the D1 input of FF1. At the positive – going edge of the second clock pulse, this ‘0’ is shifted to Q1 of FF1 and the D inputs of all other FFs are also shifted to their respective outputs. Therefore Q1 = 0, Q2 = 1, Q3 = 0 and Q4 = 0, after the second clock pulse.

Then a ‘1’ is applied at the D1 input of FF1. At the positive – going edge of the third

clock pulse, this ‘1’ is shifted into Q1 of FF1 and the D inputs of all other FFs are also

shifted to their respective outputs. Therefore, Q1 = 1, Q2 = 0, Q3 = 1 and Q4 = 0, after the

third clock pulse.

Then a ‘0’ is applied at the D1 input of FF1. At the positive – going edge of the fourth

clock pulse, this ‘0’ is shifted into Q1 of FF1 and the D inputs of all other FFs are also shifted

to their respective outputs. Therefore, Q1 = 0, Q2 = 1, Q3 = 0 and Q4 = 1, after the third clock

pulse, this ‘0’ is shifted to Q1 of FF1 and the D inputs of all other FFS are also shifted to their

respective outputs. Therefore, Q1 = 0, Q2 = 1, Q3 = 0 and Q4 = 1, after the fourth clock pulse.


This completes the serial entry of 0101 into the 4-bit register fig 11.13 shows the timing diagram of the

loading of serial input 0101 into the 4-bit serial-in, serial-out, shift register.

The shifting out of the stored data 0101 serially from the register is illustrated in fig 11.14 . It requires four

clock pulses to shift out the 4-bit stored data.

After clock pulse Serial input Q1 Q2 Q3 Q4

0

1

2

3

4

1

0

1

0

–

0

1

0

1

0

0

0

1

0

1

0

0

0

1

0

0

0

0

0

1

Fig 11.13(a) Shifting in the data 0101 serially.

Initial states

Q1

Q2

Q3

Q4

CLK

Serial inputt

t

t

t

t

t

Fig 11.13(b) Timing diagram showing the loading of the serialinput 0101 into the 4 – bit Serial-in, Serial-out, shift register.


0

1

2

3

4

0

0

0

0

–

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

1

0

0

Fig 11.14 Shifting in the data 0101 serially.

Fig. 3.25(a) Shifting in the data 0101 serially.

This completes the serial entry of 0101 into the 4-bit register Fig. 3.22 shows the timing diagram of the loading of serial input 0101 into the 4-bit serial-in, serial-out, shift register.

NOTES

Electronics-1








0

1

2

3

4

1

0

1

0

–

0

1

0

1

0

0

0

1

0

1

0

0

0

1

0

0

0

0

0

1


Initial states

Q1

Q2

Q3

Q4

CLK

Serial inputt

t

t

t

t

t



0

1

2

3

4

0

0

0

0

–

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

1

0

0

Fig 11.14 Shifting in the data 0101 serially.

Fig. 3.25(b) Timing diagram showing the loading of the serial input 0101

into the 4 – bit Serial-in, Serial-out, shift register.

The shifting out of the stored data 0101 serially from the register is illustrated in Fig.

3.26. It requires four clock pulses to shift out the 4-bit stored data.







0

1

2

3

4

1

0

1

0

–

0

1

0

1

0

0

0

1

0

1

0

0

0

1

0

0

0

0

0

1


Initial states

Q1

Q2

Q3

Q4

CLK

Serial inputt

t

t

t

t

t



0

1

2

3

4

0

0

0

0

–

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

1

0

1

0

0

Fig 11.14 Shifting in the data 0101 serially.Fig. 3.26. Shifting in the data 0101 serially

3.24 SERIAL IN, PARALLEL – OUT SHIFT REGISTERIn this type of register, the data bits are entered into the register serially, but the data stored in the register is shifted out in parallel form. Fig. 3.27 shows the logic diagram and the logic symbol of a 4-bit serial – in, parallel – out shift register. Once the data bits are stored, each bit appears on its respective output line and all bits are available simultaneously, rather than on a bit-by-bit basis as with the serial output. The serial – in, parallel-out, shift register can be used as a serial-in, serial-out, shift register, if the output is taken from the Q terminal of the

last FF.

NOTES

Digital Electronics



11.10 Serial In, Parallel – out Shift Register:

In this type of register, the data bits are entered into the register serially, but the data stored in the register

is shifted out in parallel form. Fig 11.15 shows the logic diagram and the logic symbol of a 4-bit serial – in,

parallel – out shift register.

Once the data bits are stored, each bit appears on its respective output line and all bits are available

simultaneously, rather than on a bit-by-bit basis as with the serial output. The serial – in, parallel-out, shift

register can be used as a serial-in, serial-out, shift register, if the output is taken from the Q terminal of the

last FF.

11.11 Parallel In, Serial – Out Shift Register:

In parallel – in, serial-out, shift register, the data bits are entered simultaneously into their respective

stages on parallel lines, rather than on a bit-by-bit basis on one line as with serial data inputs, but the data

bits are transferred out of the register serially, i.e., on a bit-by-bit basis over a single line.

Fig 11.16 illustrates a 4-bit parallel-in, serial out, shift register using D flip-flops. There are four data

lines A, B, C and D through which the data is entered into the register in parallel form. The signal shift /

load allows (a) the data to be entered in parallel form into the register and (b) the data to be shifted out

serially from terminal Q4.

When Shift / Load line is high, gates G1, G2 and G3 are disabled, but gates G4, G5 and G6 are enabled

allowing the data bits to shift – right from one stage to the next. When Shift / Load line is low, gates G4, G5

and G6 are disabled, whereas gates G1, G2 and G3 are enabled allowing the data input to appear at the D

Fig 11.15 A 4 – bit serial - in, parallel - out, shift register.

CLK

Data input D1 QA

FF1

D2 QBFF3

D3 QC

FF3

D4 QD

FF4

QB QC QD

(a) Logic diagram

QA

Data input SRG -4

QDQCQBQA

CLK

(b) Logic symbol

Fig. 3.27. A 4 – bit serial - in, parallel - out, shift register.

3.25 PARALLEL IN, SERIAL – OUT SHIFT REGISTERIn parallel – in, serial-out, shift register, the data bits are entered simultaneously into their respective stages on parallel lines, rather than on a bit-by-bit basis on one line as with serial data inputs, but the data bits are transferred out of the register serially, i.e., on a bit-by-bit basis over a single line.

Fig.3.28illustratesa4-bitparallel-in,serialout,shiftregisterusingDflip-flops.Thereare four data lines A, B, C and D through which the data is entered into the register in parallel form. The signal shift / load allows (a) the data to be entered in parallel form into the register and (b) the data to be shifted out serially from terminal Q4.WhenShift/Loadlineishigh,gates G1, G2 and G3 are disabled, but gates G4, G5 and G6 are enabled allowing the data bits toshift–rightfromonestagetothenext.WhenShift/Loadlineislow,gatesG4, G5 and G6 are disabled, whereas gates G1, G2 and G3 are enabled allowing the data input to appear attheDinputsoftherespectiveflip-flops.


inputs of the respective flip-flops. When a clock pulse is applied, these data bits are shifted to the Q output

terminals of the flip-flops and therefore, data is inputted in one step. The OR gate allows either the normal

shifting operation or the parallel data entry depending on which AND gates are enabled by the level on the

Shift / Load input.

11.12 Parallel In, Parallel – out Shift Register:

CLK

Shift / Load

C

(a) Logic diagram

D1 Q1

FF1

D2 Q2FF3

D3 Q3

FF3

D4 QDFF4

G1 G2 G3G4 G5 G6

A B D

Data outSRG -4

A DCB

CLK

(b) Logic symbol

Shift / Load

Fig 11.16 A 4-bit parallel, serial – out, shift register.

CLK

Figure 11.17 Logic diagram of a 4 – bitparallel – in, parallel – out, shift register

DQ

D

QD

DQ

DQ

DQ

QCQA QB

A B C

NOTES

Electronics-1






Shift / Load input.


CLK

Shift / Load

C

(a) Logic diagram

D1 Q1

FF1

D2 Q2FF3

D3 Q3

FF3

D4 QDFF4

G1 G2 G3G4 G5 G6

A B D

Data outSRG -4

A DCB

CLK

(b) Logic symbol

Shift / Load


CLK


DQ

D

QD

DQ

DQ

DQ

QCQA QB

A B C

Fig. 3.28. A 4-bit parallel, serial – out, shift register

Whenaclockpulseisapplied,thesedatabitsareshiftedtotheQoutputterminalsoftheflip-flopsandtherefore,dataisinputtedinonestep.TheORgateallowseitherthenormalshifting operation or the parallel data entry depending on which AND gates are enabled by the level on the Shift / Load input.

3.26 PARALLEL IN, PARALLEL – OUT SHIFT REGISTERIn a parallel – in, parallel – out, shift register, the data is entered into the register in parallel form, and also the data is taken out of the register in parallel form. Immediately following the simultaneous entry of all data bits, the bits appear on the parallel outputs.





Shift / Load input.


CLK

Shift / Load

C

(a) Logic diagram

D1 Q1

FF1

D2 Q2FF3

D3 Q3

FF3

D4 QDFF4

G1 G2 G3G4 G5 G6

A B D

Data outSRG -4

A DCB

CLK

(b) Logic symbol

Shift / Load


CLK


DQ

D

QD

DQ

DQ

DQ

QCQA QB

A B C

Fig. 3.29 Logic diagram of a 4 – bit parallel – in, parallel – out, shift register

Fig. 3.29 shows a 4-bit parallel-in, parallel-out, shift register using D Flip-Flops. Data isappliedtotheDinputterminalsoftheflip-flops.Whenaclockpulseisapplied,atthepositive going edge of that pulse, the D inputs are shifted in to the Q outputs of the Flip-Flops. The register now stores the data. The stored data is available instantaneously for shifting out in parallel form.

3.27 BI-DIRECTIONAL SHIFTERA bidirectional shift register is one in which the data bits can be shifted from left to right or from right to left.

Fig. 3.29 shows the logic diagram of a 4-bit serial-in, serial-out, bi-directional shift register. Right/Left is the mode signal.

NOTES

Digital Electronics



In a parallel – in, parallel – out, shift register, the data is entered into the register in parallel form, and

also the data is taken out of the register in parallel form. Immediately following the simultaneous entry of

all data bits, the bits appear on the parallel outputs.

Fig 11.17 shows a 4-bit parallel-in, parallel-out, shift register using D Flip-Flops. Data is applied to the

D input terminals of the flip-flops. When a clock pulse is applied, at the positive going edge of that pulse,

the D inputs are shifted in to the Q outputs of the Flip-Flops. The register now stores the data. The stored

data is available instantaneously for shifting out in parallel form.

11.13 Bi-directional Shifter:

A bidirectional shift register is one in which the data bits can be shifted from left to right or from right to

left.

Fig 11.18 shows the logic diagram of a 4-bit serial-in, serial-out, bi-directional shift register. Right/Left

is the mode signal.

When Right / tLef is a 1, the logic circuit works as a shift-right shift register. When Right / tLef is a 0, it

works as a shift – left register. The bidirectional operation is achieved by using the mode signal and two

AND gates and one OR gate for each stage as shown in fig 11.18.

A HIGH on the Right / tLef control input enables the AND gates G1, G2, G3 and G4 and disables the

AND gates G5, G6, G7and G8 and the state of Q output of each FF is passed through the gate to the D input of

the following FF. When a clock pulse occurs, the data bits are then effectively shifted one place to the right.

A low on the Right / tLef control input enables the AND gates G5, G6, G7and G8 and disables the AND

gates G1, G2, G3 and G4 and the Q output of each Flip-Flop is passed to the D input of the preceding FF.

Fig 11.18 Logic diagram of a 4 – bit bi-directional shift register.

CLK

Din

D1 Q1

FF1

D2 Q2

FF2

D3 Q3

FF3D4 Q4

FF4

G2 G3 G4G6

Right / Left

Q4

G1 G5 G7 G8

Fig. 3.29 Logic diagram of a 4 – bit bi-directional shift register.

WhenRight/Leftisa1,thelogiccircuitworksasashift-rightshiftregister.WhenRight/Left is a 0, it works as a shift – left register. The bidirectional operation is achieved by using the mode signal and two AND gates and one OR gate for each stage as shown in Fig. 3.29.

A HIGH on the Right /Left control input enables the AND gates G1, G2, G3 and G4 and disables the AND gates G5, G6, G7 and G8 and the state of Q output of each FF is passed throughthegatetotheDinputofthefollowingFF.Whenaclockpulseoccurs,thedatabits are then effectively shifted one place to the right. A low on the Right /Left control input enables the AND gates G5, G6, G7 and G8 and disables the AND gates G1, G2, G3 and G4 and the Q output of each Flip-Flop is passed to the D input of the preceding FF.

Whenaclockpulseoccurs,thedatabitsaretheneffectivelyshiftedoneplacetotheleft. Hence, the circuit works as a bidirectional shift register.

3.28 UNIVERSAL SHIFT REGISTER


When a clock pulse occurs, the data bits are then effectively shifted one place to the left. Hence, the circuit

works as a bidirectional shift register.

11.14 Universal Shift Register:

A universal shift Register is a bidirectional register, whose input can be either in serial form or in parallel

form and whose output also can be either in serial form or in parallel form.

Fig 11.19 shows the logic diagrams of the 74194 4-bit universal shift register. The output of each flip-

flop is routed through AOI logic to the stage on its right and to the stage on its left. The mode control

inputs, S0 and S1 are used to enable the left-to-right connections. When it is desired to shift-right, and the

right-to-left connections. When it is desired to Shift-Left.

S QA

RCL R

S QB

RCL R

S QC

RCL R

S QD

RCL R

Parallel output

Parallel input

Shift –leftserial input

A B C D

CLR

CLK

Mode S1

controlinputs S0

Shift –rightserial input

QDQA QB QC

InputsS1 S0

Clock Action

0 00 11 01 1

Xmmm

No changeShift-rightShift-leftParallel load

(b)Truth Table

Fig 11.19 The 74194 4–bit universal shift register.

(a) Logic diagram

NOTES

Electronics-1



When a clock pulse occurs, the data bits are then effectively shifted one place to the left. Hence, the circuit

works as a bidirectional shift register.

11.14 Universal Shift Register:

A universal shift Register is a bidirectional register, whose input can be either in serial form or in parallel

form and whose output also can be either in serial form or in parallel form.

Fig 11.19 shows the logic diagrams of the 74194 4-bit universal shift register. The output of each flip-

flop is routed through AOI logic to the stage on its right and to the stage on its left. The mode control

inputs, S0 and S1 are used to enable the left-to-right connections. When it is desired to shift-right, and the

right-to-left connections. When it is desired to Shift-Left.

S QA

RCL R

S QB

RCL R

S QC

RCL R

S QD

RCL R

Parallel output

Parallel input

Shift –leftserial input

A B C D

CLR

CLK

Mode S1

controlinputs S0

Shift –rightserial input

QDQA QB QC

InputsS1 S0

Clock Action

0 00 11 01 1

Xmmm

No changeShift-rightShift-leftParallel load

(b)Truth Table

Fig 11.19 The 74194 4–bit universal shift register.

(a) Logic diagram

Fig. 3.30. The 74194 4–bit universal shift register.

A universal shift Register is a bidirectional register, whose input can be either in serial form or in parallel form and whose output also can be either in serial form or in parallel form.

Fig. 3.30 shows the logic diagrams of the 74194 4-bit universal shift register. The output ofeachflipflopisroutedthroughAOIlogictothestageonitsrightandtothestageonitsleft.The mode control inputs, S0 and S1areusedtoenabletheleft-to-rightconnections.Whenitisdesiredtoshift-right,andtheright-to-leftconnections.WhenitisdesiredtoShift-Left.

The truth table (Fig. 3.30b) shows that no shifting occurs when S0 and S1 are both LOWorbothHIGH.WhenS0 = S1 = 0, there is no change in the contents of the register, and when S0 = S1 = 1, the parallel input data A, B, C and D are loaded into the register on the rising edge of the clock pulse. The combination S0 = S1 = 0 is said to inhibit the loading of serial or parallel data, since the register contents cannot change under that condition. The registerhasanasynchronousactive–LOWclearinput,whichcanbeusedtoresetalltheflip-flopsirrespectiveoftheclockandanyserialorparallelinputs.

3.29 COUNTERSAdigitalcounterisasetofflip-flops(FFs)whosestateschangeinresponsetopulsesappliedat the input to the counter. Thus, as its name implies, a counter is used to count pulses. A counter can also be used as a frequency divider to obtain waveforms with frequencies that are specificfunctionsoftheclockfrequency.Theyarealsousedtoperformthetimingfunctionas in digital watches, to create time delays, to produce non-sequential binary counts, to generate pulse trains, and to act as frequency counters, etc. Counters may be asynchronous counters or synchronous counters. The term asynchronous refers to events that do not occur at the same time. Asynchronous counters are also called Ripple counters. The asynchronous counter has a disadvantage, in so far as the unwanted spikes are concerned. This limitation is overcome in parallel counters. Propagation delay is a major disadvantage in asynchronous counters because it limits the rate at which the counter can be clocked and creates decoding problem. The term synchronous as applied to counter operation means that the counter is clockedsuchthateachflip-flopinthecounterisfrigseredatthesametime.

3.30 ASYNCHRONOUS COUNTERSInaasynchronouscounter,theflip-flopoutputtransitionservesasasourceoftriggeringotherflip-flops.Inotherwords,theCPinputsofallflip-flopsaretriggerednotbytheincoming

NOTES

Digital Electronics


pulsesbutratherby the transition that thatoccurs inotherflip-flops. In thissection,wepresent some asynchronous counters and explain their operation.

Four – Bit Asynchronous Binary CounterFour – Bit asynchronous binary counter consists of a series connection of complementing flip-flops,withtheoutputofeachflip-flopconnectedtotheCPinputofthenexthigher-orderflip-flop.Theflip-flopladingtheleastsignificantbitreceivestheincomingcountpulses.The diagram of a 4 – bit binary ripple counter is shown in Fig. 3.31. All J and K inputs are equalto‘1’.ThesmallcircleintheCPinputindicatesthattheflipflopcomplementsduringa negative-going transition or when the output to which it is connected goes from 1 to 0.


flip flop complements during a negative-going transition or when the output to which it is connected goes

from 1 to 0.

To understand the operation of the binary counter, refer to its count sequence given in Table 11.2. It is

obvious that the lowest order bit A1 must be complemented with each count pulse. Every time A1 goes from

1 to 0, it complements A2. Every time A2 goes from 1 to 0, it complements A3, and so on. For example,

take the transition from count 0111 to 1000. The arrows in the table emphasize the transition in this case.

A1 is complemented with the count pulse. Since A1 goes from 1 to 0, it triggers A2 and complements it. As

a result, A2 goes from 1 to 0, which in turn complements A3. A3 now goes from 1 to 0, which complements

A4. The output transition of A4, if connected to a next stage, will not trigger the next flip-flop, since it goes

from 0 to 1. The flip-flops change are at a time in rapid success on, and the signal propagates through the

counter in a ripple fashion. Hence asynchronous counters are sometimes called asynchronous counters.

The 7493A Four – Bit binary counter:-

The 7493A is presented as an example of a specific integrated circuit asynchronous counter. As the logic

diagram in fig 11.21 shows, this device actually consists of a single flip-flop and a three –bit asynchronous

A1A2A3A4

1 1

1 1

1

1

1

1

Q J

K

Q J

K

Q J

K

Q J

K

To nextstage Count

pulses

Fig 11.20 4 – bit binary ripple counter

Count sequenceConditions for complementing flip-flops

A4 A3 A2 A1

0 0 0 0 Complement A10 0 0 1 Complement A1 A1 will go from 1 to 0 and Complement A20 0 1 0 Complement A10 0 1 1 Complement A1 A1 will go from 1 to 0 and Complement A2

A2 will go from 1 to 0 and Complement A30 1 0 0 Complement A10 1 0 1 Complement A1 A1 will go from 1 to 0 and Complement A20 1 1 0 Complement A10 1 1 1 Complement A1 A1 will go from 1 to 0 and Complement A2

A2 will go from 1 to 0 and Complement A31 0 0 0 and so on … A3 will go from 1 to 0 and Complement A4

Table 11.2 Count sequence for a binary ripple counter

Fig. 3.31. 4 – bit binary ripple counter



flip flop complements during a negative-going transition or when the output to which it is connected goes

from 1 to 0.

To understand the operation of the binary counter, refer to its count sequence given in Table 11.2. It is

obvious that the lowest order bit A1 must be complemented with each count pulse. Every time A1 goes from

1 to 0, it complements A2. Every time A2 goes from 1 to 0, it complements A3, and so on. For example,

take the transition from count 0111 to 1000. The arrows in the table emphasize the transition in this case.

A1 is complemented with the count pulse. Since A1 goes from 1 to 0, it triggers A2 and complements it. As

a result, A2 goes from 1 to 0, which in turn complements A3. A3 now goes from 1 to 0, which complements

A4. The output transition of A4, if connected to a next stage, will not trigger the next flip-flop, since it goes

from 0 to 1. The flip-flops change are at a time in rapid success on, and the signal propagates through the

counter in a ripple fashion. Hence asynchronous counters are sometimes called asynchronous counters.

The 7493A Four – Bit binary counter:-

The 7493A is presented as an example of a specific integrated circuit asynchronous counter. As the logic

diagram in fig 11.21 shows, this device actually consists of a single flip-flop and a three –bit asynchronous

A1A2A3A4

1 1

1 1

1

1

1

1

Q J

K

Q J

K

Q J

K

Q J

K

To nextstage Count

pulses

Fig 11.20 4 – bit binary ripple counter

Count sequenceConditions for complementing flip-flops

A4 A3 A2 A1

0 0 0 0 Complement A10 0 0 1 Complement A1 A1 will go from 1 to 0 and Complement A20 0 1 0 Complement A10 0 1 1 Complement A1 A1 will go from 1 to 0 and Complement A2

A2 will go from 1 to 0 and Complement A30 1 0 0 Complement A10 1 0 1 Complement A1 A1 will go from 1 to 0 and Complement A20 1 1 0 Complement A10 1 1 1 Complement A1 A1 will go from 1 to 0 and Complement A2

A2 will go from 1 to 0 and Complement A31 0 0 0 and so on … A3 will go from 1 to 0 and Complement A4


To understand the operation of the binary counter, refer to its count sequence given in Table 3.2. It is obvious that the lowest order bit A1must be complemented with each count pulse. Every time A1 goes from 1 to 0, it complements A2. Every time A2 goes from 1 to 0, it complements A3, and so on. For example, take the transition from count 0111 to 1000. The arrows in the table emphasize the transition in this case. A1 is complemented with the count pulse. Since A1 goes from 1 to 0, it triggers A2 and complements it. As a result, A2 goes from 1 to 0, which in turn complements A3. A3 now goes from 1 to 0, which complements A4. The output transition of A4,ifconnectedtoanextstage,willnottriggerthenextflip-flop,sinceitgoesfrom0to1.Theflip-flopschangeareatatimeinrapidsuccesson,and

NOTES

Electronics-1


the signal propagates through the counter in a ripple fashion. Hence asynchronous counters are sometimes called asynchronous counters.

The 7493A Four – Bit Binary CounterThe7493Aispresentedasanexampleofaspecificintegratedcircuitasynchronouscounter.AsthelogicdiagraminFig.3.32shows,thisdeviceactuallyconsistsofasingleflip-flopandathree–bitasynchronouscounter.Thisarrangementisforflexibility.Itcanbeusedasadivide–by-2deviceusingonlythesingleflip-flop,oritcanbeusedasamodulus–8counter using only the three-bit counter position. This device also provides gated reset inputs,RO(1)andRO(2).WhenbothoftheseinputsareHIGH,thecounterisRESETtothe 0000 state by CLR .


(1)

J

KR

C

(12) (9)

J

K

J

KR R

C C

(8) (11)

QC QD

(MSB)QB

CLK B

R0 (1)(2)

J

KC

R

CLRR0 (2)(3)

CLK A (14)

Fig 11.21 The 7493A four-bit binary counter logic diagram. (Pin numbers are inparentheses, and all J-K inputs are internally connected HIGH.

QA

(LSB)

counter. This arrangement is for flexibility. It can be used as a divide – by-2 device using only the single

flip-flop, or it can be used as a modulus – 8 counter using only the three-bit counter position. This device

also provides gated reset inputs, RO(1) and RO(2). When both of these inputs are HIGH, the counter is

RESET to the 0000 state by CLR .

Additionally, the 7493A can be used as a four-bit modules-16 counter (counts 0 through 151) by

connecting QA output to the CLK B input as shown in fig 11.22.

It can also be configured as a decade counter with asynchronous recycling by using the gated reset inputs

for partial decoding of count 1010, as shown in fig 11.22(b).

Asynchronous Decade Counters:

Counters with ten states in their sequence are called decade counter. A decade counter with a count

sequence of 0(0000) through 9(1001) is a BCD decade counter because its ten-state sequence is the BCD

code. This type of counter is very useful in display applications in which BCD is required for conversion to

a decimal readout.

Fig 11.22 Two configurations of the 7493A asynchronous counter.

QA

CLK A

(a) 7493A connected as amodulus-16 counter

CLK BR0 (1)R0 (2)

QB QC QD

DIV 16Counter

CC

QA

(a) 7493A connected as adecade counter

QB QC QD

CLK ACLK B

R0 (1)R0 (2)

DIV 10Counter

CC

Fig. 3.32. The 7493A four-bit binary counter logic diagram. (Pin numbers are in parentheses, and all J-K inputs are internally connected HIGH.

Additionally, the 7493A can be used as a four-bit modules-16 counter (counts 0 through 151) by connecting QA output to the CLK B input as shown in Fig. 3.33.


(1)

J

KR

C

(12) (9)

J

K

J

KR R

C C

(8) (11)

QC QD

(MSB)QB

CLK B

R0 (1)(2)

J

KC

R

CLRR0 (2)(3)

CLK A (14)

Fig 11.21 The 7493A four-bit binary counter logic diagram. (Pin numbers are inparentheses, and all J-K inputs are internally connected HIGH.

QA

(LSB)

counter. This arrangement is for flexibility. It can be used as a divide – by-2 device using only the single

flip-flop, or it can be used as a modulus – 8 counter using only the three-bit counter position. This device

also provides gated reset inputs, RO(1) and RO(2). When both of these inputs are HIGH, the counter is

RESET to the 0000 state by CLR .

Additionally, the 7493A can be used as a four-bit modules-16 counter (counts 0 through 151) by

connecting QA output to the CLK B input as shown in fig 11.22.

It can also be configured as a decade counter with asynchronous recycling by using the gated reset inputs

for partial decoding of count 1010, as shown in fig 11.22(b).

Asynchronous Decade Counters:

Counters with ten states in their sequence are called decade counter. A decade counter with a count

sequence of 0(0000) through 9(1001) is a BCD decade counter because its ten-state sequence is the BCD

code. This type of counter is very useful in display applications in which BCD is required for conversion to

a decimal readout.

Fig 11.22 Two configurations of the 7493A asynchronous counter.

QA

CLK A

(a) 7493A connected as amodulus-16 counter

CLK BR0 (1)R0 (2)

QB QC QD

DIV 16Counter

CC

QA

(a) 7493A connected as adecade counter

QB QC QD

CLK ACLK B

R0 (1)R0 (2)

DIV 10Counter

CC

Fig. 3.33. Two configurations of the 7493A asynchronous counter

Itcanalsobeconfiguredasadecadecounterwithasynchronousrecyclingbyusingthegated reset inputs for partial decoding of count 1010, as shown in Fig. 3.33(b).

Asynchronous Decade CountersCounters with ten states in their sequence are called decade counter. A decade counter with a count sequence of 0(0000) through 9(1001) is a BCD decade counter because its ten-state sequence is the BCD code. This type of counter is very useful in display applications in which BCD is required for conversion to a decimal readout.

NOTES

Digital Electronics


Adecadecounterrequiresfourflip-flops.Wewillnowtakeafour-bitasynchronouscounter and modify its sequence in order to understand the principle of truncated counters. One method of achieving this recycling after the count of 9(1001) is to decode count 1010(1010) with a NAND gate and connect the output of the NAND gate to the clear (CLR) inputsoftheflip-flops,asshowninFig.3.24a.


A decade counter requires four flip-flops. We will now take a four-bit asynchronous counter and modify

its sequence in order to understand the principle of truncated counters. One method of achieving this

recycling after the count of 9(1001) is to decode count 1010(1010) with a NAND gate and connect the output

of the NAND gate to the clear (CLR) inputs of the flip-flops, as shown in fig 11.23a.

Notice that only QB and QD are connected to the NAND gate inputs. This is an example of partial

decoding, in which the two unique states (QB = 1and QD = 0) are sufficient to decode the count of 1010

because none of the other states (0 through 9) have both QB and QD HIGH at the same time. When the

counter goes into count 1010(1010), the decoding gate output goes LOW and asynchronously RESETS all of

the flip-flops.

The resulting timing diagrams is shown in fig. Notice that there is a glitch on the QB wave form. The

reason for this glitch is that QB must first go HIGH before the count of 1010 can be decoded. Not until

several nano seconds after the counter goes to the count of 1010 does the output of the decoding gate go

LOW. Thus, the counter is in the 1010 state for a short time before it is RESET back to 0000, thus

producing the glitch on QB.

Fig 11.23 An asynchronously clocked decadecounter with asynchronous recycling.

CLK 61 32 10

QC

QD

5 74

QA

8 9

QB

CLR

(b)

F/F A

J

K R

C

F/F B F/F C

J

K

J

KR

C

F/F D

HIGH

J

KC

R

10 decoderCLR

(a)

CLK

R

C

QA QB QCQD

Fig. 3.34. An asynchronously clocked decade counter with asynchronous recycling

Notice that only QB and QD are connected to the NAND gate inputs. This is an example of partial decoding, in which the two unique states (QB = 1and QD=0)aresufficienttodecode the count of 1010 because none of the other states (0 through 9) have both QB and QDHIGHatthesametime.Whenthecountergoesintocount1010(1010),thedecodinggateoutputgoesLOWandasynchronouslyRESETSalloftheflip-flops.

Theresultingtimingdiagramsisshowninfig.NoticethatthereisaglitchontheQB wave form. The reason for this glitch is that QBmustfirstgoHIGHbeforethecountof1010can be decoded. Not until several nano seconds after the counter goes to the count of 1010 doestheoutputofthedecodinggategoLOW.Thus,thecounterisinthe1010stateforashort time before it is RESET back to 0000, thus producing the glitch on QB.

3.31 SYNCHRONOUS COUNTERSSynchronous counters are distinguished from ripple counters in that clock pulses are applied totheCPinputsofallflip-flops.Thecommonpulsetriggersallthefilp-flopssimultaneously,

NOTES

Electronics-1


ratherthanoneatatimeinsuccessionasinaripplecounter.Thedecisionwhetheraflip-flopistobecomplementedornotisdeterminedfromthevaluesoftheJandKinputsatthetimeofthepulse.IfJ=K=0,theflip-flopremainsunchanged.IfJ=K=1,theflip-flopcomplements.Inthissection,wepresentsometypicalMSIsynchronouscountersandexplain their operation.

Three – Bit Synchronous Binary Counter Three bit synchronous binary counter is shown in Fig. 3.35(a) and its timing diagram in Fig. 3.35(b). An understanding of this counter can be achieved by a careful examination of its sequence of states as shown in Table 3.3.


11.17 Synchronous Counters:

Synchronous counters are distinguished from ripple counters in that clock pulses are applied to the CP

inputs of all flip-flops. The common pulse triggers all the filp-flops simultaneously, rather than one at a

time in succession as in a ripple counter. The decision whether a flip-flop is to be complemented or not is

determined from the values of the J and K inputs at the time of the pulse. If J = K = 0, the flip-flop remains

unchanged. If J = K = 1, the flip-flop complements. In this section, we present some typical MSI

synchronous counters and explain their operation.

Three – Bit Synchronous Binary counter:

Three bit synchronous binary counter is shown in fig 11.24(a) and its timing diagram in fig 11.24(b). An

understanding of this counter can be achieved by a careful examination of its sequence of states as shown in

Table 11.3.

First , let us look at QA. Notice that QA changes on each clock pulse as we progress from its original state to

its final state and then back to its original state. To produce this operation, FFA must be held in the toggle

mode by constant HIGH on its J and K inputs. Now let us see what QB does. Notice that it goes to the

opposite state following each time QA is a 1. This occurs at CLK2, CLK4, CLK6 and CLK8. CLK8 causes

the counter to recycle. To produce this operation, QA is connected to the J and K inputs of FFB. When QA

is a 1 and a clock pulse occurs. FFB is the toggle mode and will change state. The other times when QA is

a 0, FFB is in the no-change mode and remains in its present state.

FFA

J

K

C

FFB FFC

J

K

QB

C

QA

HIGH

J

KC

QC

Fig 11.24(a) A three – bit synchronous binary counter.

CLK

Fig 11.24(b) Timing diagram for the counterof figure.

CLK 61 32

QC

5 74

QA

8

QB

Fig. 3.35(a). A three – bit synchronous binary counter.


11.17 Synchronous Counters:

Synchronous counters are distinguished from ripple counters in that clock pulses are applied to the CP

inputs of all flip-flops. The common pulse triggers all the filp-flops simultaneously, rather than one at a

time in succession as in a ripple counter. The decision whether a flip-flop is to be complemented or not is

determined from the values of the J and K inputs at the time of the pulse. If J = K = 0, the flip-flop remains

unchanged. If J = K = 1, the flip-flop complements. In this section, we present some typical MSI

synchronous counters and explain their operation.

Three – Bit Synchronous Binary counter:

Three bit synchronous binary counter is shown in fig 11.24(a) and its timing diagram in fig 11.24(b). An

understanding of this counter can be achieved by a careful examination of its sequence of states as shown in

Table 11.3.

First , let us look at QA. Notice that QA changes on each clock pulse as we progress from its original state to

its final state and then back to its original state. To produce this operation, FFA must be held in the toggle

mode by constant HIGH on its J and K inputs. Now let us see what QB does. Notice that it goes to the

opposite state following each time QA is a 1. This occurs at CLK2, CLK4, CLK6 and CLK8. CLK8 causes

the counter to recycle. To produce this operation, QA is connected to the J and K inputs of FFB. When QA

is a 1 and a clock pulse occurs. FFB is the toggle mode and will change state. The other times when QA is

a 0, FFB is in the no-change mode and remains in its present state.

FFA

J

K

C

FFB FFC

J

K

QB

C

QA

HIGH

J

KC

QC

Fig 11.24(a) A three – bit synchronous binary counter.

CLK

Fig 11.24(b) Timing diagram for the counterof figure.

CLK 61 32

QC

5 74

QA

8

QB

Fig. 3.35(b). Timing diagram for the counter of figure.

First , let us look at QA. Notice that QA changes on each clock pulse as we progress fromitsoriginalstatetoitsfinalstateandthenbacktoitsoriginalstate.Toproducethisoperation, FFA must be held in the toggle mode by constant HIGH on its J and K inputs. Now let us see what QB does. Notice that it goes to the opposite state following each time QA is a 1. This occurs at CLK2, CLK4, CLK6 and CLK8. CLK8 causes the counter to recycle. To produce this operation, QAisconnectedtotheJandKinputsofFFB.WhenQA is a 1 and a clock pulse occurs. FFB is the toggle mode and will change state. The other times when QA is a 0, FFB is in the no-change mode and remains in its present state.

Next, let us see how FFC is made to change at the proper times according to the binary sequence. Notice that both times QC changes state, it is preceded by the unique condition of both QA and QB being HIGH. This condition is detected by the AND gate and applied totheJandKinputsofFFC.WheneverbothQAandQBbeingHIGH,theoutputoftheAND gate makes the J and K inputs of FFC HIGH, and FFC toggle on the following clock

NOTES

Digital Electronics


pulse.Atallothertimes,theJandKinputsofFFCareheldLOWbytheANDgateoutput,and FFC does not change state.

Table 3.3. State sequence for a three-stage binary counter.


Next, let us see how FFC is made to change at the proper times according to the binary sequence. Notice

that both times QC changes state, it is preceded by the unique condition of both QA and QB being HIGH.

This condition is detected by the AND gate and applied to the J and K inputs of FFC. Whenever both QA and

QB being HIGH, the output of the AND gate makes the J and K inputs of FFC HIGH, and FFC toggle on the

following clock pulse. At all other times, the J and K inputs of FFC are held LOW by the AND gate output,

and FFC does not change state.

11.18 Summary:

A flip-flop is the basic memory element; it can store a ‘0’ or a ‘1’.

A flip flop is known more formally as a bistable mutivibrator. It has two stable states.

Flip-Flops are used for data storage, counting, frequency division, parallel-to –serial and serial-to-

parallel data conversion, etc.

An unclocked flip-flop is called a latch, because the output of the flip-flop latches on to a 1 or a 0

immediately after the input is applied.

The clocked D latch is called a transparent D latch, because its output follows the input when the

clock is HIGH.

The J-K Flip-Flop is the most versatile and most widely used of all the flip-flops.

T flip-flops are not widely available as commercial items.

The master-slave flip-flop is made up of two flip-flops- a master and slave. It was developed to

make synchronous operation of flip-flops more predictable by overcoming the problem of race in

clock flip –flops.

A register is a set of FFs used to store binary data.

A register in which shifting of data takes place is called a shift register.

Clock Pulse QC QB QA

01234567

00001111

00110011

01010101

Table 11.3 State sequence for a three-stage binary counter.

3.32 DIGITAL – TO – ANALOG CONVERTER [D/A]The Digital to Analog converter accepts data in digital form and converts it to a voltage or current which is proportional to the digital value. The black diagram of a n-bit D/A converter is shown in Fig. 3.36. It has n-logic inputs and a single analog output, whose value varies discretely in response to the 2n possible input bit patterns. The internal circuit can be all electronically switched ladder network.

Normally two types of networks are used:

i)Weightedresistornetworkii)R–2Rladdernetwork.


12.2.1 The Weighted – Resistor Type D/A converter:

The diagram of the weighted – resistor D/A converter is shown in fig 12.3. The operational amplifier is

used to produce a weighted sum of the digital inputs, where the weights are proportional to the weights of

the bit positions of inputs. Since the op-amp is connected as an inverting amplifier, each input is amplified

by a factor equal to the ratio of the feedback resistance divided by the input resistance to which it is

connected. The most significant bit (MSB) i.e. D3 is amplified by Rf / R, D2 is amplified by Rf / 2R, D1 is

amplified by Rf / 4R, and D0, the LSB is amplified by Rf / 8R.

The inverting terminal of the op-amp in fig.12.3 acts a virtual ground. Since the op-amp adds and

inverts.

Vout = -

RR

8D

4D

2D

D f0123

The main disadvantage of this type of D/A Converter is, that a different-valued precision resistor must be

used for each bit position of the digital input.

12.2.2 Binary R – 2R Ladder D/A Converter:

This D/A Converter circuit avoids the above problem and requires only two values of resistors R and 2R

(hence the name R-2R), although each bit position requires two resistors instead of the single resistor per bit

Reference voltage orcurrent

OutputD/A converter

Fig 12.2 D/A Converter–Block diagram

R

2R

4R

8R

(MSB) D3

(LSB) D0

D2

D1

Rf

1

Fig 12.3 Weighted – Resistor Type D/A Converter

I

-+

Vout = -

RR

8D

4D

2D

D f0123

Fig. 3.36. D/A Converter–Block diagram

the WeIGhteD – ResIstOR type D/a cONveRteR

The diagram of the weighted – resistor D/A converter is shown in Fig. 3.37. The operational amplifierisusedtoproduceaweightedsumofthedigitalinputs,wheretheweightsareproportional to the weights of the bit positions of inputs. Since the op-amp is connected as aninvertingamplifier,eachinputisamplifiedbyafactorequaltotheratioofthefeedbackresistancedividedbytheinputresistancetowhichitisconnected.Themostsignificantbit(MSB) i.e. D3isamplifiedbyRf / R, D2isamplifiedbyRf / 2R, D1isamplifiedbyRf / 4R, andD0,theLSBisamplifiedbyRf / 8R.

NOTES

Electronics-1











inverts.

Vout = -

RR

8D

4D

2D

D f0123







OutputD/A converter


R

2R

4R

8R

(MSB) D3

(LSB) D0

D2

D1

Rf

1


I

-+

Vout = -

RR

8D

4D

2D

D f0123

Fig. 3.37. Weighted – Resistor Type D/A Converter

Theinvertingterminaloftheop-ampinfig.3.37actsavirtualground.Sincetheop-

amp adds and inverts.










inverts.

Vout = -

RR

8D

4D

2D

D f0123







OutputD/A converter


R

2R

4R

8R

(MSB) D3

(LSB) D0

D2

D1

Rf

1


I

-+

Vout = -

RR

8D

4D

2D

D f0123

The main disadvantage of this type of D/A Converter is, that a different-valued precision resistor must be used for each bit position of the digital input.

BINaRy R – 2R LaDDeR D/a cONveRteR

This D/A Converter circuit avoids the above problem and requires only two values of resistors

R and 2R (hence the name R-2R), although each bit position requires two resistors instead of

the single resistor per bit position of the binary weighted converter. The-n-bit R-2R ladder

networkwithoutputoperationalamplifierisshowninFig.3.38(a).


position of the binary weighted converter. The-n-bit R-2R ladder network with output operational amplifier

is shown in fig 12.4(a).

The circuit may be analyzed by the use of Thevenin’s theorem.

Assume that S0 = 1, S1 = S2 = ---- Sn-1 = 0. The R- 2R network above the LSB position is then effectively

the load for the circuit which can be redrawn as in Fig.12.4(b). The voltage across the open circuit terminals

is thus V/2 and the value of series resistance is R (as 2R in parallel with 2R). The Thevenin’s equivalent

circuit is always the same as fig.12.4(c) for any bit position (i.e., S1 = 1, S0 = S2 = S3 =……..Sn+1 = 0). To

find the contribution of each bit position to the output voltage, let us redraw the circuit for the 3-bit D/A

Converter and use the Thevenin’s theorem, Fig.12.5 shows the effective Thevenin’s circuits for each bit

position.

We see that the weighted value of voltage of LSB, 1st,2nd …MSB are respectively V ref/2n, Vref/2n-1, V

ref/2n-2 … V ref/2 volts. Therefore for n-bits D/A converter, the Vout at node X is given by

Vout = Vref(S02-n + S12-n-1 + S2 2-(n-2) + …Sn-2 2-2 + Sn-1 2-1) ---------- (12.1)

Vref

v0

2R MSB 3R

2R

2R

2R

2RR

R

R

R

2R

2R

+

–

S0

S1

S2

Sn-2

Sn-1

LSB

Fig 12.4(a) Binary R–2R Ladder D/A Converter.

2R2R R

VrefVref

12

VoutVout

(b) (c)

Fig 12.4(b) (c) Thevenin’s equivalent circuitswith only the LSB – switch.

Fig. 3.38(a). Binary R–2R Ladder D/A Converter.

NOTES

Digital Electronics



position of the binary weighted converter. The-n-bit R-2R ladder network with output operational amplifier

is shown in fig 12.4(a).


Assume that S0 = 1, S1 = S2 = ---- Sn-1 = 0. The R- 2R network above the LSB position is then effectively

the load for the circuit which can be redrawn as in Fig.12.4(b). The voltage across the open circuit terminals

is thus V/2 and the value of series resistance is R (as 2R in parallel with 2R). The Thevenin’s equivalent

circuit is always the same as fig.12.4(c) for any bit position (i.e., S1 = 1, S0 = S2 = S3 =……..Sn+1 = 0). To

find the contribution of each bit position to the output voltage, let us redraw the circuit for the 3-bit D/A

Converter and use the Thevenin’s theorem, Fig.12.5 shows the effective Thevenin’s circuits for each bit

position.

We see that the weighted value of voltage of LSB, 1st,2nd …MSB are respectively V ref/2n, Vref/2n-1, V

ref/2n-2 … V ref/2 volts. Therefore for n-bits D/A converter, the Vout at node X is given by

Vout = Vref(S02-n + S12-n-1 + S2 2-(n-2) + …Sn-2 2-2 + Sn-1 2-1) ---------- (12.1)

Vref

v0

2R MSB 3R

2R

2R

2R

2RR

R

R

R

2R

2R

+

–

S0

S1

S2

Sn-2

Sn-1

LSB

Fig 12.4(a) Binary R–2R Ladder D/A Converter.

2R2R R

VrefVref

12

VoutVout

(b) (c)

Fig 12.4(b) (c) Thevenin’s equivalent circuitswith only the LSB – switch.

Fig. 3.38(b) (c) Thevenin’s equivalent circuits with only the LSB – switch.


Assume that S0 = 1, S1 = S2 = ---- Sn–1 = 0. The R- 2R network above the LSB position is then effectively the load for the circuit which can be redrawn as in Fig.3.38(b). The voltage across the open circuit terminals is thus V/2 and the value of series resistance is R (as 2R in parallelwith2R).TheThevenin’sequivalentcircuitisalwaysthesameasfig.3.38(c)foranybit position (i.e., S1 = 1, S0 = S2 = S3 =……..Sn+1=0).Tofindthecontributionofeachbitposition to the output voltage, let us redraw the circuit for the 3-bit D/A Converter and use the Thevenin’s theorem, Fig.3.39 shows the effective Thevenin’s circuits for each bit position.

WeseethattheweightedvalueofvoltageofLSB,1st,2nd…MSBarerespectivelyVref/2

n, Vref/2n-1, Vref/2n-2 … Vref/2 volts. Therefore for n-bits D/A converter, the Vout at node X is given by

Vout = Vref(S02–n + S12

–n–1 + S2 2–(n–2) + …Sn–2 2

–2 + Sn–1 2–1)

In a common practice an additional resistor 2R is placed to the right of the MSB switch positionsothatthetotalloadlookingintothearrayis3R.Withafeedbackresistorofvalue3R,thegainoftheoperationalamplifieris–1.ThustheoutputofOp-amporofthen-bitR-2R ladder with Op-amp is given by


In a common practice an additional resistor 2R is placed to the right of the MSB switch position so that

the total load looking into the array is 3R. With a feedback resistor of value 3R, the gain of the operational

amplifier is –1. Thus the output of Op-amp or of the n-bit R-2R ladder with Op-amp is given by

V0 = Vref (S02-n + S12-n-1 + S2 2-(n-2) + …Sn-2 2-2 + Sn-1 2-1) ---------- (12.2)

The negative sign corresponds to the inverting property of the Op-amp.

12.2.3 D/A converter Specifications:

(1). Resolution: The resolution is specified as the value of ‘n’ or the number of bits which the D/A

converter can accept. The resolution can also be expressed as % Resolution = 100/(2n – 1)%. Thus 3-bit

D/A converter is of poor resolution. For a better resolution n must be large. The voltage conversion

resolution is generally defined as V ref/2n.

(2). Linearity: An ideal D/A converter would have equal increments of the analog output for equal

increments in the digital input. The deviation from the linear behavior is called non-linearity. It is

expressed as

% Non linearity = 100D/M,

where D is the deviation of measured output from a straight line and M is the output range, usually the non-

linearity is expressed as 21

LSB volts.

(3). Accuracy: The accuracy of a D/A converter is a measure of the difference between the actual analog

output voltage and the ideal output voltage. There are many factors contributing to accuracy including the

R(c)

12

Vref

2RR

RR(b)

12

Vref14

Vref

RR

2R2R 2R

R

R

R R(a)

12

Vref14

Vref18

Vref

Fig 12.5Effective Thevenin’s circuits for (a) MSB,(b) Next MSB and (c) LSB of the 3-bit R–2R D/A Converter.

Fig. 3.39. Effective Thevenin’s circuits for (a) MSB, (b) Next MSB and (c) LSB of the 3-bit R–2R D/A Converter.


In a common practice an additional resistor 2R is placed to the right of the MSB switch position so that

the total load looking into the array is 3R. With a feedback resistor of value 3R, the gain of the operational

amplifier is –1. Thus the output of Op-amp or of the n-bit R-2R ladder with Op-amp is given by

V0 = Vref (S02-n + S12-n-1 + S2 2-(n-2) + …Sn-2 2-2 + Sn-1 2-1) ---------- (12.2)


12.2.3 D/A converter Specifications:

(1). Resolution: The resolution is specified as the value of ‘n’ or the number of bits which the D/A

converter can accept. The resolution can also be expressed as % Resolution = 100/(2n – 1)%. Thus 3-bit

D/A converter is of poor resolution. For a better resolution n must be large. The voltage conversion

resolution is generally defined as V ref/2n.

(2). Linearity: An ideal D/A converter would have equal increments of the analog output for equal

increments in the digital input. The deviation from the linear behavior is called non-linearity. It is

expressed as


where D is the deviation of measured output from a straight line and M is the output range, usually the non-

linearity is expressed as 21

LSB volts.

(3). Accuracy: The accuracy of a D/A converter is a measure of the difference between the actual analog

output voltage and the ideal output voltage. There are many factors contributing to accuracy including the

R(c)

12

Vref

2RR

RR(b)

12

Vref14

Vref

RR

2R2R 2R

R

R

R R(a)

12

Vref14

Vref18

Vref

Fig 12.5Effective Thevenin’s circuits for (a) MSB,(b) Next MSB and (c) LSB of the 3-bit R–2R D/A Converter.


NOTES

Electronics-1


D/a cONveRteR specIFIcatIONs

(1) Resolution: Theresolutionisspecifiedasthevalueof‘n’orthenumberofbitswhich the D/A converter can accept. The resolution can also be expressed as % Resolution = 100/(2n – 1)%. Thus 3-bit D/A converter is of poor resolution. For a better resolution n must be large. The voltage conversion resolution is generally definedasVref/2

n.

(2) Linearity: An ideal D/A converter would have equal increments of the analog output for equal increments in the digital input. The deviation from the linear behavior is called non-linearity. It is expressed as


where D is the deviation of measured output from a straight line and M is the

output range, usually the nonlinearity is expressed as 12

LSB volts.

(3) Accuracy: The accuracy of a D/A converter is a measure of the difference between the actual analog output voltage and the ideal output voltage. There are many factors contributing to accuracy including the linearity of the D/A converter, tolerancesonreferencevoltages,amplifiergains,etc,andabilityofthecircuittoresist noise.

(4) Offset: Forzeroinputtheremaybeafiniteoutput,whichiscalledzeroerror.Thisis quite small and may be offset by adjustment (trimming) at the Op-amp stage.

(5) Gain error: The gain is the ratio of the D/A converter’s full scale output value and the reference input value. The gain error is deviation of actual gain from the designed value. It can be minimized by using external preset resistors.

(6) Response or setting time: Thesettingtimeisdefinedasthetimerequiredfortheoutputtoreachandremainwithin,aspecifiedbandofvoltage(orcurrent)afteraninput change has occurred. It is caused by transients set up by voltage switching and the effects on the stray capacitance in the circuit. It is of the order of nano to micro seconds.

(7) Temperature Sensitivity: Foragivenfixedinputvaluetheoutputanalogvaluevaries with temperature, because of the sensitivity of the reference voltage, the resistors, Op-amp to temperature. It may be as high as ±50 ppm/°C.

3.33 ANALOG – TO – DIGITAL CONVERTERAnalog–to–digital conversion is slightly more complex than digital–to–analog conversion, and a number of different methods may be used. Four common conversion methods are described in this section. Of these, the successive approximation counter is the most widely used A/D converter, because it provides excellent performance for a wide range of applications at a reasonable cost.

NOTES

Digital Electronics


The comparator circuit forms the basis of all A/D converters. This circuit compares an unknown voltage with a reference voltage and indicates which of the two voltages is larger. A comparatorisessentiallyamultistagehighgaindifferentialamplifier,wherethestateoftheoutput is determined by the relative polarity of the two input signals. If, for instance, input signal A is greater than input signal B, the output voltage is maximum and the comparator is on. If input signal A is smaller than input signal B, the output voltage is minimum and the comparatorisoff.Sincetheamplifierhasaveryhighgain,iteithersaturatesorcutsoffatrelatively low differential input levels, so that it acts as a binary device.

sIMuLtaNeOus a/D cONveRteR

Simultaneous A/D converter is shown in Fig. 3.40, where three comparator circuit are used. Each of the three comparators has a reference input voltage, derived from a precision reference voltage source. A resistive divider consisting of four equal precision resistors is

connected across the reference supply and provides output voltages of 34

V, 12

V, and 14

V, where V is the reference output voltage. The other input terminal of each comparator is driven by the unknown analog voltage.


provides output voltages of43

V,21

V, and41

V, where V is the reference output voltage. The other input

terminal of each comparator is driven by the unknown analog voltage.

In this example the comparator is on (providing an output) if the analog voltage is larger than the

reference voltage. If none of the comparators is on, the analog input must be smaller than41

V. If

comparator C1 is on and both C2 and C 3 are off, the analog voltage must be between41

V and21

V.

Similarly, if C1 and C2 are both on and C 3 is off, the analog voltage must be between21

V and43

V; if all

comparators are on, the analog voltage must be greater than43

V. In total, four different output conditions

may exist from no comparators on to all comparators on. The analog input voltage can therefore be resolved

in four equal steps. These four output conditions can be coded to give two binary bits of information. This

is shown in the table alongside the diagram of 12.6. Seven comparators would give three binary bits of

information, fifteen comparators would give four bits, etc.

The advantage of the simultaneous system of A/D conversion is its simplicity and speed of

operation, especially when low resolution is required. For a high – resolution system (a large number of

bits), this method requires so many comparators that the system becomes bulky and very costly.

C1

Off

on

on

on

C2

off

off

on

on

C3

off

off

off

on

Input voltage

0 to 14 V

14 V to

12 V

12 V to 3

4 V

>34 V

C3

C2

C1

R

V

R

R

R12 V

34 V

14 V

Comparatoroutputs

Referencevoltage

Analoginput

Fig 12.6 Simultaneous analog-to-digital converter.Fig. 3.41. Simultaneous analog-to-digital converter.

In this example the comparator is on (providing an output) if the analog voltage is larger than the reference voltage. If none of the comparators is on, the analog input must be

smaller than 14

V. If comparator C1 is on and both C2 and C3 are off, the analog voltage

must be between 14

V and 12

V. Similarly, if C1 and C2 are both on and C3 is off, the analog

voltage must be between 12

V and 34

V; if all comparators are on, the analog voltage must

NOTES

Electronics-1


be greater than 34

V. In total, four different output conditions may exist from no comparators on to all comparators on. The analog input voltage can therefore be resolved in four equal steps. These four output conditions can be coded to give two binary bits of information. This is shown in the table alongside the diagram of 3.41. Seven comparators would give three binarybitsofinformation,fifteencomparatorswouldgivefourbits,etc.

The advantage of the simultaneous system of A/D conversion is its simplicity and speed of operation, especially when low resolution is required. For a high – resolution system (a large number of bits), this method requires so many comparators that the system becomes bulky and very costly.

successIve – appROXIMatION a/D cONveRteR

This is one of the most popular A/D converter and has a resemblance with counter type A/D converter. Fig. 3.42(a) gives the outline of a successive approximation A/D converter.


12.3.2 Successive – approximation A/D Converter:

This is one of the most popular A/D converter and has a resemblance with counter type A/D converter.

Fig 12.7(a) gives the outline of a successive approximation A/D converter.

The converter circuit comprises of a control logic that is used to set or reset the flip-flops X0, X1…..X7.

The output of these flip flops are given to the level amplifiers and then to the binary ladder which provides

the digital output as well as the analog reference voltage.

S RQ7

S RQ6

S RQ5

S RQ4

S RQ3

S RQ2

S RQ1

S RQ0

LEVEL AMPLIFIERS

BINARY LADDER

Controllogic

R–Sflip–flop

N – Lines

N – LinesDigital output

COMP

Analoginput Reference

voltage

Fig 12.7(a) Block diagram of a successive approximation A/D converter

Start0000

1000

1100

0100

1110

0001

0010

1010

0110

1111

1101

1011

0011

1110

0101

0111

1001

1111

1101

1100

1011

10101001

10000111

01100101

0100

0011

0010

0001

0000

Fig 12.7(b) Operation diagram for a 4-bitsuccessive approximation A/D Converter

Fig. 3.42(a). Block diagram of a successive approximation A/D converter

Theconvertercircuitcomprisesofacontrollogicthatisusedtosetorresettheflip-flopsX0, X1…..X7.Theoutputoftheseflipflopsaregiventothelevelamplifiersandthentothe binary ladder which provides the digital output as well as the analog reference voltage.

Initially,thecontrollogicresetsalltheflip-flopsQ0 to Q7. Now its MSB is set to 1 so that digital signal reaching the binary ladder is 1000 0000. Analog voltage produced by binary ladder is now compared with the analog input signal. If the reference signal is smaller than the analog input, the comparator output gives a signal to the control logic which now switches the output of Q6 to 1 so that digital signal becomes 1100 0000 and its equivalent analogvoltageiscomparedwiththeinputsignal.Ontheotherhandifinthefirstcomparison,comparatorfindsthatreferencevoltageismorethantheanaloginput,thenasignalisgivento the control logic to reduce the reference voltage accordingly. Q7 is reset to ‘0’ and Q6 is set to 1. The digital signal now becomes 0100 0000 which is again compared with the analog signal. This process is repeated until analog input and reference voltage produced become equal. At this stage, a stable digital output is produced. The complete approximation

NOTES

Digital Electronics


procedure is illustrated for a four bit successive approximation A/D converter with the help of operation diagram Fig. 3.42(b).


12.3.2 Successive – approximation A/D Converter:

This is one of the most popular A/D converter and has a resemblance with counter type A/D converter.

Fig 12.7(a) gives the outline of a successive approximation A/D converter.

The converter circuit comprises of a control logic that is used to set or reset the flip-flops X0, X1…..X7.

The output of these flip flops are given to the level amplifiers and then to the binary ladder which provides

the digital output as well as the analog reference voltage.

S RQ7

S RQ6

S RQ5

S RQ4

S RQ3

S RQ2

S RQ1

S RQ0

LEVEL AMPLIFIERS

BINARY LADDER

Controllogic

R–Sflip–flop

N – Lines

N – LinesDigital output

COMP

Analoginput Reference

voltage

Fig 12.7(a) Block diagram of a successive approximation A/D converter

Start0000

1000

1100

0100

1110

0001

0010

1010

0110

1111

1101

1011

0011

1110

0101

0111

1001

1111

1101

1100

1011

10101001

10000111

01100101

0100

0011

0010

0001

0000

Fig 12.7(b) Operation diagram for a 4-bitsuccessive approximation A/D Converter

Fig. 3.42(b) Operation diagram for a 4-bit successive approximation A/D Converter

An important feature of successive approximation A/D converter is that an ‘n-bit’ A/D converter requires only ‘n’ clock cycles for conversion. For a 8-bit A/D converter of this type, if a clock frequency of 1MHz is employed, the conversion time is only 8s; which is quite low as compared to counter type or continuous type A/D converter.

Advantages1. It is more accurate than the staircase A/D converter.

2. It maintains a high resolution.

3. It is much faster.

4. Conversion time is much less.

Disadvantages1. It requires a complex register called the successive-approximation register (SAR).

2. It is costly, as it contains more components.

DuaL – sLOpe a/D cONveRteR

The Dual – slope A/D converter is shown in Fig. 3.43.

The basic principle of operation of the circuit can be understood from Fig. 3.39. In Fig. 3.44,wefindthatwechargeacapacitorCforafixedduration.Thismeansthattheintegratorcapacitor will charge to a voltage level depending on the value of the input analog voltage. Now, after the charging interval is over, the integrator capacitor is allowed to discharge at a

NOTES

Electronics-1


constant (uniform) rate through a constant-current circuit. Depending on the level to which the capacitor had been initially charged to, the discharge time varies as shown, and hence the binary counter’s counting time varies. This then reads the input voltage in terms of the count duration. The larger this duration, the more the count.


Initially, the control logic resets all the flip-flops Q0 to Q7. Now its MSB is set to 1 so that digital signal

reaching the binary ladder is 1000 0000. Analog voltage produced by binary ladder is now compared with

the analog input signal. If the reference signal is smaller than the analog input, the comparator output gives

a signal to the control logic which now switches the output of Q6to 1 so that digital signal becomes 1100

0000 and its equivalent analog voltage is compared with the input signal. On the other hand if in the first

comparison, comparator finds that reference voltage is more than the analog input, then a signal is given to

the control logic to reduce the reference voltage accordingly. Q7 is reset to ‘0’ and Q6 is set to 1. The

digital signal now becomes 0100 0000 which is again compared with the analog signal. This process is

repeated until analog input and reference voltage produced become equal. At this stage, a stable digital

output is produced. The complete approximation procedure is illustrated for a four bit successive

approximation A/D converter with the help of operation diagram fig 12.7(b).

An important feature of successive approximation A/D converter is that an ‘n-bit’ A/D converter requires

only ‘n’ clock cycles for conversion. For a 8-bit A/D converter of this type, if a clock frequency of 1MHz is

employed, the conversion time is only 8s; which is quite low as compared to counter type or continuous

type A/D converter.

Advantages:

1. It is more accurate than the staircase A/D converter.

2. It maintains a high resolution.

3. It is much faster.

4. Conversion time is much less.

Disadvantages:-

1. It requires a complex register called the successive-approximation register (SAR).

2. It is costly, as it contains more components.

12.33 Dual – slope A/D Converter:

The Dual – slope A/D converter is shown in fig 12.8

C

R

Integrator

Constant currentsource

Stopcurrent

Count pulse

Binarycounter

Binarycounter

Controllogic

Clockgenerator

Clearpulse

Count over

C

VREF

Fig 12.8 Circuit of dual–slope A/D converter.

V

Fig. 3.43. Circuit of dual–slope A/D converter

In the circuit shown in Fig. 3.44, there is a toggle switch that connects the input data and the constantcurrent generator to the integrator, alternately. The toggle switch is controlled by a control-logic circuit. The output of the integrator, alternately. This toggle switch is controlled by a control-logic circuit. The output of the integrator is applied to a comparator, which gives a stop command once its output exceeds the reference voltage Vref. The control logic controls the clock, start count and clear count pulses of the binary counter, as well as the signal-pole, double-throw (SPDT) toggle switch.


The basic principle of operation of the circuit can be understood from fig 12.9. In Fig 12.9, we find

that we charge a capacitor C for a fixed duration. This means that the integrator capacitor will charge to a

voltage level depending on the value of the input analog voltage. Now, after the charging interval is over,

the integrator capacitor is allowed to discharge at a constant (uniform)

rate through a constant-current circuit. Depending on the level to which the capacitor had been initially

charged to, the discharge time varies as shown, and hence the binary counter’s counting time varies. This

then reads the input voltage in terms of the count duration. The larger this duration, the more the count.

In the circuit shown in fig 12.8, there is a toggle switch that connects the input data and the constant-

current generator to the integrator, alternately. The toggle switch is controlled by a control-logic circuit.

The output of the integrator, alternately. This toggle switch is controlled by a control-logic circuit. The

output of the integrator is applied to a comparator, which gives a stop command once its output exceeds the

reference voltage Vref. The control logic controls the clock, start count and clear count pulses of the binary

counter, as well as the signal-pole, double-throw (SPDT) toggle switch.

At the start command, the integrator starts charging to the level of the input voltage for a fixed interval.

Digital counter is not energized in this interval. At the end of the fixed-time interval the control switch

throws the SPDT switch back to the constant-current generator, and the binary counter starts counting.

When the integrator voltage drops to a value such that Vref > Vint, the comparator stops the count. The

reading on the digital counter represents the value of the input Va.

Advantages:

1. Clock frequency drift is compensated for, as the same clock and integrator are used to perform

conversions during the positive and negative intervals of the count period.

tt1

t2

t3

t3 > t2 > t1

Uniform discharge of capacitorAmplitude

Large Va

Medium Va

Small Va

Fixed timeinterval forcharging ofcapacitor

Fig 12.9 Charge–discharge intervals of integrator.Fig. 3.44. Charge–discharge intervals of integrator

At the start command, the integrator starts charging to the level of the input voltage for afixedinterval.Digitalcounterisnotenergizedinthisinterval.Attheendofthefixed-timeinterval the control switch throws the SPDT switch back to the constant-current generator,

NOTES

Digital Electronics


andthebinarycounterstartscounting.WhentheintegratorvoltagedropstoavaluesuchthatVref > Vint, the comparator stops the count. The reading on the digital counter represents the value of the input Va.

Advantages1. Clock frequency drift is compensated for, as the same clock and integrator are

used to perform conversions during the positive and negative intervals of the count period.

2. The above reason also increases accuracy.

3. Setting the clock rate and reference-input value can give desired scaling of the counter output.

4. The counter can be designed to be in binary, BCD, or any other desired display form.

5. Low conversion time.

Disadvantages1. Complicated circuitry

2. Higher cost.

cOuNteR type a/D cONveRteR

The principle is to adjust the D/A converter’s input code until the D/A converter’s output comes within (1/2) LSB to the analog input Va which is to be converted to binary digital form. Thus in addition to the D/A converter, we need suitable logic circuitry to perform the code search and a comparator of adequate quality to announce when the D/A converter output has come within (1/2) LSB to Va.


2. The above reason also increases accuracy.

3. Setting the clock rate and reference-input value can give desired scaling of the counter output.

4. The counter can be designed to be in binary, BCD, or any other desired display form.

5. Low conversion time.

Disadvantages:-

1. Complicated circuitry2. Higher cost.

12.3.4 Counter Type A/D Converter: The principle is to adjust the D/A converter’s input code until the

D/A converter’s output comes within (1/2) LSB to the analog input Va which is to be converted to binary

digital form. Thus in addition to the D/A converter, we need suitable logic circuitry to perform the code

search and a comparator of adequate quality to announce when the D/A converter output has come within

(1/2) LSB to Va.

A 3-bit counting A/D Converter based upon the above principle is shown in Fig.12.10 (a). The counter is

reset to zero count by the reset pulse. Upon the release of RESET, the clock pulses are counted by the

binary counter. These pulses go through the AND gate which is enabled by the voltage comparator high

output. The number of pulses counted increase with time. The binary word representing this count is used

as the input of a D/A converter whose output is a staircase of the type shown in Fig.12.10(b). The analog

output Vd of D/A converter is compared to the analog input Va by the comparator. If Va > Vd, the output of

the comparator becomes high and the AND gate is enabled to allow the transmission of the clock pulses to

the counter. When Va < Vd, the output of the comparator becomes low and the AND gate is disabled. This

stops the counting at the time Va Vd and the digital output of the counter represents the analog input

voltage Va. For a new value of analog input Va, a second reset pulse is applied to clear the counter. Upon

the reset, the counting begins again as shown in Fig 12.10(b). The counter frequency must be low enough to

give sufficient time for the D/A converter to settle and for the comparator to respond. Low speed is the

Va

Analog input

–+

Reset

Clock

Vd

Comparator

Binarycounter

D/A converter

Digitaloutput

MSB

LSB

Fig 12.10(a) A counter type A/D converter.Fig. 3.45(a) A counter type A/D converter

A 3-bit counting A/D Converter based upon the above principle is shown in Fig.3.45 (a). The counter is reset to zero count by the reset pulse. Upon the release of RESET, the clock pulses are counted by the binary counter. These pulses go through the AND gate which is enabled by the voltage comparator high output. The number of pulses counted increase with time. The binary word representing this count is used as the input of a D/A converter

NOTES

Electronics-1


whose output is a staircase of the type shown in Fig.3.45(b). The analog output Vd of D/A converter is compared to the analog input Va by the comparator. If Va > Vd, the output of the comparator becomes high and the AND gate is enabled to allow the transmission of the clockpulsestothecounter.WhenVa < Vd, the output of the comparator becomes low and the AND gate is disabled. This stops the counting at the time Va Vd and the digital output of the counter represents the analog input voltage Va. For a new value of analog input Va, a second reset pulse is applied to clear the counter. Upon the reset, the counting begins again asshowninFig.3.45(b).Thecounterfrequencymustbelowenoughtogivesufficienttimefor the D/A converter to settle and for the comparator to respond. Low speed is the most serious drawback of the method. The conversion time can be as long as (2n-1) clock periods depending upon the magnitude of input voltage Va. For instance, a 12-bit system with 1 MHz clock frequency, the counter will take (212-1)s = 4.095 ms to convert a full scale input.


most serious drawback of the method. The conversion time can be as long as (2n-1) clock periods depending

upon the magnitude of input voltage Va. For instance, a 12-bit system with 1 MHz clock frequency, the

counter will take (212-1)s = 4.095 ms to convert a full scale input.

If the analog input voltage varies with time, the input signal is sampled, using a sample and hold circuit

before it is applied to the comparator. If the maximum value of the analog voltage is represented by n-

pulses and if the clock period is T seconds, the minimum interval between samples is nT seconds.

12.35 A/D Converter Specifications:

(i) Analog input voltage:- This is the maximum allowable input voltage range.

(ii) Resolution:- It is the voltage charge at the input needed for 1 bit charge at the

output. It is the resolution of D/A converter which is in A/D Converter, which is

also known as the “quantization error”. Thus all 8-bit A/D Converter has better

resolution thus that of 4-bit A/D Converter.

(iii) Accuracy:- The accuracy of all A/D Converter is the maximum deviation of the

digital output from the ideal linear curve. It depends upon the accuracy of its

circuit elements, such as the D/A converter, comparator and reference supplies.

This is in addition to the quantization error and is in general temperature

dependent.

Vd

volts

Va

Counterstops

0 1 2 3 4 5 6 7 8 9 10 210

ClockReset

Endreset

BeginReset

Endreset

Fig 12.10(b) D/A output staircase waveform.Fig. 3.45(b) D/A output staircase waveform.

If the analog input voltage varies with time, the input signal is sampled, using a sample and hold circuit before it is applied to the comparator. If the maximum value of the analog voltage is represented by npulses and if the clock period is T seconds, the minimum interval between samples is nT seconds.

3.34 A/D CONVERTER SPECIFICATIONS(i) Analog input voltage: This is the maximum allowable input voltage range.

(ii) Resolution: It is the voltage charge at the input needed for 1 bit charge at the output. It is the resolution of D/A converter which is in A/D Converter, which is also known as the “quantization error”. Thus all 8-bit A/D Converter has better resolution thus that of 4-bit A/D Converter.

(iii) Accuracy: The accuracy of all A/D Converter is the maximum deviation of the

NOTES

Digital Electronics


digital output from the ideal linear curve. It depends upon the accuracy of its circuit elements, such as the D/A converter, comparator and reference supplies. This is in addition to the quantization error and is in general temperature dependent.

(iv) Conversion time: Itisdefinedasthetimebetweentwosuccessiveconversionsatthe maximum possible rate. It depends upon the analog voltage, clock frequency and number of bits.

3.35 SAMPLE & HOLD CIRCUITThesample-and-holdcircuitisbasicallyanoperationalamplifierthatchargesacapacitorduring the sample mode and retains the charge of the capacitor during the hold mode. The sample-andholdcircuitcanberepresentedbythesimpleswitchandcapacitoroffig.3.46.


(iv) Conversion time:- It is defined as the time between two successive conversions

at the maximum possible rate. It depends upon the analog voltage, clock

frequency and number of bits.

12.4 Sample & Hold Circuit:-

The sample-and-hold circuit is basically an operational amplifier that charges a capacitor during

the sample mode and retains the charge of the capacitor during the hold mode. The sample-and-

hold circuit can be represented by the simple switch and capacitor of fig.12.11

When the switch is first closed, the capacitor charges to the value of the input voltage and then

follows the input (assuming a low driving source impedance). When the switch is opened, the

capacitor holds the voltage that it had at the time the switch was opened (assuming a high-

impedance load).

The acquisition time of the sample-and-hold is the time required for the capacitor to charge up

to the value of the input signal after the switch is first shorted. The aperture time is the time

required for the switch to change state and the uncertainty in the time that this change of state

occurs. The holding time is the length of time the circuit can hold the charge without dropping

more than a specified percentage of its initial value.

t

Vin

Fig 12.11(b) Input waveform

C

Vout

SVin

Switchdrive

Fig 12.11(a) Circuit

t

Fig 12.11(c) Operation of the sample-and-hold circuit.

Vout

HoldSample

Fig. 3.46(a) Circuit












impedance load).






t

Vin


C

Vout

SVin

Switchdrive


t


Vout

HoldSample

Fig. 3.46(b) Input waveform












impedance load).






t

Vin


C

Vout

SVin

Switchdrive


t


Vout

HoldSample

Fig. 3.46(c) Operation of the sample-and-hold circuit.

Whentheswitchisfirstclosed,thecapacitorchargestothevalueoftheinputvoltageandthenfollowstheinput(assumingalowdrivingsourceimpedance).Whentheswitchis opened, the capacitor holds the voltage that it had at the time the switch was opened (assuming a highimpedance load).

NOTES

Electronics-1


The acquisition time of the sample-and-hold is the time required for the capacitor to chargeuptothevalueoftheinputsignalaftertheswitchisfirstshorted.Theaperturetimeis the time required for the switch to change state and the uncertainty in the time that this change of state occurs. The holding time is the length of time the circuit can hold the charge withoutdroppingmorethanaspecifiedpercentageofitsinitialvalue.

It is possible to build a sample-and-hold circuit exactly as shown in Fig.3.48. However the sample-and-hold circuit is built, it always acts as the simple switch and capacitor shown.


It is possible to build a sample-and-hold circuit exactly as shown in Fig.12.11. However the

sample-and-hold circuit is built, it always acts as the simple switch and capacitor shown.

An actual sample-and-hold circuit is shown in the schematic diagram of Fig.12.12. The sample

pulse operates switches 1 and 3; the hold pulse operates switches 2 and 4. The sample-and-hold

control pulses are complementary. In the sample mode, the hold capacitor is charged up by the

operational amplifier. In the hold mode the capacitor is switched into the feedback loop, while the

input resistor R, and the feedback resistor Rf are switched to ground. Since the input to the

amplifier remains within a few V to ground (except during switching), the input impedance is

10k in both the sample and the hold modes.

12.5 Summary:-

Digital to analog conversion is the process of converting a value represented in a digital

code to a voltage or current proportional to the digital value.

The output of a D/A converter can be either a voltage or current.

D/A converter essentially requires resistors, electronic switches and op-amp.

A weighted resistor D/A converter requires a wide range of resistor values for better

resolution where as, an R-2R ladder D/A converter requires only two values of resistors.

The R-2R ladder type D/A converter is the most popular D/A converter.

Analog to digital conversion is the process of converting an analog input voltage to a

number of equivalent digital output levels.

Output

Input

Switches 1 24

3

Sample

Hold

HoldCapacitorC

Ri Rf

10 K 1

9.5 K 1

1 K

Fig 12.12 Sample–and–hold circuitFig. 3.47. Sample–and–hold circuit

An actual sample-and-hold circuit is shown in the schematic diagram of Fig.3.47. The sample pulse operates switches 1 and 3; the hold pulse operates switches 2 and 4. The sample-and-hold control pulses are complementary. In the sample mode, the hold capacitor ischargedupbytheoperationalamplifier.Intheholdmodethecapacitorisswitchedintothe feedback loop, while the input resistor R, and the feedback resistor Rf are switched to ground.SincetheinputtotheamplifierremainswithinafewV to ground (except during switching), the input impedance is 10k in both the sample and the hold modes.

3.36 SUMMARYDigital electronics mainly deals with binary number system. Binary number system has a base of 2. It has two numerals 0 and 1. Any big number can be expressed in the form of 0s and 1s. In a digital system, logic 1 means high positive signal value, logic 0 means low positive signal value in a positive logic system. But in a negative logic system, zero value represents logic 1 and a negative value represents logic ‘0’. Digital electronics mainly depends on Boolean algebra and logic gates. Using the gates, one can construct bit circuits that can perform complex operations. These gates possess, in general, 2 or more inputs and only one output.

NOT, OR and AND are the basic logics and circuits used to implement higher logic. However semiconductor technology prefers NAND and NOR logic gates. Using only NAND or using only NOR gates other logic gates can be constructed. Because of this reason, NAND

NOTES

Digital Electronics


and NOR are called Universal logic gates.

DeMorgan’s first theorem says that aNOR gate and bubbled inputANDgateare equivalent. Similarly De Morgan’s second theorem says that a NAND gate and bubbled input OR gate are equivalent. If Boolean expressions are given, one can construct logic circuits. On the other hand if logic circuits are given, one can write the Boolean expressions. Logic gates can be fabricated using various Semiconductor technologies like TTL, NMOS, and CMOS etc. Each technology has its own advantages. Logiccircuitscanbeeithercombinationalorsequential.Thefivebasicgates(OR,AND,NOT, NAND,

NOR) and their combinations – half, full and parallel adders are known as combinational logic circuits.

Here there is no feedback. These have no memory elements. Their output only depends upon their present input. Thus can operate as fast as the devices of which they are made. Half and full adders are bit adders, where as parallel adder is an adder of two n – bit word. The function performed by a multiplexer is to select 1 out of N input data sources and to transmit the selected data to a single information channel. A multiplexer performs the increase process of a demultiplexer. A decoder is a system which 1 on one (and only one) of 2m output lines. In other words, a decoder recognizes a particular code, A decodes with an enable input can function as a demultiplexer. An encoder produces reverse operation from that of a decoder.

The combinational logic circuits are mainly employed in ALUS.

Aflip-flopisthebasicmemoryelement;itcanstorea‘0’ora‘1’.Aflipflopisknownmore formally as a bistable mutivibrator. It has two stable states. Flip-Flops are used for data storage, counting, frequency division, parallel-to –serial and serial-toparallel data conversion, etc.Anunclockedflip-flopiscalledalatch,becausetheoutputoftheflip-floplatchesontoa 1 or a 0 immediately after the input is applied.

The clocked D latch is called a transparent D latch, because its output follows the input when the clock is HIGH. The J-K Flip-Flop is the most versatile and most widely used of all theflip-flops.Tflip-flopsarenotwidelyavailableascommercial items.Themaster-slaveflip-flopismadeupoftwoflip-flops-amasterandslave.Itwasdevelopedtomakesynchronousoperationofflip-flopsmorepredictablebyovercomingtheproblemofraceinclockflip–flops.AregisterisasetofFFsusedtostorebinarydata.Aregisterinwhichshifting of data takes place is called a shift register. In a serial - in, serial - out, shift register, data is fed in serially, that is one bit at a time on a single line and data is also shifted out serially. In a serial-in, parallel-out, shift register, data is fed in serially but data is shifted out in parallel form, that is all bits at a time. In a parallel-in, serial-out, shift register, data is fed in, in parallel form but shifted out in serial form.

In a parallel – in, parallel – out, shift register, data is both fed in and shifted out in parallel form. In a universal shift register, data can be shifted from left – to – right or right –to – left and also data can be shifted in or shifted out in serial form or in parallel form. Shift registers are used in digital system to provide time delays. They are also used for serial

NOTES

Electronics-1


/ parallel data conversion and in construction of ring counters. A digital counter is a set of FFS whose states change in response to pulses applied at the input to the counter. Counters may be asynchronous counters or synchronous counters. Asynchronous counters are also called ripple counters.

In asynchronous counters, all the FF s do not change states simultaneously. They are serial counters. In synchronous counters, all the FF s change state simultaneously. They are parallel counters. In asynchronous counters if the clock frequency is very high owing to accumulation of propagation delay, skipping of states may occur. In synchronous counters, the propagation delays of individuals FF s do not add together. Synchronous counters have the advantages of high speed and less severe decoding problems, but the disadvantage of more circuitry than that of asynchronous counters. Generation of pulse trains using indirect logic has the advantage that any counter (ripple or synchronous) with the correct number of states can form the generator.

Digital to analog conversion is the process of converting a value represented in a digital code to a voltage or current proportional to the digital value. The output of a D/A converter can be either a voltage or current. D/A converter essentially requires resistors, electronic switches and op-amp. A weighted resistor D/A converter requires a wide range of resistor values for better resolution where as, an R-2R ladder D/A converter requires only two values of resistors. The R-2R ladder type D/A converter is the most popular D/A converter. Analog to digital conversion is the process of converting an analog input voltage to a number of equivalent digital output levels.

An A/D Converter produces a digital output proportional to the value of the input analog signal. A/D converts are either direct type or indirect type. Most direct type A/D Converter’s require a D/A converter. The important direct A/D Converter techniques are counting type, parallel comparator and successive approximation technique. The important indirect A/D Converter techniques are Dual slope A/D Converter and charging balancing A/D Converter and dual slope A/D Converter. Successive approximation type A/D Converter is the most versatile. It completes n-bit conversion in just n-clock periods. Most monolithic A/D Converter’s are successive approximation type.

Dual slope converters are suitable for precise measurement of slowly varying signals. All digital voltmeters use dual-slope A/D Converter. The disadvantage is of long conversion time. Monolithic dual slope A/D Converter’s are available in microprocessor compatible and display – oriented versions. The successive – approximation type A/D Converter is the most widely used type of A/D Converter. The important converter characteristics are: Resolution, linearity, Accuracy, monotonocity, settling time, stability etc.

3.37 KEYWORDSzz Gate: An electronic circuit with one or more inputs but with only one output.

zz Logic Gate: As the gates simulate mental processes, these are often called Logic Gates.

NOTES

Digital Electronics


zz Universal Gate: The gate with which other logic circuits / gates can be constructed (Ex: NAND, NOR)

zz Boolean Algebra: The modern algebra that uses the set of numbers 0 and 1.

zz Complement: The output of an inverter gate.

zz Truth table: A table that shows all input and output possibilities for a logic circuit.

zz Word: A string of bits that represent a coded instruction or data.

zz Fan – in: The maximum number of inputs that can be applied to a logic gate.

zz Fan – out: The number of gates that can be driven by a logic gate.

zz Binary Adder: A logic circuit that can add two binary numbers.

zz Half Adder: A logic circuit that adds 2 bits.

zz Full Adder: A logic circuit than can add 3 bits.

zz Over flow: As the sum or difference that of lies outside the normal range.

zz ALU: ALU stands for arithmetic logic unit. It performs arithmetic one logic operations.

zz Encoding: The process of generating binary codes.

zz Decoding: The reverse process of encoding.

zz Demultiplexer: A combinational logic circuit, that accepts a single input and sends it to 1 out of N output lines which is selected by select lines.

zz Flip – Flop: A memory device capable of storing a logic level.

zz D flip-flop: A type of bit table , multi vibrator in which the output follows the state of the D Input.

zz Register: Agroupofflip–flopscapableofstoringdata.

zz Shift Register: A digital circuit capable of storing and shifting binary data.

zz Universal shift register: Shift – right, shift – left, shift register which can input and output data either serially or parallely.

zz Counter: A digital circuit capable of counting electronic events, such as pulses, by processing through a sequence of binary states.

zz Asynchronous counter: A type of counter in which the external clock signal is appliedonlytothefirstFFandtheoutputofeachFFservesastheclockinputtothe next FF in the chain.

zz Synchronous counter: A counter in which the circuit out puts can change state only on the transitions of a clock.

zz Binary counter: A counter in which the states of FF s represent the binary number equivalent to the number of pulses that have occurred at the input of the counter.

NOTES

Electronics-1


zz Ripple counter: AcounterinwhichtheexternalclocksignalisappliedtothefirstFFand then the clock input to every other FF is the output of the preceding FF.

zz A/D Converter: The circuit, which converts all

zz D/A Converter: The circuit, which converts a digital input into an analog output.

zz Linearity error: The maximum deviation in step size from the ideal step size in D/A converter.

zz Percentage Resolution: The ratio of the step size to the full-scale value of a D/A converter. Itcanalsobedefinedas thereciprocalof themaximumnumberofsteps of a D/A converter.

zz Resolution: In a D/A converter, the smallest that can occur in the output for a change in the digital input. It is also called the step size. In all A/D Converter, the smallest amount by which the analog input must change to produce a change in the digital output.

zz Monotonicity: A property whereby the output of a D/A converter either increase or stays at the same value, but never decrease as the input is increased.

3.38 REVIEW QUESTIONS1. Prove the De Morgan’s Theorems.

2. Draw the truth table of 3 – input, EX – OR gate.

3. Draw the truth table of 4 – input NOR gate.

4. WhatistheBooleanequationofthefiguregivenbelow?


9.8 Self – assessment questions:

1. Prove the De Morgan’s Theorems.

2. Draw the truth table of 3 – input, EX – OR gate.

3. Draw the truth table of 4 – input NOR gate.

4. What is the Boolean equation of the figure given below?

5. Draw the logic circuits of the Boolean expressions given below.

(i)Y = A . B + B . C + C.A

(ii) Y = A . B . C + B.A + C.B

(iii) Y = BCA . ACB

6. Apply De Morgan’s Laws to the following expressions.

B.BA , C.BA , D.CB.A

9.9 Reference books:

1. Principles of Digital Electronics – Malvino & Leach (Tata - McGraw Hill Publishers)

2. Digital Electronics – William H. Gothman. (P.H.I publishers)

3. Digital Computer Electronics – Albert Paul Malvino. (Tata - McGraw Hill publishers)

Name of the Author

Dr B.V.S Goud,

Associate Professor and Head,

Department of Electronics and Instrumentation Technology

Acharya Nagarjuna University

Nagarjuna Nagar.

Y =

5. Draw the logic circuits of the Boolean expressions given below.(i) Y = A . B + B . C + A.C(ii) Y = A . B . C + A.B +B.C(iii) Y=ACB.ACB

6. Apply De Morgan’s Laws to the following expressions.

AB.B,AB.C,A.BC.D

7. Explain is a binary addition. Give examples.

8. Whatisafulladder?Howitadds3bits?

9. Draw a full adder circuit, without using half adders.

10. Construct a 5-bit parallel adder.

11. Implement a full adder circuit with multiplexers.

NOTES

Digital Electronics


12. Distinguish between combinational and sequential switching circuits

13. Howdoyoubuildalatchusinguniversalgates?

14. ExplaintheoperationofclockedSRflip-flop.

15. Listthedifferenttypesoflatchesandflip-flops.Nametheapplicationsofeachtype.

16. HowdoesaJ-Kflip–flopdifferfromanS-Rflip-flopinitsbasicoperation?WhatisitsadvantageoveranS-Rflip–flop?

17.Whatdoyoumeanbytoggling?

18.Whatisaserial-in,serial-out,shiftregister?Explaintheoperationofit.

19.Whatisaparallel-in,serial-out,shiftregister?Explaintheoperationofcircuit.

20.Whatisaserial–in,parallel-out,shiftregister?Explaintheoperationofthecircuit.

21.Whatisaparallel–in,Parallel–out,shiftregister?Explaintheoperationofthecircuit.

22.Whatisauniversalshiftregister?Explaintheoperationofthecircuit.

23.Whatisthebasicdifferencebetweenacounterandashiftregister?

24.Whatistheadvantageofasynchronouscounteroverasynchronouscounter?Whatisitsdisadvantage?

25. Explain the operation of 4-bit Asynchronous Binary counter.

26. Explain the operation of Decade counter.

27.Whatissynchronouscounter?Explaintheoperationof3-bitsynchronousbinarycounters.

28. Explain the operation of synchronous decade counter.

29.WiththehelpofneatdiagramsexplaintheworkingofR-2Rladdertypedigitalto analog converter.

30.WhatistheadvantageoftheR-2RladderD/AconverterovertheweightedresistortypeD/Aconverter?.

31. Explain the operation of Dual-slope A/D Converter.

32. Explain the operation of successive – approximation type A/D Converter.

33. ExplaintheimportantspecificationsofD/AandA/Dconverters.

34. Give two advantages and one disadvantage of the dual – slope A/D Converter.

35. Explain the operation of counter – type A/D Converter.

3.39 FURTHER READINGSzz Principles of Digital Electronics – Malvino & Leach (Tata - McGraw Hill

Publishers)

zz DigitalElectronics–WilliamH.Gothman.(P.H.Ipublishers)

NOTES

Electronics-1


zz Digital Computer Electronics – Albert Paul Malvino. (Tata - McGraw Hill publishers)

zz Integrated Electronics – Millman and Halkias

zz Principles of digital Electronics – Malvino and Leach.

zz Digital Logic and Computer Design – M. Morris Mano, Prentice Hall Inc,.

zz Digital Fundamentals – 3rd Edition – Floyd, UBS Publishers.

zz Digital Electronics: An Introduction to Theory and Practice, 2nd edn., Prentice – Hall of India, New Delhi, 1987.

zz Switching and Finite Automatic Theory, 2nd edn., Tata -McGraw – Hill, New Delhi, 1978.

zz Tokheim, T., Digital Principles, Tata -McGraw – Hill, New Delhi, 1988.

zz Op-amps and linear Integrated circuit Technology, Gayakwad, R.A., Prentice-Hall India Ltd., New Delhi.

zz Digital Circuit and Logic design, Lee, S.C., Prentice – Hall of India Ltd., New Delhi.

zz Digital Integrated Electronics, Taub & Schilling, McGraw Hill, New York.

zz Linear Integrated circuits, Roy Choudhury, Shail Jain. New Age International (p) Limited, Publishers. New Delhi.

NOTES

Intel 8085 Microprocessor


CHAPTER – 4

INTEL 8085 MICROPROCESSORSTRUCTURE

4.1 Learning Objectives 4.2 Introduction 4.3 Introduction to Microcomputer 4.4 Architecture of 8085 Microprocessor 4.5 Addressing Modes 4.6 Instruction Set 4.7 Writing and Executing an AL Program 4.8 Illustrative Programs 4.9 Developments in Microprocessors and Applications 4.10 Summery 4.11 Keywords 4.12 Review questions 4.13 Further Readings


zz To understand what a microprocessor is and what are its applications

zz To understand what is a microcomputer system.

zz To understand the function of various parts of 8085 microprocessor and its internal architecture.

zz To understand the propose of various pins and the bus-timings of 8085

zz To acquire knowledge about various groups of instructions and addressing modes.

zz To understand what is an assembly language.

zz To know, what is an assembly language (AL) program.

zz To know how to write an AL program and how to execute it.

zz To learn about flow charting

zz To know the latest developments.

NOTES

Electronics-1


4.2 INTRODUCTIONThe latest development in the field of computer technology is the microprocessor, which is

the central processing unit of a microcomputer. The microprocessors are the outcome of the

trend towards smaller computers, which started in the middle of 1960s. The microprocessors

appeared in 1970s and had made a remarkable progress in recent years. It has numerous

applications such as industrial control, military applications, consumer and commercial

equipment etc.

The Central Processing Unit (CPU) of a digital computer built on a single semiconductor

chip using LSI or VLSI technology is called a microprocessor. A digital computer whose

CPU is a microprocessor, is called a Microcomputer.

The first microprocessor INTEL 4004, introduced in 1971 by INTEL corporation, was an instant success. Several applications were developed using this programmable device. In quick succession, several processors with enhanced address bus size, improved instruction set were introduced into the market. INTEL 8080, 8085A, Zilog 80 (Z80), 6500, 6800 are examples of popular 8-bit processors.

Unlike several other manufactures, the INTEL corporation supplied detailed instruction set, technical details and developed a kit for learning about 8085 microprocessor. The 16-bit processors of INTEL namely 8086 and 8088 are similar members with similar internal architecture. IBM adopted INTEL processors as CPUs in its brand of personal computers. Further, all over the world INTEL 8085 is being used as model to acquaint about processors and various interfacing aspects. So, it is still in circulation and we will learn about this processor in this lesson.

Microprocessors are programmable devices like computers. In fact they are the CPUs of present day personal computers. For computers, high level languages are preferred. High level languages, how much versatile they are, do not allow the users to middle with hardware. So to deal with hardware and to create code to produce special effects needed by the individuals it becomes necessary to program the processor in its machine code. Machine codes are binary codes written in terms of 1s and 0s only. As it is very difficult to understand binary codes, English like assembly language were developed. Assembly language usually consists of mnemonics and hexadecimal numbers. Assemblers which convert assembly language programs written in terms of mnemonics and hexadecimal code to machine language also were developed. Assembly language programs can also be written manually on paper and entered in the program area of memory of a microprocessor system. One disadvantage with assembly language is that it is not portable. It means programs written in the code of one processor cannot be used for another processor. If two 8085 systems differ in their memory map, then also the code cannot be transported and run directly.

NOTES



INTEL developed microprocessors which have 8086 mode of working. Assembly language programs written with 8086 can be run on all upgraded versions of 8086, above 8086 to Pentium. Writing ALP for 8086 is difficult for the biginners.To understand programming techniques for writing ALPs, 8085 is convenient. In this lesson details about assembly language programming of 8085 are given.

Program is a set of instructions written in a specific sequence to accomplish a task.

A set of programs written for a particular computer is known as software for that computer. A program written using `0’s and ‘1’s is called a machine language program. If the program is written using mnemonics, then it is called Assembly Language (AL) program. Here the term mnemonic represents the shorthand form of English words for the operation performed by the instruction. For example ADD, SUB, MOV are the mnemonics for the addition, subtractions, movement of data respectively. The AL program written using mnemonics is then converted into machine language either by manual translation with the help of binary for each instruction given in the manufacturer’s data books or by using a special program called assembler. The assembler is a program, that translates an AL program written mnemonics into a machine language program. The assembler performs various functions such as error checking and memory allocation.

4.3 INTRODUCTION TO MICROCOMPUTERComputer being a general purpose device, can be used in different varieties of applications – word processing, computation or controlling industrial process are few of them. But the microcomputers, as the name implies, are small computers having limited capacity, are used for specific applications.

Figure (4.1) shows a block diagram of a simple micro computer consists of a CPU, memory, input and output devices.

M.Sc. Physics 2 Intel 8085 Microprocessor

The first microprocessor INTEL 4004, introduced in 1971 by INTEL corporation, was an instant

success. Several applications were developed using this programmable device. In quick succession, several

processors with enhanced address bus size, improved instruction set were introduced into the market.

INTEL 8080, 8085A, Zilog 80 (Z80), 6500, 6800 are examples of popular 8-bit processors.

Unlike several other manufactures, the INTEL corporation supplied detailed instruction set, technical

details and developed a kit for learning about 8085 microprocessor. The 16-bit processors of INTEL namely

8086 and 8088 are similar members with similar internal architecture. IBM adopted INTEL processors as

CPUs in its brand of personal computers. Further, all over the world INTEL 8085 is being used as model to

acquaint about processors and various interfacing aspects. So, it is still in circulation and we will learn

about this processor in this lesson.

13.2 Introduction to microcomputer:

Computer being a general purpose device, can be used in different varieties of applications – word

processing, computation or controlling industrial process are few of them. But the microcomputers, as the

name implies, are small computers having limited capacity, are used for specific applications.

Figure (13.1) shows a block diagram of a simple micro computer consists of a CPU, memory, input and

output devices.

The function of a microcomputer is receiving data and information and processing it. It means

performing arithmetic are logical computations on data, store the results or data or information in memory

and display the results of the computation.

The means used to receive data are known as input devices. Some of the input device are: keyboards,

switches, mouse etc. A device which performs computations is known as arithmetic logic unit (ALU). In

CPU

Address Bus

Memory Input

device

Outputdevice

Data Bus

Control Bus

Fig 13.1 Block diagram of a simple microcomputerconsists of a CPU

Fig. 4.1. Block diagram of a simple microcomputer consists of a CPU

The function of a microcomputer is receiving data and information and processing it. It means performing arithmetic are logical computations on data, store the results or data

NOTES

Electronics-1


or information in memory and display the results of the computation. The means used to receive data are known as input devices. Some of the input device are: keyboards, switches, mouse etc. A device which performs computations is known as arithmetic logic unit (ALU). In microcomputers, this task , together with control of all devices is performed by a single chip called microprocessors. Some of the well-known microprocessors are: 8085, 8086, Z80, 650Z etc. Storage of data instructions is accomplished using memories. Cassettes, floppy disks, CD ROMs, semiconductor memories are some examples for memories. Presenting of results is done by output devices. Commonly used output devices are monitor (VDU), printers, Seven segment LED displays, LCDs. Figure (13.1) gives a block diagram of a typical microcomputer.

Various peripherals-I/o devices, memories etc – are connected to the microprocessor by means of three types of buses: Address bus, data bus and control bus. A bus is a group of conducting wires.

Over the address bus, the microprocessor transmits the address of the device, with which it desires to communicate (access). The number of devices or memory locations that a CPU can address is determined by the number of address lines. For example, a CPU with 16 address lines can address 216 or 65,536 or 64K(210 = 1024 = 1K) locations. This bus is unidirectional. It means information can flow in one direction only. The CPU sends the address information on these lines.

Over the data bus, CPU can read in or writes out the data to various memory or I/O devices. Therefore, this bus is bi-directional. Normally data bus widths of sizes 8, 16, 32 etc. are used.

Contol bus may consist of some input lines, some output lines and some bi-directional lines depending upon the processor. CPU sends out some control signals like memory read, I/O write etc that are necessary for memory and I/O devices to work.

4.4 ARCHITECTURE OF 8085 MICROPROCESSORThe internal logic design of the microprocessor is called its architecture, determines how and what various operations are performed by the microprocessor. As shown in the block diagram (figure 4.2), it consists of arithmetic and logic unit ALU, register section, a timing and control unit and other sections like address / date bus buffers, interrupt control and serial I / O control.

RegisteR section:Inside the 8085, there are several internal registers, which are used for executing a program.

1. Accumulator: It is also designated as register ‘A’ or Acc. It is an 8-bit register used for executing various arithmetic and logical operations. In executing many of the instructions, one of the operands must be in Acc. The accumulated result will also be in Acc, as the name ‘Accumulator’ implies. For example, during the

NOTES



addition of two 8-bit integers, one of the operands must be in Acc and the result also stored in Acc. In the I/O mapped I/O mode of data transfer communication with external devices takes place via Accumulator. To send data to output devices in I/O mapped I/O mode the 8-bit data to be sent must be kept in Acc before give OUT instruction. Similarly IN instruction transfers data from input port addressed to Acc.

2. General purpose registers: The 8085 has six general purpose 8-bit registers labeled as B, C, D, E, H and L. They can be used individually to store 8-bit information or can be used in pairs to hold 16-bit information or data or address. When used in pairs, only contains combinations viz., B – C, D – E and H – L are permitted. These registers are programmable, means that a programmer can use them to load or transfer data from the registers by using instructions.


In the I/O mapped I/O mode of data transfer communication with external devices takes place via

Accumulator. To send data to output devices in I/O mapped I/O mode the 8-bit data to be sent must be

kept in Acc before give OUT instruction. Similarly IN instruction transfers data from input port

addressed to Acc.

b) General purpose registers: The 8085 has six general purpose 8-bit registers labeled as B, C, D, E, H

and L. They can be used individually to store 8-bit information or can be used in pairs to hold 16-bit

information or data or address. When used in pairs, only contains combinations viz., B – C, D – E

and H – L are permitted. These registers are programmable, means that a programmer can use them

to load or transfer data from the registers by using instructions.

c) Program Counter (PC): PC is a 16-bit register used to point the memory address from which the

next instruction is to be fetched. Some times it is also called memory pointer. The contents of the

PC is automatically incremented by the microprocessor during the execution of the instruction, so

that at the end of execution of the present instruction it points to the address of the next instruction

in the memory.

To control bus To control bus

Serial I/Ocontrol unit

Interruptcontrol unit

Accumulator (8)

Temp.Register

(8)Flags

5

Instructionregister

(8)

Incrementer/Decrementer address Latch

RegisterArray

B (8)D (8)H (8)

C (8)E (8)L (8)

SP (16)PC (16)

8–bit internal data bus

ALU (8)Instruction

decoder(8)

AddressBuffer

Address / DataBuffer

Control Bus

Timing and control unit

A15–A8address bus

AD7– AD0 ADDRESSDATA BUS

Fig 13.2 Block diagram of 8085 MicroprocessorFig. 4.2. Block diagram of 8085 Microprocessor

3. Program Counter (PC): PC is a 16-bit register used to point the memory address from which the next instruction is to be fetched. Some times it is also called memory pointer. The contents of the PC is automatically incremented by the microprocessor during the execution of the instruction, so that at the end of

NOTES

Electronics-1


execution of the present instruction it points to the address of the next instruction in the memory. The signal of RESET pin of timing and control unit presets the PC to 0000H memory location which is the address of the very first instruction to be executed. The instruction JUMP and subroutine call, also change the contents of PC.

4. Stack Pointer (SP): Stack is a portion of R/W memory set aside by the programmer. The stack is used to save the contents of a register during the execution of a program. Stack pointer holds the address of the top element of the stack. Whenever something is added to the stack, the stack pointer is decremented and whenever something is received from the stack, the stack pointer is incremented. Hence, the SP always points to the top of the stack.

5. Instruction register and instruction decoder: After fetching an instruction code from memory, the microprocessor stores it in the instruction register, which is then decoded by instruction decoder and then microprocessor performs the required operation.

6. Statusflagregister:The flag register or status register consists of five status flip-flops called flags. Each of these flip-flops holds 1-bit information that indicates certain condition that occurs during an arithmetic or logic operation. The five status flags available in 8085 as shown below are Sign (S), Zero (Z), Auxiliary carry (AC), Parity (P), and carry (Cy).


The signal of RESET pin of timing and control unit presets the PC to 0000H memory

location which is the address of the very first instruction to be executed. The instruction

JUMP and subroutine call, also change the contents of PC.

d) Stack Pointer (SP): Stack is a portion of R/W memory set aside by the programmer. The stack is

used to save the contents of a register during the execution of a program. Stack pointer holds the

address of the top element of the stack. Whenever something is added to the stack, the stack pointer

is decremented and whenever something is received from the stack, the stack pointer is incremented.

Hence, the SP always points to the top of the stack.

e) Instruction register and instruction decoder: After fetching an instruction code from memory, the

microprocessor stores it in the instruction register, which is then decoded by instruction decoder and

then microprocessor performs the required operation.

f) Status flag register: The flag register or status register consists of five status flip-flops called flags.

Each of these flip-flops holds 1-bit information that indicates certain condition that occurs during an

arithmetic or logic operation. The five status flags available in 8085 as shown below are Sign (S),

Zero (Z), Auxiliary carry (AC), Parity (P), and carry (Cy).

Sign flag S – After the execution of a signed arithmetic or logical operation in ALU, if D7 bit of the result in

accumulator is 1, the sign flag is 1 indicating that the result is negative.

Zero flag Z – Zero flag is set to 1, if the ALU operation results in 0, and the flag resets to zero, if the result is

not 0.

Auxiliary Carry AC – In an arithmetic operation, when a carry is generated by digit D3 and passed on to D4,

the AC flag is set.

Parity flag P – If an operation produces even number of 1 in its result, the flag is set to 1. For odd number of

1s in the result, the flag is reset to 0.

Carry flag C – If an ALU operation produces a carry or borrow in its result, the carry flag set to 1, otherwise

it is reset.

g) Temporary register: This register is used to hold information from the memory or from the register

array of the ALU. The other input to the ALU comes from the accumulator.

h) Address Buffer and Address/Data buffer: Through these buffers microprocessor transfers address as

well as data required for memory and input/output devices.

Fig 13.3: Bit position of the flags in flag register. (X stands for unused)

S CYPACXZ X X

D7 D6 D5 D4 D3 D2 D1 D0

Fig.4.3.Bitpositionoftheflagsinflagregister.(Xstandsforunused)

Sign flag S – After the execution of a signed arithmetic or logical operation in ALU, if D7 bit of the result in accumulator is 1, the sign flag is 1 indicating that the result is negative.

Zero flag Z – Zero flag is set to 1, if the ALU operation results in 0, and the flag resets to zero, if the result is not 0.

Auxiliary Carry AC – In an arithmetic operation, when a carry is generated by digit D3 and passed on to D4, the AC flag is set.

Parity flag P – If an operation produces even number of 1 in its result, the flag is set to 1. For odd number of 1s in the result, the flag is reset to 0.

Carry flag C – If an ALU operation produces a carry or borrow in its result, the carry flag set to 1, otherwise it is reset.

7. Temporary register: This register is used to hold information from the memory or from the register array of the ALU. The other input to the ALU comes from the accumulator.

NOTES



8. Address Buffer and Address/Data buffer: Through these buffers microprocessor transfers address as well as data required for memory and input/output devices.

the ARithmetic And Logic Unit (ALU)The ALU performs the computing functions like addition, subtraction, logical AND, OR and EX-OR, increment, decrement, complement, compare etc. It includes the accumulator, the temporary register, the arithmetic and logic circuits and flag register. The result is stored in accumulator and flags one set or reset according to the result of the operation.

timing And contRoL Unit

Main function of the microprocessor in the microcomputer system is to perform computations and controlling peripherals like memory and I/o devices. The timing and control unit provides status, control and timing signals, which are necessary for the control of these peripherals.

Pin configURAtion of 8085 micRoPRocessoR

The INTEL 8085 is an 8-bit microprocessor fabricated in a 40 Pin DIP package. It operates with single +5VDC supply and with a clock speed of 3 MHz. All the signals corresponding to 40 pins can be divided into six functional groups: 1) Address bus, 2) data bus, 3) Control and status signals, 4) power supply and clock signals, 5) Interrupts and peripheral initiated signals, and 6) serial I/O ports. The pin diagram and signal diagram are shown in Figs15.4 a and 15.4b.


13.3.2 The Arithmetic and Logic Unit (ALU):

The ALU performs the computing functions like addition, subtraction, logical AND, OR

and EX-OR, increment, decrement, complement, compare etc. It includes the accumulator, the temporary

register, the arithmetic and logic circuits and flag register. The result is stored in accumulator and flags one

set or reset according to the result of the operation.

13.3.3 Timing and Control Unit:

Main function of the microprocessor in the microcomputer system is to perform computations and

controlling peripherals like memory and I/o devices. The timing and control unit provides status, control

and timing signals, which are necessary for the control of these peripherals.

13.4 Pin Configuration of 8085 microprocessor:

The INTEL 8085 is an 8-bit microprocessor fabricated in a 40 Pin DIP package. It operates with single

+5VDC supply and with a clock speed of 3 MHz. All the signals corresponding to 40 pins can be divided

into six functional groups: 1) Address bus, 2) data bus, 3) Control and status signals, 4) power supply and

clock signals, 5) Interrupts and peripheral initiated signals, and 6) serial I/O ports. The pin diagram and

signal diagram are shown in Figs15.4 a and 15.4b.

13.4.1 Address Bus:

The 8085 has 16-bit address bus capable of addressing 216 (= 26 x 210 = 64 x 1k = 64k) memory locations.

The high order 8 address lines A8 – A15 carries high order address of memory through this bus.

Fig 13 . 4(a) 8085 IC pin diagram

123456789

1011121314151617181920 21

22232425262728293031323334353637383940

RST 7.5

A14

SID

A8A9A10A11A12A13

AD7

AD3AD4AD5AD6

AD2

AD0AD1

GND

CLK (OUT)

INTR

High orderaddress pins

A15

VCC

RESET OUT

X1

On-chiposcillator pins

READY

ALE

HLDAHOLD

TRAPRESET IN

DMA

RD

INTA

SOD

Interruptpins

Serial datatransfer pins

S1

S0

IO/ M

WR

X2

RST 6.5RST 5.5

Low orderaddress pins

Fig. 4 4(a) 8085 IC pin diagram

AddRess BUs

The 8085 has 16-bit address bus capable of addressing 216 (= 26 x 210 = 64 x 1k = 64k) memory locations. The high order 8 address lines A8 – A15 carries high order address of memory through this bus.

NOTES

Electronics-1


mULtiPLexed AddRess/dAtA BUs

These 8 lines are time multiplexed low order 8-bit address as well as 8-bit data bus. In the execution of an instruction, during the first clock cycle microprocessor sends out low order 8-bit address and during the remaining clock cycle microprocessor sends out 8-bit data on these pins in multiplexed mode. However, the low – order address bus is separated from data bus using a latch.


13.4.2 Multiplexed Address/data bus:

These 8 lines are time multiplexed low order 8-bit address as well as 8-bit data bus. In the execution of

an instruction, during the first clock cycle microprocessor sends out low order 8-bit address and during the

remaining clock cycle microprocessor sends out 8-bit data on these pins in multiplexed mode. However, the

low – order address bus is separated from data bus using a latch.

13.4.3 Control and status signals:

This group of signals includes two control signals, RD and WR , three status signals, IO/ M , S1 and S0,

and one special signal ALE. The functions of these signals are as follows:

ALE – Address Latch Enable: A positive going pulse is generated every time when microprocessor sends

out address over multiplexed bus. It is used to latch the low-order address from the multiplexed

address/data bus on to an octal latch, to generate separate set of eight address lines A0 to A7.

RD - This active low control signal indicates that the selected I/O or memory device is to be read and data

is available on the data bus.

WR - This active low write control signal indicates that the data on the data bus, is to be written into a

selected memory or I/O device.

High-orderAddress Bus

multiplexedAddress/Data bus

Controlandstatussignals

InterruptsandExternallyInitiatedsignals

SerialI/oports

A15 28

A8

AD7

AD0

21

19

12

3029

34

3111

32

33

38

36

35

4

67

5

39

1098

ALES0S1IO/MRDWRINTAALDA

HOLDREADY

RESET IN

SIDSOD

INTRRST 5.5RST 6.5RST 7.5

TRAP

RESETOUT

CLOCKOUT

3 37

X1 X2 VCC

VSS+5V

1 2 2040

Fig 13.4b 8085 signal diagramFig. 4.4(b) 8085 signal diagram

contRoL And stAtUs signALs

This group of signals includes two control signals, RD and WR, three status signals, IO/M,

S1 and S0, and one special signal ALE. The functions of these signals are as follows:

ALE – Address Latch Enable: A positive going pulse is generated every time when microprocessor sends out address over multiplexed bus. It is used to latch the low-order address from the multiplexed address/data bus on to an octal latch, to generate separate set of eight address lines A0 to A7.

RD –This active low control signal indicates that the selected I/O or memory device is to be read and data is available on the data bus.

NOTES



WR – This active low write control signal indicates that the data on the data bus, is to be written into a selected memory or I/O device.

IO/M - This status signal is used to differentiate between I/O and memory operations. A high on this line indicates an I/O operation whereas a low indicates a memory operation. This signal is combined with RD and WR to generate I/o and memory control signals.

S1 and S0 – These status signals can be used to identify various operations of microprocessor as shown below.


IO/ M - This status signal is used to differentiate between I/O and memory operations. A high on this line

indicates an I/O operation whereas a low indicates a memory operation. This signal is combined with RD

and WR to generate I/o and memory control signals.

S1 and S0 - These status signals can be used to identify various operations of microprocessor as shown

below.

13.4.4 Power Supply and clock frequency:

The power supply signals: Vcc is +5 volts DC supply and Vss - ground reference X1 & X2 – An external

crystal connected to these two pins generates a clock frequency by the internal oscillator for the operation of

microprocessor. The oscillator frequency is divided by two internally; therefore, to operate a system at

3MHz, the crystal should have the frequency of 6MHz.

CLK OUT – This signal can be used as the system clock for other devices.

13.4.5 Interrupts and Externally initiated operations:

Interrupts : When an interrupt is recognized, the next instruction is executed from a fixed location in the

memory. The 8085 has five interrupt signals that can be used to interrupt a main program execution. These

are TRAP, RST 7.5, RST 6.5 RST5.5 and INTR. The TRAP is a non-maskable interrupt having highest

priority among the other interrupts.

INTR – INTR is an interrupt request signal. An interrupt is used by an I/O device to transfer data to the

microprocessor without wasting its time.

INTA - INTA is an interrupt acknowledge signal sent by the microprocessor after INTR is received.

INRESET - It resets the program counter to zero, causes the microprocessor to execute the first instruction

at the 0000H location.

Status signals OperationsIo/M S1 S0

0 1 1 Opcode fetch

0 1 0 Memory Read

0 0 1 Memory write

1 1 0 I/O Read

1 0 1 I/O write

1 1 1 Interrupt Knowledge

PoweR sUPPLy And cLock fReqUency

The power supply signals: Vcc is +5 volts DC supply and Vss - ground reference X1 & X2 – An external crystal connected to these two pins generates a clock frequency by the internal oscillator for the operation of microprocessor. The oscillator frequency is divided by two internally; therefore, to operate a system at 3MHz, the crystal should have the frequency of 6MHz.

CLK OUT – This signal can be used as the system clock for other devices.

inteRRUPts And exteRnALLy initiAted oPeRAtions

Interrupts: When an interrupt is rec, the next instruction is executed from a fixed location in the memory. The 8085 has five interrupt signals that can be used to interrupt a main program execution. These are TRAP, RST 7.5, RST 6.5 RST5.5 and INTR. The TRAP is a non-maskable interrupt having highest priority among the other interrupts.

INTR – INTR is an interrupt request signal. An interrupt is used by an I/O device to transfer data to the microprocessor without wasting its time.

INTA – INTA is an interrupt acknowledge signal sent by the microprocessor after INTR is received.

RESET IN – It resets the program counter to zero, causes the microprocessor to execute the first instruction at the 0000H location.

NOTES

Electronics-1


READY – Input signal . It is used by slower devices to request the microprocessor to wait until they are ready for data transfer.. Microprocessor enters into WAIT states as long as this pin is active.

seRiAL i/o PoRts

The 8085 has two signals to implement the serial date transmission.

SID – Serial data input line. A serial data bit on this line is loaded into the most significant bit (D7) of accumulator, when RIM instruction is executed.

SOD – Serial data output line. The most significant bit (D7) of accumulator is output on this line when SIM instruction is executed.

8085 BUs configURAtion

The program instructions are stored in memory. To execute an instruction the microprocessor first sends out the address of the memory location on address bus. The address is decoded and the memory location ,where the instruction is stored is accessed. The instruction operation code(op code) is fetched through data bus, and placed in instruction decoder. Here the number of bytes further needed is identified and the number of machine cycles needed is determined . Timing and control section issues necessary signals to proceed further with the instruction and the execution of the instruction is completed. These steps are known as “Fetch, Decode and Execute”. All these operations are performed in synchronization with system clock. Therefore these operations are performed at a given time period, depending on the clock frequency. During these operations the 8085 signal activity be visualized by studying its timing diagram. The timing diagrams will give us a clear understanding of how the microprocessor works.

Timing DiagramFigure 13.5 is the timing diagram of MOV B, A ( op code 47H ) stored in a memory location say, 3050H. Figure shows the timing activities of various signals like address bus, data bus, RD , WR , ALE, IO/Metc.

The first one in the figure is the clock waveform. One cycle of this clock is called a state labeled as T.

A basic microprocessor’s operation such as reading a byte from memory or writing into a port is called a machine cycle. The time a microprocessor requires to fetch and execute an entire instruction is known as an instruction cycle. An instruction cycle may consist of one or more machine cycles.

The sequence of steps involved in the execution of an instruction MOV B, A having the operation code 47H stored in memory location 3050H are as follows (See figure 4.5):

Step 1 – The microprocessor places the contents of program counter 3050H on the address bus, such as 30H on the high order address bus and 50H on the low – order AD0-AD1 bus.

NOTES




The sequence of steps involved in the execution of an instruction MOV B, A having the operation code

47H stored in memory location 3050H are as follows (See figure 13.5):

Step 1 – The microprocessor places the contents of program counter 3050H on the address bus, such as 30H

on the high order address bus and 50H on the low – order AD0-AD1 bus.

Step 2 – ALE goes high indicating AD0 – AD7 bus contains low order address. This signal is used to store

lower byte of address in an octal latch for further use as AD bus gets converted to data bus from second

clock cycle.

Step 3 – IO/ M goes low to indicate the operation relates to memory.

Step 4 – Both S1 and S0 goes high to tell the operation is op code fetch. All these operations from step 1 to

step 5 is performed in T1 state.

Step 5 – During T2, RD goes low since it is memory read operation, the program counter is incremented by

one i.e.3051H, ALE goes low. The content of memory location 3050H, which is 47H, the op code of MOV

B, A is placed on the data bus.

Step 6 – In T3 state, 47H is read by microprocessor and transferred instruction decoder.

Step 7 – During T4, microprocessor decodes the instruction and executes the specified operation i.e.

transferring of accumulator contents into register B.

Above figure shows a complete machine cycle (in this case it is also equal to one instruction cycle)

consisting of four states. If the clock frequency (f) is 2 MHz, the time for one clock period is

T1 T2 T3 T4

S0 = 1, S1=1 op code fetch

30 H

CLK

A15 – A8

AD7 – AD0

ALE

RD

S0S1

IO / MIO / M

High-order address Undefined

50H 47H op codeaddress

Low-order

Status

Fig. 13.5 MOV B,A timing diagramFig. 4.5. MOV B,A timing diagram

Step 2 – ALE goes high indicating AD0 – AD7 bus contains low order address. This signal is used to store lower byte of address in an octal latch for further use as AD bus gets converted to data bus from second clock cycle.

Step 3 – IO/M goes low to indicate the operation relates to memory.

Step 4 – Both S1 and S0 goes high to tell the operation is op code fetch. All these operations from step 1 to

step 5 is performed in T1 state.

Step 5 – During T2, RD goes low since it is memory read operation, the program counter is incremented by one i.e.3051H, ALE goes low. The content of memory location 3050H, which is 47H, the op code of MOV B, A is placed on the data bus.

Step 6 – In T3 state, 47H is read by microprocessor and transferred instruction decoder.

Step 7 – During T4, microprocessor decodes the instruction and executes the specified operation i.e. transferring of accumulator contents into register B.

Above figure shows a complete machine cycle (in this case it is also equal to one instruction cycle) consisting of four states. If the clock frequency (f) is 2 MHz, the time for one clock period is


T =f1

= 61021

=2

10 6

= 0.5s

Total execution time = T- states x clock period = 4 x 0.5 x 10 – 6 = 2 s.

13.6 Addressing modes:

A microprocessor system operates under the control by a series of instructions that make up a program.

An instruction is a command to the microprocessor to perform a specific operation on certain data.

Let us consider the following instructions

a) MOV C, B – This instruction moves the contents of register B into register C.

b) LDA 2050H – Loads the contents of the memory location 2050H into accumulator.

Each instruction has two parts: first part indicates the task to be performed and it is called

Mneumonic (code in English characters that stands for binary op code) The second part is called

operand.

In the first example MOV specifies the tasks of instruction (to move the content of one register to

another)and is therefore called op code. In the remaining part of the instruction two data registers

(source , destination) called operands are specified

In the second instruction, LDA is the op code(in this instruction Acc is one of the operands). A 16

bit number is specified for operand . This number stands for a memory location and represents the

second operand. According to INTEL notation if 2050 location is intended the instruction has to be

entered in the order as op code, lower byte of address, upper byte of address i.e 3A 50 20 . Here 3A

is the hexadecimal equivalent for the mneumonic of LDA op code.

Above examples indicates that each instruction specifies an operation to be performed on certain data.

There are certain techniques by which the address of the data to be operated upon may be specified. The

various ways of specifying the operand are called the addressing modes.

There are five addressing modes

i) Direct addressing mode ii) Register addressing mode iii) Register indirect addressing mode

iv) Immediate addressing mode v) Implicit addressing mode

13.6.1 i) Direct addressing modes: In this mode, the address of the operand is specified directly within the

second and third byte of the instruction itself.

Examples:

a) STA 1850H: Store the contents of accumulator into memory location 1850H.

Total execution time = T- states x clock period = 4 × 0.5 × 10 – 6 = 2 s.

NOTES

Electronics-1


4.5 ADDRESSING MODESA microprocessor system operates under the control by a series of instructions that make up a program. An instruction is a command to the microprocessor to perform a specific operation on certain data.

Let us consider the following instructions

(a) MOV C, B – This instruction moves the contents of register B into register C.

(b) LDA 2050H – Loads the contents of the memory location 2050H into accumulator.

Each instruction has two parts: first part indicates the task to be performed and it is called

Mneumonic (code in English characters that stands for binary op code) The second part is called operand.

In the first example MOV specifies the tasks of instruction (to move the content of one register to another)and is therefore called op code. In the remaining part of the instruction two data registers (source , destination) called operands are specified

In the second instruction, LDA is the op code(in this instruction Acc is one of the operands). A 16 bit number is specified for operand . This number stands for a memory location and represents the second operand. According to INTEL notation if 2050 location is intended the instruction has to be entered in the order as op code, lower byte of address, upper byte of address i.e 3A 50 20 . Here 3A is the hexadecimal equivalent for the mneumonic of LDA op code.

Above examples indicates that each instruction specifies an operation to be performed on certain data. There are certain techniques by which the address of the data to be operated upon may be specified. The various ways of specifying the operand are called the addressing modes.

There are five addressing modes

(i) Direct addressing mode (ii) Register addressing mode (iii) Register indirect addressing mode (iv) Immediate addressing mode v) Implicit addressing mode

(i) Direct addressing <odesIn this mode, the address of the operand is specified directly within the second and third

byte of the instruction itself.

Examples:

(a) STA 1850H: Store the contents of accumulator into memory location 1850H.

(b) LHLD 2015H: Load the contents of memory location 2015H into register L and the contents 2016H into register H.

(ii) Register Addressing ModeIn this addressing mode, the source or destination or both operands are located in the microprocessor registers

NOTES



Examples:

(a) MOV A, B: The contents of register B is copied into register A

(b) ADD B: The contents of register B is added to the contents of accumulation and the result stored in accumulator.

(iii) Register Indirect Addressing Mode In this addressing mode, the address of the operand is specified by a register pair.

Examples:

(a) MOV A, M: The contents of the memory location whose address is specified in H-L register pair is copied into accumulator.

(b) LDAX B: The contents of the memory location whose address is specified by B-C register pair is copied into register A.

(iv) Immediate Addressing ModeIn this addressing mode, the operand is specified in the instruction itself.

Examples:

(a) MVI B, 25H: The 8-bit data 25H is moved in to register B

(b) LXI H, OF5AH: The 16-bit data OF5AH is moved into H-L register pair such that 5AH is moved into register L and OFH is moved into register H.

(v) Implicit Addressing ModeSome instructions do not require the address of the operand. The operands are implicit in the instruction itself. Most of these instructions operate on the contents of the accumulator.

Examples:

(a) CMA – Compliment the contents of accumulator.

(b) STC – Set carry flag.

4.6 INSTRUCTION SETIt is clear from the previous studies that the 8085 has a collection of 8-bit and 16-bit registers and 8-bit memory locations that can be used for programming purpose. The collection of these register and memory locations used by the programmer is called programmer’s model. The programmer’s model of 8085 consists of

(i) 8-bit Accumulator (ii) Six 8-bit registers: B, C, D, E, H & L or three 16-bit registers: B-C, D-E & H-L (iii) 16-bit program counter PC (iv)16-bit stack pointer SP v) 8-bit flags register (vi) 64KBmemory locations divided into ROM, RAM and stack areas and (vii) 64 I/O ports.

NOTES

Electronics-1


An instruction is a command to the microprocessor to program a specific task. The entire group of instructions are called its instruction set. The 8085 instruction set has 74 op-codes that result in 246 instructions. Depending on their function all these instructions can be classified into the following categories:

(i) Data transfer group (ii) Arithmetic group (iii) Logical group (iv) Branch group (v) Stack, I/o and machine – control group.

(i) Data Transfer GroupThese instructions copy data from a source into a destination without modifying the contents of the source and without affecting the flags. 8-bit data transfer as

1. MOV destination, source: Copies the contents of source into destination where the source may be

– an immediate value (e.g.# 35H)

– an 8-bit register (A, B, C, D, E, H & L)

– the contents of a memory location whose address is specified in H-L reg. Pair

The destination may be

– an 8-bit register (reg.)

– the contents of a memory location whose address is specified in H-L reg. pair.

But both source and destination should not be memory contents and the destination should not be an immediate value.

Examples:

Between registers :

MOV B, C – data of register C is copied into register B.

Specific data byte into a register or memory

MVI B, 2FH – data 2FH copied into register B

MVI M, 2FH – data 2FH into a memory location whose address is specified by H-L pair (Before this instruction H-L pair should be loaded with a memory address)

Data transfer between memory location and a register

MOV M, B – copy the contents of reg. B into a memory location address by H-L pair.

MOV B, M – copy the contents of memory location address by H-L pair into reg. B.

LDA 16-bit address: Load accumulator directly the contents of memory location whose address is specified in the second and third byte of instruction.

e.g.: LDA 2050 H – Load the contents of memory location 2050H into the acc.

STA 16-bit address: Store accumulator direct.

NOTES



The contents accumulator is stored into a memory location whose address is specified with second and third byte of instruction.

STA 30A0H – Store accumulator content directly into memory location whose address is 30A0H.

LDAX rp: Load acc . indirect rp = B – C / D – C.

The contents of memory location whose address in the register pair rp is loaded into the acc.

STAX rp: Store acc. Indirect rp = B – C / D – E.

The contents of acc. is stored in memory, whose address is in the register pair rp.

e.g.: STAX B – Store the contents of acc. Into the memory location addressed by B – C.

16-bit Data Transfer1. LXI rp. data 16: Load register pair immediate.

rp = B – C / D – C | H – C | sp.

The 16-bit immediate data is loaded into the specified register pair.

e.g. LXI H, 2450H – Loads 2450H into HL pair such that 50H is in L and 24H in H.

e.g: LDAX B – This instruction will load the contents of the memory location, whose address is in B – C reg. Pair into acc.

2. LHLD 16-bit addr. : Load H – L pair direct.

The contents of memory location, whose address is specified in second and third byte of instruction is loaded into register L. The contents of the next memory location is loaded into register H. e.g: LHLD 3050H – This instruction loads the contents of 3050H into register L and the contents of 3051H into register H.

3. SHLD 16-bit addr: Store H – L pair direct.

The contents of register L is stored into the memory location whose address is specified in the instruction, and the contents of register H is stored in the next memory location.

e.g: SHLD 3500H – This instruction will store the contents of register L in the memory location 3500H and the contents of register H is the location 3501H.

4. XCHG: Exchange the contents of H – L with D – E.

The contents of register pair H – L are exchanged with that of the register pair D – E. e.g. if DE=2050;HL=307F ; after the execution of XCHG instruction DE=307F; HL=2050.

NOTES

Electronics-1


(ii) Arithmetic groupThese instructions perform arithmetic operations such as addition, subtraction, increment and decrement.

i) 8-bit addition and subtraction: The 8085 can execute two types of addition /

subtraction instructions – addition or subtraction with out carry and addition or

subtraction with carry. Both addition instructions can be used to add the contents of

accumulator to the contents of one of the general purpose registers or the contents

of memory locations (address in H – L pair) or all immediate data byte.

(a) These instructions assume that the acc. is one of the operands.

(b) Place the result in the acc.

(c) Do not affect the contents of another operand and

(d) Modify all the flags according to the data condition in acc.

e.g.1: ADD B – Adds the contents of register B with the contents of the accumulator

and the result is stored in the acc. If a=05H and B-0 7H ,execution of ADD B

modifies the content of A as 0CH. Reg B content is not altered. As 8085 handles

data in binary in the display we see the hexadecimal equivalent of result OCH.

Don’t expect the decimal answer of 12.

e.g.2: ADD M – The contents of the memory location addressed by the pair is

added to the contents of acc. one result is stored in the acc.

e.g.3: ADI 35H – The 8-bit immediate data 35H is added to the contents of the

accumulator and the result is stored in acc.

e.g.4: ADC D – The contents of register D and carry flag are added to the contents

of acc. and result is stored in the acc.

e.g.5: ADC M – The contents of memory location addressed by H – L and carry

are added to the contents of the acc and the result is stored in the acc.

e.g.6: ACI 35H – 35H with carry are added to the contents of acc.

e.g.7: SUB B – The contents of register B is subtracted from the contents of the

acc. and the result is stored in the acc.

e.g.8: SBB M – The contents of the memory location addressed by H – L pair and

carry are subtracted from the contents of acc. And the result is stored in the acc.

16-bit Addition: This instruction adds 16-bit data of H – L register to the 16-bit

data of another 16-bit register contents. Result is stored in HL pair. Except carry

no other flags are effected.

NOTES



DAD rp: Add the content of register pair specified to the content of H-L pair and

store the result in H-L pair.

rp = B-C / D-E / H-L / sp.

The contents of register pair rP are added to the contents of H – L pair and the

result is stored in H – L pair.

e.g.: DAD D – The contents of register pair D – E are added to the contents of HL

pair and the result is stored in H – L pair. If the result is more than 16-bits carry

flag is set. No other flags are affected.

8-bit Increment/decrement: These instructions increment or decrement the contents of 8-bit registers or the contents of memory location whose address is specified in H – L register pair.

Carry flag is not affected.

e.g.: INR D – The contents of register D is incremented by one.

INR M – The contents of memory location addressed by H – L pair is incremented by one.

DCR C – The contents of register C is decremented by one.

DCR M – The contents of the memory location addressed by H – L pair is decremented by one.

(iv) 16-bit Increment/decrement:

1N x rp: Increment register pair contents

rp = B – C / D – E / H – L / sp.

e.g.: 1NX H – The contents of the H – L pair is incremented by one. No flags are affected.

DCX rp: decrement register pair contents.

rp = B – C / D – E / H – L / sp.

e.g.: DCX B – The contents of the B – C pair is decremented by one. No flags are affected.

However it becomes necessary in some programs to check whether the execution of DCX rp resulted in zero or not . After each decrement by checking the logical OR result of the registers involved one can ascertain it

See how this is done in program no. .

(v) Decimal Adjusting Data

DAA: Decimal adjusting accumulator.

NOTES

Electronics-1


DAA instruction is used in the program after an addition instruction. The DAA instruction operates on the result in the accumulator and the final result in decimal form. It uses carry and auxiliary carry for decimal adjustment. To use the DAA instruction the two numbers added should be in BCD form.

(iii) Logical InstructionThese instructions perform logical operations such as AND, OR, EX-OR, compare, rotate and

complement of data in register or memory.

1. Logical OR, AND, NOT and EX-OR operations.

(a) These instructions implicitly assume that the accumulator is one of the operands

(b) Place the result in accumulator.

(c) Do not affect the contents of the operand reg. (except NOT operation)

(d) Some of the flags are affected according to the result.

e.g.1: ORA D – The contents of the register D is logically OR ed with the contents of the accumulator and the result is stored in the accumulator.

e.g.2: ANI 23H – The data 23H is logically AND ed with the contents of the accumulator and the result is stored in the accumulator.

e.g.3: XRA M – The contents of the memory location addressed by H – L pair is EX – OR ed with the contents of the accumulator and the result is stored in the acc.

e.g.4: CMA – The contents of the accumulator is complemented and the result stored in accumulator.

2. Comparison: The contents of the accumulator is compared with the contents of the other register or the contents of the memory location addressed by H – L pair or an 8-bit data.

CMP R – Compare register with accumulator

CMP M – Compare memory contents with accumulator.

CPI 8-bit data – Compare immediate data with accumulator

Here comparison is performed through subtraction. However, neither contents are modified, but the result of the subtraction is only reflected in the form of conditional flags.

(i) If the content of A is lesser than compared data , carry flag set 1.

(ii) If the content of A is greater than compared data, carry flag is zero.

(iii) If both are equal, zero flag set to 1.

NOTES



3. Rotate Instructions:

(a) The rotate instructions are register specific, operates only on the accumulator

(b) In these instructions, the bit that is shifted out is used as the new bit shifted in

c) There are four rotate instructions to rotate a bit pattern in the accumulator to the left or to the right with or without carry.

RLC – rotate accumulator left

RRC – rotate accumulator right

RAL – rotate all (including carry) left

RAR – rotate all (including carry) right.

(iv) Branching InstructionsThe flow of a program proceeds sequentially, from instruction to instruction, unless a control transfer command is executed. The branch instructions allow microprocessor to go to a different memory location, either unconditionally or conditionally (under certain test conditions) and continues executing instructions from that new location.

The branch instructions are classified in three categories:

– Unconditional/conditional jump instructions.

– Unconditional / conditional call and return instructions

– Restart instructions.

Jump Instructions:

(a) Unconditional jump

JMP addr – The program counter is loaded with 16-bit address and the program execution jumps to that address unconditionally.

(b) Conditional jump conditional jump instructions first check for the condition and if the condition is satisfied then only execution jumps to new location. Flag(I), sign flag(S), and purity flag (P).

e.g.1: JC addr – Jump on Carry

JNZ addr – Jump on No zero

JPE addr – Jump on even parity.

Call and Return instructions

The call instruction is used in the main program to call a subroutine, and the return instruction is used at the end of the subroutine to return to the main program. When a subroutine is called, the contents of the program counter, which is the address of the instruction following the call instruction, is stored in the stack and the program

NOTES

Electronics-1


execution is transferred to the subroutine address. When the return instruction is executed at the end of the subroutine, the memory address stored in the stack is retrieved, and the sequence of execution is resumed in the main program.

(a) Unconditional call

CALL addr – unconditional call

(b) Conditional call:

CC addr – call if the carry flag set

CNC addr – call of the carry flag not set

CNF addr – call on No zero

(a) Unconditional return

RET – unconditional return

(b) Conditional return

RC – Return on carry

RNC – Return on No carry

RP – Return on positive

Restart Instructions:

Restart is a one byte CALL instruction. Because these instructions are having specific call addresses for

specific restart instructions as specified bellow. The program jumps to the instruction starting at restart location.

Restart Instruction Location

RST 0 0000H

RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H

RST 7 0038H

One interesting use of RST instruction is to create break point. Finding mistakes(bugs) in a big program can be made simple by inserting break points at desired places. Program terminates when RST instruction is executed. If there are no bugs up to that point, the break point can be shifted to some other place . The process of removing bugs is called debugging. Instead of HALT instruction one may use Break point for the safe transfer of control to monitor program.

NOTES



(v) Stack, I/o and machine – control group:(a) Stack instructions

PUSH rp – PUSH register pair onto stack

rp = B – C / D – C / H – C / psw.

The content of the specified register pair is pushed onto stack after the stack pointer is decremented by two.

e.g.: PUSH B – The contents of register pair B – C is pushed on to stack.

POP rp – POP off stack to register pair.

rp = B – C / D – C | H – C | psw.

The top two elements of the stack are POPed into the specified register pair. The stack pointer is incremented by two.

e.g.: POP D – The contents of stack top POPed into register pair D – E.

In some programs the available internal registers may not be sufficient to write the program. However some of the registers may not be needed immediately. In such situations the contents of immediately not used register contents are pushed on to the stack. These registers are used for the present need and once the purpose is served, they are reloaded with their earlier values with POP instruction. If a series of push instructions like PUSH B, PUSH D, PUSH H are used, to restore their original contents the POP instructions must be in the order POP H, POP D, POP B as stack operations follow first in last out policy.

(b) I/O Instructions

IN port-addr – Input to accumulator from input port

The data available on the port is moved into the accumulator. Port address is 8-bit.

OUT port-addr – Out put from accumulator to output port. The contents of the accumulator is moved to the port whose 8-bit address is specified in the instruction

External devices with suitable interfacing can be connected to input and output ports. The power of microprocessor lies in its ability communicating with external devices. Industrial digital control systems, Robots and other smart devices work under microprocessor control. All together 256 I/O devices can be connected . The devices which use IN and OUT instruction for data transfer are said to be operating in I/o mapped I/o mode. If more than 256 devices are to be connected, Memory mapped I/O mode can be used. In this mode each device is assigned with a 16 bit address.

(c) Machine control instructions

These instructions are used to control the microprocessor operation.

e.g.: HLT – Halt

The execution of the HLT instruction stops the microprocessor.

NOTES

Electronics-1



Load / Store Opcode Cycles States Flags

LDAX B 0A 2 7 noneLDAX D 1A 2 7 noneLHLD addr 2A 5 16 noneLDA addr 3A 4 13 noneSTAX B 02 2 7 noneSTAX D 12 2 7 none

SHLD addr 22 5 16 noneSTA addr 32 4 13 noneXCHG EB 1 4 none

MOV A,B 78A,C 79A,D 7AA,E 7BA,H 7CA,L 7DA,M 7EA,A 7F

MOV E,B 58E,C 59E,D 5AE,E 5BE,H 5CE,L 5DE,M 5EE,A 5F

MOV B,B 40B,C 41B,D 42B,E 43B,H 44B,L 45B,M 46B,A 47

MOV H,B 60H,C 61H,D 62H,E 63H,H 64H,L 65H,M 66H,A 67

MOV C,B 48C,C 49C,D 4AC,E 4BC,H 4CC,L 4DC,M 4EC,A 4F

MOV L,B 68L,C 69L,D 6AL,E 6BL,H 6CL,L 6DL,M 6EL,A 6F

MOV D,B 50D,C 51D,D 52D,E 53D,H 54D,L 55D,M 56D,A 57

MOV M,B 70M,C 71M,D 72M,E 73M,H 74M,L 75M,M 76M,A 77

MOV r1,r2 Cycles:1 States:4 Flags: noneMOV r, M Cycles:2 States:7 Flags: noneMOV M, r Cycles:2 States:7 Flags: none

Move immediate

MVI A,data 3EB,data 06C,data 0ED,data 16E,data 1EH,data 26L,data 2EM,data 36

Load immediate

LXI B,data 01D,data 11H,data 21

SP,data 31

MVI r, data Cycles:2 States:7 Flags: noneMVI M, data Cycles:3 States:10 Flags: noneLXI rp, data 16 Cycles:3 States:10 Flags: none

8085 Instruction setData transfer group

NOTES




ADD B 80C 81D 82E 83H 84L 85M 86A 87

INR A 3CB 04C 0CD 14E 1CH 24L 2CM 34

ADC B 88C 89D 8AE 8BH 8CL 8DM 8EA 8F

SUB B 90C 91D 92E 93H 94L 95M 96A 97

INX B 03D 13H 23SP 33

DCX B 0BD 1BH 2BSP 3B

DCR A 3DB 05C 0DD 15E 1DH 25L 2DM 35

SBB B 98C 99D 9AE 9BH 9CL 9DM 9EA 9F

Cycles States FlagsADD r, ADC r, SUB r, SBB r 1 4 AllADD M, ADC M, SUB M, SBB M 2 7 AllADI data, ACI data, SUI data, SBI data 2 7 AllINR r, DCR r, 1 4 Z, S, P, ACINR M, DCR M 3 10 Z, S, P, ACINX rp, DCX rp 1 6 noneDAD rp, 3 10 CYDAA 1 4 All

Arithmetic group

DAA 27DAD B 09DAD D 19DAD H 29

ADI data C6ACI data CESUI data D6SBI data DE

ANA B A0C A1D A2E A3H A4L A5M A6A A7

XRA B A8C A9D AAE ABH ACL ADM AEA AF

ORA B B0C B1D B2E B3H B4L B5M B6A B7

CMP B B8C B9D BAE BBH BCL BDM BEA BF

ANI data E6XRI data EEORI data F6CPI data FE

Logical groupCycles States Flags

ANA r, ORA r, XRA r, CMP r 1 4 AllANA M, ORA M,XRA M, CMP M 2 7 AllANI data, ORI data, XRI data, CPI data 2 7 AllRLC, RRC, RAL, RAR 1 4 CYCMA 1 4 noneCMC, STC 1 4 CY

RLC 07RRC 0FRAL 17RAR 1F

DAA 27CAN 2FSTC 37CMC 3F

NOTES

Electronics-1



13.7 Summery:

The central processing unit of a digital computer built into a single LSI or VLSI chip is called a

microprocessor. It is the latest development in the field of computer technology. A VLSI chip

contains more than 10,000 transistors. Intel 8085 is an 8-bit NMOS microprocessor. This means the

transistors used in the manufacturing of 8085 IC are N-channel Metal Oxide Semiconductor Field

Effect Transistors. The 8085 IC has 40 pins and operates on a single +5V DC power supply. Its

clock speed is 3MHz. Its memory capacity is 64k Bytes. In the IC, there are 4 functional units:

RETURN Cycles States Flags

RET C9 3 10 noneRNZ C0 1/3 6/12 noneRZ C8 1/3 6/12 noneRNC D0 1/3 6/12 noneRC D8 1/3 6/12 noneRPO E0 1/3 6/12 noneRPE E8 1/3 6/12 noneRP F0 1/3 6/12 noneRM F8 1/3 6/12 none

RESTART Cycles States Flags

RST 0 C7 3 12 noneRST 1 CF 3 12 noneRST 2 D7 3 12 noneRST 3 DF 3 12 noneRST 4 E7 3 12 noneRST 5 EF 3 12 noneRST 6 F7 3 12 noneRST 7 F8 3 12 none

STACK operation Cycles States Flags

PUSH B C5 3 12 nonePUSH D D5 3 12 nonePUSH H E5 3 12 nonePUSH PSW F5 3 12 nonePOP B C1 3 12 nonePOP D D1 3 12 nonePOP H E1 3 12 nonePOP PSW F1 3 12 noneXTRL E3 5 16 noneSPHL F9 1 6 none

I / O and Machine control

INPUT / OUTPUT Cycles States Flags

OUT data D3 3 10 noneIN data DB 3 10 none

CONTROL

DI F3 1 4 noneEI FB 1 4 noneNOP 00 1 4 noneHLT 76 1 5 noneSIM 30 1 4 noneRIM 20 1 4 none

Cycles States FlagsJMP addr C3 3 10 noneJNZ addr C2 2/3 7/10 noneJZ addr CA 2/3 7/10 noneJNC addr D2 2/3 7/10 noneJC addr DA 2/3 7/10 noneJPO addr E2 2/3 7/10 noneJPE addr EA 2/3 7/10 noneJP addr F2 2/3 7/10 noneJM addr FA 2/3 7/10 nonePCHL E9 1 6 none

Cycles States FlagsCALL addr CD 5 18 noneCNZ addr C4 2/5 9/18 noneCZ addr CC 2/5 9/18 noneCNC addr D4 2/5 9/18 noneCC addr DC 2/5 9/18 noneCPO addr E4 2/5 9/18 noneCPE addr EC 2/5 9/18 noneCP addr F4 2/5 9/18 noneCM addr FC 2/5 9/18 none

Branch CONTROL Instructions

4.7 WRITING AND EXECUTING AN AL PROGRAMIn writing an Assembly language program to solve a particular problem, first step is to develop an algorithm, next draw a flow chat and finally the actual AL program to solve the problem.

The algorithm is a precise statement of the procedure received for solving the problem. It may be expressed using the English language. A flow chart is a pictorial representation of steps necessary to write the program. Various symbols are used in flow chart representation. They are: circle with an arrow, rectangle, diamond, oval, double-sided rectangle. Some of the common symbols used in flow charts. From flow charts one can visualize the program flow

NOTES



and can identify the flaws in the algorithm. Based on flowchart, algorithm is revised and again the flow chart is redrawn for consistency. After satisfying oneself that both flow chart and algorithms are in harmony, one starts writing assembly language programs which are directly hand coded in to machine language or converted in to machine code using an Assembler.


and again the flow chart is redrawn for consistency. After satisfying oneself that both flow chart

and algorithms are in harmony, one starts writing assembly language programs which are directly

hand coded in to machine language or converted in to machine code using an Assembler.

A standard AL program statement consists of four fields namely: Label, op code, operand and

comment.

A label field represents the address, the op code field contains the mnemonics of the instruction,

the operand field contains the data and comment field contains comments related to that operation.

EXECUTING A PROGRAM;- To manually write and execute an AL program on a Micro

processor trainer kit with a hexadecimal (hex) keyboard for input, we follow the steps given below.

An AL program written for specific task can be executed and tested for its validity in the following

steps.

(i) Write an AL program using algorithm, flow chart and instructions.

(ii) Write the hexadecimal (hex) code for each instruction by searching

through the instruction set.

(iii) Enter the program in the user memory (RAM) in a sequential order by

using keyboard as the input device.

(iv) Execute the program by pressing the execute key. The answer will be displayed

on the seven segment display.

Fig 14.1 Flow chart symbols.

Continuation to a different page.

Process of an operation

Decision making block.

Beginning or end of a program.

Predefined process or subroutine

Fig. 4.6. Flow chart symbols

A standard AL program statement consists of four fields namely: Label, op code, operand and comment.

A label field represents the address, the op code field contains the mnemonics of the instruction, the operand field contains the data and comment field contains comments related to that operation.

Executing a Program;- To manually write and execute an AL program on a Micro processor trainer kit with a hexadecimal (hex) keyboard for input, we follow the steps given below.

An AL program written for specific task can be executed and tested for its validity in the following steps.

(i) Write an AL program using algorithm, flow chart and instructions.(ii) Write the hexadecimal (hex) code for each instruction by searching through the

instruction set.(iii) Enter the program in the user memory (RAM) in a sequential order by using

keyboard as the input device.(iv) Execute the program by pressing the execute key. The answer will be displayed

on the seven segment display.

4.8 ILLUSTRATIVE PROGRAMSExample 1: To give a better idea of how the data transfer group of instructions are used in programs, we will now write a simple program to input a value from the key board, store this value in memory location and display it. Here we assume that the key board is connected through input port 1 whose address is 05 H, display is connected through output port of address 02H and memory location address is 1050H.

NOTES

Electronics-1


Solution :Algorithm for the above program:1. Input a value from key board connected to the port at address 05H.2. Store the value in memory location 1050H.3. Output the value to a display connected to the port at address 02H.Assembly language program

Table 4.1

M.Sc. Physics 4 8085 Assembly Language…

14.3 Illustrative programs:

Example 1: To give a better idea of how the data transfer group of instructions are used in

programs, we will now write a simple program to input a value from the key board, store this value

in memory location and display it. Here we assume that the key board is connected through input

port 1 whose address is 05 H, display is connected through output port of address 02H and memory

location address is 1050H.

Solution :

Algorithm for the above program:

1. Input a value from key board connected to the port at address 05H.

2. Store the value in memory location 1050H.

3. Output the value to a display connected to the port at address 02H.

Assembly language program:

Example 2:-

To use the arithmetic group and branching group of instructions and to have better concept about

counters and loops, we will write a program to find the sum of a series of numbers stored in the

memory locations, starting from 0850H to 0856H. Store the 16-bit sum in 0860H and 0861H

locations.

In this example, we use the concept of looping. Looping is a technique used to instruct the

processor to execute certain instructions repeatedly. The number of repetitions are specified in a

counter.

Label CommentMnemonics

Op code Operand

IN

STA

OUT

HLT

05H

1050H

02H

; Input from port 05H

; Store in memory

; Send it to display

; End of the program

Table 14.1

Example 2: To use the arithmetic group and branching group of instructions and to have better concept about counters and loops, we will write a program to find the sum of a series of numbers stored in the memory locations, starting from 0850H to 0856H. Store the 16-bit sum in 0860H and 0861H locations.

Flow chart:


Flow chart:

Algorithm:

1) Take initial sum as zero

2) Add the first number to the previous sum (initial sum)

3) Reduce the number of items by one.

4) Add the next number of the given series to the previous sum

5) Reduce the number of items by one

6) Repeat the steps (4) and (5) till all the numbers are added

7) Final sum is the result

8) Stop the process.

Fig 14.2

NO

START

K

Initialize H-L pair asmemory pointer.

Get the count in‘C’ register

Initial Value ofSum = 00 Carry = 00

Sum = previous sum +next number

YES

NO

YES

K

IS CARRY?

CARRY = CARRY + 1

Increment the pointerto get next number

Decrement count

ISCOUNT = 0

?

Store the sum

STOP

Fig. 4.7.

NOTES



In this example, we use the concept of looping. Looping is a technique used to instruct the processor to execute certain instructions repeatedly. The number of repetitions are specified in a counter.

Algorithm1. Take initial sum as zero2. Add the first number to the previous sum (initial sum)3. Reduce the number of items by one.4. Add the next number of the given series to the previous sum5. Reduce the number of items by one6. Repeat the steps (4) and (5) till all the numbers are added7. Final sum is the result8. Stop the process.Program:

Table 4.2


Program:-

The above program can be executed on a microprocessor kit, after converting the program into hex

code and assigning one address to each byte of the program as in the previous example.

Example 3:- 8085 micro processor does not have a multiply instruction. So, when we want to

multiply two numbers, we have to write a program for this. There are various algorithms for the

multiplication of two numbers. Here we adopt a simple repeated addition algorithm .The method

is to initialize a register with zero value and call it RESULT and go on adding one number to the

RESULT second number times. For example if 5 is to be multiplied by 6 it can be done adding 6

to itself 5 times or adding 6 to itself 5 of times.

Algorithm:

1) Take the multiplicand ( I number )

2) Take the initial sum as zero

MnemonicsLabel Comments

LXI

MVI

MVI

MVI

ADD

JNC

INR

INX

DCR

JNZ

STA

MOV

STA

HLT

H, 0850

C, 07

A, 00

B, 00

M

Next

B

H

C

Repeat

0861

A, B

0860

; Initialize the memory

; Get the count

; Clear A register

; Clear B register

; Add the number to previous sum

; Jump to ‘next’ if there is no carry

; Register carry

; Increment the memory pointer

; Decrements the counter

; Jump to ‘repeat’ if counter is not zero.

; Store the sum

; Save the carry

; Store the carry

; End of the program

Repeat:

Next:

Op code Operand

Table 14.2The above program can be executed on a microprocessor kit, after converting the program into hex code and assigning one address to each byte of the program as in the previous example.

Example 3: 8085 micro processor does not have a multiply instruction. So, when we want to multiply two numbers, we have to write a program for this. There are various algorithms for the multiplication of two numbers. Here we adopt a simple repeated addition

NOTES

Electronics-1


algorithm .The method is to initialize a register with zero value and call it RESULT and go on adding one number to the RESULT second number times. For example if 5 is to be multiplied by 6 it can be done adding 6 to itself 5 times or adding 6 to itself 5 of times.

Algorithm1. Take the multiplicand ( I number )

2. Take the initial sum as zero

3. Add the multiplicand to the previous sum

4. Decrement the multiplier

5. Repeat the steps (3) and (4) till the multiplier becomes zero

6. The final sum gives the products of two numbers

7. Stop the process

Flow chart


3) Add the multiplicand to the previous sum

4) Decrement the multiplier

5) Repeat the steps (3) and (4) till the multiplier becomes zero

6) The final sum gives the products of two numbers

7) Stop the process

Flow chart:

Let the numbers (multiplicand, multiplier) be stored at memory locations with the address 0850,

0851; let the result (product) be of 16-bit be stored at locations with the address 0852, 0853 (for

higher and lower order byte of the product). Product is found by using repetitive addition.

Fig 14.3

Get multiplicandGet multiplier

START

Initial value ofproduct = 00

Get multiplierinto counter

Product = product +multiplicand

Count = count - 1

ISCOUNT = 0

?

Store the product

STOP

Fig. 4.8

Let the numbers (multiplicand, multiplier) be stored at memory locations with the address 0850, 0851; let the result (product) be of 16-bit be stored at locations with the address 0852, 0853 (for higher and lower order byte of the product). Product is found by using repetitive addition.

NOTES



Program:

Table 4.3


Program:

EXAMPLE 4:- To have the better concept of using compare instruction in finding the smaller or

bigger or equality of two given numbers we write a program to find the largest number among the

given set of n- numbers.

Let the list starts from a memory location with the address 0850H and let the largest number

be stored at a memory location 0870H

Algorithm:

1) Take the first number from the given series

2) Compare this number, with the next number of given series

3) If the first number is larger than the next number then retain the first number

4) If the first number is smaller than the next number then retain the next number

5) Decrement the number of comparisons

6) Repeat the process of comparison till the largest number in the given list is found.



LXIMOVINXMOVSUBMOVADDJNCINRDCRJNZINXMOVINXMOVHLT

H, 0850B, MHC, MAD, ABLoopDCNextHM, DHM, A

Next:

Loop:

Op code Operand; Initialize the memory pointer; Get the multiplicand; Increment the pointer; Get the multiplier; Make the initial product as 00; Clear reg ‘D’ for carry; Add the multiplicand; Check for carry; Register the carry; Decrement the multiplier; If (C) 0, go to ‘next’; Increment the pointer; Save the carry; Increment the pointer; Save the sum; End of the program

Table 14.3EXAMPLE 4:- To have the better concept of using compare instruction in finding the smaller or bigger or equality of two given numbers we write a program to find the largest number among the given set of n- numbers.

Flow chart:


Flow chart:

PROGRAM:

YES

NO

START

Initialize thememory pointer

Get the count

Get the number

ISNumber >

Next number?

Get larger number

Insert the pointer

K

Decrement the count

Store the result

ISCount = 0

?

K

STOP

YES

NO

Fig 14.4


MVILXIMOVINXCMPJNCMOVDCRJNZSTAHLT

C, n – 1H, 0850A, MHMLoopA, MCNext0870

; Get the count; Initialize the memory pointer; Get the number; Increment the pointer; Compare with memory for largeness; If larger, jump to ‘loop’; If smaller change with memory; Reduce the counter; If comparisons are not over, go to‘next’; Store the largest; End of the program

Next:

Loop:

Op code Operand

Table 14.4

Fig. 4.9

NOTES

Electronics-1


Let the list starts from a memory location with the address 0850H and let the largest number be stored at a memory location 0870H

Algorithm1. Take the first number from the given series

2. Compare this number, with the next number of given series

3. If the first number is larger than the next number then retain the first number

4. If the first number is smaller than the next number then retain the next number

5. Decrement the number of comparisons

6. Repeat the process of comparison till the largest number in the given list is found.

7. Stop the process.

Program:

Table 4.4


Flow chart:

PROGRAM:

YES

NO

START

Initialize thememory pointer

Get the count

Get the number

ISNumber >

Next number?

Get larger number

Insert the pointer

K

Decrement the count

Store the result

ISCount = 0

?

K

STOP

YES

NO

Fig 14.4


MVILXIMOVINXCMPJNCMOVDCRJNZSTAHLT

C, n – 1H, 0850A, MHMLoopA, MCNext0870

; Get the count; Initialize the memory pointer; Get the number; Increment the pointer; Compare with memory for largeness; If larger, jump to ‘loop’; If smaller change with memory; Reduce the counter; If comparisons are not over, go to‘next’; Store the largest; End of the program

Next:

Loop:

Op code Operand

Table 14.4


Here, after converting the AL program into its hex codes and assigning with suitable addresses, the

actual series of data items is to be to loaded into the memory, whose starting address is specified in

the second instruction of above program. The method of loading the data items into the memory is

same as that of loading the program. As an example, suppose the number of items , n is 8, and let

the data items are

0A, 29, 02, 0B, 0E, 22, 39, 49

After executing the program using the above data, the largest number i.e. OE can be viewed at the

specified memory location 0870.

Note that the same program can be used to find the smallest number simply using JC instruction

instead of JNC in the above program.

Example 5:. In most of the microprocessor systems, the key board input is in BCD format( in BCD

format a decimal digit, 0 to 9, is represented by its 4-bit binary equivalent). But the processing of

data inside of the microprocessor is performed in binary format. Hence there is a need to convert

BCD number into its equivalent binary value. In doing so we appreciate the usage of logical AND

and ROTATE instructions.

Algorithm:

1) Take the given 8-bit packed BCD number,

2) Separate the number into two 4-bit un packed BCD digits BCD, and BCD2

3) Convert each digit into its binary value according to its position.

4) Add both binary numbers to obtain the binary equivalent of the given BCD number


Address Data

0870 0E08500851085208530854085508560857

0A29020B0E223949

Address Data

Fig 14.4b

Result

Fig. 4.10

Here, after converting the AL program into its hex codes and assigning with suitable addresses, the actual series of data items is to be to loaded into the memory, whose starting address is specified in the second instruction of above program. The method of loading the

NOTES



data items into the memory is same as that of loading the program. As an example, suppose the number of items , n is 8, and let the data items are

0A, 29, 02, 0B, 0E, 22, 39, 49

After executing the program using the above data, the largest number i.e. OE can be viewed at the specified memory location 0870.

Note that the same program can be used to find the smallest number simply using JC instruction instead of JNC in the above program.

Example 5: In most of the microprocessor systems, the key board input is in BCD format( in BCD format a decimal digit, 0 to 9, is represented by its 4-bit binary equivalent). But the processing of data inside of the microprocessor is performed in binary format. Hence there is a need to convert BCD number into its equivalent binary value. In doing so we appreciate the usage of logical AND and ROTATE instructions.

Flow chart:


Flow chart:

In this example we assume that the packed BCD number stored in memory location 1050H and

we store the result in 1060H.

The conversion of a BCD number into its equivalent binary number employs the principle of

positional weighting in a given number. For example in a number 9610, the digit 9 represents 90

based on its second position from the right. So while converting 96BCD into its binary equivalent

requires the multiplication of 9 by 10 and adding the first digit of 6.

START

Get the BCD number

Get the copy of aboveBCD number

AND with OF

Save the result inunpacked BCD

Sum1

K

Get BCD number

AND with FO

Fig 14.5

K

Rotate towards right(4 times)

Save the result treatas count

Initial sum2 = 00

Sum2 = Sum2 + 0A

Decrement the count

Sum = Sum2 + Sum 1

Save the sum

STOP

ISCOUNT = 0

?

Fig. 4.11

NOTES

Electronics-1


Algorithm1. Take the given 8-bit packed BCD number,

2. Separate the number into two 4-bit un packed BCD digits BCD, and BCD2

3. Convert each digit into its binary value according to its position.

4. Add both binary numbers to obtain the binary equivalent of the given BCD number

5. Stop the process.

In this example we assume that the packed BCD number stored in memory location 1050H and we store the result in 1060H.

The conversion of a BCD number into its equivalent binary number employs the principle of positional weighting in a given number. For example in a number 9610, the digit 9 represents 90 based on its second position from the right. So while converting 96BCD into its binary equivalent requires the multiplication of 9 by 10 and adding the first digit of 6.

Table 4.5


Example 6: Accurate time delays between two events can be generated using assembly language

programming. For example clock generators, digital clocks, flashing of lights etc require these

time delays. The process of generating time delays using software instructions is more flexible than

generation of time delays using hardware. To illustrate this , we write a program to generate time

delay by using counters.

ALGORITHM:

1) Load a register with required delay.

2) Decrement the register.

3) Repeat it till register becomes zero.

Label CommentsMnemonicsOp code Operand

LDA

ANI

MOV

LDA

ANI

RRC

RRC

RRC

RRC

MOV

XRA

MVI

ADE

DCR

JNZ

ADD

STA

HLT

1005H

0FH

C, A

1050H

FOH

D, A

A

E, 0AH

E

D

C

1060H

; Get packed BCD number

; Mask most significant four bits

; Save unpacked BCD, in regC

; Get BCD again

; Mask least significant four bits

; Save BCD2 in D

Table 14.5

AGAIN:

Example 6: Accurate time delays between two events can be generated using assembly language programming. For example clock generators, digital clocks, flashing of lights etc require these time delays. The process of generating time delays using software instructions is more flexible than generation of time delays using hardware. To illustrate this , we write a program to generate time delay by using counters.

ALGORITHM1. Load a register with required delay.

NOTES



2. Decrement the register.

3. Repeat it till register becomes zero.

4. Get out of the loop.

Flow chart:


4) Get out of the loop.

Flow chart:

In the above program, the number N in register C determines the duration of the time delay. For

the calculation of N, we should know the number of states required for the execution of each

instruction and the number of times the instruction is executed. The number of states required can

be found from the data supplied by the microprocessor manufacturer(see the instruction set given)

and the number of times the instruction is executed is determined by the program as shown below.

Instruction States Total number of states

MVI C,N 7 7 x 1

DCRC 4 4 x N

JNZ 10/7 10(N-1)+7 x 1

HLT 5 5 x 1

Decrementregister

Is register = 0

Load delayregister

StopYES

NO

Fig 14.6


Op code Operand

MVI

DCR

JNZ

HLT

C, N

C

BACK

; Load RegC with number N

; Decrement C

;If C 0 Jump to BACK to decrement

Table 14.6

BACK:

Fig. 4.12

Table 4.6


4) Get out of the loop.

Flow chart:

In the above program, the number N in register C determines the duration of the time delay. For

the calculation of N, we should know the number of states required for the execution of each

instruction and the number of times the instruction is executed. The number of states required can

be found from the data supplied by the microprocessor manufacturer(see the instruction set given)

and the number of times the instruction is executed is determined by the program as shown below.


MVI C,N 7 7 x 1

DCRC 4 4 x N

JNZ 10/7 10(N-1)+7 x 1

HLT 5 5 x 1

Decrementregister

Is register = 0

Load delayregister

StopYES

NO

Fig 14.6


Op code Operand

MVI

DCR

JNZ

HLT

C, N

C

BACK

; Load RegC with number N

; Decrement C

;If C 0 Jump to BACK to decrement

Table 14.6

BACK:

In the above program, the number N in register C determines the duration of the time delay. For the calculation of N, we should know the number of states required for the execution of each instruction and the number of times the instruction is executed. The number of states required can be found from the data supplied by the microprocessor manufacturer(see the instruction set given) and the number of times the instruction is executed is determined by the program as shown below.


MVI C,N 7 7 x 1

DCRC 4 4 x N

JNZ 10/7 10(N-1)+7 x 1

HLT 5 5 x 1

Total states = 7x1 + 4N + 10(N-1) + 7x1 + 5x1

NOTES

Electronics-1


= 7+4N+10N-10+7+5 = 14N + 4

Time for one state if the processor is operative with 2MHz clock = .5s

Therefore Time delay = .5*10-6 (N-1)

Using the above relation, the N value can be calculated for the required time delay.

Example 7:

To have the concept of subroutine, we write an assembly language program

to switch ON and OFF an LED connected to an out port of the address 05H.

To visualize the ON and OFF states of LED we include a delay program in between these ON and OFF states.

Algorithm

1) Switch ON the LED

2) Insert delay

3) Switch OFF the LED

4) Insert delay

5) Loop continuously

Flowchart


Total states = 7x1 + 4N + 10(N-1) + 7x1 + 5x1

= 7+4N+10N-10+7+5

= 14N + 4

Time for one state if the processor is operative with 2MHz clock = .5s

Therefore Time delay = .5*10-6 (N-1)

Using the above relation, the N value can be calculated for the required time delay.

Example 7:

To have the concept of subroutine, we write an assembly language program

to switch ON and OFF an LED connected to an out port of the address 05H.

To visualize the ON and OFF states of LED we include a delay program in between these ON and

OFF states.

Algorithm

1) Switch ON the LED

2) Insert delay

3) Switch OFF the LED

4) Insert delay

5) Loop continuously

FlowchartStart

Switch ON LED

CACC Delay

Switch OFF LED

CACC delay

Fig 14.7Fig. 4.13

Program


Program

14.4 Developments in Microprocessors and Applications:

With the success of INTEL 8 bit Micro processors as programmable devices and CPUs of

personal computers, several manufacturers produced a variety of Microprocessors. IBM , the

Computer Giant was rather forced to enter in to PC market. To suit the computational needs INTEL

produced the 8086, a 16 bit microprocessor in 1972 . It’s data bus size is 16-bits. It can handle 16

bit data . It can directly access one mega byte of memory, because its address bus is 20-lines width

(220 = 1MB). It uses 16-bit data bus. The 8086 processor is available in a 40-pin DIP. A single

+5V power supply is required. The clock input signal is generated by the 8284 clock generator /

driver chip. Instruction execution times vary between 2 clock cycles and 30 clock cycles. The

8086 family consists of two types of 16-bit microprocessors, the 8086 and 8088. The main

difference is how the processors communicate with the out side world. The 8088 has an 8-bit, data

path to memory and I/O, while the 8086 has a 16-bit external data path. The 8088 was used in

designing the IBM PC – XT personal computers.

Next, Intel introduced the high performance 80186 and 80188 processors, which are enhanced

versions of the 8086 and 8088 respectively. These were followed by 80286 and 80386 and 80486

processors.

The 80286 is fabricated in a 68-pin package. The 80286 has added memory protection and

management capabilities to the basic 8086 architecture. An external 82284 clock generator chip is

required to generate the clock. The 80286 was used as the CPU of the IBM PC/AT personal

computer. An enhanced version of the 80286 is the 80386 microprocessor. It is a 32-bit processor.

The 80386 is used as the microprocessor in the IBM 386PC. The 80486 with its advanced features

and support from Microsoft software survived long in the market. It has on-chip floating-point

circuitry. It contained a circuitry of 2,75,000 transistors. It could directly address 4 giga bytes (232

START:MVI A, FFHOUT O5HCALL DELAYMVI A, 00HOUT 05HCALL DELAYJMP START

Table 14.7aTable 14.7b

DelayMVI B, FFH

Back: DCR BJNZ BackRET


Program

14.4 Developments in Microprocessors and Applications:

With the success of INTEL 8 bit Micro processors as programmable devices and CPUs of

personal computers, several manufacturers produced a variety of Microprocessors. IBM , the

Computer Giant was rather forced to enter in to PC market. To suit the computational needs INTEL

produced the 8086, a 16 bit microprocessor in 1972 . It’s data bus size is 16-bits. It can handle 16

bit data . It can directly access one mega byte of memory, because its address bus is 20-lines width

(220 = 1MB). It uses 16-bit data bus. The 8086 processor is available in a 40-pin DIP. A single

+5V power supply is required. The clock input signal is generated by the 8284 clock generator /

driver chip. Instruction execution times vary between 2 clock cycles and 30 clock cycles. The

8086 family consists of two types of 16-bit microprocessors, the 8086 and 8088. The main

difference is how the processors communicate with the out side world. The 8088 has an 8-bit, data

path to memory and I/O, while the 8086 has a 16-bit external data path. The 8088 was used in

designing the IBM PC – XT personal computers.

Next, Intel introduced the high performance 80186 and 80188 processors, which are enhanced

versions of the 8086 and 8088 respectively. These were followed by 80286 and 80386 and 80486

processors.

The 80286 is fabricated in a 68-pin package. The 80286 has added memory protection and

management capabilities to the basic 8086 architecture. An external 82284 clock generator chip is

required to generate the clock. The 80286 was used as the CPU of the IBM PC/AT personal

computer. An enhanced version of the 80286 is the 80386 microprocessor. It is a 32-bit processor.

The 80386 is used as the microprocessor in the IBM 386PC. The 80486 with its advanced features

and support from Microsoft software survived long in the market. It has on-chip floating-point

circuitry. It contained a circuitry of 2,75,000 transistors. It could directly address 4 giga bytes (232

START:MVI A, FFHOUT O5HCALL DELAYMVI A, 00HOUT 05HCALL DELAYJMP START

Table 14.7aTable 14.7b

DelayMVI B, FFH

Back: DCR BJNZ BackRET

Table 4.7(a) Table 4.7(b)

NOTES



4.9 DEVELOPMENTS IN MICROPROCESSORS ANDAPPLICATIONSWith the success of INTEL 8 bit Micro processors as programmable devices and CPUs of personal computers, several manufacturers produced a variety of Microprocessors. IBM , the Computer Giant was rather forced to enter in to PC market. To suit the computational needs INTEL produced the 8086, a 16 bit microprocessor in 1972 . It’s data bus size is 16-bits. It can handle 16 bit data . It can directly access one mega byte of memory, because its address bus is 20-lines width (220 = 1MB). It uses 16-bit data bus. The 8086 processor is available in a 40-pin DIP. A single +5V power supply is required. The clock input signal is generated by the 8284 clock generator / driver chip. Instruction execution times vary between 2 clock cycles and 30 clock cycles. The 8086 family consists of two types of 16-bit microprocessors, the 8086 and 8088. The main difference is how the processors communicate with the out side world. The 8088 has an 8-bit, data path to memory and I/O, while the 8086 has a 16-bit external data path. The 8088 was used in designing the IBM PC – XT personal computers.

Next, Intel introduced the high performance 80186 and 80188 processors, which are enhanced versions of the 8086 and 8088 respectively. These were followed by 80286 and 80386 and 80486 processors.

The 80286 is fabricated in a 68-pin package. The 80286 has added memory protection and management capabilities to the basic 8086 architecture. An external 82284 clock generator chip is required to generate the clock. The 80286 was used as the CPU of the IBM PC/AT personal computer. An enhanced version of the 80286 is the 80386 microprocessor. It is a 32-bit processor. The 80386 is used as the microprocessor in the IBM 386PC. The 80486 with its advanced features and support from Microsoft software survived long in the market. It has on-chip floating-point circuitry. It contained a circuitry of 2,75,000 transistors. It could directly address 4 giga bytes (232 bytes) of physical memory. With these processor based systems several new applications like desktop publishing, computer based digital communications were realized. INTEL introduced a new generation PC named Pentium. Even in this generation several versions are available and already up to Pentium III,excepting CELRON a locost version of Pentium II, all have become obsolete. Pentium IV is the current processor with a clock speed of 2.5GHz Even the Celron sytem was upgraded in clock speed to 2.8 GHz INTEL has introduced a new generation processor named Ethenium. The trend of developing new and powerful processors will go on.

Even other manufactures too introduced micro-processors. To quote some of them, Zilog introduced Z80, an 8-bit processor . Z8000 series 16-bit processors. Motorola introduced MC 6800 an 8-bit NMOS processor MC 68000 series 16-bit processors. Advanced Microdevices Inc is also producing processors which can compete with INTEL processors. INTEL processors have become so popular that several manufactures are fabricating clones to INTEL processors and IBM PC compatibles.

NOTES

Electronics-1


ApplicationsMicroprocessors find applications in the area of science, for the measurement and control of various physical parameters like temperature, pressure, PH value, humidity etc; in industries for process control; in day-to-day life for traffic control, for automatic lighting systems; in computers as their CPUs for data collection, analysis; in navigation, in aviation, in remote sensing, in satellite communications, in home appliances, in kid’s toys, video games, in Robotics, in sun tracking systems, in data loggers for recording the data. Besides as CPUs, to suit dedicated applications Micro controllers, single chip computers and bit-slice systems were also developed.

4.10 SUMMERYThe central processing unit of a digital computer built into a single LSI or VLSI chip is called a microprocessor. It is the latest development in the field of computer technology. A VLSI chip contains more than 10,000 transistors. Intel 8085 is an 8-bit NMOS microprocessor. This means the transistors used in the manufacturing of 8085 IC are N-channel Metal Oxide Semiconductor Field Effect Transistors. The 8085 IC has 40 pins and operates on a single +5V DC power supply. Its clock speed is 3MHz. Its memory capacity is 64k Bytes. In the IC, there are 4 functional units:

Timing and control unit, to send central signals and synchronize the p operations with the clock; ALU, to perform arithmetic-logic operations on the data given, Interrupt control unit, to interrupt the execution of program; and serial I/O central unit, to content, the serial form of data into 8-bit, parallel data and vice versa. To reflect the data conditions, 5 Flags are used.

In order to use the microprocessor for a particular application, it has to be connected to various devices. To communicate with the outside world or internal parts, a Microprocessor uses 3 buses namely: address bus, data bus and control bus. The address bus is unidirectional, data bus is bidirectional. Some lines in control bus are input lines and others are output lines. The internal architecture of 8085 Microprocessor determines how and what operations can be performed with data. The operations are: To transfer 8-bit data, to perform arithmetic and logic operations, to text, for a condition and to sequence the execution of instructions.

The 8085 Microprocessor instruction set, has 74 operation codes that result in 246 instructions. The set includes data transfer, arithmetic, logic, branching and machine control instructions. All these instructions may be either one byte, two byte or three byte long. In the instructions, the source and destinations are operands. There are various ways or formats of specifying the operands, which are called the addressing modes. The 8085 microprocessor has 5 types of addressing modes namely., direct, Register, Immediate, Register indirect and Implicit.

NOTES



A microprocessor can be used for a specific application, only, when it is programmed properly. The microprocessor can be programmed using assembly language. The assembly language uses mnemonics to write the program. The AL program consists of statements. Each statement is to be written with four fields namely: Label, op code, operand and comment. Labels are to be followed with a colon, and comments are to be preceded with a semi colon. Before writing the AL program, the idea of solving the problem is to be first expressed in the form of algorithm. After this, the idea is to be interpreted in the form of flow chart. Finally, the AL program is to be written using the mnemonics. In this chapter programming techniques-such as looping, counting and indexing were illustrated using memory related and date transfer instruction.

4.11 KEWYWORDSzz LSI: Large scale Integration: The process of designing more than a thousand

gates on a single semiconductor chip. Similarly VLSI stands for very large scale Integration.

zz Unidirectional: If the bits flow in one direction, i.e. from the microprocessor to the devices, then the operation is called unidirectional.

zz Bi-directional: If the bits follow in both directions, then the operation is called Bi-directional. 8085 data bus is Bi-directional.

zz Interrupt: To break the execution of program temporarily.

zz Flag: It is a Flip-flop which keeps track of changing conditions.

zz Flip-flop:It is bi-stable multi-vibrator exhibiting two states 0 and 1.

zz Program-center: It is a 16-bit register that deals with the operation of sequencing and execution of instructions.

zz Buffer: It, is a logic circuit which amplifier the current or power.

zz DMA: Direct memory access. i.e. accessing the memory directly, by bypassing the microprocessor, with I/O devices.

zz Mnemonic: Symbolic code for each instruction.

zz Flow chart: The pictorial format, representing the thinking process and steps necessary to write the program.

zz Byte: A group of 8-bits

zz Assembly language: A medium of communication that, with a microprocessor in which programs are written in English-link words for representing binary instructions.

zz Assembler: A program that translates an AL program from mnemonics to the binary machine code.

zz Instruction cycle: Time required to complete the execution of an instruction

NOTES

Electronics-1


4.12 REVIEW QUESTIONS1. Define op code, operand and specify the operand in the instruction ADD B.

2. Classify the instructions as per the length of instructions and give examples.

3. Explain the function of ALE and IO/M signals. of 8085 microprocessor.

4. What are the functions of serial I/O control unit and timing and control unit?.

5. Why data bus is bi-directional in 8085 microprocessor? Explain.

6. Explain few branching instructions with an example.

7. Differentiate between machine language and assembly language.

8. What is an assembler? What are its uses?

9. Name the four fields of standard AL program statement.

10. Write an AL program to find the largest between two given numbers.

11. Write an AL program to divide two 8-bit hexadecimal numbers using repetitive subtraction.

12. Write an AL program to count the number of 1 s in a given 8-bit number.

4.13 FURTHER READINGS zz Microprocessor Architecture, Programming and Applications – Gaonkar (Wiley

eastrun)zz Microprocessor Theory and Applications – M.Rafiquzzaman (P.H.I.)zz Digital Computer Electronics – Albert Paul Malvino (TMH)zz Fundamentals of microprocessors and Microcomputers – B.Ram (Dhanpat Rai

& Sons)zz Microprocessor, Architecture, Programming and Applications – Gaonkar.(Wiley

Eastern)zz Fundamentals of Microprocessors and Microcomputers – B. Ram. (Dhanpat Rai

& Sons Publications)

NOTES

Optical Fiber Waveguides


CHAPTER – 5

OPTICAL FIBER WAVEGUIDES


To understand the some losses in optical fi bres

To describe the propagation of light in optical fi bre

To explain the Ray Theory Transmission & Cylindrical Fiber

To understand the Single-mode Fibers & Photonic Crystal Fibers

5.2 INTRODUCTIONThe transmission of light via a dielectric waveguide structure was fi rst proposed and

investigated at the beginning of the twentieth century. In 1910 Hondros and Debye conducted

a theoretical study, and experimental work was reported by Schriever in 1920 [Ref. 2].

However, a transparent dielectric rod, typically of silica glass with a refractive index of

around 1.5, surrounded by air, proved to be an impractical waveguide due to its unsupported

NOTES

Electronics-1


structure (especially when very thin waveguides were considered in order to limit the number

of optical modes propagated) and the excessive losses at any discontinuities of the glass–air

interface. Nevertheless, interest in the application of dielectric optical waveguides in such

areas as optical imaging and medical diagnosis (e.g. endoscopes) led to proposals [Refs

3, 4] for a clad dielectric rod in the mid-1950s in order to overcome these problems. This

structure is illustrated in Figure 5.1, which shows a transparent core with a refractive index

n1 surrounded by a transparent cladding of slightly lower refractive index n

2. The cladding

supports the waveguide structure while also, when suffi ciently thick, substantially reducing

the radiation loss into the surrounding air. In essence, the light energy travels in both the

core and the cladding allowing the associated fi elds to decay to a negligible value at the

cladding–air interface

Fig. 5.1. Optical fi ber waveguide showing the core of refractive index n1, surrounded by the cladding of slightly lower refractive index n2

The invention of the clad waveguide structure led to the fi rst serious proposals by Kao

and Hockham and Werts, in 1966, to utilize optical fi bers as a communications medium, even

though they had losses in excess of 1000 dB km−1. These proposals stimulated tremendous

efforts to reduce the attenuation by purifi cation of the materials.

This has resulted in improved conventional glass refi ning techniques giving fi bers with

losses of around 4.2 dB km−1. Also, progress in glass refi ning processes such as depositing

vapor-phase reagents to form silica [Ref. 8] allowed fi bers with losses below 1 dB km−1 to

be fabricated.

Most of this work was focused on the 0.8 to 0.9 μm wavelength band because the fi rst

generation of optical sources fabricated from gallium aluminum arsenide alloys operated in

this region. However, as silica fi bers were studied in further detail it became apparent that

transmission at longer wavelengths (1.1 to 1.6 μm) would result in lower losses and reduced

signal dispersion. This produced a shift in optical fi ber source and detector technology in order

to provide operation at these longer wavelengths. Hence at longer wavelengths, especially

around 1.55 μm, typical high-performance fi bers have losses of 0.2 dB km−1.

As such losses are very close to the theoretical lower limit for silicate glass fi ber,

there is interest in glass-forming systems which can provide low-loss transmission in the

midinfrared (2 to 5 μm) optical wavelength regions. Although a system based on fl uoride

glass offers the potential for ultra-low-loss transmission of 0.01 dB km−1 at a wavelength

of 5.55 μm, such fi bers still exhibit losses of at least 0.65 dB km−1 and they also cannot yet

be produced with the robust mechanical properties of silica fi bers.

In order to appreciate the transmission mechanism of optical fi bers with dimensions

approximating to those of a human hair, it is necessary to consider the optical waveguiding of a

NOTES



cylindrical glass fi ber. Such a fi ber acts as an open optical waveguide, which may be analyzed

utilizing simple ray theory. However, the concepts of geometric optics are not suffi cient when

considering all types of optical fi ber, and electromagnetic mode theory must be used to give

a complete picture. The following sections will therefore outline the transmission of light in

optical fi bers prior to a more detailed discussion of the various types of fi ber.

We continue the discussion of light propagation in optical fi bers using the ray theory

approach in order to develop some of the fundamental parameters associated with optical fi ber

transmission (acceptance angle, numerical aperture, etc.). Furthermore, this provides a basis

for the discussion of electromagnetic wave propagation presented, where the electromagnetic

mode theory is developed for the planar (rectangular) waveguide. We discuss the waveguiding

mechanism within cylindrical fi bers prior to consideration of both step and graded index

fi bers. Finally, in theoretical concepts and important parameters (cutoff wavelength, spot

size, propagation constant, etc.) associated with optical propagation in single-mode fi bers are

introduced and approximate techniques to obtain values for these parameters are described.

All consideration in the above sections is concerned with what can be referred to

as conventional optical fi ber in the context that it comprises both solid-core and cladding

regions as depicted in Figure 5.1. In the mid-1990s, however, a new class of microstructured

optical fi ber, termed photonic crystal fi ber, was experimentally demonstrated which has

subsequently exhibited the potential to deliver applications ranging from light transmission

over distance to optical device implementations (e.g. power splitters, amplifi ers, bistable

switches, wavelength converters). The signifi cant physical feature of this microstructured

optical fi ber is that it typically contains an array of air holes running along the longitudinal

axis rather than consisting of a solid silica rod structure. Moreover, the presence of these

holes provides an additional dimension to fi ber design which has already resulted in new

developments for both guiding and controlling light. Hence the major photonic crystal fi ber

structures and their guidance mechanisms are outlined and discussed in order to give an

insight into the fundamental developments of this increasingly important fi ber class.

A thin fl exible and transparent wire prepared for light propagation is called optical

fi bre. The optical fi bre has been constructed for the following reasons:

The light wave cannot traverse long distance in air without any losses.

To make loss less light wave communication, the optical waves can be guided

through optical fi bre.

Cladding Core

Outer protective

Outer Protective

The optical fi bre can be used for the many of industrial application and medical

applications as well. The optical fi bre consists of two media kept one inside the other. The

centre transparent medium of optical fi bre is called “core” and the outer is cladding. The

refractive index of core will be always higher than the refractive index of cladding.

NOTES

Electronics-1


5.3 RAY THEORY TRANSMISSION

To consider the propagation of light within an optical fi ber utilizing the ray theory model it

is necessary to take account of the refractive index of the dielectric medium. The refractive

index of a medium is defi ned as the ratio of the velocity of light in a vacuum to the velocity

of light in the medium. A ray of light travels more slowly in an optically dense medium

than in one that is less dense, and the refractive index gives a measure of this effect. When

a ray is incident on the interface between two dielectrics of differing refractive indices (e.g.

glass–air), refraction occurs, as illustrated in Figure 5.2(a). It may be observed that the ray

approaching the interface is propagating in a dielectric of refractive index n1 and is at an

angle φ1 to the normal at the surface of the interface. If the dielectric on the other side of

the interface has a refractive index n2 which is less than n

1, then the refraction is such that

the ray path in this lower index medium is at an angle φ2 to the normal, where φ

2 is greater

than φ1. The angles of incidence φ

1 and refraction φ

2 are related to each other and to the

refractive indices of the dielectrics by Snell’s law of refraction, which states that:

n1 sin φ

1 = n

2 sin φ

2

Fig. 5.2. Light rays incident on a high to low refractive index interface (e.g. glass–air): (a) refraction; (b) the limiting case of refraction showing the critical ray at an

angle φc; (c) total internal refl ection where φ > φc

or:

...(5.1)

NOTES



It may also be observed in Figure 5.2(a) that a small amount of light is refl ected back

into the originating dielectric medium (partial internal refl ection). As n1 is greater than n

2,

the angle of refraction is always greater than the angle of incidence. Thus when the angle of

refraction is 90° and the refracted ray emerges parallel to the interface between the dielectrics,

the angle of incidence must be less than 90°. This is the limiting case of refraction and the

angle of incidence is now known as the critical angle φc, as shown in Figure 5.2(b). From

Eq. (5.1) the value of the critical angle is given by:

...(5.2)

At angles of incidence greater than the critical angle the light is refl ected back into the

originating dielectric medium (total internal refl ection) with high effi ciency (around 99.9%).

Hence, it may be observed in Figure 5.2(c) that total internal refl ection occurs at the interface

between two dielectrics of differing refractive indices when light is incident on the dielectric

of lower index from the dielectric of higher index, and the angle of incidence of the ray

exceeds the critical value. This is the mechanism by which light at a suffi ciently shallow

angle (less than 90° − φc) may be considered to propagate down an optical fi ber with low

loss. Figure 5.3 illustrates the transmission of a light ray in an optical fi ber via a series of

total internal refl ections at the interface of the silica core and the slightly lower refractive

index silica cladding. The ray has an angle of incidence φ at the interface which is greater

than the critical angle and is refl ected at the same angle to the normal.

Fig. 5.3. The transmission of a light ray in a perfect optical fi ber

The light ray shown in Figure 5.3 is known as a meridional ray as it passes through

the axis of the fi ber core. This type of ray is the simplest to describe and is generally used

when illustrating the fundamental transmission properties of optical fi bers. It must also be

noted that the light transmission illustrated in Figure 5.3 assumes a perfect fi ber, and that

any discontinuities or imperfections at the core–cladding interface would probably result in

refraction rather than total internal refl ection, with the subsequent loss of the light ray into

the cladding.

Having considered the propagation of light in an optical fi ber through total internal refl ection

at the core–cladding interface, it is useful to enlarge upon the geometric optics approach with

reference to light rays entering the fi ber. Since only rays with a suffi ciently shallow grazing

angle (i.e. with an angle to the normal greater than φc) at the core–cladding interface are

NOTES

Electronics-1


transmitted by total internal refl ection, it is clear that not all rays entering the fi ber core will

continue to be propagated down its length.

The geometry concerned with launching a light ray into an optical fi ber is shown in

Figure 5.4, which illustrates a meridional ray A at the critical angle φc within the fi ber at the

core–cladding interface. It may be observed that this ray enters the fi ber core at an angle θa

to the fi ber axis and is refracted at the air–core interface before transmission to the core–

cladding interface at the critical angle. Hence, any rays which are incident into the fi ber core

at an angle greater than θa will be transmitted to the core–cladding interface at an angle less

than φc, and will not be totally internally refl ected. This situation is also illustrated in Figure

5.4, where the incident ray B at an angle greater than θa is refracted into the cladding and

eventually lost by radiation. Thus for rays to be transmitted by total internal refl ection within

the fi ber core they must be incident on the fi ber core within an acceptance cone defi ned by the

conical half angle θa. Hence θ

a is the maximum angle to the axis at which light may enter the

fi ber in order to be propagated, and is often referred to as the acceptance angle for the fi ber.

Fig. 5.4. The acceptance angle θa when launching light into an optical fi ber

If the fi ber has a regular cross-section (i.e. the core–cladding interfaces are parallel

and there are no discontinuities) an incident meridional ray at greater than the critical angle

will continue to be refl ected and will be transmitted through the fi ber. From symmetry

considerations it may be noted that the output angle to the axis will be equal to the input

angle for the ray, assuming the ray emerges into a medium of the same refractive index from

which it was input.

The acceptance angle for an optical fi ber was defi ned in the preceding section. However, it is

possible to continue the ray theory analysis to obtain a relationship between the acceptance

angle and the refractive indices of the three media involved, namely the core, cladding and

air. This leads to the defi nition of a more generally used term, the numerical aperture of the

fi ber. It must be noted that within this analysis, as with the preceding discussion of acceptance

angle, we are concerned with meridional rays within the fi ber.

NOTES



Fig. 5.5. The ray path for a meridional ray launched into an optical fi ber in air at an input angle less than the acceptance angle for the fi ber

Figure 5.5 shows a light ray incident on the fi ber core at an angle θ1 to the fi ber axis

which is less than the acceptance angle for the fi ber θa. The ray enters the fi ber from a medium

(air) of refractive index n0, and the fi ber core has a refractive index n

1, which is slightly

greater than the cladding refractive index n2. Assuming the entrance face at the fi ber core

to be normal to the axis, then considering the refraction at the air–core interface and using

Snell’s law given by Eq. (5.1):

n0 sin θ

1 = n

1 sin θ

2 ...(5.3)

Considering the right-angled triangle ABC indicated in Figure 5.5, then:

φ =

2 − θ

2 ...(5.4)

where φ is greater than the critical angle at the core–cladding interface. Hence Eq.

(5.3) becomes:

n0 sin θ

1 = n

1 cos φ ...(5.5)

Using the trigonometrical relationship sin2 φ + cos

2 φ = 1, Eq. (5.5) may be written

in the form:

n0 sin θ

1 = n

l (l − sin

2 φ)1/2 (5.6)

When the limiting case for total internal refl ection is considered, φ becomes equal

to the critical angle for the core–cladding interface and is given by Eq. (5.2). Also in this

limiting case θ1 becomes the acceptance angle for the fi ber θ

a. Combining these limiting

cases into Eq. (5.6) gives:

n0 sin θ

a = (n

12 − n

22 )1/2 ...(5.7)

Equation (5.7), apart from relating the acceptance angle to the refractive indices, serves

as the basis for the defi nition of the important optical fi ber parameter, the numerical aperture

(NA). Hence the NA is defi ned as:

NA = n0 sin θ

a = (n

12 − n

22)1/2 ...(5.8)

Since the NA is often used with the fi ber in air where n0 is unity, it is simply equal to

sin θa. It may also be noted that incident meridional rays over the range 0 ≤ θ1 ≤ θ

a will be

propagated within the fi ber.

The NA may also be given in terms of the relative refractive index difference Δ between

the core and the cladding which is defi ned as:

NOTES

Electronics-1


* Sometimes another parameter Δn = n1 − n

2 is referred to as the index difference and

Δn/n1 as the fractional index difference. Hence Δ also approximates to the fractional index

difference.

...(5.9)

Hence combining Eq. (5.8) with Eq. (5.9) we can write:

...(5.10)

The relationships given in Eqs (5.8) and (5.10) for the numerical aperture are a very

useful measure of the light-collecting ability of a fi ber. They are independent of the fi ber

core diameter and will hold for diameters as small as 8 μm. However, for smaller diameters

they break down as the geometric optics approach is invalid. This is because the ray theory

model is only a partial description of the character of light. It describes the direction a plane

wave component takes in the fi ber but does not take into account interference between such

components. When interference phenomena are considered it is found that only rays with

certain discrete characteristics propagate in the fi ber core. Thus the fi ber will only support a

discrete number of guided modes. This becomes critical in smallcore- diameter fi bers which

only support one or a few modes. Hence electromagnetic mode theory must be applied in

these cases.

Example 5.1A silica optical fi ber with a core diameter large enough to be considered by ray theory analysis

has a core refractive index of 1.50 and a cladding refractive index of 1.47.

Determine: (a) the critical angle at the core–cladding interface; (b) the NA for the fi ber;

(c) the acceptance angle in air for the fi ber.

Solution: (a) The critical angle φc at the core–cladding interface is given by Eq. (5.2)

where:

φc = sin−1

n2

n1

= sin−1 1.47

1.50

= 78.5°

(b) From Eq. (5.8) the NA is:

NA = (n12 − n

22 )1/2 = (1.502 − 1.472)1/2

= (2.25 − 2.16)1/2

= 0.30

(c) Considering Eq. (5.8) the acceptance angle in air θa is given by:

θa = sin−1 NA = sin−1 0.30

= 17.4°

NOTES



Example 5.2A typical relative refractive index difference for an optical fi ber designed for longdistance

transmission is 1%. Estimate the NA and the solid acceptance angle in air for the fi ber when

the core index is 1.46. Further, calculate the critical angle at the

core–cladding interface within the fi ber. It may be assumed that the concepts of geometric

optics hold for the fi ber.

Solution: Using Eq. (5.10) with Δ = 0.01 gives the NA as:

NA = n1(2Δ)1/2 = 1.46(0.02)1/2

= 0.21

For small angles the solid acceptance angle in air ζ is given by:

ζ πθa2 = π sin2 θ

a

Hence from Eq. (5.8):

ζ π (NA)2 = π × 0.04

= 0.13 rad

Using Eq. (5.9) for the relative refractive index difference Δ gives:

Δ n

1 –

n

2

n1

= 1 − n

2

n1

Hence

n

2

n1

= 1 − Δ = 1 − 0.01

= 0.99

From Eq. (5.2) the critical angle at the core–cladding interface is:

φc = sin−1

n2

n1

= sin−1 0.99

= 81.9°

In the preceding sections we have considered the propagation of meridional rays in the optical

waveguide. However, another category of ray exists which is transmitted without passing

through the fi ber axis. These rays, which greatly outnumber the meridional rays, follow a

helical path through the fi ber, as illustrated in Figure 5.6, and are called skew rays. It is not

easy to visualize the skew ray paths in two dimensions, but it may be observed from Figure

5.6(b) that the helical path traced through the fi ber gives a change in direction of 2γ at each

refl ection, where γ is the angle between the projection of the ray in two dimensions and the

radius of the fi ber core at the point of refl ection. Hence, unlike meridional rays, the point

of emergence of skew rays from the fi ber in air will depend upon the number of refl ections

they undergo rather than the input conditions to the fi ber. When the light input to the fi ber

is nonuniform, skew rays will therefore tend to have a smoothing effect on the distribution

of the light as it is transmitted, giving a more uniform output. The amount of smoothing is

dependent on the number of refl ections encountered by the skew rays follow a helical path

NOTES

Electronics-1


Fig. 5.6. The helical path taken by a skew ray in an optical fi ber: (a) skew ray path down the fi ber; (b) crosssectional view of the fi ber

through the fi ber, as illustrated in Figure 5.6, and are called skew rays. It is not easy to

visualize the skew ray paths in two dimensions, but it may be observed from Figure 5.6(b) that

the helical path traced through the fi ber gives a change in direction of 2γ at each refl ection,

where γ is the angle between the projection of the ray in two dimensions and the radius of

the fi ber core at the point of refl ection. Hence, unlike meridional rays, the point of emergence

of skew rays from the fi ber in air will depend upon the number of refl ections they undergo

rather than the input conditions to the fi ber. When the light input to the fi ber is nonuniform,

skew rays will therefore tend to have a smoothing effect on the distribution of the light as

it is transmitted, giving a more uniform output. The amount of smoothing is dependent on

the number of refl ections encountered by the skew rays.

A further possible advantage of the transmission of skew rays becomes apparent when

their acceptance conditions are considered. In order to calculate the acceptance angle for a

skew ray it is necessary to defi ne the direction of the ray in two perpendicular planes. The

geometry of the situation is illustrated in Figure 5.7 where a skew ray is shown incident

on the fi ber core at the point A, at an angle θs to the normal at the fi ber end face. The ray

is refracted at the air–core interface before traveling to the point B in the same plane. The

angles of incidence and refl ection at the point B are φ, which is greater than the critical angle

for the core–cladding interface.

When considering the ray between A and B it is necessary to resolve the direction of

the ray path AB to the core radius at the point B. As the incident and refl ected rays at the

point B are in the same plane, this is simply cos φ. However, if the two perpendicular planes

through which the ray path AB traverses are considered, then γ is the angle between the core

radius and the projection of the ray onto a plane BRS normal to the core axis, and θ is the

angle between the ray and a line AT drawn parallel to the core axis. Thus to resolve the ray

path AB relative to the radius BR in these two perpendicular planes requires multiplication

by cos γ and sin θ.

NOTES



Fig. 5.7. The ray path within the fi ber core for a skew ray incident at an angle θs to the normal at the air–core interface

Hence, the refl ection at point B at an angle φ may be given by:

cos γ sin θ = cos φ ...(5.11)

Using the trigonometrical relationship sin2 φ + cos2 φ = 1, Eq. (5.11) becomes:

cos γ sin θ = cos φ = (1 − sin2 φ)12

...(5.12)

If the limiting case for total internal refl ection is now considered, then φ becomes equal

to the critical angle φc for the core–cladding interface and, following Eq. (5.2), is given by

sin φc = n

2/n

1. Hence, Eq. (5.12) may be written as:

...(5.13)

Furthermore, using Snell’s law at the point A, following Eq. (5.1) we can write:

n0 sin θa = n

1 sin θ ...(5.14)

where θa represents the maximum input axial angle for meridional rays, as expressed

in Section 5.2.2, and θ is the internal axial angle. Hence substituting for sin θ from Eq. (5.13)

into Eq. (5.14) gives:

...(5.15)

where θas now represents the maximum input angle or acceptance angle for skew

rays. It may be noted that the inequality shown in Eq. (5.13) is no longer necessary as all

the terms in Eq. (5.15) are specifi ed for the limiting case. Thus the acceptance conditions

for skew rays are:

n0 sin θas cos γ = (n1

2 − n)1

2 = NA ...(5.16)

and in the case of the fi ber in air (n0 = 1):

sin θas cos γ = NA ...(5.17)

Therefore by comparison with Eq. (5.8) derived for meridional rays, it may be noted

that skew rays are accepted at larger axial angles in a given fi ber than meridional rays,

depending upon the value of cos γ. In fact, for meridional rays cos γ is equal to unity

NOTES

Electronics-1


and θasbecomes equal to θa. Thus although θa is the maximum conical half angle for the

acceptance of meridional rays, it defi nes the minimum input angle for skew rays. Hence,

as maybe observed from Figure 5.6, skew rays tend to propagate only in the annular region

near the outer surface of the core, and do not fully utilize the core as a transmission medium.

However, they are complementary to meridional rays and increase the light-gathering capacity

of the fi ber. This increased light-gathering ability may be signifi cant for large NA fi bers, but

for most communication design purposes the expressions given in Eqs (5.8) and (5.10) for

meridional rays are considered adequate.

Example 5.3An optical fi ber in air has an NA of 0.4. Compare the acceptance angle for meridional rays

with that for skew rays which change direction by 100° at each refl ection.

Solution: The acceptance angle for meridional rays is given by Eq. (5.8) with n0 = 1 as:

θa = sin−1 NA = sin−1 0.4

= 23.6°

The skew rays change direction by 100° at each refl ection, therefore γ = 50°. Hence

using Eq. (5.17) the acceptance angle for skew rays is:

as

= sin–1 NA

cos = sin–1 0.4

cos 50°

= 38.5°

In this example, the acceptance angle for the skew rays is about 15° greater than the

corresponding angle for meridional rays. However, it must be noted that we have only

compared the acceptance angle of one particular skew ray path. When the light input to the

fi ber is at an angle to the fi ber axis, it is possible that γ will vary from zero for meridional

rays to 90° for rays which enter the fi ber at the core–cladding interface giving acceptance

of skew rays over a conical half angle of π/2 radians.

5.4 ELECTROMAGNETIC MODE THEORY FOR OPTICALPROPAGATION

WIn order to obtain an improved model for the propagation of light in an optical fi ber,

electromagnetic wave theory must be considered. The basis for the study of electromagnetic

wave propagation is provided by Maxwell’s equations. For a medium with zero conductivity

these vector relationships may be written in terms of the electric fi eld E, magnetic fi eld H,

electric fl ux density D and magnetic fl ux density B as the curl equations:

...(5.18)

...(5.19)

and the divergence conditions:

NOTES



D = 0 (no free charges) ...(5.20)

. B = 0 (no free poles) ...(5.21)

where is a vector operator.

The four fi eld vectors are related by the relations:

D = E ...(5.22)

B = H

where ε is the dielectric permittivity and μ is the magnetic permeability of the medium.

Substituting for D and B and taking the curl of Eqs (5.18) and (5.19) gives:

...(5.23)

...(5.24)

Then using the divergence conditions of Eqs (5.20) and (5.21) with the vector identity:

× ( × Y) = ( . Y) − 2(Y)

we obtain the nondispersive wave equations:

...(5.25)

and:

...(5.26)

where 2 is the Laplacian operator. For rectangular Cartesian and cylindrical polar

coordinates the above wave equations hold for each component of the fi eld vector, every

component satisfying the scalar wave equation:

...(5.27)

where ψ may represent a component of the E or H fi eld and υp is the phase velocity

(velocity of propagation of a point of constant phase in the wave) in the dielectric medium.

It follows that:

...(5.28)

where r and r are the relative permeability and permittivity for the dielectric medium

and 0 and

0 are the permeability and permittivity of free space. The velocity of light in

free space c is therefore:

...(5.29)

If planar waveguides, described by rectangular Cartesian coordinates (x, y, z), or

circular fi bers, described by cylindrical polar coordinates (r, φ, z), are considered, then the

Laplacian operator takes the form:

...(5.30)

NOTES

Electronics-1


or:

...(5.31)

respectively. It is necessary to consider both these forms for a complete treatment of

optical propagation in the fi ber, although many of the properties of interest may be dealt

with using Cartesian coordinates.

The basic solution of the wave equation is a sinusoidal wave, the most important form

of which is a uniform plane wave given by:

= 0 exp[j(ωt − k . r)] ...(5.32)

where ω is the angular frequency of the fi eld, t is the time, k is the propagation vector

which gives the direction of propagation and the rate of change of phase with distance, while

the components of r specify the coordinate point at which the fi eld is observed. When λ is

the optical wavelength in a vacuum, the magnitude of the propagation vector or the vacuum

phase propagation constant k (where k = |k |) is given by:

...(5.33)

It should be noted that in this case k is also referred to as the free space wave number.

P GThe planar guide is the simplest form of optical waveguide. We may assume it consists of a

slab of dielectric with refractive index n1 sandwiched between two regions of lower refractive

index n2. In order to obtain an improved model for optical propagation it is useful to consider

the interference of plane wave components within this dielectric waveguide.

Fig. 5.8. The formation of a mode in a planar dielectric guide: (a) a plane wave propagating in the guide shown by its wave vector or equivalent ray – the wave

vector is resolved into components in the z and x directions; (b) the interference of plane waves in the guide forming the lowest order mode (m = 0)

The conceptual transition from ray to wave theory may be aided by consideration of a

plane monochromatic wave propagating in the direction of the ray path within the guide (see

NOTES



Figure 5.8(a)). As the refractive index within the guide is n1, the optical wavelength in this

region is reduced to λ/n1, while the vacuum propagation constant is increased to n

1k. When

θ is the angle between the wave propagation vector or the equivalent ray and the guide axis,

the plane wave can be resolved into two component plane waves propagating in the z and

x directions, as shown in Figure 5.8(a). The component of the phase propagation constant

in the z direction βz is given by:

z = n1k cos ...(5.34)

The component of the phase propagation constant in the x direction βx is:

x = n1k sin θ ...(5.35)

The component of the plane wave in the x direction is refl ected at the interface

between the higher and lower refractive index media. When the total phase change* after

two successive refl ections at the upper and lower interfaces (between the points P and Q)

is equal to 2mπ radians, where m is an integer, then constructive interference occurs and a

standing wave is obtained in the x direction. This situation is illustrated in Figure 5.8(b),

where the interference of two plane waves is shown. In this illustration it is assumed that the

interference forms the lowest order (where m = 0) standing wave, where the electric fi eld is

a maximum at the center of the guide decaying towards zero at the boundary between the

guide and cladding. However, it may be observed from Figure 5.8(b) that the electric fi eld

penetrates some distance into the cladding, a phenomenon which is discussed in Section 5.3.4.

Nevertheless, the optical wave is effectively confi ned within the guide and the electric

fi eld distribution in the x direction does not change as the wave propagates in the z direction.

The sinusoidally varying electric fi eld in the z direction is also shown in Figure 5.8(b). The

stable fi eld distribution in the x direction with only a periodic z dependence is known as a

mode. A specifi c mode is obtained only when the angle between the propagation vectors or

the rays and the interface have a particular value, as indicated in Figure 5.8(b). In effect, Eqs

(5.34) and (5.35) defi ne a group or congruence of rays which in the case described represents

the lowest order mode. Hence the light propagating within the guide is formed into discrete

modes, each typifi ed by a distinct value of θ. These modes have a periodic z dependence of

the form exp(− j zz ) where z becomes the propagation constant for the mode as the modal

fi eld pattern is invariant except for a periodic z dependence. Hence, for notational simplicity,

and in common with accepted practice, we denote the mode propagation constant by ,

where = z. If we now assume a time dependence for the monochromatic electromagnetic

light fi eld with angular frequency of exp( j t), then the combined factor exp[ j( t − z)]

describes a mode propagating in the z direction.

To visualize the dominant modes propagating in the z direction we may consider

plane waves corresponding to rays at different specifi c angles in the planar guide. These

plane waves give constructive interference to form standing wave patterns across the guide

following a sine or cosine formula. Figure 5.9 shows examples of such rays for m = 1, 2,

3, together with the electric fi eld distributions in the x direction. It may be observed that m

β θ

β

ββ

β

β β

β

NOTES

Electronics-1


denotes the number of zeros in this transverse fi eld pattern. In this way m signifi es the order

of the mode and is known as the mode number.

Fig. 5.9. Physical model showing the ray propagation and the corresponding transverse electric (TE) fi eld patterns of three lower order models (m = 1, 2, 3) in the

planar dielectric guide

When light is described as an electromagnetic wave it consists of a periodically

varying electric fi eld E and magnetic fi eld H which are orientated at right angles to each

other. The transverse modes shown in Figure 5.9 illustrate the case when the electric fi eld is

perpendicular to the direction of propagation and hence Ez = 0, but a corresponding component

of the magnetic fi eld H is in the direction of propagation. In this instance the modes are

said to be transverse electric (TE). Alternatively, when a component of the E fi eld is in the

direction of propagation, but Hz = 0, the modes formed are called transverse magnetic (TM).

The mode numbers are incorporated into this nomenclature by referring to the TEm

and

TMm modes, as illustrated for the transverse electric modes shown in Figure 5.9. When the

total fi eld lies in the transverse plane, transverse electromagnetic (TEM) waves exist where

both Ez and Hz are zero. However, although TEM waves occur in metallic conductors (e.g.

coaxial cables) they are seldom found in optical waveguides.

Within all electromagnetic waves, whether plane or otherwise, there are points of constant

phase. For plane waves these constant phase points form a surface which is referred to as a

wavefront. As a monochromatic lightwave propagates along a waveguide in the z direction

these points of constant phase travel at a phase velocity υp given by:

NOTES



Fig. 5.10. The formation of a wave packet from the combination of two waves with nearly equal frequencies. The envelope of the wave package or group of waves

travels at a group velocity υg

...(5.36)

where ω is the angular frequency of the wave. However, it is impossible in practice

to produce perfectly monochromatic lightwaves, and light energy is generally composed of

a sum of plane wave components of different frequencies. Often the situation exists where

a group of waves with closely similar frequencies propagate so that their resultant forms a

packet of waves. The formation of such a wave packet resulting from the combination of two

waves of slightly different frequency propagating together is illustrated in Figure 5.10. This

wave packet does not travel at the phase velocity of the individual waves but is observed to

move at a group velocity υg given by:

...(5.37)

The group velocity is of greatest importance in the study of the transmission

characteristics of optical fi bers as it relates to the propagation characteristics of observable

wave groups or packets of light.

If propagation in an infi nite medium of refractive index 1 is considered, then the

propagation constant may be written as:

...(5.38)

where c is the velocity of light in free space. Equation (5.38) follows from Eqs (5.33)

and 5.34) where we assume propagation in the z direction only and hence cos θ is equal to

unity. Using Eq. 5.36) we obtain the following relationship for the phase velocity:

...(5.39)

Similarly, employing Eq. (5.37), where in the limit δω/δβ becomes dω/dβ, the group

velocity:

NOTES

Electronics-1


...(5.40)

The parameter Ng is known as the group index of the guide.

S T I R T EFThe discussion of electromagnetic wave propagation in the planar waveguide given in Section

5.3.2 drew attention to certain phenomena that occur at the guide–cladding interface which

are not apparent from ray theory considerations of optical propagation. In order to appreciate

these phenomena it is necessary to use the wave theory model for total internal refl ection

at a planar interface. This is illustrated in Figure 5.11, where the arrowed lines represent

wave propagation vectors and a component of the wave energy is shown to be transmitted

through the interface into the cladding. The wave equation in Cartesian coordinates for the

electric fi eld in a lossless medium is:

Fig. 5.11. A wave incident on the guide–cladding interface of a planar dielectric waveguide. The wave vectors of the incident, transmitted and refl ected waves

are indicated (solid arrowed lines) together with their components in the z and x irections (dashed arrowed lines)

...(5.41)

As the guide–cladding interface lies in the y–z plane and the wave is incident in the x–z

plane onto the interface, then ∂/∂y may be assumed to be zero. Since the phase fronts must

match all points along the interface in the z direction, the three waves shown in Figure 5.11

will have the same propagation constant β in this direction. Therefore from the discussion

NOTES



of Section 5.3.2 the wave propagation in the z direction may be described by exp[ j(ωt −

βz)]. In addition, there will also be propagation in the x direction. When the components

are resolved in this plane:

x1 = n

1k cos

1 ...(5.42)

x2 = n

2k cos

2 ...(5.43)

where x1 and x2

are propagation constants in the x direction for the guide and cladding

respectively. Thus the three waves in the waveguide indicated in Figure 5.11, the incident, the

transmitted and the refl ected, with amplitudes A, B and C, respectively, will have the forms:

A = A0 exp[−( j x

1x)] exp[ j( t − z)] ...(5.44)

B = B0 exp[−( j x

2x)] exp[ j( t − z)] ...(5.45)

C = C0 exp[( j x

1x)] exp[ j( t − z)] ...(5.46)

Using the simple trigonometrical relationship cos2 + sin2 = 1:

...(5.47)

and:

...(5.48)

When an electromagnetic wave is incident upon an interface between two dielectric

media, Maxwell’s equations require that both the tangential components of E and H and the

normal components of D (= E) and B (= H) are continuous across the boundary. If the

boundary is defi ned at x = 0 we may consider the cases of the transverse electric (TE) and

transverse magnetic (TM) modes.

Initially, let us consider the TE fi eld at the boundary. When Eqs (5.44) and (5.46)

are used to represent the electric fi eld components in the y direction Ey and the boundary

conditions are applied, then the normal components of the E and H fi elds at the interface

may be equated giving:

A0 + C

0 = B

0 ...(5.49)

Furthermore, it can be shown (see Appendix A) that an electric fi eld component in the

y direction is related to the tangential magnetic fi eld component Hz following:

...(5.50)

Applying the tangential boundary conditions and equating Hz by differentiating Ey

gives:

− x1A0 + x2

C0 = − x2

B0 ...(5.51)

Algebraic manipulation of Eqs (5.49) and (5.51) provides the following results:

...(5.52)

(5.53)

θ

θ

θ θ

β

β

β β

β

β

β

β

β

β

β β β

NOTES

Electronics-1


where rER and rET are the refl ection and transmission coeffi cients for the E fi eld at

the interface respectively. The expressions obtained in Eqs (5.52) and (5.53) correspond to

the Fresnel relationships [Ref. 12] for radiation polarized perpendicular to the interface (E

polarization).

When both x1 and x2

are real it is clear that the refl ected wave C is in phase with the

incident wave A. This corresponds to partial refl ection of the incident beam. However, as

1 is increased the component z (i.e. ) increases and, following Eqs (5.47) and (5.48), the

components x1 and x2

decrease. Continuation of this process results in x2 passing through

zero, a point which is signifi ed by 1 reaching the critical angle for total internal refl ection.

If 1 is further increased the component x2

becomes imaginary and we may write it in the

form −j2. During this process x1

remains real because we have assumed that n1 > n

2. Under

the conditions of total internal refl ection Eq. (5.52) may therefore be written as:

...(5.54)

where we observe there is a phase shift of the refl ected wave relative to the incident

wave. This is signifi ed by δE which is given by:

tan ...(5.55)

Furthermore, the modulus of the refl ected wave is identical to the modulus of the

incident wave (| C0 | = | A

0 |). The curves of the amplitude refl ection coeffi cient | rER | and

phase shift on refl ection, against angle of incidence 1, for TE waves incident on a glass–air

interface are displayed in Figure 5.12. These curves illustrate the above results,

Fig. 5.12. Curves showing the refl ection coeffi cient and phase shift on refl ection for transverse electric waves against the angle of incidence for

a glass–air interface (n1 = 1.5, n2 = 1.0). From J. E. Midwinter, Optical Fibers for Transmission, John Wiley & Sons Inc., 1979

where under conditions of total internal refl ection the refl ected wave has an equal

amplitude to the incident wave, but undergoes a phase shift corresponding to E degrees.

A similar analysis may be applied to the TM modes at the interface, which leads to

expressions for refl ection and transmission of the form:

...(5.56)

θ

β β

β

β

β

β β

ββ

θ

θ

θ

NOTES



and:

...(5.57)

where rHR and rHT are, respectively, the refl ection and transmission coeffi cients for the

H fi eld at the interface. Again, the expressions given in Eqs (5.56) and (5.57) correspond

to Fresnel relationships, but in this case they apply to radiation polarized parallel to the

interface (H polarization). Furthermore, considerations of an increasing angle of incidence

1, such that x

2 goes to zero and then becomes imaginary, again results in a phase shift

when total internal refl ection occurs. However, in this case a different phase shift is obtained

corresponding to:

C0 = A

0 exp(2j H) ...(5.58)

where:

...(5.59

Fig. 5.13. The exponentially decaying evanescent fi eld in the cladding of the optical waveguide

Thus the phase shift obtained on total internal refl ection is dependent upon both the

angle of incidence and the polarization (either TE or TM) of the radiation.

The second phenomenon of interest under conditions of total internal refl ection is

the form of the electric fi eld in the cladding of the guide. Before the critical angle for total

internal refl ection is reached, and hence when there is only partial refl ection, the fi eld in the

cladding is of the form given by Eq. (5.45). However, as indicated previously, when total

internal refl ection occurs, x2 becomes imaginary and may be written as −j

2. Substituting

for x2 in Eq. (5.45) gives the transmitted wave in the cladding as:

B = B0 exp(−

2x) exp[ j( t − z)] ...(5.60)

Thus the amplitude of the fi eld in the cladding is observed to decay exponentially* in

the x direction. Such a fi eld, exhibiting an exponentially decaying amplitude, is often referred

to as an evanescent fi eld. Figure 5.13 shows a diagrammatic representation of the evanescent

fi eld. A fi eld of this type stores energy and transports it in the direction of propagation (z)

but does not transport energy in the transverse direction (x). Nevertheless, the existence of

an evanescent fi eld beyond the plane of refl ection in the lower index medium indicates that

optical energy is transmitted into the cladding.

θ β

β

β

β

NOTES

Electronics-1


The penetration of energy into the cladding underlines the importance of the choice of

cladding material. It gives rise to the following requirements:

1. The cladding should be transparent to light at the wavelengths over which the

guide is to operate.

2. Ideally, the cladding should consist of a solid material in order to avoid both

damage to the guide and the accumulation of foreign matter on the guide walls.

These effects degrade the refl ection process by interaction with the evanescent

fi eld. This in part explains the poor performance (high losses) of early optical

waveguides with air cladding.

3. The cladding thickness must be suffi cient to allow the evanescent fi eld to decay

to a low value or losses from the penetrating energy may be encountered. In many

cases, however, the magnitude of the fi eld falls off rapidly with distance from the

guide–cladding interface. This may occur within distances equivalent to a few

wavelengths of the transmitted light.

Therefore, the most widely used optical fi bers consist of a core and cladding, both made

of glass. The cladding refractive index is thus higher than would be the case with liquid or

gaseous cladding giving a lower numerical aperture for the fi ber, but it provides a far more

practical solution.

SThe phase change incurred with the total internal refl ection of a light beam on a planar

dielectric interface may be understood from physical observation. Careful examination

shows that the refl ected beam is shifted laterally from the trajectory predicted by simple

ray theory analysis, as illustrated in Figure 5.14. This lateral displacement is known as the

Goos–Haenchen shift, after its fi rst observers.

The geometric refl ection appears to take place at a virtual refl ecting plane which is

parallel to the dielectric interface in the lower index medium, as indicated in Figure 5.14.

Utilizing wave theory it is possible to determine this lateral shift although it is very small (d

0.06 to 0.10 μm for a silvered glass interface at a wavelength of 0.55 μm) and diffi cult to

observe. However, this concept provides an important insight into the guidance mechanism

of dielectric optical waveguides.

Fig. 5.14. The lateral displacement of a light beam on refl ection at a dielectric interface (Goos–Haenchen shift)

NOTES



5.5 CYLINDRICAL FIBER

The exact solution of Maxwell’s equations for a cylindrical homogeneous core dielectric

waveguide involves much algebra and yields a complex result. Although the presentation of

this mathematics is beyond the scope of this text, it is useful to consider the resulting modal

fi elds. In common with the planar guide (Section 5.3.2), TE (where Ez = 0) and TM (where Hz

= 0) modes are obtained within the dielectric cylinder. The cylindrical waveguide, however,

is bounded in two dimensions rather than one. Thus two integers, l and m, are necessary in

order to specify the modes, in contrast to the single integer (m) required for the planar guide.

For the cylindrical waveguide we therefore refer to TElm and TMlm modes. These modes

correspond to meridional rays traveling within the fi ber. However, hybrid modes where Ez

and Hz are nonzero also occur within the cylindrical waveguide. These modes, which result

from skew ray propagation within the fi ber, are designated HElm and EHlm depending upon

whether the components of or E make the larger contribution to the transverse (to the

fi ber axis) fi eld. Thus an exact description of the modal fi elds in a step index fi ber proves

somewhat complicated.

Fortunately, the analysis may be simplifi ed when considering optical fi bers for

communication purposes. These fi bers satisfy the weakly guiding approximation [Ref. 16]

where the relative index difference Δ < 1. This corresponds to small grazing angles θ in

Eq. (5.34). In fact Δ is usually less than 0.03 (3%) for optical communications fi bers. For

weakly guiding structures with dominant forward propagation, mode theory gives dominant

transverse fi eld components. Hence approximate solutions for the full set of HE, EH, TE and

TM modes may be given by two linearly polarized components [Ref. 16]. These linearly

polarized (LP) modes are not exact modes of the fi ber except for the fundamental (lowest

order) mode. However, as Δ in weakly guiding fi bers is very small, then HE–EH mode

pairs occur which have almost identical propagation constants. Such modes are said to be

degenerate. The superpositions of these degenerating modes characterized by a common

propagation constant correspond to particular LP modes regardless of their HE, EH, TE or

TM fi eld confi gurations. This linear combination of degenerate modes obtained from the

exact solution produces a useful simplifi cation in the analysis of weakly guiding fi bers.

The relationship between the traditional HE, EH, TE and TM mode designations and

the LPlm mode designations is shown in Table 5.1. The mode subscripts l and m are related

to the electric fi eld intensity profi le for a particular LP mode (see Figure 5.15(d)). There are

in general 2l fi eld maxima around the circumference of the fi ber core and m fi eld maxima

along a radius vector. Furthermore, it may be observed from Table 5.1 that the notation for

labeling the HE and EH modes has changed from that specifi ed for the exact solution in

the cylindrical waveguide mentioned previously. The subscript l in the LP notation now

corresponds to HE and EH modes with labels l + 1 and l − 1 respectively.

NOTES

Electronics-1


Table 5.1. Correspondence between the lower order in linearly polarized modes and the traditional exact modes from which they are formed

Linearly polarized Exact

lm m m m

lm l l m l m

Fig. 5.15. The electric fi eld confi gurations for the three lowest LP modes illustrated in terms of their constituent exact modes: (a) LP mode designations; (b) exact

mode designations; (c) electric fi eld distribution of the exact modes; (d) intensity distribution of Ex for the exact modes indicating the electric fi eld intensity profi le for

the corresponding LP modes

The electric fi eld intensity profi les for the lowest three LP modes, together with the

electric fi eld distribution of their constituent exact modes, are shown in Figure 5.15. It may

be observed from the fi eld confi gurations of the exact modes that the fi eld strength in the

transverse direction (Ex or Ey) is identical for the modes which belong to the same LP mode.

Hence the origin of the term ‘linearly polarized’.

Using Eq. (5.31) for the cylindrical homogeneous core waveguide under the weak

guidance conditions outlined above, the scalar wave equation can be written in the form:

NOTES



...(5.61)

where ψ is the fi eld (E or H), n1 is the refractive index of the fi ber core, k is the

propagation constant for light in a vacuum, and r and φ are cylindrical coordinates. The

propagation constants of the guided modes β lie in the range:

n2k < β < n

1k ...(5.62)

where n2

is the refractive index of the fi ber cladding. Solutions of the wave equation

for the cylindrical fi ber are separable, having the form:

...(5.63)

where in this case ψ represents the dominant transverse electric fi eld component. The

periodic dependence on φ following cos lφ or sin lφ gives a mode of radial order l. Hence

the fi ber supports a fi nite number of guided modes of the form of Eq. (5.63). Introducing the

solutions given by Eq. (5.63) into Eq. (5.61) results in a differential equation of the form:

...(5.64)

Fig. 5.16. (a) Variation of the Bessel function J l(r) for l = 0, 1, 2, 3 (fi rst four orders), plotted against r. (b) Graph of the modifi ed Bessel function Kl(r) against r for l = 0, 1

NOTES

Electronics-1


For a step index fi ber with a constant refractive index core, Eq. (5.64) is a Bessel

differential equation and the solutions are cylinder functions. In the core region the solutions

are Bessel functions denoted by Jl. A graph of these gradually damped oscillatory functions

(with respect to r) is shown in Figure 5.16(a). It may be noted that the fi eld is fi nite at r = 0

and may be represented by the zero-order Bessel function J0. However, the fi eld vanishes as

r goes to infi nity and the solutions in the cladding are therefore modifi ed Bessel functions

denoted by Kl. These modifi ed functions decay exponentially with respect to r, as illustrated

in Figure 5.16(b). The electric fi eld may therefore be given by:

...(5.65)

where G is the amplitude coeffi cient and R = r/a is the normalized radial coordinate

when a is the radius of the fi ber core; U and W, which are the eigenvalues in the core and

cladding respectively,* are defi ned as:

...(5.66)

...(5.67)

The sum of the squares of U and W defi nes a very useful quantity [Ref. 18] which is

usually referred to as the normalized frequency* V where:

...(5.68)

It may be observed that the commonly used symbol for this parameter is the same as

that normally adopted for voltage. However, within this chapter there should be no confusion

over this point. Furthermore, using Eqs (5.8) and (5.10) the normalized frequency may be

expressed in terms of the numerical aperture NA and the relative refractive index difference

Δ, respectively, as:

...(5.69)

...(5.70)

The normalized frequency is a dimensionless parameter and hence is also sometimes

simply called the V number or value of the fi ber. It combines in a very useful manner the

information about three important design variables for the fi ber: namely, the core radius a,

the relative refractive index difference Δ and the operating wavelength λ. It is also possible

to defi ne the normalized propagation constant b for a fi ber in terms of the parameters of Eq.

(5.68) so that:

...(5.71)

Referring to the expression for the guided modes given in Eq. (5.62), the limits of β

are n2k and n

1k, hence b must lie between 0 and 1.

NOTES



In the weak guidance approximation the fi eld matching conditions at the boundary

require continuity of the transverse and tangential electric fi eld components at the core–

cladding interface (at r = a). Therefore, using the Bessel function relations outlined previously,

an eigenvalue equation for the LP modes may be written in the following form:

...(5.72)

Solving Eq. (5.72) with Eqs (5.66) and (5.67) allows the eigenvalue U and hence β

to be calculated as a function of the normalized frequency. In this way the propagation

characteristics of the various modes, and their dependence on the optical wavelength and

the fi ber parameters, may be determined.

Considering the limit of mode propagation when β = n2k, then the mode phase velocity

is equal to the velocity of light in the cladding and the mode is no longer properly guided.

In this case the mode is said to be cut off and the eigenvalue W = 0 (Eq. 5.67). Unguided

or radiation modes have frequencies below cutoff where β < kn2, and hence W is imaginary.

Nevertheless, wave propagation does not cease abruptly below cutoff. Modes exist

where β < kn2 but the difference is very small, such that some of the energy loss due to

radiation is prevented by an angular momentum barrier formed near the core–cladding

interface. Solutions of the wave equation giving these states are called leaky modes, and

often behave as very lossy guided modes rather than radiation modes. Alternatively, as β is

increased above n2k, less power is propagated in the cladding until at β = n

1k all the power

is confi ned to the fi ber core. As indicated previously, this range of values for β signifi es the

guided modes of the fi ber.

Fig. 5.17. The allowed regions for the LP modes of order l = 0, 1 against normalized frequency (V) for a circular optical waveguide with a constant refractive index core (step index fi ber). Reproduced with permission from D. Gloge. Appl. Opt., 10, p. 2552, 1971

The lower order modes obtained in a cylindrical homogeneous core waveguide are

shown in Figure 5.17. Both the LP notation and the corresponding traditional HE, EH, TE

and TM mode notations are indicated. In addition, the Bessel functions J0 and J

1 are plotted

NOTES

Electronics-1


against the normalized frequency and where they cross the zero gives the cutoff point for

the various modes. Hence, the cutoff point for a particular mode corresponds to a distinctive

value of the normalized frequency (where V = Vc) for the fi ber. It may be observed from

Figure 5.17 that the value of Vc is different for different modes. For example, the fi rst zero

crossing J1 occurs when the normalized frequency is 0 and this corresponds to the cutoff for

the LP01

mode. However, the fi rst zero crossing for J0 is when the normalized frequency is

5.405, giving a cutoff value Vc of 5.405 for the LP11

mode. Similarly, the second zero of J1

corresponds to a normalized frequency of 3.83, giving a cutoff value Vc for the 02

mode of

3.83. It is therefore apparent that fi bers may be produced with particular values of normalized

frequency which allow only certain modes to propagate. This is further illustrated in Figure

5.18 [Ref. 16] which shows the normalized propagation constant for a number of LP

modes as a function of V. It may be observed that the cutoff value of normalized frequency

Vc which occurs when β = n2k corresponds to b = 0.

The propagation of particular modes within a fi ber may also be confi rmed through visual

analysis. The electric fi eld distribution of different modes gives similar distributions of light

intensity within the fi ber core. These waveguide patterns (often called mode patterns) may

give an indication of the predominant modes propagating in the fi ber. The fi eld intensity

distributions for the three lower order LP modes were shown in Figure 5.15. In Figure 5.19

we illustrate the mode patterns for two higher order LP modes. However, unless the fi ber is

designed for the propagation of a particular mode it is likely that the superposition of many

modes will result in no distinctive pattern.

Fig. 5.18. The normalized propagation constant b as a function of normalized frequency V for a number of LP modes. Reproduced with permission

from D. Gloge. Appl. Opt., 10, p. 2552, 1971

NOTES



Fig. 5.19. Sketches of fi ber crosssections illustrating the distinctive light intensity distributions (mode patterns) generated by propagation of individual linearly

polarized modes

We have thus far considered the propagation aspects of perfect dielectric waveguides.

However, waveguide perturbations such as deviations of the fi ber axis from straightness,

variations in the core diameter, irregularities at the core–cladding interface and refractive

index variations may change the propagation characteristics of the fi ber. These will have

the effect of coupling energy traveling in one mode to another depending on the specifi c

perturbation.

Ray theory aids the understanding of this phenomenon, as shown in Figure 5.20, which

illustrates two types of perturbation. It may be observed that in both cases the ray no longer

maintains the same angle with the axis. In electromagnetic wave theory this corresponds

to a change in the propagating mode for the light. Thus individual modes do not normally

propagate throughout the length of the fi ber without large energy transfers to adjacent

modes, even when the fi ber is exceptionally good quality and is not strained or bent by its

surroundings. This mode conversion is known as mode coupling or mixing. It is usually

analyzed using coupled mode equations which can be obtained directly from Maxwell’s

equations. However, the theory is beyond the scope of this text and the reader is directed to

for a comprehensive treatment. Mode coupling affects the transmission properties of fi bers

in several important ways, a major one being in relation to the dispersive properties of fi bers

over long distances.

The optical fi ber considered in the preceding sections with a core of constant refractive

index n1 and a cladding of a slightly lower refractive index n

2 is known as step index fi ber.

This is because the refractive index profi le for this type of fi ber makes a step change at the

core–cladding interface, as indicated in Figure 5.21, which illustrates the two major types

of step index fi ber. The refractive index profi le may be defi ned

NOTES

Electronics-1


Fig. 5.20. Ray theory illustrations showing two of the possible fi ber perturbations which give mode coupling: (a) irregularity at the core–cladding interface; (b) fi ber bend

Fig. 5.21. The refractive index profi le and ray transmission in step index fi bers: (a) multimode step index fi ber; (b) singlemode step index fi ber

...(5.73)

in both cases.

NOTES



Figure 5.21(a) shows a multimode step index fi ber with a core diameter of around 50

μm or greater, which is large enough to allow the propagation of many modes within the fi ber

core. This is illustrated in Figure 5.21(a) by the many different possible ray paths through

the fi ber. Figure 5.21(b) shows a single-mode or monomode step index fi ber which allows

the propagation of only one transverse electromagnetic mode (typically HE11

), and hence

the core diameter must be of the order of 2 to 10 μm. The propagation of a single mode is

illustrated in Figure 5.21(b) as corresponding to a single ray path only (usually shown as

the axial ray) through the fi ber.

The single-mode step index fi ber has the distinct advantage of low intermodal dispersion

(broadening of transmitted light pulses), as only one mode is transmitted, whereas with

multimode step index fi ber considerable dispersion may occur due to the differing group

velocities of the propagating modes. This in turn restricts the maximum bandwidth attainable

with multimode step index fi bers, especially when compared with single-mode fi bers.

However, for lower bandwidth applications multimode fi bers have several advantages over

single-mode fi bers. These are:

(a) The use of spatially incoherent optical sources (e.g. most light-emitting diodes)

which cannot be effi ciently coupled to single-mode fi bers;

(b) Larger numerical apertures, as well as core diameters, facilitating easier coupling

to optical sources;

(c) Lower tolerance requirements on fi ber connectors.

Multimode step index fi bers allow the propagation of a fi nite number of guided modes

along the channel. The number of guided modes is dependent upon the physical parameters

(i.e. relative refractive index difference, core radius) of the fi ber and the wavelengths of

the transmitted light which are included in the normalized frequency V for the fi ber. It

was indicated in Section 5.4.1 that there is a cutoff value of normalized frequency Vc for

guided modes below which they cannot exist. However, mode propagation does not entirely

cease below cutoff. Modes may propagate as unguided or leaky modes which can travel

considerable distances along the fi ber. Nevertheless, it is the guided modes which are of

paramount importance in optical fi ber communications as these are confi ned to the fi ber over

its full length. It can be shown that the total number of guided modes or mode volume Ms

for a step index fi ber is related to the V value for the fi ber by the approximate expression:

...(5.74)

which allows an estimate of the number of guided modes propagating in a particular

multimode step index fi ber.

Example 5.4A multimode step index fi ber with a core diameter of 80 μm and a relative index difference

of 1.5% is operating at a wavelength of 0.85 μm. If the core refractive index is 1.48, estimate:

(a) the normalized frequency for the fi ber; (b) the number of guided modes.

NOTES

Electronics-1


Solution: (a) The normalized frequency may be obtained from Eq. (5.70) where:

V 2

an2 (2Δ)1/2 =

2 × 40 × 10 –8 × 1.48

0.85 × 10–8 2 (2 × 0.015)1/2 = 75.8

(b) The total number of guided modes is given by Eq. (5.74) as:

Ms V2

2 =

5745.6

2 = 2873

Hence this fi ber has a V number of approximately 76, giving nearly 3000 guided modes.

Therefore, as illustrated in Example 5.4, the optical power is launched into a large

number of guided modes, each having different spatial fi eld distributions, propagation

constants, etc. In an ideal multimode step index fi ber with properties (i.e. relative index

difference, core diameter) which are independent of distance, there is no mode coupling,

and the optical power launched into a particular mode remains in that mode and travels

independently of the power launched into the other guided modes. Also, the majority of these

guided modes operate far from cutoff, and are well confi ned to the fi ber core. Thus most of

the optical power is carried in the core region and not in the cladding.

The properties of the cladding (e.g. thickness) do not therefore signifi cantly affect the

propagation of these modes.

Graded index fi bers do not have a constant refractive index in the core* but a decreasing

core index n(r) with radial distance from a maximum value of n1 at the axis to a constant

value n2 beyond the core radius a in the cladding. This index variation may be represented as:

...(5.75)

Fig. 5.22. Possible fi ber refractive index profi les for different values of α (given in Eq. (5.75))

where Δ is the relative refractive index difference and α is the profi le parameter which

gives the characteristic refractive index profi le of the fi ber core. Equation (5.75) which is a

NOTES



convenient method of expressing the refractive index profi le of the fi ber core as a variation

of α, allows representation of the step index profi le when α = ∞, a parabolic profi le when α

= 2 and a triangular profi le when α = 1. This range of refractive index profi les is illustrated

in Figure 5.22.

The graded index profi les which at present produce the best results for multimode

optical propagation have a near parabolic refractive index profi le core with α 2. Fibers with

such core index profi les are well established and consequently when the term ‘graded index’

is used without qualifi cation it usually refers to a fi ber with this profi le. For this reason in

this section we consider the waveguiding properties of graded index fi ber with a parabolic

refractive index profi le core.

Fig. 5.23. The refractive index profi le and ray transmission in a multimode graded index fi ber

A multimode graded index fi ber with a parabolic index profi le core is illustrated in

Figure 5.23. It may be observed that the meridional rays shown appear to follow curved

paths through the fi ber core. Using the concepts of geometric optics, the gradual decrease in

refractive index from the center of the core creates many refractions of the rays as they are

effectively incident on a large number or high to low index interfaces. This mechanism is

illustrated in Figure 5.24 where a ray is shown to be gradually curved, with an ever increasing

angle of incidence, until the conditions for total internal refl ection are met, and the ray travels

back towards the core axis, again being continuously refracted.

Fig. 5.24. An expanded ray diagram showing refraction at the various high to low index interfaces within a graded index fi ber, giving an overall curved ray path

NOTES

Electronics-1


Fig. 5.25. A helical skew ray path within a graded index fi ber

Multimode graded index fi bers exhibit far less intermodal dispersion (see Section

3.10.2) than multimode step index fi bers due to their refractive index profi le. Although many

different modes are excited in the graded index fi ber, the different group velocities of the

modes tend to be normalized by the index grading. Again considering ray theory, the rays

traveling close to the fi ber axis have shorter paths when compared with rays which travel into

the outer regions of the core. However, the near axial rays are transmitted through a region of

higher refractive index and therefore travel with a lower velocity than the more extreme rays.

This compensates for the shorter path lengths and reduces dispersion in the fi ber. A similar

situation exists for skew rays which follow longer helical paths, as illustrated in Figure 5.25.

These travel for the most part in the lower index region at greater speeds, thus giving the

same mechanism of mode transit time equalization. Hence, multimode graded index fi bers

with parabolic or near-parabolic index profi le cores have transmission bandwidths which may

be orders of magnitude greater than multimode step index fi ber bandwidths. Consequently,

although they are not capable of the bandwidths attainable with single-mode fi bers, such

multimode graded index fi bers have the advantage of large core diameters (greater than 30

μm) coupled with bandwidths suitable for longdistance communication.

The parameters defi ned for step index fi bers (i.e. NA, Δ, V) may be applied to graded

index fi bers and give a comparison between the two fi ber types. However, it must be noted

that for graded index fi bers the situation is more complicated since the numerical aperture is

a function of the radial distance from the fi ber axis. Graded index fi bers, therefore, accept less

light than corresponding step index fi bers with the same relative refractive index difference.

Electromagnetic mode theory may also be utilized with the graded profi les. Approximate

fi eld solutions of the same order as geometric optics are often obtained employing the WKB

method from quantum mechanics after Wentzel, Kramers and Brillouin. Using the WKB

method modal solutions of the guided wave are achieved by expressing the fi eld in the form:

...(5.76)

where G and S are assumed to be real functions of the radial distance r.

Substitution of Eq. (5.76) into the scalar wave equation of the form given by Eq.

(5.61) (in which the constant refractive index of the fi ber core n1 is replaced by n(r)) and

neglecting the second derivative of Gi(r) with respect to r provides approximate solutions

for the amplitude function Gi(r) and the phase function S(r). It may be observed from the

NOTES



ray diagram shown in Figure 5.23 that a light ray propagating in a graded index fi ber does

not necessarily reach every point within the fi ber core. The ray is contained within two

cylindrical caustic surfaces and for most rays a caustic does not coincide with the core–

cladding interface. Hence the caustics defi ne the classical turning points of the light ray within

the graded fi ber core. These turning points defi ned by the two caustics may be designated

as occurring at r = r1 and r = r

2.

The result of the WKB approximation yields an oscillatory fi eld in the region r1 < r <

r2 between the caustics where:

... (5.77)

(where D is an amplitude coeffi cient) and:

...(5.78)

Outside the interval r1 < r < r

2 the fi eld solution must have an evanescent form. In the

region inside the inner caustic defi ned by r < r1 and assuming r

1 is not too close to r = 0, the

fi eld decays towards the fi ber axis giving:

(5.79)

...(5.80)

where the integer m is the radial mode number and:

...(5.81)

Also outside the outer caustic in the region r > r2, the fi eld decays away from the fi ber

axis and is described by the equations:

...(5.82)

...(5.83)

...(5.84)

The WKB method does not initially provide valid solutions of the wave equation

in the vicinity of the turning points. Fortunately, this may be amended by replacing the

actual refractive index profi le by a linear approximation at the location of the caustics. The

solutions at the turning points can then be expressed in terms of Hankel functions of the

fi rst and second kind of order 1 --3. This facilitates the joining together of the two separate

solutions described previously for inside and outside the interval r1 < r < r

2. Thus the WKB

theory provides an approximate eigenvalue equation for the propagation constant β of the

guided modes which cannot be determined using ray theory. The WKB eigenvalue equation

of which β is a solution is given by:

...(5.85)

NOTES

Electronics-1


where the radial mode number m = 1, 2, 3 . . . and determines the number of maxima

of the oscillatory fi eld in the radial direction. This eigenvalue equation can only be solved

in a closed analytical form for a few simple refractive index profi les. Hence, in most cases

it must be solved approximately or with the use of numerical techniques.

Finally the amplitude coeffi cient D may be expressed in terms of the total optical power

PG within the guided mode. Considering the power carried between the turning points r1

and r2 gives a geometric optics approximation of:

...(5.86)

where:

...(5.87)

Fig. 5.26. Graphical representation of the functions (n2(r)k2 − β2) and (l2/r2) that are important in the WKB solution and which defi ne the turning points r1 and r2. Also shown is an example of the corresponding WKB solution for a guided mode where

an oscillatory wave exists in the region between the turning points

The properties of the WKB solution may by observed from a graphical representation

of the integrand given in Eq. (5.78). This is shown in Figure 5.26, together with the

corresponding WKB solution. Figure 5.26 illustrates the functions (n2(r)k2 − β2) and (l2/r2).

The two curves intersect at the turning points r = r1 and r = r

2. The oscillatory nature of the

WKB solution between the turning points (i.e. when l2/r2 < n2(r)k2 − β2) which changes into

a decaying exponential (evanescent) form outside the interval r1 < r < r

2 (i.e. when l

2/r

2 >

n2(r)k

2 − β

2) can also be clearly seen.

NOTES



It may be noted that as the azimuthal mode number l increases, the curve (l2/r2) moves

higher and the region between the two turning points becomes narrower. In addition, even

when l is fi xed the curve (n2(r)k2 − β2) is shifted up and down with alterations in the value

of the propagation constant β. Therefore, modes far from cutoff which have large values of

β exhibit more closely spaced turning points. As the value of β decreases below n2k, (n2(r)

k2 − β2) is no longer negative for large values of r and the guided mode situation depicted in

Figure 5.26 changes to one corresponding to Figure 5.27. In this case a third turning point

r = r3 is created when at r = a the curve (n

2(r)k

2 − β

2) becomes constant, thus allowing the

curve (l2/r

2) to drop below it. Now the fi eld displays an evanescent, exponentially decaying

form in the region r2 < r < r

3, as shown in Figure 5.27. Moreover, for r > r

3 the fi eld resumes

an oscillatory behavior and therefore carries power away from the fi ber core. Unless mode

cutoff occurs at β = n2k, the guided mode is no longer fully contained within the fi ber core

but loses power through leakage or tunneling into the cladding. This situation corresponds

to the leaky modes mentioned previously in Section 5.4.1.

The WKB method may be used to calculate the propagation constants for the modes

in a parabolic refractive index profi le core fi ber where, following Eq. (5.75):

Fig. 5.27. Similar graphical representation as that illustrated in Fig. 5.26. Here the curve (n2(r)k

2 − β2) no longer goes negative and a third turning point r3 occurs. This corresponds to leaky mode solutions in the WKB method

...(5.88)

Substitution of Eq. (5.88) into Eq. (5.85) gives:

...(5.89)

NOTES

Electronics-1


The integral shown in Eq. (5.89) can be evaluated using a change of variable from r

to u = r2. The integral obtained may be found in a standard table of indefi nite integrals. As

the square root term in the resulting expression goes to zero at the turning points (i.e. r = r1

and r = r2), then we can write:

...(5.90)

Solving Eq. (5.90) for β2 gives:

...(5.91)

It is interesting to note that the solution for the propagation constant for the various

modes in a parabolic refractive index core fi ber given in Eq. (5.91) is exact even though

it was derived from the approximate WKB eigenvalue equation (Eq. (5.85)). However,

although Eq. (5.91) is an exact solution of the scalar wave equation for an infi nitely extended

parabolic profi le medium, the wave equation is only an approximate representation of

Maxwell’s equation. Furthermore, practical parabolic refractive index profi le core fi bers

exhibit a truncated parabolic distribution which merges into a constant refractive index at

the cladding. Hence Eq. (5.91) is not exact for real fi bers.

Fig. 5.28. The mode number plane illustrating the mode boundary and the guided fi ber modes

Equation (5.91) does, however, allow us to consider the mode number plane spanned

by the radial and azimuthal mode numbers m and l. This plane is displayed in Figure 5.28,

where each mode of the fi ber described by a pair of mode numbers is represented as a

point in the plane. The mode number plane contains guided, leaky and radiation modes.

The mode boundary which separates the guided modes from the leaky and radiation modes

is indicated by the solid line in Figure 5.28. It depicts a constant value of β following Eq.

(5.91) and occurs when β = n2k. Therefore, all the points in the mode number plane lying

below the line β = n2k are associated with guided modes, whereas the region above the line

is occupied by leaky and radiation modes. The concept of the mode plane allows us to count

the total number of guided modes within the fi ber. For each pair of mode numbers m and

l the corresponding mode fi eld can have azimuthal mode dependence cos lφ or sin lφ and

NOTES



can exist in two possible polarizations. Hence the modes are said to be fourfold degenerate.

If we defi ne the mode boundary as the function m = f(l), then the total number of guided

modes M is given by:

...(5.92)

as each representation point corresponding to four modes occupies an element of unit

area in the mode plane. Equation (5.92) allows the derivation of the total number of guided

modes or mode volume Mg supported by the graded index fi ber. It can be shown that:

...(5.93)

Furthermore, utilizing Eq. (5.70), the normalized frequency V for the fi ber when Δ 1

is approximately given by:

...(5.94)

Substituting Eq. (5.94) into Eq. (5.93), we have:

...(5.95)

Hence for a parabolic refractive index profi le core fi ber (α = 2), Mg V2/4, which is half

the number supported by a step index fi ber (α = ∞) with the same V value.

5.6 SINGLE-MODE FIBERSThe advantage of the propagation of a single mode within an optical fi ber is that the signal

dispersion caused by the delay differences between different modes in a multimode fi ber

may be avoided. Multimode step index fi bers do not lend themselves to the propagation

of a single mode due to the diffi culties of maintaining single-mode operation within the

fi ber when mode conversion (i.e. coupling) to other guided modes takes place at both input

mismatches and fi ber imperfections. Hence, for the transmission of a single mode the fi ber

must be designed to allow propagation of only one mode, while all other modes are attenuated

by leakage or absorption.

Following the preceding discussion of multimode fi bers, this may be achieved through

choice of a suitable normalized frequency for the fi ber. For single-mode operation, only the

fundamental LP01

mode can exist. Hence the limit of single-mode operation depends on the

lower limit of guided propagation for the LP11

mode. The cutoff normalized frequency for

the LP11

mode in step index fi bers occurs at Vc = 2.405 (see Section 5.4.1). Thus single-mode

propagation of the LP01

mode in step index fi bers is possible over the range:

0 ≤ V < 2.405 ...(5.96)

as there is no cutoff for the fundamental mode. It must be noted that there are in fact

two modes with orthogonal polarization over this range, and the term single-mode applies

to propagation of light of a particular polarization. Also, it is apparent that the normalized

NOTES

Electronics-1


frequency for the fi ber may be adjusted to within the range given in Eq. (5.96) by reduction

of the core radius, and possibly the relative refractive index difference following Eq. (5.70),

which, for single-mode fi bers, is usually less than 1%.

It is clear from Example 5.6 that in order to obtain single-mode operation with a

maximum V number of 5.4, the single-mode fi ber must have a much smaller core diameter

than the equivalent multimode step index fi ber (in this case by a factor of 32). However, it

is possible to achieve single-mode operation with a slightly larger core diameter, albeit still

much less than the diameter of multimode step index fi ber, by reducing the relative refractive

index difference of the fi ber. Both these factors create diffi culties with single-mode fi bers.

The small core diameters pose problems with launching light into the fi ber and with fi eld

jointing, and the reduced relative refractive index difference presents diffi culties in the fi ber

fabrication process.

Graded index fi bers may also be designed for single-mode operation and some specialist

fi ber designs do adopt such non step index profi les (see Section 3.12). However, it may be

shown that the cutoff value of normalized frequency Vc to support a single mode in a graded

index fi ber is given by:

Vc = 2.405(1 + 2/α)1/2 ...(5.97)

Therefore, as in the step index case, it is possible to determine the fi ber parameters

which give single-mode operation.

Fig. 5.29. The refractive index profi le for a singlemode W fi ber

It may be noted that the critical value of normalized frequency for the parabolic profi le

graded index fi ber is increased by a factor of √2 on the step index case. This gives a core

diameter increased by a similar factor for the graded index fi ber over a step index fi ber

with the equivalent core refractive index (equivalent to the core axis index) and the same

relative refractive index difference. The maximum V number which permits single-mode

operation can be increased still further when a graded index fi ber with a triangular profi le is

employed. It is apparent from Eq. (5.97) that the increase in this case is by a factor of √3 over

a comparable step index fi ber. Hence, signifi cantly larger core diameter single-mode fi bers

NOTES



may be produced utilizing this index profi le. Such advanced refractive index profi les, which

came under serious investigation in the early 1980s, have now been adopted, particularly in

the area of dispersion modifi ed fi ber design.

A further problem with single-mode fi bers with low relative refractive index differences

and low V values is that the electromagnetic fi eld associated with the LP10

mode extends

appreciably into the cladding. For instance, with V values less than 1.4, over half the modal

power propagates in the cladding. Thus the exponentially decaying evanescent fi eld may

extend signifi cant distances into the cladding. It is therefore essential that the cladding is of a

suitable thickness, and has low absorption and scattering losses in order to reduce attenuation

of the mode. Estimates show that the necessary cladding thickness is of the order of 50 μm

to avoid prohibitive losses (greater than 1 dB km−1) in single-mode fi bers, especially when

additional losses resulting from microbending (see Section 4.7.1) are taken into account.

Therefore, the total fi ber cross-section for single-mode fi bers is of a comparable size to

multimode fi bers.

Another approach to single-mode fi ber design which allows the V value to be increased

above 5.405 is the W fi ber. The refractive index profi le for this fi ber is illustrated in Figure

5.29 where two cladding regions may be observed. Use of such two-step cladding allows the

loss threshold between the desirable and undesirable modes to be substantially increased.

The fundamental mode will be fully supported with small cladding loss when its propagation

constant lies in the range kn3 < β < kn

1.

If the undesirable higher order modes are excited or converted to have values of

propagation constant β < kn3, they will leak through the barrier layer between a

1 and a

2

(Figure 5.29) into the outer cladding region n3. Consequently these modes will lose power by

radiation into the lossy surroundings. This design can provide single-mode fi bers with larger

core diameters than can the conventional single-cladding approach which proves useful for

easing jointing diffi culties; W fi bers also tend to give reduced losses at bends in comparison

with conventional single-mode fi bers. Following the emergence of single-mode fi bers as a

viable communication medium in 1983, they quickly became the dominant and the most widely

used fi ber type within telecommunications. Major reasons for this situation are as follows:

1. They exhibit the greatest transmission bandwidths and the lowest losses of the

fi ber transmission media.

2. They have a superior transmission quality over other fi ber types because of the

absence of modal noise.

3. They offer a substantial upgrade capability (i.e. future proofing) for future

widebandwidth services using either faster optical transmitters and receivers or

advanced transmission techniques.

4. They are compatible with the developing integrated optics technology.

5. The above reasons 1 to 4 provide confi dence that the installation of single-mode

fi ber will provide a transmission medium which will have adequate performance

such that it will not require replacement over its anticipated lifetime of more than

20 years.

NOTES

Electronics-1


Widely deployed single-mode fi bers employ a step index (or near step index) profi le

design and are dispersion optimized (referred to as standard single-mode fi bers, see

Section 3.11.2) for operation in the 1.3 μm wavelength region. These fi bers are either of a

matchedcladding (MC) or a depressed-cladding (DC) design, as illustrated in Figure 5.30. In

the conventional MC fi bers, the region external to the core has a constant uniform refractive

index which is slightly lower than the core region, typically consisting of pure silica.

Fig. 5.30. Singlemode fi ber step index profi les optimized for operation at a wavelength of 1.3 μm: (a) conventional matchedcladding design; (b) segmented core matchedcladding design; (c) depressedcladding design; (d) profi le specifi cations of

a depressedcladding fi ber [Ref. 42]

Alternatively, when the core region comprises pure silica then the lower index cladding

is obtained through fl uorine doping. A mode-fi eld diameter (MFD) (see Section 5.5.2) of

10 μm is typical for MC fi bers with relative refractive index differences of around 0.3%.

However, improved bend loss performance (see Section 3.6) has been achieved in the 1.55

μm wavelength region with reduced MFDs of about 9.5 μm and relative refractive index

differences of 0.37% [Ref. 40].

An alternative MC fi ber design employs a segmented core as shown in Figure 5.30(b)

[Ref. 41]. Such a structure provides standard single-mode dispersion-optimized performance

at wavelengths around 1.3 μm but is multimoded with a few modes (two or three) in the

shorter wavelength region around 0.8 μm. The multimode operating region is intended to

help relax both the tight tolerances involved when coupling LEDs to such single-mode fi bers

and their connectorization. Thus segmented core fi ber of this type provides for applications

which require an inexpensive initial solution but upgradeability to standard single-mode

fi ber performance at the 1.3 μm wavelength in the future.

In the DC fi bers shown in Figure 5.30 the cladding region immediately adjacent to

the core is of a lower refractive index than that of an outer cladding region. A typical MFD

NOTES



(see Section 5.5.2) of a DC fi ber is 9 μm with positive and negative relative refractive index

differences of 0.25% and 0.12% (see Figure 5.30(d)) [Ref. 42].

It may be noted by rearrangement of Eq. (5.70) that single-mode operation only occurs above

a theoretical cutoff wavelength λc given by:

...(5.98)

where Vc is the cutoff normalized frequency. Hence μ c is the wavelength above which

a particular fi ber becomes single-moded. Dividing Eq. (5.98) by Eq. (5.70) for the same

fi ber we obtain the inverse relationship:

...(5.99)

Thus for step index fi ber where Vc = 2.405, the cutoff wavelength is given by [Ref. 43]:

...(5.100)

An effective cutoff wavelength has been defi ned by the ITU-T which is obtained from

a 2 m length of fi ber containing a single 14 cm radius loop. This defi nition was produced

because the fi rst higher order LP11

mode is strongly affected by fi ber length and curvature

near cutoff. Recommended cutoff wavelength values for primary coated fi ber range from

1.1 to 1.28 μm for single-mode fi ber designed for operation in the 1.3 μm wavelength region

in order to avoid modal noise and dispersion problems. Moreover, practical transmission

systems are generally operated close to the effective cutoff wavelength in order to enhance

the fundamental mode confi nement, but suffi ciently distant from cutoff so that no power is

transmitted in the second-order LP11

mode.

Example 5.6Determine the cutoff wavelength for a step index fi ber to exhibit single-mode operation

when the core refractive index and radius are 1.46 and 4.5 μm, respectively, with the relative

index difference being 0.25%.

Solution: Using Eq. (5.98) with Vc = 5.405 gives:

λc =

2an1(2l)1/2

2.405 =

24.5 × 1.46 (0.05)1/2

2.405 μm

= 1.214 μm

= 1214 nm

Hence the fi ber is single-moded to a wavelength of 1214 nm.

Many properties of the fundamental mode are determined by the radial extent of its

electromagnetic fi eld including losses at launching and jointing, microbend losses, waveguide

NOTES

Electronics-1


dispersion and the width of the radiation pattern. Therefore, the MFD is an important

parameter for characterizing single-mode fi ber properties which takes into account the

wavelength-dependent fi eld penetration into the fi ber cladding. In this context it is a better

measure of the functional properties of single-mode fi ber than the core diameter. For step

index and graded (near parabolic profi le) single-mode fi bers operating near the cutoff

wavelength λc, the fi eld is well approximated by a Gaussian distribution (see Section 5.5.5).

In this case the MFD is generally taken as the distance between the opposite 1/e = 0.37 fi eld

amplitude points and the power 1/e2 = 0.135 points in relation to the corresponding values

on the fi ber axis, as shown in Figure 5.31.

Another parameter which is directly related to the MFD of a single-mode fi ber is the

spot size (or mode-fi eld radius) ω0. Hence MFD = 2ω

0, where ω

0 is the nominal half width of

the input excitation (see Figure 5.31). The MFD can therefore be regarded as the singlemode

analog of the fi ber core diameter in multimode fi bers. However, for many refractive index

profi les and at typical operating wavelengths the MFD is slightly larger than the single-mode

fi ber core diameter.

Fig. 5.31. Field amplitude distribution E(r) of the fundamental mode in a singlemode fi ber illustrating the modefi eld diameter (MFD) and spot size (ω0)

Often, for real fi bers and those with arbitrary refractive index profi les, the radial fi eld

distribution is not strictly Gaussian and hence alternative techniques have been proposed.

However, the problem of defi ning the MFD and spot size for non-Gaussian fi eld distributions

is a diffi cult one and at least eight defi nitions exist. Nevertheless, a more general defi nition

based on the second moment of the far fi eld and known as the Petermann II defi nition

is recommended by the ITU-T. Moreover, good agreement has been obtained using this

defi nition for the MFD using different measurement techniques on arbitrary index fi bers.

The rate of change of phase of the fundamental LP01

mode propagating along a straight fi ber

is determined by the phase propagation constant β (see Section 5.3.2). It is directly related

NOTES



to the wavelength of the LP01

mode λ01

by the factor 2π, since β gives the increase in phase

angle per unit length. Hence:

...(5.101)

Moreover, it is convenient to defi ne an effective refractive index for single-mode fi ber,

sometimes referred to as a phase index or normalized phase change coeffi cient [Ref. 48]

neff

, by the ratio of the propagation constant of the fundamental mode to that of the vacuum

propagation constant:

...(5.102)

Hence, the wavelength of the fundamental mode λ01

is smaller than the vacuum

wavelength λ by the factor 1/neff where:

...(5.103)

It should be noted that the fundamental mode propagates in a medium with a refractive

index n(r) which is dependent on the distance r from the fi ber axis. The effective refractive

index can therefore be considered as an average over the refractive index of this medium.

Within a normally clad fi ber, not depressed-cladded fi bers (see Section 5.5), at long

wavelengths (i.e. small V values) the MFD is large compared to the core diameter and hence

the electric fi eld extends far into the cladding region. In this case the propagation constant β

will be approximately equal to n2k (i.e. the cladding wave number) and the effective index

will be similar to the refractive index of the cladding n2. Physically, most of the power is

transmitted in the cladding material. At short wavelengths, however, the fi eld is concentrated

in the core region and the propagation constant β approximates to the maximum wave

number nlk. Following this discussion, and as indicated previously in Eq. (5.62), then the

propagation constant in single-mode fi ber varies over the interval n2k < β < n

1k. Hence, the

effective refractive index will vary over the range n2 < n

eff < n

1.

In addition, a relationship between the effective refractive index and the normalized

propagation constant defi ned in Eq. (5.71) as:

...(5.104)

may be obtained. Making use of the mathematical relation A2 − B2 = (A + B)(A − B),

Eq. (5.104) can be written in the form:

...(5.105)

However, taking regard of the fact that β n1k, then Eq. (5.105) becomes:

Finally, in Eq. (5.102) neff

is equal to β/k, therefore:

... (5.106)

NOTES

Electronics-1


The dimensionless parameter b which varies between 0 and 1 is particularly useful

in the theory of single-mode fi bers because the relative refractive index difference is very

small, giving only a small range for β. Moreover, it allows a simple graphical representation

of results to be presented as illustrated by the characteristic shown in Figure 5.32 of the

normalized phase constant of β as a function of normalized frequency V in a step index fi ber.

It should also be noted that b(V) is a universal function which does not depend explicitly

on other fi ber parameters.

Fig. 5.32. The normalized propagation constant (b) of the fundamental mode in a step index fi ber shown as a function of the normalized frequency (V)

D M D FThe transit time or group delay μ

g for a light pulse propagating along a unit length of fi ber

is the inverse of the group velocity υg (see Section 5.3.3). Hence:

...(5.107)

The group index of a uniform plane wave propagating in a homogeneous medium has

been determined following Eq. (5.40) as:

However, for a single-mode fi ber, it is usual to defi ne an effective group index* Nge

[Ref. 48] by:

...(5.108)

where υg is considered to be the group velocity of the fundamental fi ber mode. Hence,

the specifi c group delay of the fundamental fi ber mode becomes:

...(5.109)

NOTES



Moreover, the effective group index may be written in terms of the effective refractive

index neff

defi ned in Eq. (5.102) as:

...(5.110)

It may be noted that Eq. (5.110) is of the same form as the denominator of Eq. (5.40)

which gives the relationship between the group index and the refractive index in a transparent

medium (planar guide).

Rearranging Eq. (5.71), β may be expressed in terms of the relative index difference Δ

and the normalized propagation constant b by the following approximate expression:

β = k[(n12 − n

22)b + n

22 ] kn

2[1 + bΔ] ...(5.111)

Furthermore, approximating the relative refractive index difference as (n1 − n

2)/n

2, for

a weakly guiding fi ber where Δ1, we can use the approximation [Ref. 16]:

Fig. 5.33. The mode delay factor (d(Vb)/dV) for the fundamental mode in a step index fi ber shown as a function of normalized frequency (V)

where Ng1 and Ng

2 are the group indices for the fi ber core and cladding regions

respectively. Substituting Eq. (5.111) for β into Eq. (5.107) and using the approximate

expression given in Eq. (5.112), we obtain the group delay per unit distance as:

...(5.113)

The dispersive properties of the fi ber core and the cladding are often about the same

and therefore the wavelength dependence of Δ can be ignored [Ref. 19]. Hence the group

delay can be written as:

...(5.114)

The initial term in Eq. (5.114) gives the dependence of the group delay on wavelength

caused when a uniform plane wave is propagating in an infi nitely extended medium with a

NOTES

Electronics-1


refractive index which is equivalent to that of the fi ber cladding. However, the second term

results from the waveguiding properties of the fi ber only and is determined by the mode

delay factor d(Vb)/dV, which describes the change in group delay caused by the changes in

power distribution between the fi ber core and cladding. The mode delay factor [Ref. 50] is

a further universal parameter which plays a major part in the theory of singlemode fi bers.

Its variation with normalized frequency for the fundamental mode in a step index fi ber is

shown in Figure 5.33.

The fi eld shape of the fundamental guided mode within a single-mode step index fi ber for two

values of normalized frequency is displayed in Figure 5.34. As may be expected, considering

the discussion in Section 5.4.1, it has the form of a Bessel function (J0(r)) in the core region

matched to a modifi ed Bessel function (K0(r)) in the cladding. Depending on the value of

the normalized frequency, a signifi cant proportion of the modal power is propagated in the

cladding region, as mentioned earlier. Hence, even at the cutoff value (i.e. Vc) only about

80% of the power propagates within the fi ber core.

Fig. 5.34. Field shape of the fundamental mode for normalized frequencies, V = 1.5 and V = 2.4

It may be observed from Figure 5.34 that the shape of the fundamental LP01

mode is

similar to a Gaussian shape, which allows an approximation of the exact fi eld distribution

by a Gaussian function. The approximation may be investigated by writing the scalar wave

equation Eq. (5.27) in the form:

...(5.115)

where k is the propagation vector defi ned in Eq. (5.33) and n(x, y) is the refractive

index of the fi ber, which does not generally depend on z, the coordinate along the fi ber

axis. It should be noted that the time dependence exp( jωt) has been omitted from the scalar

wave equation to give the reduced wave equation† in Eq. (5.115). This representation is

valid since the guided modes of a fi ber with a small refractive index difference (i.e. Δ 1)

NOTES



have one predominant transverse fi eld component, for example Ey. By contrast Ex and the

longitudinal component are very much smaller.

The fi eld of the fundamental guided mode may therefore be considered as a scalar

quantity and need not be described by the full set of Maxwell’s equations. Hence Eq. (5.115)

may be written as:

...(5.116)

where φ represents the dominant transverse electric fi eld component.

The near-Gaussian shape of the predominant transverse fi eld component of the

fundamental mode has been demonstrated for fi bers with a wide range of refractive index

distributions. This proves to be the case not only for the LP01

mode of the step index fi ber,

but also for the modes with fi bers displaying arbitrary graded refractive index distributions.

Therefore, the predominant electric fi eld component of the single guided mode may

be written as the Gaussian function:

...(5.117)

where the radius parameter r2 = x2 + y2, ω0 is a width parameter which is often called

the spot size or radius of the fundamental mode (see Section 5.5.2) and β is the propagation

constant of the guided mode fi eld.

The factor preceding the exponential function is arbitrary and is chosen for normalization

purposes. If it is accepted that Eq. (5.117) is to a good approximation the correct shape [Ref.

26], then the parameters β and ω0 may be obtained either by substitution or by using a

variational principle. Using the latter technique, solutions of the wave equation, Eq. (5.116),

are claimed to be functions of the minimum integral:

...(5.118)

where the asterisk indicates complex conjugation. The integration range in Eq. (5.118)

extends over a large cylinder with the fi ber at its axis. Moreover, the length of the cylinder

L is arbitrary and its radius is assumed to tend towards infi nity. Use of variational calculus

[Ref. 53] indicates that the wave equation Eq. (5.116) is the Euler equation of the variational

expression given in Eq. (5.118). Hence, the functions that minimize J satisfy the wave equation.

Firstly, it can be shown that the minimum value of J is zero if φ is a legitimate guided mode

fi eld. We do this by performing a partial integration of Eq. (5.118) which can be written as:

...(5.119)

where the surface element ds represents a vector in a direction normal to the outside of

the cylinder. However, the function φ for a guided mode disappears on the curved cylindrical

surface with infi nite radius. In this case the guided mode fi eld may be expressed as:

...(5.120)

NOTES

Electronics-1


It may be observed from Eq. (5.120) that the z dependence is limited to the exponential

function and therefore the integrand of the surface integral in Eq. (5.119) is independent of

z. This indicates that the contributions to the surface integral from the two end faces of the

cylinder are equal in value, opposite in sign and independent of the cylinder length. Thus the

entire surface integral goes to zero. Moreover, when the function φ is a solution of the wave

equation, the volume integral in Eq. (5.119) is zero and hence J is also equal to zero. The

variational expression given in Eq. (5.118) can now be altered by substituting Eq. (5.120).

In this case the volume integral becomes an integral over the infi nite crosssection of the

cylinder (i.e. the fi ber) which may be integrated over the length coordinate z. Integration over

z effectively multiplies the remaining integral over the cross-section by the cylinder length

L because the integrand is independent of z. Hence dividing by L we can write:

...(5.121)

where the operator t indicates the transverse part (i.e. the x and y derivatives) of .

We have now obtained in Eq. (5.121) the required variational expression that will facilitate

the determination of spot size and propagation constant for the guided mode fi eld. The latter

parameter may be obtained by solving Eq. (5.121) for β2 with J = 0, as has been proven to

be the case for solutions of the wave equation. Thus:

...(5.122)

Equation (5.122) allows calculation of the propagation constant of the fundamental

mode if the function φ is known. However, the integral expression in Eq. (5.122) exhibits

a stationary value such that it remains unchanged to the fi rst order when the exact mode

function D is substituted by a slightly perturbed function. Hence a good approximation to

the propagation constant can be obtained using a function that only reasonably approximates

to the exact function. The Gaussian approximation given in Eq. (5.117) can therefore be

substituted into Eq. (5.122) to obtain:

...(5.123)

Two points should be noted in relation to Eq. (5.123). Firstly, following Marcuse [Ref.

23] the normalization was picked to bring the denominator of Eq. (5.122) to unity. Secondly,

the stationary expression of Eq. (5.123) was obtained from Eq. (5.122) by assuming that the

refractive index was dependent only upon the radial coordinate r. This condition is, however,

satisfi ed by most common optical fi ber types.

Finally, to derive an expression for the spot size ω0 we again make use of the stationary

property of Eqs (5.122) and (5.123). Hence, if the Gaussian function of Eq. (5.117) is the

correct mode function to give a value for ω0, then β

2 will not alter if ω

0 is changed slightly.

NOTES



This indicates that the derivative of β2 with respect to ω

0 becomes zero (i.e. dβ

2/dω

0 = 0).

Therefore, differentiation of Eq. (5.123) and setting the result to zero yields:

...(5.124)

Equation (5.124) allows the Gaussian approximation for the fundamental mode within

single-mode fi ber to be obtained by providing a value for the spot size ω0. This value may

be utilized in Eq. (5.123) to determine the propagation constant β.

For step index profi les it can be shown [Ref. 52] that an optimum value of the spot

size ω0 divided by the core radius is only a function of the normalized frequency V. The

optimum values of ω0/a can be approximated to better than 1% accuracy by the empirical

formula [Ref. 52]:

...(5.125)

...(5.126)

The approximate expression for spot size given in Eq. (5.126) is frequently used to

determine the parameter for step index fi bers over the usual range of λ/λc (i.e. 0.8 to 1.9) .

The accuracy of the Gaussian approximation has also been demonstrated for graded

index fi bers, having a refractive index profi le given by Eq. (5.76) (i.e. power-law profi les in

the core region). When the near-parabolic refractive index profi le is considered (i.e. α = 2)

and the square-law medium is assumed to extend to infi nity rather than to the cladding where

n(r) = n2, for r ≥ a (Eq. (5.76)), then the Gaussian spot size given in Eq. (5.124) reduces to:

...(5.127)

Furthermore, the propagation constant becomes:

...(5.128)

It is interesting to note that the above relationships for ω0 and β in this case are identical

to the solutions obtained from exact analysis of the square-law medium. Numerical solutions

of Eqs (5.123) and (5.124) are shown in Figure 5.35 (dashed lines) for values of α of 6

and ∞ for profi les with constant refractive indices in the cladding region. In this case Eqs

(5.123) and (5.124) cannot be solved analytically and computer solutions must be obtained.

The solid lines in Figure 5.35 show the corresponding solutions of the wave equation, also

obtained by a direct numerical technique. These results for the spot size and propagation

constant are provided for comparison as they are not infl uenced by the prior assumption of

Gaussian shape.

NOTES

Electronics-1


Fig. 5.35. Comparison of ω0/a approximation obtained from Eqs (5.123) and (5.124) (dashed lines) with values obtained from numerical integration of the wave equation and subsequent optimization of its width (solid lines). Reproduced with permission from D. Marcuse, ‘Gaussian approximation of the fundamental modes of graded

index fi bers’, J. Opt. Soc. Am., 68, p. 103, 1978

The Gaussian approximation for the transverse fi eld distribution is very much simpler

than the exact solution and is very useful for calculations involving both launching effi ciency

at the single-mode fi ber input as well as coupling losses at splices or connectors. In this

context it describes very well the fi eld inside the fi ber core and provides good approximate

values for the guided mode propagation constant. It is a particularly good approximation for

fi bers operated near the cutoff wavelength of the second-order mode but when the wavelength

increases, the approximation becomes less accurate. In addition, for single-mode fi bers

with homogeneous cladding, the true fi eld distribution is never exactly Gaussian since the

evanescent fi eld in the cladding tends to a more exponential function for which the Gaussian

provides an underestimate.

However, for the calculations involving cladding absorption, bend losses, crosstalk

between fi bers and the properties of directional couplers, then the Gaussian approximation

should not be utilized. Better approximations for the fi eld profi le in these cases can, however,

be employed, such as the exponential function, or the modifi ed Hankel function of zero order],

giving the Gaussian–exponential and the Gaussian– Hankel approximations respectively.

Unfortunately, these approximations lose the major simplicity of the Gaussian approximation,

NOTES



in which essentially one parameter (the spot size) defi nes the radial amplitude distribution,

because they necessitate two parameters to characterize the same distribution.

Another strategy to obtain approximate values for the cutoff wavelength and spot size in

graded index single-mode fi bers (or arbitrary refractive index profi le fi bers) is to defi ne an

equivalent step index (ESI) fi ber on which to model the fi ber to be investigated. Various

methods have been proposed in the literature which commence from the observation that

the fi elds in the core regions of graded index fi bers often appear similar to the fi elds within

step index fi bers. Hence, as step index fi ber characteristics are well known, it is convenient

to replace the exact methods for graded index single-mode fi bers by approximate techniques

based on step index fi bers. In addition, such ESI methods allow the propagation characteristics

of single-mode fi bers to be represented by a few parameters.

Fig. 5.36. Refractive index distributions n(r) and electric fi eld distributions E(r) for graded index fi bers and their ESI fi bers for: (a) α = 2, V = 3.5; (b) α = 4, V = 3.0. The fi eld distributions for the graded index and corresponding ESI profi les are shown

by solid circles and open triangles respectively. Reproduced with permission from H. Matsumura and T. Suganuma, Appl. Opt., 19, p. 3151, 1980

NOTES

Electronics-1


Several different suggestions have been advanced for the choice of the core radius aESI,

and the relative index difference ΔESI, of the ESI fi ber which lead to good approximations

for the spot size (and hence joint and bend losses) for the actual graded index fi ber. They

are all conceptually related to the Gaussian approximation (see Section 5.5.5) in that they

utilize the close resemblance of the fi eld distribution of the LP01

mode to the Gaussian

distribution within single-mode fi ber. An early proposal for the ESI method [Ref. 58] involved

transformation of the basic fi ber parameters following:

...(5.129)

where the subscript s is for the ESI fi ber and X, Y are constants which must be

determined. However, these ESI fi ber representations are only valid for a particular value

of normalized frequency V and hence there is a different X, Y pair for each wavelength. The

transformation can be carried out on the basis of either compared radii or relative refractive

index differences. Figure 5.36 compares the refractive index profi les and the electric fi eld

distributions for two graded index fi bres (α = 2, 4) and their ESI fi bers. It may be observed

that their fi elds differ slightly only near the axis.

An alternative ESI technique is to normalize the spot size ω0 with respect to an

optimum effective fi ber core radius aeff

. This latter quantity is obtained from the experimental

measurement of the fi rst minimum (angle θ min) in the diffraction pattern using transverse

illumination of the fi ber immersed in an index-matching fl uid. Hence:

...(5.130)

where k = 2π/λ. In order to obtain the full comparison with single-mode step index

fi ber, the results may be expressed in terms of an effective normalized frequency Veff which

relates the cutoff frequencies/wavelengths for the two fi bers:

...(5.131)

The technique provides a dependence of ω0/a

eff on V

eff which is almost identical for a

reasonably wide range of profi les which are of interest for minimizing dispersion (i.e. 1.5

< Veff

< 2.4).

A good analytical approximation for this dependence is given by:

...(5.132)

Refractive index profi le-dependent deviations from the relationship shown in Eq.

(5.132) are within ±2% for general power-law graded index profi les.

Other ESI methods involve the determination of the equivalent parameters from

experimental curves of spot size against wavelength. All require an empirical formula,

relating spot size to the normalized frequency for a step index fi ber, to be fi tted by some

means to the data. The usual empirical formula employed is that derived by Marcuse for the

Gaussian approximation and given in Eq. (5.125). An alternative formula which is close to

Eq. (5.125) is provided by Snyder as:

...(5.133)

NOTES



However, it is suggested that the expression given in Eq. (5.133) is probably less

accurate than that provided by Eq. (5.125). A cutoff method can also be utilized to obtain the

ESI parameters. In this case the cutoff wavelength λc and spot size ω

0 are known. Therefore,

substituting V = 2.405 into Eq. (5.125) gives:

...(5.134)

Then using Eq. (5.70) the ESI relative index difference is:

...(5.135)

where n1 is the maximum refractive index of the fi ber core.

Alternatively, performing a least squares fi t on Eq. (5.125) provides ‘best values’ for

the ESI diameter (2aESI) and relative index difference (ΔESI). It must be noted, however,

that these best values are dependent on the application and the least squares method appears

most useful in estimating losses at fi ber joint. In addition, some work has attempted to provide

a more consistent relationship between the ESI parameters and the fi ber MFD. Overall, the

concept of the ESI fi ber has been relatively useful in the specifi cation of standard MC and

DC fi bers by their equivalent aESI and ΔESI values. Unfortunately, ESI methods are unable

accurately to predict MFDs and waveguide dispersion in dispersion-shifted and dispersion-

fl attened fi bers.

5.7 PHOTONIC CRYSTAL FIBERSThe previous discussion in this chapter has concentrated on optical fi bers comprising solid

silica core and cladding regions in which the light is guided by a small increase in refractive

index in the core facilitated through doping the silicon with germanium. More recently,

however, a new class of microstructured optical fi ber containing a fi ne array of air holes

running longitudinally down the fi ber cladding has been developed. Since the microstructure

within the fi ber is often highly periodic due to the fabrication process, these fi bers are usually

referred to as photonic crystal fi bers (PCFs), or sometimes just as holey fi bers. Whereas in

conventional optical fi bers electromagnetic modes are guided by total internal refl ection in

the core region, which has a slightly raised refractive index, in PCFs two distinct guidance

mechanisms arise.

Although the guided modes can be trapped in a fi ber core which exhibits a higher

average index than the cladding containing the air holes by an effect similar to total internal

refl ection, alternatively they may be trapped in a core of either higher, or indeed lower,

average index by a photonic bandgap effect. In the former case the effect is often termed

modifi ed total internal refl ection and the fi bers are referred to as index guided, while in the

latter they are called photonic bandgap fi bers. Furthermore, the existence of two different

guidance mechanisms makes PCFs versatile in their range of potential applications.

For example, PCFs have been used to realize various optical components and devices

including long period gratings, multimode interference power splitters, tunable coupled

cavity fi ber lasers, fi ber amplifi ers, multichannel add/ drop fi lters, wavelength converters

and wavelength demultiplexers As with conventional optical fi bers, however, a crucial

NOTES

Electronics-1


issue with PCFs has been the reduction in overall transmission losses which were initially

several hundred decibels per kilometer even with the most straightforward designs. Increased

control over the homogeneity of the fi ber structures together with the use of highly purifi ed

silicon as the base material has now lowered these losses to a level of a very few decibels

per kilometer for most PCF types, with a loss of just 0.3 dB km−1 at 1.55 μm for a 100 km

span being recently reported.

Although the principles of guidance and the characteristics of index-guided PCFs are

similar to those of conventional fi ber, there is greater index contrast since the cladding

contains air holes with a refractive index of 1 in comparison with the normal silica cladding

index of 1.457 which is close to the germanium-doped core index of 1.462. A fundamental

physical difference, however, between index-guided PCFs and conventional fi bers arises

from the manner in which the guided mode interacts with the cladding region. Whereas in a

conventional fi ber this interaction is largely fi rst order and independent of wavelength, the

large index contrast combined with the small structure dimensions cause the effective cladding

index to be a strong function of wavelength. For short wavelengths the effective cladding

index is only slightly lower than the core index and hence they remain tightly confi ned to

the core. At longer wavelengths, however, the mode samples more of the cladding and the

effective index contrast is larger. This wavelength dependence results in a large number

of unusual optical properties which can be tailored. For example, the high index contrast

enables the PCF core to be reduced from around 8 μm in conventional fi ber to less than 1

μm, which increases the intensity of the light in the core and enhances the nonlinear effects.

Fig. 5.37. Two indexguided photonic crystal fi ber structures. The dark areas are air holes while the white areas are silica

Two common index-guided PCF designs are shown diagrammatically in Figure 5.37.

In both cases a solid-core region is surrounded by a cladding region containing air holes.

The cladding region in Figure 5.37(a) comprises a hexagonal array of air holes while in

Figure 5.37(b) the cladding air holes are not uniform in size and do not extend too far from

the core. It should be noted that the hole diameter d and hole to hole spacing or pitch Λ are

critical design parameters used to specify the structure of the PCF. For example, in a silica

PCF with the structure depicted in Figure 5.37(a) when the air fi ll fraction is low (i.e. d/Λ <

0.4), then the fi ber can be single-moded at all wavelengths. This property, which cannot be

attained in conventional fi bers, is particularly signifi cant for broadband applications such

NOTES



as wavelength division multiplexed transmission. As PCFs have a wider range of optical

properties in comparison with standard optical fi bers, they provide for the possibility of new

and technologically important fi ber devices.

When the holey region covers more than 20% of the fi ber cross-section, for instance,

index-guided PCFs display an interesting range of dispersive properties which could fi nd

application as dispersion-compensating or dispersion-controlling fi ber components. In

such fi bers it is possible to produce very high optical nonlinearity per unit length in which

modest light intensities can induce substantial nonlinear effects. For example, while several

kilometers of conventional fi ber are normally required to achieve 2R data regeneration, it

was obtained with just 3.3 m of large air-fi lling fraction PCF. In addition, fi lling the cladding

holes with polymers or liquid crystals allows external fi elds to be used to dynamically vary

the fi ber properties. The temperature sensitivity of a polymer within the cladding holes may

be employed to tune a Bragg grating written into the core [Ref. 83]. By contrast, index-

guided PCFs with small holes and large hole spacings provide very large mode area (and

hence low optical nonlinearities) and have potential applications in high-power delivery (e.g.

laser welding and machining) as well as high-power fi ber lasers and amplifi ers. Furthermore,

the large index contrast between silica and air enables production of such PCFs with large

multimoded cores which also have very high numerical aperture values (greater than 0.7).

Hence these fi bers are useful for the collection and transmission of high optical powers in

situations where signal distortion is not an issue. Finally, it is apparent that PCFs can be

readily spliced to conventional fi bers, thus enabling their integration with existing components

and subsystems.

Photonic bandgap (PBG) fi bers are a class of microstructured fi ber in which a periodic

arrangement of air holes is required to ensure guidance. This periodic arrangement of

cladding air holes provides for the formation of a photonic bandgap in the transverse plane

of the fi ber. As a PBG fi ber exhibits a two-dimensional bandgap, then wavelengths within

this bandgap cannot propagate perpendicular to the fi ber axis (i.e. in the cladding) and they

can therefore be confi ned to propagate within a region in which the refractive index is lower

than the surrounding material. Hence utilizing the photonic bandgap effect light can, for

example, be guided within a low-index, air-fi lled core region creating fi ber properties quite

different from those obtained without the bandgap. Although, as with index-guided PCFs,

PBG fi bers can also guide light in regions with higher refractive index, it is the lower index

region guidance feature which is of particular interest. In addition, a further distinctive

feature is that while index-guiding fi bers usually have a guided mode at all wavelengths,

PBG fi bers only guide in certain wavelength bands, and furthermore it is possible to have

wavelengths at which higher order modes are guided while the fundamental mode is not.

Two important PBG fi ber structures are displayed in Figure 5.38. The honeycomb

fi ber design shown in Figure 5.38(a) was the fi rst PBG fi ber to be experimentally realized

in 1998 and adaptations of this structure continue to be pursued. A triangular array of air

holes of suffi cient size as displayed in Figure 5.38(b), however, provides for the possibility,

NOTES

Electronics-1


unique to PBG fi bers, of guiding electromagnetic modes in air. In this case a large hollow

core has been defi ned by removing the silica around seven air holes in the center of the

structure. These fi bers, which are termed air-guiding or hollow-core PBG fi bers, enable

more than 98% of the guided mode fi eld energy to propagate in the air regions. Such air-

guiding fi bers have attracted attention because they potentially provide an environment in

which optical propagation can take place with little attenuation as the localization of light

in the air core removes the limitations caused by material absorption losses. The fabrication

of hollow-core fi ber with low propagation losses, however, has proved to be quite diffi cult,

with losses of the order of 13 dB km−1. Moreover, the fi bers tend to be highly dispersive

with narrow transmission windows and while single-mode operation is possible, it is not as

straightforward to achieve in comparison with index-guiding PCFs.

Fig. 5.38. Photonic bandgap (PBG) fi ber structures in which the dark areas are air (lower refractive index) and the lighter area is the higher refractive index:

(a) honeycomb PBG fi ber; (b) airguiding PBG fi ber

More recently, the fabrication and characterization of a new type of solid silica-based

photonic crystal fi ber which guides light using the PBG mechanism has been reported. This

fi ber employed a two-dimensional periodic array of germanium-doped rods in the core

region. It was therefore referred to as a nanostructure core fi ber and exhibited a minimum

attenuation of 5.6 dB km−1 at a wavelength of 1.59 μm. Furthermore, the fi ber displayed

greater bending sensitivity than conventional singlemode fi ber as a result of the much smaller

index difference between the core and the leaky modes which could provide for potential

applications in the optical sensing of curvatur and stress. In addition, it is indicated that

the all-solid silica structure would facilitate fi ber fabrication using existing technology and

birefringence of the order of 10−4 is easily achievable with a large mode fi eld diameter up

to 10 μm, thus enabling its use within fi ber lasers and gyroscope applications.

5.8 PROPAGATION OF LIGHT IN OPTICAL FIBREThe light propagates through optical fi bre through “Total internal refl ection”. The total

internal refl ection appears due following reasons.

When light traverse from optically rarer medium (like air) to denser medium

(glass) the refracted ray moves towards the normal drawn on the interface of

media as in Snell’s law. Conversely, if light traverse from denser to optically rarer

medium, the refracted ray moves away from the normal drawn on the interface

of the medium fi g.(5.39a)

NOTES



If the angle of incidence increases (fi g.5.39b), to certain value for which the

refracted ray happen to be on the interface of medium. The angle of incidence s

known as critical angle (θc)(fi g.5.39c).

If the incident angle (fi g.5.39d) increases more than critical angle, then the refracted

ray falls on the same denser medium with no refraction. “This refl ection of light

is called total internal refl ection”.

Thus, following are the conditions for total internal refl ection:

Cladding1. The ray of light should be traverse from denser to rare medium.

2. The incident angle should be more than the Critical angle (θi >θ

c).

Fig. 5.39. Propagation of light from rarer to denser medium

Total Internal Refl ectionIf the incident ray exceeds the critical angle, the refraction would be turned in to refl ection

called total internal refl ection. The critical angle is used for the mathematical expression to

the occurrence of total internal refl ection (fi g.5.39c)

0

Since, sin 90 =1

1

2c Since,

1

21

c

NOTES

Electronics-1


Therefore, to propagate the light through optical fi bre, the incident angle should be

made higher than the critical angle at various points on the core, so that the light can be

traversed by the total internal refl ection at those points.

To achieve the above, the size of core should be adjusted suitably which causes different

types of optical fi bre based on size, (no. of modes) refractive index and modes of propagation.

5.9 CLASSIFICATIONIn the optical fi bres the materials used, refractive index and mode of propagation of light

are used for classifi cation as follows:

The material based classifi cation results to the following types:

1. Plastic made fi bres.

2. Glass made fi bres.

The plastic made fi bres are obtained from polymers of transparent to light, fl exibility

and interaction less to light etc,.

For example poly methyl metha acrylate (PMMA), polyethylene (PE), polystyrene

(PS) are used as core materials.

Glass made fi bre is also fabricated from fl exible glass as core with suitable drawing

technique in presence of impurities. Therefore, the above types of optical fi bres are limited

to some application.

The types of optical fi bre can be classifi ed based on the refractive index are:

1. Step index fi bres.

2. Graded index fi bres.

Step indexIf the refractive index of core remains the same from the centre of the core to the core-cladding

interface; those optical fi bres are known as step index fi bres (fi g.5.40a). The distance from

centre of core to interface of fi bre vs. refractive index is shown as below:

Graded Index

axis

Core

Cladding

Refractive index

Distance

Fig. 5.40(a) Step Index fi bre profi le

NOTES



These types are made of varying refractive index of core material. Therefore, the

refractive index changes with distance form the centre of fi bre to core-cladding interface.

The profi le of above is as shown in the fi g 5.40.

axis

Core

Cladding

Refractive index

Distance

Fig. 5.40(b) Graded Index fi bre profi le

P B O FBased on modes of propagation of light through core, the following are the types of optical

fi bre identifi ed.

Single mode fi bres

Multimode fi bres

Single Mode FibresConsidering the light as electromagnetic radiation, the possible modes of propagation are

transverse electric (TE) modes and transverse magnetic (TM) modes. Among them, the TE10

,

TE11

, TE01

and TM10

, TM11

, TM01

are possible, within which the modes TE10

and TM11

are

signifi cant. If the core size is adjusted to allow only one mode of light wave propagation is

single mode fi bre, whose profi le (fi g.5.40c) is shown below:

axis

Core

Cladding

Refractive index

Distance

Fig. 5.40(c) Single mode fi bre profi le

Multi Mode Optical FibreIf the core size has been adjusted to allow more than one mode of propagation of light wave

is multimode fi bre. The profi le of multimode fi bres is as shown below:

axis

Core

Cladding

Refractive index

Distance

Fig. 5.40(d) Multi mode fi bre profi le

NOTES

Electronics-1


Combination of Optical FibresThe refractive index of core and mode of propagation of light in optical fi bre is used to form

combination types of optical fi bre.

Step index-single mode fi bres

Step index-multi mode fi bres

Graded index-Single mode fi bres

Graded index-Multi mode fi bres

5.10 PARAMETERS OF OPTICAL FIBRESThe parameters of optical fi bres are:

Radius of the core

Numerical Aperture

Acceptance angle

The size of optical fi bres plays crucial role in the light wave propagation through fi bre.

Therefore, radius of the core is signifi cant to decide mode of propagation in fi bre. The

thickness/diameter of the core can be measured in spite of measurement of radius. For the

purpose the profi le projector can be used.

Numerical aperture (NA) is a light gathering property of optical fi bre, which gives the quantity

of light that brought into the centre of optical fi bre in terms of incidence angle. To calculate

NA, consider a longitudinal section of fi bre as in fi g.(5.41). Let n0, n

1, n

2 are the refractive

indices of air (outside optical fi bre), core and cladding respectively.

Fig. 5.41. Longitudinal Section of optical fi bre

NOTES



Substituting (2) in (1)

or

(Where =1 for air)

It is a semi vectorial angle that formed by the set of incident rays at the centre of fi bre,

which helps to decide the size of core.

From

5.11 APPLICATIONS OF OPTICAL FIBRES IN INDUSTRYAND MEDICINE

F CThe conventional method of communication has more limitation toward signal security and

also affected by change in atmospheric factors. To overcome these limitations and factors,

te optical fi bres are introduced in communication system. In optical fi bre communication

the protocol consist of transmitter unit and receiving unit in the system.

The Transmitter UnitThe transmitter unit contains light source, signal to be transmitted, light modulator, amplifi ers

and coupler. Similarly, the receiver unit consists of couplers, light detectors, amplifi ers, fi lters

and output device. The transmitter unit and receiver unit are connected by suitable optical

fi bre. The layout of optical fi bre communication is shown in the fi g. 5.42.

NOTES

Electronics-1


Electric transmitter External

Modulator

Isolator

Transmitter laser

Optical

coupler

Polarizer control

Op-Isolator

laser

Photo

diode

Amplifier

LP

O/p Detector

Transmitter

Receiver

Fig. 5.42. Optical Fibre in communication System

The SignalThe signal to be transmitter can be voice, music as audio or movie as video signals. Generally,

the signals will be in analog form which can be converted to digital using A/D converters

in the transmitter.

The optical communication system (fi g) system consist of transmitter unit containing

digital source, electrical transmitter, laser as light source, modulator and transmitter channel.

In receiving end, the light detector, amplifi er, optical coupler and the de modulator

are available.

In transmitter, the digital signal will be converted in to electrical signal, which modulates

optical carrier wave through transmitter wave by laser in terms of intensity, frequency or

phase.

ModulatorIn the modulator the mixing of signal with optical carrier wave takes place. The modulation

can be

Simple ON-OFF keying (OOK)

Amplitude shift keying (ASK)

Frequency shift keying (FSK)

Phase shift keying (PSK)

Multi level modulation keying (MMK)

The function of the modulator may be electro optic or acoustic optic phenomenon.

Receiver UnitThe output of transmitter can be connected to the optical fi bre which ends at receiver.

The receiver unit can be two type, they are:

Homodyne receiver

Heterodyne receiver

NOTES



In homodyne receiver, one way communication is encouraged where as the heterodyne

receiver encourages to transmit and receive the signal in a single receiver unit. If the

transmitted signal alone be received through the receiver whose frequency synchronize with

the local laser frequency, it will be homodyne receiver (fs = fl ).

Heterodyne ReceiverIf the transmitted signal be received through the receiver whose frequency does not

synchronize with the local laser frequency, it will be heterodyne receiver (fs = f

l). The

homodyne and heterodyne receivers are shown in present fi g 5.5.

Transmitter LaserTo achieve high bit rate and long range data transmission with low error rate a single mode

transmitter laser can be used as in fi g. 5.5.

Isolators

There can be undesired refl ection between transmitter lasers to the external modulator. To

avoid the consequence as refl ection this improves laser emission spectrum. Further, it causes

quality deterioration which causes quality of transmission. To avoid above, a optical isolation

is used across external modulator and transmitter laser.

External ModulatorsThe direct modulation technique contain semiconductor component such devices directly

modulates using injection current by charge carriers in terms of intensity amplitude and

frequency adding additional noise. The above can be avoided in external modulators.

Optical CouplerThe optical coupler mixes the receiving signal and local light wave from laser to improve

system performance, quality of emission spectrum of laser. This optical coupler has 2 inputs

through super imposed optical waves and one output to photodiode.

PhotodiodeThe photo diode gives electric current corresponding to optical input power. Normally, PIN

diodes or avalanche diode (APD) are used. Among them, the PIN diodes are signifi cant due

to input optical power proportional to square of input electric fi eld.

It generates electric current proportional to optical input power. For the purpose PIN

and APD are used. The gain of APD is improved by performance of coherent optical radiation

PIN diodes are used in practice. As the optical power is proportional to the square of the

electric fi eld, the superposing of two fi elds is linear. In photodiodes current also contain an

immediate frequency which referred as IF signals.

Inter Mediate Frequency (IF) FiltersThe IF signal, the difference of local laser frequency and frequency of received light are

signifi cant in the present communication system.

NOTES

Electronics-1


To get homodyne detection, care should be taken to get phase and frequency to match.

To get heterodyne detection, the signal should be selected by IF fi lter and the demodulated

with respect to amplitude/frequency or phase.

All type of demodulator can be used. The output of demodulator may also contain

noise which can be eliminated by low pass fi lter.

Output DeviceThe fi ltered nose will be sampled and hold receives the signal after fi lter to be connected

to output device.

5.12 SOME LOSSES IN OPTICAL FIBRESThe optical fi bre does not experience the loss in terms of intensity of light. However, the

presence of impurities, scattering at the edges, geometry of structure and dispersion of light

causes some losses.

Transmission loss/attenuation (α)If the intensity of light at the second end of the optical fi bre be Iout and intensity at fi rst

end be Iin

.

The attenuation,

In decibel the attenuation,

Other Possible Losses in Optical FibreThe possible losses are absorption, scattering, radiation losses and geometric losses.

The absorption lossThe absorption losses appears as

Extrinsic losses

Intrinsic losses

Atomic defect losses

Extrinsic LossesThe extrinsic loss appears due to presence of impurities which absorbed the light. The

impurities may be due to presence of Fe, Cr, Co and Cu in the core material. The impurities

could absorb the energy that may reemit the absorbed energy during the de excitation in

different wavelength which causes loss of intensity to original light of specifi c wavelength.

Intrinsic LossSince, the fi bre core itself absorbs some quantity of energy which is known as intrinsic loss.

NOTES



Scattering and Radiation LossesSince, optic fi bre contains glass as core, where impurities are present. The scattering of

light at these impurities causes Raleyeigh scattering where the energy of scattered wave

directly proportional to 4th power (E = /4 ) of wavelength. Therefore, small change of

energy causes 4th power of wavelength. The loss of energy at couplers and interfaces are

known as radiative losses.

Geometrical LossDue to bending of optical fi bres there are 2 types of losses from macroscopic bending and

microscopic bending. If the fi bre be rounded as big circle of known radius of curvature, the

loss may be less called macroscopic bending loss.

For small bending of fi bre the loss of energy in microscopic bending is larger. Some

time the irregularities in the dimensions cause geometrical losses.

Dispersion LossIn the transmission of light through optical fi bres the pulse width varies due to dispersion of

light through the core. The loss of intensity caused as result of dispersion of light is due to

Material dispersion

Waveguide dispersion

Inter modal dispersion

Material DispersionThe refractive index of core causes the changes in the wavelength/frequency called material

dispersion. If narrow pulse passes trough fi bre, causes broadening of pulse width due to

material property. It can be overcome by highly monochromatic source of light. The single

mode fi bre could reduce the material dispersion to maximum extent.

Waveguide DispersionThe optical fi bre can be considered as circular wave guide where refractive index varies with

modes of propagation with wavelength causes wave guide dispersion.

Intermodal DispersionThe optical power in the pulsed wave distribution over the mode of light through the fi bre

decreases during the propagation, these changes are known as intermodal dispersion.

5.13 OPTICAL FIBRES AS SENSORSGenerally, optic sensor consists of light source, optical fi bres and detector. The sensors are

Two types viz., active sensors and passive sensors.

The physical changes directly changes the electrical responses called active sensors;

where as the physical changes are indirectly recorded to sensing is called passive sensors.

NOTES

Electronics-1


Temperature SensorThe light can be arranged to fall on refl ecting surface and the associated phase angle is be

measured. The refl ecting surface can be varied using temperature variation, which causes

additional phase angle to light wave as seen in the fi g.5.43. When light thrown on the refl ector

by optical fi bre, the initial and fi nal response can be compared for measure of temperature

by relative correlation.

Glass tube

Fig. 5.43. Temperature sensor

Displacement SensorsThe light is sent through transmitting fi bre and further it is allowed to fall on moving target.

The light ray falls on the surface and gets refl ected. The incident ray could mix with refl ected

wave and forms standing wave to which the phase angle shift can be measured. The fi g

indicates displacement sensors.

Fig. 5.44. Displacement sensor

F

EndoscopeThe endoscope is a instrument through which small surgery could be performed. The

construction details are given as in fi g. 5.45. The ray of light is obtained using laser the

light is partially allowed to pass through optical fi bre kept inside the tube as shown in the

fi gure. The output of fi bre is connected to lens system and then to prism to split the object.

NOTES



The refl ected light can be obtained using polished prism and returning ray will be visualize

to get the real position of inner organs.

Fig. 5.45. Endoscope

5.14 SUMMERYThe centre transparent medium of optical fi bre is called “core” and the outer is cladding.

The refractive index of core will be always higher than the refractive index of cladding. If

the incident ray exceeds the critical angle, the refraction would be turned in to refl ection

called total internal refl ection.

Therefore, to propagate the light through optical fi bre, the incident angle should be made

higher than the critical angle at various points on the core, so that the light can be traversed by

the total internal refl ection at those points. Considering the light as electromagnetic radiation,

the possible modes of propagation are transverse electric (TE) modes and transverse magnetic

(TM) modes. Among them, the TE10

, TE11

, TE01

and TM10

, TM11

, TM01

are possible, within

which the modes TE10

and TM11

are signifi cant.

It generates electric current proportional to optical input power. For the purpose PIN

and APD are used. The gain of APD is improved by performance of coherent optical radiation

PIN diodes are used in practice. As the optical power is proportional to the square of the

electric fi eld, the superposing of two fi elds is linear. In photodiodes current also contain

an immediate frequency which referred as IF signals. The refractive index of core causes

the changes in the wavelength/frequency called material dispersion. If narrow pulse passes

trough fi bre, causes broadening of pulse width due to material property. It can be overcome

by highly monochromatic source of light.

The Einstein’s coeffi cients A and β account for spontaneous and stimulated emission/

absorption probabilities of light by a system of dissimilar particles. It is also explains the

importance of meta stable states and condition for laser action.

The no. of atoms in the ground state will be more than that the atom in the excited state

and it is called ideal state of atom. The he reverse of this a state of achieving more no. of

atoms in the higher energy level than that of the lower energy is called population inversion.

Coherent sources are the sources which have same wavelength and frequency. It has

correlation with the amplitude and phase at any point with any other point in propagation.

NOTES

Electronics-1


Total internal refl ection is used in fi bre optic communication. When light travels from a

denser to rarer medium at a particular angle of incidence called critical angle the ray emerges

along the surface of separation. The angle of incidence exceeds the critcal angle the incident

ray is refl ected in the same medium and this phenomenon is called total internal refl ection.

The difference in refractive indices between the core and the cladding is obtained in a

single step and hence called step index. The light ray propagate as marginal rays and pass

through fi bre. The light rays meridian ray propagate as meridian ray propagate as medium

rays and pass thought fi bre axis It follows a zig -zag light propagation, low band width Due

to non uniform refractive indices. In their difference in refractive indices between the core

and the cladding, which gradually increase from centre towards interface and hence called,

graded index fi bre. Light propagates in the form of skew rays and does not cross the fi bre

centre. It has high value of band width.

It is the state for which the life time of electron is more than the excited state, i.e, it is the

semi stable which lies between the excited state and the lower state. The atom in the excited

state returns to ground state thereby emitting a photon without any external inducement is

called spontaneous emission. The emitted photons can move randomly,

An atom in the excited state is induced to return to ground state thereby resulting in two

photons of same frequency and energy is called as stimulated emission. The emitted photons

move in same direction and they are highly directional, the radiation is highly intense mono

chromatics and coherent photons are in phase. The max. Length up to which two wave trains

have correlations with the amplitude and phase is called coherent length and the time up

to which they are correlated is called coherent time they are also related as coherent length

The four important characteristics of the laser beams are: It is highly directional it has high

intensity the beam is purely monochromatic it has coherence. Higer power lasers are useful

for blast holes, Cracks fl ows, blow holes etc. in the materials. They are used to test the

presence of pores Cracks fl ows, blow holes etc., in the materials they are used for welding.

Lasers are used in microsurgery and bloodless operations,treatment of detached retina

and cancer treatment. Low excitation threshold potential,it has higher thermal conductivity

than ruby rod,high pulse repetition rate, quasi continuous waves and high effi ciency.

Homo junction lasers are made up of single crystals, power out put is low, pulsed &

continuous and high current density. The hetero junction lasers may contain polycrystal,power

out put is high,continuous,low threshold current density.

Acceptance angle is the maximum angle to the axis at which light may enter into the

fi bre so that it can have total internal refl ection inside the fi bre. An optical fi bre consists

of core which is surrounded by cladding. Here, the role of cladding is to make the light to

suffer total internal refl ection inside the fi bre. Satisfying the condition that light should travel

from denser to rarer medium. During the transmission of light through the optical fi bre, three

major losses will occur viz., attenuation, Distortions and dispersion, Attenuation is mainly

caused due to the absorption, scattering and radiation of light inside the fi bers. Distortion

and dispersion occurs due to spreading of light and also due to manufacturing defects.

The medical endoscope is a tubular optical instrument used to inspect /view the internal

parts of human body which are not visible to the eyes normally. The photograph of the internal

part can also be taken using endoscope. It can be used in long distance communication for

NOTES



transmission lines. Large no of signal can be accommodated. It can be used in Local area

networks LAN and it also be used as sensors in the devices. . It could be used in external

interface, used in remote sensing, signal security, compactness. It is light gathering power

of optical fi bre. it is also measure of light that can be accepted by the fi bre.

In active sensors the physical parameter to be sensed directly acts on the fi bre itself to

produce the changes in the transmission characteristics. In extrinsic sensors separate sensing

element will be used and the fi bre will act as a guiding media to the sensors. It is light weight,

fl exile to handle, small in size, non inductive, non conductive and non radiative, high band

width can be accommodated, no sort circuit as in line communication Following are the

conditions for total internal refl ection: The ray of light should be traverse from denser to

rare medium. (1)The incident angle should be more than the Critical angle (θi >θ

c). (2) Light

produced should be mono chromatic, it must modulate with source of light in modulator,

should be high effi ciency, and should require small power for the operation. In single mode

only one mode of propagation is possible, core size is small, and whereas in multi mode

more than one mode is possible core size is large. ,Considering the light as electromagnetic

radiation, the possible modes of propagation are transverse electric (TE) mode and transverse

magnetic (TM) mode. Among them, the TE10

, TE11

, TE01

and TM10

, TM11

, TM01

are possible,

within which the modes TE10

and TM11

are signifi cant. If the core size is adjusted to allow

only one mode of light wave propagation then it should be single mode fi bre.

5.15 REVIEW QUESTIONS1. Briefl y indicate with the aid of suitable diagrams the difference between meridional

and skew ray paths in step index fi bers.

2. Explain the concept of electromagnetic modes in relation to a planar optical

waveguide. Discuss the modifi cations that may be made to electromagnetic

mode theory in a planar waveguide in order to describe optical propagation in a

cylindrical fi ber.

3. Describe the effects of these phenomena on the propagation of light in optical

fi bers.

4. Explain the graded index optical fi ber, giving an expression for the possible

refractive index profi le. Using simple ray theory concepts, discuss the transmission

of light through the fi ber. Indicate the major advantage of this type of fi ber with

regard to multimode propagation.

5. A single-mode step index fi ber has a core diameter of 7 μm and a core refractive

index of 1.49. Estimate the shortest wavelength of light which allows single-mode

operation when the relative refractive index difference for the fi ber is 1%.

6. Describe what is implied by the term photonic crystal fi ber (PCF) and explain the

guidance mechanisms for electromagnetic modes in such optical fi bers.

7. Compare and contrast the performance attributes, potential drawbacks and possible

applications of index-guided PCFs and photonic bandgap fi bers.

8. A multimode graded index fi ber has an acceptance angle in air of 8°. Estimate the

relative refractive index difference between the core axis and the cladding when

the refractive index at the core axis is 1.52.

NOTES

Electronics-1


9. Describe with the aid of simple ray diagrams:

(a) The multimode step index fi ber;

(b) The single-mode step index fi ber.

10. Briefl y discuss, with the aid of suitable diagrams, the following concepts in optical

fi ber transmission:

(a) The evanescent fi eld;

(b) Goos–Haenchen shift;

(c) Mode coupling.

11. What is meant by population inversion?

12. What are Einstein’s coeffi cients?

13. Defi ne coherent length and coherent time? How are they related to each other?

14. What are the characteristics of light?

15. State some of the applications of lasers in engineering and/industry?

16. What are Einstein coeffi cients for atomic transition?

17. Explain the principle, structure and working of Nd-YAG laser with energy level

diagram.

18. Give four applications of optical fi bre.

19. Explain the basic principle of optical fi bre communication.

20. Defi ne acceptance angle.

21. What is the role of cladding in an optical fi bre?

22 What is meant by endoscope?

23. Defi ne numerical aperture?

24. What is the condition to the total internal refl ection?

25. What is mode of propagation in optical fi bre?

26. How will you classify the optical fi bre?

27. What are the main requirements of light source used in fi bre optic communication?

5.16 FURTHER READINGS Microprocessor Architecture, Programming and Applications – Gaonkar (Wiley

eastrun)

Microprocessor Theory and Applications – M.Rafi quzzaman (P.H.I.)

Digital Computer Electronics – Albert Paul Malvino (TMH)

Fundamentals of microprocessors and Microcomputers – B.Ram (Dhanpat Rai

& Sons)

Microprocessor, Architecture, Programming and Applications – Gaonkar.(Wiley

Eastern)

Fundamentals of Microprocessors and Microcomputers – B. Ram. (Dhanpat Rai

& Sons Publications)

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