Mp2-SUPER!_Memory Basics and Memory System Design_v0.3

1

COM 353 MicroprocessorsLecture 2

COM 353 MicroprocessorsLecture 2

Prof. Dr. Halûk Gümüş[email protected]

[email protected] http://www.gumuskaya.com

Computer Engineering Department

Sunday, November 04, 2012 2

Introduction toMemory Basics and Memory System Design

3

Microprocessor Based System: Collection of Addressable Registers

We can view the entire microprocessor-based systemsystem – microprocessor, ROM, RWM, and I/O ports –as a collection of addressable registers.

• Registers in the microprocessor are internal registers,

• Those exist in the ROM, RWM (RAM), and I/O ports are external registers.

So we will start from basic Register concepts and Memory Devices

4

Topics for Memory Basics

• A simple memory block Memory design with D flip

flops Problems with the design

• Techniques to connect to a bus Using multiplexers Using open collector

outputs Using tri-state buffers

• Building a memory block

• Building larger memories• Mapping memory

Full mapping Partial mapping

• Alignment of data• Interleaved memories

Synchronized access organization

Independent access organization

Number of banks

5

Memory Devices Before attempting to interface memory to the

microprocessor, it is essential to understand the operation of memory components.

In this lecture, we explain functions of the2 common types of memory: Random Access Memory (RAM) (SRAM, DRAM,

NV-DRAM) Read-Only Memory (ROM) (PROM, EPROM,

EEPROM, Flash EPROM, mask ROM)

6

OBJECTIVESthis lecture enables to:• Define the terms capacity, organization, and

speed as used in semiconductor memories.• Calculate the chip capacity and organization

of semiconductor memory chips.• Compare and contrast the variations of ROM

– PROM, EPROM, EEPROM, Flash EPROM, mask ROM.• Compare and contrast the variations of RAM

– SRAM, DRAM, NV-DRAM.• Design address decoding methods for memory

chips.• Design a memory system for an 8085 based

systems in terms of RAM and ROM allocation.

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1. Memory Basics2. Memory Design with D Flip Flops3. Random Access Memory4. DRAM5. Read Only Memory6. Memory Decoding7. Memory System Design for Microprocessors8. Designing Larger Memories

Lecture Outline

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Memories

• To store a single bit, we can use Flip Flops or Latches

• Larger memories can be built by Using a 2D array of these 1-bit devices

» “Horizontal” expansion to increase word size» “Vertical” expansion to increase number of words

• Dynamic RAMs use a tiny capacitor to store a bit• Design concepts are mostly independent of the

actual technique used to store a bit of data

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Semiconductor Memories

• In all computer design, semiconductor memories are used as primary storage for code & data. Connected directly to the CPU, they asked first

by the CPU for information (code and data). » Referred to as primary memory.

• Primary memory must respond fast to the CPU. Only semiconductor memories can do that

» Among the most widely used are ROM and RAM.

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Flip-Flop – 1-bit Register

D Q

CLK

CLR

SET=Q

n+1D

n

Q

D: Senkron veri girişiCLK: Saat girişiQ: ÇıkışQ: Çıkışın tersiSET: Asenkron 1'leme girişiCLR: Asenkron 0'lama girişi

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Clock Pulse

0

1Öndeki Kenar Takip eden Kenar

Öndeki Kenar Takip eden Kenar

(a) (b)t

(a) Positive clock pulse, (b) negative clock pulse.

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Flip-Flop and Latch Triggering Symbols

D Q

CLK

(a)

D Q

CLK

(b)

D Q

CLK

(c)

D Q

CLK

(d)

(a) Positive edge triggered, (b) negative edge triggered, (c) positive level triggered, (d) negative level triggered

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m-bit Register

DQ

CLK

DQ

CLK

DQ

CLK

Qm-1 Q

m-2

Dm-1

Dm-2

D 0

Q 0

CLK

GirişVeri Yolu

ÇıkışVeri Yolu

14

1. Memory Basics

2. Memory Design with D Flip Flops3. Random Access Memory4. DRAM5. Read Only Memory6. Memory Decoding7. Memory System Design for Microprocessors8. Designing Larger Memories

Lecture Outline

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Memory Design with D Flip Flops

• An example 4x3 memory design Uses 12 D flip flops in a 2D array Uses a 2-to-4 decoder to select a row (i.e. a word) Multiplexers are used to gate the appropriate output A single WRITE (WR) is used to serve as a write and

read signal – zero is used to indicate write operation– one is used for read operation

Two address lines are needed to select one of four words of 3 bits each

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Memory Design with D Flip Flops (cont’d)

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Memory Design with D Flip Flops (cont’d)

• Problems with the design Requires separate data in

and out lines» Cannot use the

bidirectional data bus Cannot use this design as a

building block to design larger memories

» To do this, we need a chip select input

• We need techniques to connect multiple devices to a bus

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Common Bus Problem

Giriş Çıkış

Q1

Q2

Vcc

Giriş Çıkış

Vcc

ON

OFF

Vcc

OFF

ON

A B

Uygun olmayanbağlantı

A

B

Q1

Q2

(d)(c)

(a) (b)

(a) Logic diagram of a standard TTL inverter with totem pole output and its internal structure (b).

(c) logic diagram of improper connection.

(d) short circuit of two inverters with outputs connected;

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Techniques to Connect to a Bus

• Three techniques Use multiplexers

» Example

– We used multiplexers in the last memory design

» We cannot use MUXs to support bidirectional buses

Use open collector outputs» Special devices that facilitate connection of several outputs

together

Use tri-state buffers» Most commonly used devices

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Techniques to Connect to a Bus (cont’d)

Open collector technique

21


Open collector register chip

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Tri-State Buffers

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Tri-State Buffer

E E E E

X Y X Y X Y X Y

Y = X, E = 1 ise Y = X, E = 0 ise Y = X, E = 1 ise Y = X, E = 0 ise(a) (b) (c) (d)

3-state buffers with noninverting (a), (b) and inverting (c), (d) outputs.

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m-bit Register having 3-state outputsD

Q

CLK

DQ

CLK

DQ

CLK

Qm-1 Q

m-2

Dm-1

Dm-2

D 0

Q 0

CLK

GirişVeri Yolu

3-durumluÇıkışVeri Yolu

E

25

Techniques to Connect to a Bus (cont’d)Two example tri-state buffer chips

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8-bit tri-state register

27

8-bit (octal) Registers having 3-state outputs

CLK

(a)

OE

D0

D7

Q0

Q7

CLK

(b)

OE

D0

D7

Q0

Q7

GirişKontrolü

ÇıkışKontrolü

GirişKontrolü

ÇıkışKontrolü

8-bit 8-bit 8-bit 8-bit

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Building a Memory Block with 3-state Buffers

A 4 X 3 memory designusing D flip-flops

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Building a Memory Block (cont’d)

Block diagram representation of a 4x3 memory

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Building Larger Memories: 2 x 16-bit Register File

2 X 16 memory module using 74373 chips

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Memory Organization• Memory chips are organized into a number of

locations within the IC. – Each can hold 1, 4, 8, or even 16 bits.

• Depending on internal design. – The number of bits each location can hold is always

equal to the number of data pins on the chip.– The number of locations in a memory chip depends

on the number of address pins. • Always 2x, where x is the number of address pins.

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Memory Address Bits and Memory Capacity– Each memory IC chip contains 2x locations,

where x is the number of chip address pins.• Each location contains y bits, where y is the

number of data pins on the chip.– The entire chip contains 2x x y bits, where x is

the number of address pins and y the number of data pins.

• The 2x x y is referred to as the organization of the memory chip, with x expressed as the number of address pins, and y the number of data pins.

– 210 = 1024 = 1K. (Kilo = 1000. 1 Kilobyte)• Note that in common speech, 1K is 1000, but in

computer terminology it is 1024. See Table 10-1.

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Memory Capacities and Number of Bits Required for Addressing

Memory Capacity Number of Words Bits1K 1024 10-bit

2K 2048 11-bit

4K 4096 12-bit

8K 8192 13-bit

16K 16384 14-bit

32K 32768 15-bit

64K 65536 16-bit

128K 2 64K 17-bit

256K 4 64K 18-bit

512K 8 64K 19-bit

1M 1024 1024 (16 64K) 20-bit

16M 16 1M 24-bit

1G 1024 1024 1024 30-bit

4G 4 1G 32-bit

1T 1024 1024 1024 1024 40-bit

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1. Memory Basics2. Memory Design with D Flip Flops

3. Random Access Memory4. DRAM5. Read Only Memory6. Memory Decoding7. Memory System Design for Microprocessors8. Designing Larger Memories

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RAM: Random Access Memory• RAM memory is called volatile memory since

cutting off the power to the IC will mean the loss of data. – Sometimes referred to as RWM (Read & Write Memory).

• There are three types of RAM: – Static RAM (SRAM)– Dynamic RAM (DRAM)– NV-RAM (nonvolatile RAM)

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SRAM• Storage cells in static RAM memory are made of

flip-flops & do not require refreshing to keep data. • Each cell requires at least 6 transistors to build.

– Each cell holds only 1 bit of data. • Recently 4-transistor cells have been made, still too many.

• 4-transistor cells, plus use of CMOS technologyhas given led to a high-capacity SRAM.– Still far below DRAM capacity.

• Table in the next slide shows some examples of SRAM.

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Static R/W Memory (RAM)

SRAM Examples

Memory Capacity Pin Number Control Lines I/O Type

2115A 1K 1 16 CS, WE Separate

2147H 4K 1 18 CS, WE Separate

51C67 16K 1 20 CS, WE Separate

2114A 1K 4 18 CS, WE Common

6168 4K 4 20 CS, WE Common

6116 2K 8 24 CS, WE, OE Common




CSRDWR

Adres Veri

CSOEWE

A 0 A n-1 D 0 D m-1n m

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6116 2K x 8 SRAM

A Simple SRAM Example: 6116 Pinouts– 6116 has a capacity of 2K bits.

• As indicated in the part number.

– A0–A10 are address inputs• Where 11 address lines gives 211 = 2K

– I/O0–I/O7 are for data I/O• 8-bit data lines give 2K x 8 organization.

– WE (write enable) is for writing data into SRAM. (active low)

– OE (output enable) is for reading data out of SRAM. (active low)

– CS (chip select) is used to select the memory chip. (active low)

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SRAM 6116 diagramThe functional block diagram for the 6116 SRAM

6116 Functional Diagram40

Memory Write Timing for SRAM 6116 Functional Diagram

SRAM data write steps– 1. Provide an address to pins A0–A10.– 2. Activate the CS pin.– 3. Make WE = 0 while RD = 1. – 4. Provide the data to pins I/O0–I/O7.– 5. Make CS = 1 and data will be written into SRAM on

the positive edge of the CS signal.

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Memory Read Timing for SRAM 6116 Functional Diagram

SRAM data read steps– 1. Provide the addresses to pins A0–A10, the start of the

access time (tAA).– 2. Activate the CS pin.– 3. While WE = 1, a high-to-low pulse on the OE pin will

read the data out of the chip.

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• A most important characteristic of a memory chip is the speed at which data can be accessed from it. – To access the data, the address is presented to the

address pins, and after a certain amount of time has elapsed, the data shows up at the data pins.

• The shorter this elapsed time, the better, (and moreexpensive) the memory chip.

• The speed of the memory chip is commonly referred to as its access time. – Varies from a few nanoseconds to hundreds of

nanoseconds.

Memory Speed: Access Time

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SRAM 6116 Access & Read TimeAccess time, tAA, is measured as time elapsed from the moment an address is provided to the address pins to the moment data is available at the pins. Speed for the 6116 chip can vary from 100 ns to 15 ns.

Memory Read Timing for SRAM

100 ns - 15 ns

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SRAM 6116 Access & Read timeRead cycle time, tRC, is defined as the minimum amount of time required to read one byte of data, that is, from the moment the address of the byte is applied, to the moment the next read operation can begin.

Memory Read Timing for SRAM

45

SRAM 6116 Access & Read TimeIn SRAM for which tAA = 100 ns, tRC is also 100 ns, which implies the contents of consecutive addresses can be read with each taking no more than 100 ns, hence, in SRAM and ROM: tAA = tRC.

100 ns

100 ns

Memory Read Timing for SRAM46

Read and Write Timing Diagrams

CS

Adres

Geçerli VeriVeri Çıkışı

tA

Okuma Çevrimi

CS

Adres

Veri DeğişebilirVeri Girişi

WE

Veri DeğişebilirVeri Kararlı

Yazma Çevrimi

tw

Read Cycle

Write Cycle

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1. Memory Basics2. Memory Design with D Flip Flops3. Random Access Memory

4. DRAM5. Read Only Memory6. Memory Decoding7. Memory Decoding8. Memory System Design for Microprocessors9. Designing Larger Memories

48

DRAM: Dynamic RAM• In 1970, Intel Corporation introduced the first

dynamic RAM. – Density (capacity) was 1024 bits.

• It used a capacitor to store each bit. – After the 1K-bit (1024) chip came the 4K-bit in 1973.

• Advancing steadily, until the 256M DRAM chip in the 1990s.

• Using a capacitor to store data reduces the total number of transistors needed to build the cell.– Use of capacitors as storage cells in DRAM results

in a much smaller memory cell size.• They require constant refreshing due to leakage.

49

DRAM Advantages/Disadvantages and Terms• Major advantages:

– high density (capacity), – cheaper cost– lower power consumption per bit.

• Disadvantages:– It must be refreshed periodically, as the capacitor cell

loses its charge.– While it is being refreshed, the data cannot be accessed.

• When referring to IC memory chips, capacity is always assumed to be in bits. – A 1G chip means a 1-gigabit chip and a 256M chip

means a 256M-bit chip. 50

DRAM Packaging Issues• It is difficult to pack large numbers of cells into single

DRAM chips, with normal numbers of address pins. – A 64K-bit chip (64K x 1) must have 16 address lines and

one data line, requiring 16 pins to send in the address.• In addition to VCC power, ground & read/write control pins.

– Multiplexing/demultiplexing reduces the number of pins.• Addresses are split & each half is sent through the same pins.

• Internally, the DRAM structure is divided into a square of rows and columns. – The first half of the address is called the row.– The second half is called the column.

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DRAM Packaging Issues

• The second address half issent through the same pins– Activating CAS (column address

strobe), latches the second half.

• In a 64K x 1 organization, the first half of the address is sent through pins A0–A7. – Internal latches grab the first half.

• Using RAS (row address strobe)

256K × 1 DRAM

• 8 address pins, plus RAS &CAS make a total of 10 pins

• Instead of 16, without multiplexing.

52

DRAM Packaging Issues

• The WE (write enable) pinis for read and write actions.

• There must be a 2-by-1 multiplexer outside the DRAM chip, which has its owninternal demultiplexer. – To access a bit of data from,

both row & column addressmust be provided.

256K × 1 DRAM

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DRAM, SRAM, ROM Organizations• Organizations for SRAMs & ROMs are always x 8.

– DRAM can have x 1, x 4, x 8, or x 16 organizations. • In some memory chips (notably SRAM), the data

pins are called I/O. – In some DRAMs, there are separate pins Din and Dout.

• DRAMs with x1 organization are widely used for parity bit.

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NV-RAM: Nonvolatile RAM• Nonvolatile RAM allows the CPU to read & write to

it & when power is turned off, contents are not lost. • NV-RAM chip internal components:

– 1. Extremely power-efficient (low power consumption) SRAM cells, built out of CMOS.

– 2. Internal lithium battery as a backup energy source.– 3. Intelligent control circuitry.

• To monitor the VCC pin, and automatically switch tothe lithium battery on for loss of external power.

• NV-RAM is used to save x86 PC system setup. – Commonly referred to as CMOS RAM.

1. Memory Basics2. Memory Design with D Flip Flops3. Random Access Memory4. DRAM

5. Read Only Memory6. Memory Decoding7. Memory System Design for Microprocessors8. Designing Larger Memories

56

ROM Read-Only Memory• ROM is a type of memory that does not lose its

contents when the power is turned off. – Also called nonvolatile memory.

• There are different types of read-only memory:– PROM, EPROM, EEPROM, Flash ROM, and mask ROM.

57

PROM programmable ROM or OTP ROM• PROM refers to the kind of ROM that the user can

burn information into. – A user-programmable memory.

• The programming process is called burning, using special equipment. (A ROM burner or programmer)

• For every bit of the PROM, there exists a fuse. – PROM is programmed by blowing the fuses. – If information burned into PROM is wrong, it must be

discarded, as the internal fuses are blown permanently. – For this reason, PROM is also referred to as OTP.

(one-time programmable)58

EPROM: Erasable Programmable ROM• EPROM was invented to allow changes in

the contents of PROM after it is burned. – One can program/erase the memory chip

many times. • Useful during prototyping of a microprocessor-

based projects. • All EPROM chips have a window, to shine ultraviolet

(UV) radiation to erase the chip's contents. – EPROM is also referred to as UV-erasable EPROM

or simply UV-EPROM. – Erasing EPROM contents can take up to 20 minutes.– It cannot be programmed while in the system board

(motherboard).

EPROM (Erasable Programmable Read Only Memory )

5 V 5 V 5 V

8

Vcc Vpp PGM

(a)

DışarıOkunan Veri

2712816K x 8

A13 - A0 D7 - D0

CSRD

CEOE

14

5 V0 V

Vcc Vpp PGM

(b)

2712816K x 8

A13 - A0 D7 - D0

CEOE

14

6 V 12.5 V

ProgramlamaDarbesi

8

YazılacakVeri

EPROM Examples

Memory Capacity Pin Number Control Lines I/O Type

2716 2K 8 24 CE, OE Common

2732A 4K 8 24 CE, OE Common



27256 32K 8 28 CE, OE Common

27512 64K 8 28 CE, OE Common

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An EPROM Chip: 2764

– Note the A0–A12 address pins and O0–O7 (output) for D0–D7 data pins.

• OE (out enable) is for the read signal.

Fig. 10-1 UV-EPROM Chip

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A Simple EPROM Programmer

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EPROM Programming Steps• 1. Erase the contents.

– Remove it from its system board socket, and use EPROM erasure equipment to expose it to UV radiation.

• 2. Program the chip.– To burn code & data into EPROM, the

ROM burner uses 12.5 volts or higher, (called VPP), depending on type.

• EEPROM with VPP of 5–7 V is available, but it is more expensive.

• 3. Replace the chip in its socket.Fig. 10-1 UV-EPROM Chip

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Flash Memory • Since the early 1990s, Flash ROM has become

a popular user-programmable memory chip. – The process of erasure of the entire contents takes

only a few seconds. (In a flash, hence the name) – Electrical erasure lends the nickname Flash EEPROM.

• To avoid confusion, it is commonly called Flash ROM.

• When Flash memory's contents are erased the entire device is erased.– In contrast to EEPROM, where one sections or bytes. – Some Flash memories recently available are divided

into blocks, and erasure can be done by block.• No byte erasure option is yet available.

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Flash Memory • Because Flash ROM can be programmed while in

its system board socket, it is widely used to upgrade PC BIOS ROM, or Cisco router operating systems. – Some designers believe that Flash memory will

replace the hard disk as a mass storage medium. • The program/erase cycle is 500,000 for Flash

and EEPROM; 2000 for UV-EPROM; infinite for RAM & disks. – Program/erase cycle is the number of times a chip can

be erased and programmed before it becomes unusable.

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Memory Identification

See the entire table on page 259 of your textbook.

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• Capacity of the memory chip is indicated in the part number, with access time given with a zero dropped.


– 27128-20 refers to UV-EPROM that has a capacity of128K bits and access time of 200 nanoseconds.


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• In part numbers, C refers to CMOS technology.


– 28xx for EEPROM. – 27xx is for UV-E PROM


68

Mask ROM• Mask ROM refers to a kind of ROM whose contents

are programmed by the IC manufacturer. – Not a user-programmable ROM. – The terminology mask is used in IC fabrication.

• Mask ROM is used when needed volume is high &it is absolutely certain the contents will not change.– Since the process is costly.

• The cost is significantly cheaper than other kinds of ROM, but if an error in the data is found, the entire batch must be discarded.

69

1. Memory Basics2. Memory Design with D Flip Flops3. Random Access Memory4. DRAM5. Read Only Memory

6. Memory Decoding7. Memory System Design for Microprocessors8. Designing Larger Memories

70

Simple Logic Gate as Address Decoder• Current system designs use CPLDs.

(complex programmable logic devices)– Memory & address decoding circuitry are integrated

into one programmable chip. – A task which can be performed with common logic

gates.• NAND and 74LS138 chips act as decoders.

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Fig. 10-8 Using Simple Logic Gate as Decoder

Simple Logic Gate as Address Decoder• In connecting a memory chip to the CPU, the data

bus is connected directly to the data pins of the memory. – Control signals MEMR & MEMW

are connected to the OE & WR pins.

72

MEMORY ADDRESS DECODING simple logic gate as address decoder• On the address buses, the lower bits of the address

go directly to memory chip address pins.– The upper ones activate the CS pin of the memory chip.

• CS pin, with RD/WR allows data flow in/out of the chip. – No data can be written into or read from the memory

chip unless CS is activated. • CS input is active-low and can be activated using

simple logic gates, such as NAND and inverters. – For every block of memory, we need a NAND gate.

• See Figs. 10-9 & 10-10 on page 266.

73

MEMORY ADDRESS DECODING simple logic gate as address decoder• Example 10-6 shows the address range calculation

for Fig. 10-10 on page 266.– Note the output of the NAND gate is active-low.

• The CS pin is also active-low .

74

74LS138 Decoder

Three inputs:A, B & C, generateeightactive-lowoutputs:Y0–Y7.

Using the 74LS138 as Decoder• In the absence of CPLD or FPGA as address

decoders, the 74LS138 chip is an excellent choice.

The 3-to-8 Line Decoder (74LS138)

Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high, respectively.

Each output of the decoder can be attached directly to CS or CE pin of an EPROM or RAM chip.76

74LS138 Decoder

MEMORY ADDRESS DECODINGusing the 74LS138 as decoder

Each Y output connects to the CS of a memory chip, allowing controlof 8 memory blocks bya single 74LS138.


• The need for NAND and inverter gates is eliminated when using 74SL138.

77

74LS138 Decoder

MEMORY ADDRESS DECODINGusing the 74LS138 as decoder• To enable 74SL138: G2A = 0, G2B = 0, G1 = 1.

– G2A & G2B are grounded; G1 = 1 selects this 74LS138.

Each Y output connects to the CS of a memory chip, allowing controlof 8 memory blocks bya single 74LS138.


Inputs G2A, G2B & G1, can be used for address or control signal selection

78

1. Memory Basics2. Memory Design with D Flip Flops3. Random Access Memory4. DRAM5. Read Only Memory6. Memory Decoding

7. Memory System Design for Microprocessors8. Designing Larger Memories

79

To design a memory system for a microprocessor based system:The lengths of memory bus and address bus of the

microprocessor used.The starting address of microprocessor reset where the

program execution starts.The control lines that the microprocessor uses in

memory access.…..

Memory System Design

80

Memory Address Decoding The processor can usually address a memory space that

is much larger than the memory space covered by an individual memory chip.

In order to splice a memory device into the address space of the processor, decoding is necessary.

For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space.

However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.

A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space.

81

Data Transfer Between Registers

D Q

CLK

W

D Q

CLKWDX

X

D Q

CLKRDY

Y

D Q

CLK

Z

D Q

CLK

MWRM

D Q

CLK

NWRN

D Q

CLK

OWRO

D Q

CLK

PWRP

Kaynak Saklayıcılar Hedef Saklayıcılar

1-bittekyönlüVeri Yolu

RDZ

RDW

Sadece bir çıkışaktif düşük

1B 1Y01Y11Y21Y3

1A

1G

A0

A1

RD

2x4 Decoder

RDWRDXRDYRDZ

2B 2Y02Y12Y22Y3

2A

2G

B0

B1

WR

2x4 Decoder

WRMWRNWROWRP

0 0 W0 1 X1 0 Y1 1 Z

A0A1

SeçilenSaklayıcı

Adres

0 0 M0 1 N1 0 O1 1 P

B0B1

Adres SeçilenSaklayıcı

Use of three-state buffers to share data bus lines

82

Timing Diagram for Two Successive Data Transfers

0

1

0

1

0

1

A1

A0

B1

B0

0

1

RD0

1

Birinci Çevrim İkinci Çevrim

OkumaAdresi

YazmaAdresi

WR0

1

WRP0

1

WRO0

1

0

1VERİ

(Y) (P) (X) (O)1 veya 0

Yüksekempedans

Veri yolundaki 1-bitverinin tutturulma anları

83

Memory System Design Steps1. Estimate the amount of ROM and RWM required for

the application.2. Determine the address boundaries of each type of

memory. Draw an initial memory map.3. Select the memory devices to be used.4. Determine the arrangement of memory devices

necessary to provide the required word length and number of words. Draw the detailed memory map.

5. Design the address decoding logic.6. Determine the buffering required, if any.7. Determine the required speed of the memory devices.

84

Basic 4 Data Transfers of a Microprocessor

Data transfers between a microprocessor and memory and I/O devices

Data Transfer RD WR IO/M Cycle Comment

I M 0 1 0 MEMR Memory read

I M 1 0 0 MEMW Memory write

I IO 0 1 1 IOR I/O read

I IO 1 0 1 IOW I/O write

Intel control signals for basic microprocessor data transfers:

RD: Read (active low)WR: Write (active low)IO / M: Input Output / Memory

85

A Memory Design Example for 8085 Microprocessor

8085 signals which will be used in the memory system design: 16-bit Address Bus, A15-A0, 8-bit Data Bus, D7-D0, 3 control lines, IO.H/M.L , RD.L and WR.L

86

A Simple Memory System Design Example 4K8 EPROM ve 2K8 RWM EPROM starts from 0000h, after EPROM RWM starts.

ROM

0000h

FFFFh

4K

RWM

2K

58KBoş

0FFFh1000h

17FFh1800h

Memory map

A15 - A12

0 0 0 00 0 0 0

A11 - A8

0 0 0 01 1 1 1

A7 - A4

0 0 0 01 1 1 1

A3 - A0

0 0 0 01 1 1 1

0000h0FFFh

4K ROM içinde birhafıza hücresini seçer

İlk 4K'lık bloğu seçer

0 0 0 10 0 0 1

0 0 0 00 1 1 1

0 0 0 01 1 1 1

0 0 0 01 1 1 1

1000h17FFh

2K RWM içinde birhafıza hücresini seçer

Üçüncü 2K'lık bloğuseçer

Address bit map

87

A Design Using Full Decoding

27324K x 8

EPROM

A11 - A0 D7 - D0

RDCEOE

12

61162K x 8RWM

A11 - A0 D7 - D0

RDCSOE

11

WR WE

Veri Yolu

D7 - D0

74LS138

Y0Y1Y2Y3Y4Y5Y6Y7

CBA

G2BG2A

G1

07FFh-0000h

0FFFh-0800h

A11 - A0

A10 - A0

17FFh-1000hA11

A12

A13

A15

A14IO / M

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Another Design Using Partial Decoding

89

1. Memory Basics2. Memory Design with D Flip Flops3. Random Access Memory4. DRAM5. Read Only Memory6. Memory Decoding

7. Memory System Design for Microprocessors8. Designing Larger Memories

90

Designing Larger Memories

• Issues involved Selection of a memory chip

» Example: To design a 64M X 32 memory, we could use– Eight 64M X 4 in 1 X 8 array (i.e., single row)

– Eight 32M X 8 in 2 X 4 array

– Eight 16M X 16 in 4 X 2 array

• Designing M X N memory with D X W chips Number of chips = M.N/D.W Number of rows = M/D Number of columns = N/W

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Designing Larger Memories (cont’d)

64M X 32 memory using 16M X 16 chips

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Designing Larger Memories (cont’d)

• Design is simplified by partitioning the address lines (M X N memory with D X W memory chips) Z bits are not connected (Z = log2(N/8)) Y bits are connected to all chips (Y = log2D) X remaining bits are used to map the memory block

» Used to generate chip selects

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Memory Mapping

Full mapping

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Memory Mapping (cont’d)

Partial mapping

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Alignment of Data

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Alignment of Data (cont’d)

• Alignment 2-byte data: Even address

» Rightmost address bit should be zero

4-byte data: Address that is multiple of 4» Rightmost 2 bits should be zero

8-byte data: Address that is multiple of 8» Rightmost 3 bits should be zero

Soft alignment» Can handle aligned as well as unaligned data

Hard alignment» Handles only aligned data (enforces alignment)

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Interleaved Memory

• In our memory designs Block of contiguous memory addresses is mapped to a module

» One advantage– Incremental expansion

» Disadvantage– Successive accesses take more time

Not possible to hide memory latency

• Interleaved memories Improve access performance

» Allow overlapped memory access» Use multiple banks and access all banks simultaneously

– Addresses are spread over banks Not mapped to a single memory module

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Interleaved Memory (cont’d)

• The n-bit address is divided into two r and m bits:n = r + m

• Normal memory Higher order r bits identify a module Lower order m bits identify a location in the module

» Called high-order interleaving

• Interleaved memory Lower order r bits identify a module Higher order m bits identify a location in the module

» Called low-order interleaving Memory modules are referred to as memory banks

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• Two possible implementations Synchronized access organization

» Upper m bits are presented to all banks simultaneously» Data are latched into output registers (MDR)» During the data transfer, next m bits are presented to initiate

the next cycle

Independent access organization» Synchronized design does not efficiently support access to

non-sequential access patterns» Allows pipelined access even for arbitrary addresses» Each memory bank has a memory address register (MAR)

– No need for MDR

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Synchronized access organization

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Interleaved memory allows pipelined access to memory

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Independent access organization

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• Number of banks M = memory access time in cycles To provide one word per cycle

» Number of banks M

• Drawbacks of interleaved memory Involves complex design

» Example: Need MDR or MAR Reduced fault-tolerance

» One bank failure leads to failure of the whole memory Cannot be expanded incrementally

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AcknowledgementThe slides have been based in-part upon original slides of a numberof books including: The x86 PC: Assembly Language, Design, and Interfacing, 5/E,

M. A. Mazidi, J. G. Mazidi, D. Causey, Prentice Hall, 2010. Fundamentals of Computer Organization and Design, S. P.

Dandamudi, Springer, 1060 pages, 2003. Mikroişlemciler ve Bilgisayarlar, 6. Basım, H. Gümüşkaya, ALFA,

2011.

Mp2-SUPER!_Memory Basics and Memory System Design_v0.3

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