MCWOO

Ii 8-BIT MICROPROCESSING UNIT (MPU)I The MC6800 is a monolithic 8-bit microprocessor forming the central control function for Motorolas M68~ family. Compatible with TTL, the MC6B~, as with all M6800 system parts, requires only one + 5.O-volt power supply, and no external TTL devices for bus interface. The MC6800 is capable of addressing 64K bytes of memory with its 16-bit address lines. The 8-bit data bus is bidirectional as well as threestate, making direct memory addressing and multiprocessing applications realizable. q 8-Bit Parallel Processingq Bidirectional

Data Bus Variable Length Indexed,

. .

16-Bit Address Bus WK Bytes of Addressing Seven Addressing Modes Direct, Relative, Immediate, Extended, Implied and Accumulator

q 72 Instructions

,>: ,,*!. )!.IC,[ . Vectored Restart .}. .*$ ,,2:+.( ~ ~%1 *F. . Maskable Interrupt Vector ~ ..!. . Separate Non-Maskable Interrupt Internal Registers Saved i#::$$ , +, ~. ,{). ~, ,)i .Y,:>, .,,,!,. -,,,.... Stack .... *: ,.. is . Six Internal Registers Two Accumulators, Index Regist~#?Y:Y Program Counter, Stack Pointer and Condition Code Re~@te~ q Direct Memory Addressing (D MA) and Multiple P~@$essor .:;.!,.,,>s,-. Capability , ., . .+ ,., -->, *V,1.- ,,:+~.., \>>>., **. q Simplified Clocking Characteristics ~:?iii ...*,+< * ,,:+,.., .~;:),t.{t,. . Clock Rates as High as 2.0 MHz ,~> *:;.> q Simple Bus Interface Without TTL ,$~~~~i$~q Variable Length Stack q Halt and Single Instruction

uu. -

SUFFIXCERAMIC PACKAGE CASE 715

PIN ASSIGNMENT Vss[ HALT[ 10 2 ~ JRESET 39 ]TSC 38 ]N. C.37

Executlo*k$~~$bility ,.*. .\ ~ ~$$~ ;:$*Y*:,F . .., .it~ ,.,.$,.>. i,\,.*> & ~~$ ,{, ..,. ,:&f*, ~ ,>$ $$:$ .~~ ~: ... ~+~, \*:,.: ,*.. .+~ \,\.\\ Where K is a constant pertaining to the parti~$~$~~~it. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K the va~~~~:Qft,@Dand TJ can be obtained \\*:*,..,, value of TA, ,>f:?>,{,,,>i, ,t .~\ ~,.,,\ ,,,..,,.,

5,0 Vdc, +5%,

Vss = O, TA= TL to TH unless otherwise noted) Svmkl Logic 41,42 Logic ~1 ,42 Logic @l, #2 D&D7 AO-A15, Rlw DO-D7 VMA BA VSS+2.4 VSS+2.4 VSS+2.41 VSS0,3 VSS0,3 1,0 VSS+O.8 VSS+O.4 2.5 v

.&i,t. ~~ \t$.? a?+$,}.,,~ ~.,t...t, Input Low Voltage ~w$&~$,$# .,. , .,:..,.,.: ~:~, Y ~:.. d *:*:*L $$:fi+s:~

tt tr, tf ~ td

Rise and Fall Time (Measured between VSS +0.4 and VCC O.6) Delay Time or Clock Separation (Figure 1) (Measured at VOV=VSS+O.6 V@tr=tf=l~ ns) (Measured at VOV= VSS + 1.0 V@tr=tf S35 ns}

1, ,,,, ,,fj:$,i~ ,;? ,..~ %$*t& , ,, >+1,: $; y< $, ~ .$:~, ?\:i..\*., $

ns

td+

+

d+. ,, ,,,.

b,.,,,. .~t~ 4:.- . $~~+ C=30 pF ,,.., .. > Peripheral Read Access ~fi&~f: tacc = tut (tAD +~~~$~. Data Setup Tim$,:( ~~~?: Input Data H@me Output D~@ ~l,#Time Addressf&,&,Jime Ena~~i~@Time Data ~lav (Address, R/~, for DBE Input VMA) *T,

,+1

Symbol

MC~ Min 605 lm 10 10 30 450 2m o Iw Typ 25 50 Max 270 2W 225 Im 29 40 270 25 Min m 60 10 10 30 280 140 0 120

MC8BAO0 Typ 25 a Max 1BO 165 2W 100 165 40 270 25 Min 2W 40 10 10 m 220 110 0 75

MC6BBO0 Typ 25 50 Max 150 135 160 100 135 m 220 25

Unit

tA D

ns

tacc tDSR tH tH tA H tEH tDDW tpcs tpcr, tpcf tBA tTSE tTSD tDBE tDBEr, tDBEf

ns ns ns ns ns ns ns

Time (Write)

Processor Controls Processor Control Setup Time Processor Control Rise and Fall Time 8US Available DelaV Hi-Z Enable Hi-Z DelaV Data Bus Enable Down Time During @l Up Time Data Bus Enable Rise and Fall Times

ns

m

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1

FIGURE 2 READ DATA FROM MEMORY OR PERIPHERALS

Start

of

/ @l

Cycle+

VIHC ~0.4 v7

0.4 v

Data

Not

Valid

~

Start of Cvcle

):.,Data From MPU

2.4

V

[

0.4 vI ktDDw+

k\\\\\\Y

Data

Not

Valid

NOTES: 1. Voltage levels shown are VLSO.4, 2. Measurement

VH> 2.4 V, unless otherwise specified noted

points shown are 0.8 V and 2.0 V, unless otherwise

MOTOROLA@

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Inc.

FIGURE 4 TYPICAL DATA BUS OUTPUT DELAY versus CAPACITIVE LOADING (TDDw) 600lo

FIGURE 5 TYPICAL READ/WRITE, VMA, AND ADDRESS OUTPUT DELAY versus CAPACITIVE LOADING (TAD)600lo 500

I OH

=-205A

max @ 2.4 V

lo H=-145*max@2.4V L=l.6mAmax@0.4v

L=l.6mAmax@0.4V

500 - Vcc = 5.0v 1A= 25C ~ = u z F > ~ : 400 z u z / / 200 100 / CL includes stray capacitance 0 0 100 200 CL, LOAO 300CAPACITANCE

-VCC=5.OV TA = 25C

-$ ,:,

400

300 ~ /

/ ~

~ ~ u 0

300

200

100 CL includes stray capacitance 600 o 0 100

400(pF)

500

2og~+~~ ,i$oo

400

500

600

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I

FIGURE

7

=PANDED

BLOCK

DIAGRAM

A15

A14

A13

A12

All

A1O

A9

A8

A7

A6

A5

A4

A3

A2

Al

AO

Clock, @l Clock, @2 RESET Non-Maskable Interrupt HALT Interrupt Three-State Request Control 37 40 6 a 2 4 39 3 Instruction Decode and Control

Data Bus Enable Bus Available Valid Memory Read/Wtite, Address Rl~

36+

34+

1

Instruction Register * ..l.t\,, !*

.

.

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MPU SIGNAL DESCRIPTION

Proper

operation

of the MPU requires

that certain

control

Read (high)

or Wrile

(low) state,

The normal

standby

state of

and timing signals be provided to accomplish tions and that other signal lines be monitored the state of the processor. (o1, 42)

specific functo determine

this signal is Read (high). Three-State Control going high will turn Read/Write to the off (high impedance) state. Also, when the processor is halted, it will be in the off state. This output 90 pF. is capable of drivina one standard TTL Ioa&?iqnd~+,r+i~ .:}

Clocks Phase One and Phase Two are used for a two-phase non-overlapping the VCC voltage level. Figure 1 shows the microprocessor

Two

pins

clock that

runs at

clocks.

The high level

is specified at VIHC and the low level is specified at VILC. The allowable clock frequency is specified by f (frequency). The minimum @l and @2 high level pulse widths are specified by PW~H (pulse access time for specified. Clock voltage of VOV of clock width high time). To guarantee the required the peripherals, the clock up time, tut, is separation, td, is measured at a maximum (overlap voltage), This allows for a multitude at the system frequency rate.

RESET The RESET input is used to rese~&}N~&~rt the M PU from a power down condition resulti~~,jf~% a power failure or initial start-up of the processor,+:~@l%~i&el sensitive at any time input can also be used to reinitialize t,$~~~~~ne .) k%}?* after start-up. :t:;l,\ \ If a high level is detected in th~ Inpw; this will signal the MPU to begin the reset seqe~$~. During the reset sequence, the contents of th,~?%f$wb locations (FFFE, FFFF) in memory will be loade@{~~&,Jtie Program Counter to point to the routine, beginning of..,$~b.:wet routine. During the reset ~.\J ~t.~,,~y.. the interrupt ~s~ bit is set and must be cleared

variations

Address

Bus (AOA15)

Sixteen are three-state

pins are used for the adbus drivers capable of

dress bus. The outputs

driving one standard TTL load and 90 pF. When the output is turned off, it is essentially an open circuit. This permits the MPU to be used in DMA applications. Putting TSC in its high state forces the Address Data Bus (DO-D7) It is bidirectional, bus to go into the three-state mode.

Eight pins are used for the data bus. data to and from the memory

transferring

and peripheral devices. It also has three-state output buffer$ capable of driving one standard TTL load and 130 pF. D,a~$, Bus is placed in the three-state DBE is Io#t\,t w~$. ,{.y...:>.:> ,,:!:.?.. .+,. $,. ? +:+ This level sensitive i~[~t~$sthe mode when

under program c~~ol, before the M PU can be interrupted by (assuming minimum of8 clock a IRQ. While K%Jklow cycles have ~Jcc~$r8d) the MPU output signals will be in the followinqj$&MVMA= low, BA= low, Data Bus= high impeda~~e,>~~~= high (read state), and the Address Bus will con$&8 the reset address FFFE. Figure 8 illustrates a power ?}4 &~q@~nce using the RESET control line. After the power ~i. ~,P@ reaches 4.75 V, a minimum of eight clock cycles are ?$:jlj$~qtiired for the processor to stabilize in preparation for ~trestarting. During these eight cycles, VMA will be in an in.lp~ determinate state so any devices that are enabled by VMA which could accept a false write during this time (such as battery-backed low after eight with the system RAM) must be disabled until VMA is forced cycles. RESET can go high asynchronously clock is shown any time after in Figure the eighth cycle. rise and

Data Bus Enable (DBE)

three-state control signal for the M PU data ~$~l:~yd will enable the bus drivers when in the high st~:&$$@j9 Input is TTL compatible; however in normal op~,atib~~$twould be driven by the phase two clock. Durin&@n~~,K~ read cycle, the data bus drivers will be disabled,~~t~nal ly. When it is desired that another device contr$PtR~&ata bus, such as in Direct Memory Access (DMA)j+~k~@~ions, DBE should be .>.:,:,.,, . , ~t~ ,x held low. If additional data setup+p[+ho~d~?me is required on an MPU write, the DB E down ,~,~~ @n be decreased, as shown in Figure 3 (DBE#@2\R:~~e~inimum down time for DBE is tDB E as shown, ~~~.s}~ting D B E with setup or hold t~,$@# be increased. \\\$. ;>L:.,.?J , ~ Bus Ay~i$~l~.(bA) The respect to E, data

RESET timing

8. The maximum

fall transition times are specified by tpcr and tpcf. If RESET is high at tpcs (processor control setup time), as shown in Figure 8, in any given cycle then the restart sequence will begin on the next cycle as shown. The RESET control line may also be used to reinitialize the MPU system at any time during its operation. This is accomplished by pulsing RESET low for the duration of a minimum of three complete 42 cycles. The RESET pulse can be completely asynchronous with the MPU system clock and will be recognized during 42 if setup time tpcs Request is met. (~Q) This level sensitive input re-

Interrupt signal will nor-

Bus Available

mally ~%~ ~}$low state; when activated, it will go to the ..,*.:* Y high.?ata~:+indicating that the microprocessor has stopped * *l+ and @,@tfhe address bus is available. This will occur if the HALT~ne is in the low state or the processor is in the WAIT state as a result of the execution of a WAIT instruction. At such time, all three-state output drivers will go to their off state and other outputs to their normally inactive level. The processor is removed from the WAIT state by the occurrence of a maskable (mask bit I = O) or nonmaskable interrupt, This output is capable of driving one standard TTL load and 30 pF. If TSC is in the high state, Bus Available will be low, Read/Write the peripherals (R/~) This TTL compatible devices wether output the MPU signals is in a

quests that an interrupt sequence be generated within the machine. The processor will wait until it completes the current instruction that is being executed before it recognizes the request. At that time, if the interrupt mask bit in the Condition Code Register is not set, the machine will begin an interrupt sequence. The Index Register, Program Counter, Accumulators, and Condition Code Register are stored away on the stack. Next, the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts may occur. At the end of the cycle, a 16-bit address will be loaded that points is located in memory locations to a vectoring address which FFF8 and FFF9. An address

and memory

loaded at these locations causes the MPU to branch to an interrupt routine in memory. Interrupt timing is shown in Figure 9.

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time PW@H without destroying data within the M PU. TSC then can be used in a short Direct Memory Access (DMA) application. Figure 12 shows the effect of TSC on the MPU. TSC must have its transitions at tTSE (three-state enable) while holding +1 high and +2 low as shown, The Address Bus and Rl~ line will reach the high-impedance state at tTSD (three-state Non-Maskable Interrupt (NMI) and Wait for Interrupt delay), with VMA being forced low. In this exampl$~%the Data Bus is also in the high-impedance state while,,~;~@&(WAI) The MCWCO is capable of handling two types of interrupts: maskable (~) as described earlier, and noning held low since DBE= 42. At this point in ti@e~,$,)~MA maskable (~) which is an edge sensitive input. IRQ is transfer could occur on cycles #3 and #4. -+$~SC is maskable by the interrupt mask in the condition code register returned low, the MPU Address and R/~lfl&/&Mrn to the while ~ is not maskable. The handling of these interrupts bus. Because it is too late in cycle #5 to,,~cp~,~emory, this cycle is dead and used for synchroni$~~w.i$~rogram execuby the M PU is the same except that each has its own vector ..>;. .* .!~:l tion resumes in cycle #6. address. The behavior of the MPU when interrupted is .~\k:\, .:~:.3, ~.:~ shown in Figure 9 which details the MPU response to an in1~$ ~ Valid Memory Address (VM&,~~$ This output indicates to terruDt while the MPU is executina the control ~roaram. The peripheral devices that the~@&.@~a~?d ddress on the address a interrupt shown could be either ~Q or ~ and ca~ be asynbus. In normal operation~ .,,+$s: Register (IX), Accumulators (ACCX), and the Condition ..?XL?* >.~~. Code Register (CCR) are pushed onto the stack, HALT - ~h~$~%is level sensitive input is in the low state, The Interrupt Mask bit is set to prevent further interrupts. all activik~~o?~~e machine will be halted. This input is level -.:), The M PU has three 16-bit registers and thra-$,8~*@ registers available for use by the programmer (FJ$@?~d@. *.Y -I:,.,~~> ,$Program Counter The program count~$&~?:&t&o byte (16 bits) register that points to the curre~~,w~$m address. ,+$, ~,i Stack Pointer The stack pon~*i~%,;&o byte register that contains the address of the ne&,,a$ilable location in an external push-down/pop-up st$~~$~fs stack is normally a random access Read/Write,,,%b*~.#that may have any location (address) that is conV@ieJ~t. In those applications that require storage of inf@~atidB In the stack when power is lost, the stack muskl~~~~volatile. ,.,,,$:.,,, ~?, ..

.,

FIGURE14 PROGRAMMING MODEL OF THE MICROPROCESSINGUNIT

Accumulator

A

Accumulator

B

Index

Register

Pc15 0

Program

Counter

Index RWis~~~~~$%e index register is a two byte register that is used x~i$~$?data or a sixteen bit memory address for the lnde&& &&e of memory addressing. ;8 ,.:,. * :$.,,,{.. .. . ....\..:+L.\:!!i,

SP7 llt m

Stack

Pointer

The MPU contains two 8-bit accwuktprs that are used to hold operands and results from a~~{~~metic logic unit (ALU). ...Aq~$#~ators

code register indicates the results of an Arithmetic Logic Unit operation: Negative (N), Zero (Z), Overflow (V), Carry from bit 7 (C), and half carry from bit 3 (H). These bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the interrupt mask bit (l). The unused bits of the Condition Code Register (b6 and b7) are ones.Condition Code Register

The condition

woCondition Registar INZVC Carrv

Code

(From

Bit 7)

II -

Overflow

zeroCarrv (From Bit 3)

r

;:::t.

Half

@

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MPU INSTRUCTIONThe MC~ instructions are described in detail in the MWW Programming Manual. This Section will provide a brief introduction and discuss their use in developing MC~ control programs. The MC66W has a set of 72 different executable source instructions. Included are binary and decimal arithmetic, logical, shift, rotate, load, store, conditional or unconditional branch, interrupt and stack manipulation instructions. Each of the 72 executable instructions of the source language assembles into 1 to 3 bytes of machine code. The number of bytes depends on the particular instruction and on the addressing mode. (The addressing modes which are available for use with the various executive instructions are discussed later, ) The coding of the first (or only) byte corresponding to an executable instruction is sufficient to identify the instruction and the addressing mode. The hexadecimal equivalents of the binary codes, which result from the translation of the 72 instructions in all valid modes of addressing, are shown in Table 1. There are 197 valid machine codes, 59 of the 256 possible codes being unassigned.

SET

When an instruction translates into two or three bytes of code, the second byte, or the second and third bytes contain(s) an operand, an address, or information from which an address is obtained during execution. Microprocessor instructions are often divided into three general classifications: (1) memory reference, so called because they operate on specific memory locations; (2) operating instructions that function without needing a memory reference; (3) 1/0 instructions for transferring data between the microprocessor and peripheral devices. $+cl+ In many instances, the M Cm performs the sarn$*ation on both its internal accumulators and ~#r@rnal memory locations. In addition, the MC%:,~@terface adapters (PIA and ACIA) allow the MPU t~$~~~k~peripheral devices exactly like other memory loca@~$.3@#nce, no 1/0 instructions as such are required. Beca&Wq@these features, $,? ~ other classifications are more sui~@fl~&~~b~ introducing the MC66WS instruction set: (1) ,$cc%hlator and memory operations; (2) Program cont~~t~perations; (3) Condition ~ i~~~ Code Register operations, ,,,~~~~, % ~~-~ ,.,,\., ,,, , ,\ OPERATf ON (All register labels refer to contents)

BOOLEAN/ARITHMETIC EXTNO

OPERATIONS Add Add Acmltrs Add wlfh Carry And Blt Tesl Clear

MNEMONIC ADDA ADOB ABA AOCA AOCB ANDA ANOB BITA BITE CLR CLRA CLRB CMPA CMPB CBA COM COMA COMB

1P-=

.B21

F21 F21

Compare Compare Acmltrs Complement, 1s

121 1321 i321 lo2f io21 1921

Complement, (Negate)

2s

NEG NEGA NEGB A OAA OEC oECA OECB IA21 ,A21

Dec!mal Adi.st, Decrement

ExcIsie OR Increment

EORA EORB INC INCA INCB 1C21 iC21

Load Acmltr Or, Inclusive Push Oata Pull Oata Rotate Left

LOAA LDAB O RAA ORAB PSHA ?SHB PU LA PU LB ROL ROLA ROLB ROR RORA RORB !6 j6 $8 58 a7 57 44 54 2 2 2 2 2 2 2 2 1 1 1 1 1 1 M 1 1 A B} A-M B-M A B 10 2 1 M-A M-B o-~ b7 bO 0 C !9 j9 2 2 A+ M-A B+M+B 1 1 A+ MSp, SP-f-SP B-, Msp, SPl+SP SP+I-SP, SP+I+SP, M A c B }L-J M A B lk-[dc b7 bO b7 bO MSP-A MSP-B

1I 1 1

.

Rotate R,ght

Shift Left, Ar!thmet!c

ASL ASLA ASLB

Sh[ft Right, Arfthmet!c

ASR ASRA ASRB LSR LSRA LSRB

Sh!f! Right, Logic

Store Acmltr. Subtract Subtracf Acmltrs.

A B-A AM C-A BM C-B A-B B-A M00 A00 BDO

16 17 $0 50

2 2 2 2

I 1 1 1

CON OtTION

CODE SYMBOL5

CON OITION

COOE REGISTER

NOTES: otherwise]

(Bit Set if testis H I N Arithmetic MSP & M + o 00 Minus; location pointed to be Stack Pointer: Boolean ANO: contents Of memow Boolean Inclusive OR; Boolean Exclusive OR; Complement of M; Transfer Into; Bit = Zero; Byte = Zero; z v c R s Hal f.carrv from bit 3; Interrupt mask Negative (tign bit) Zero (byte) Ovetilow, 2s complement Carv from bit 7 Rewt Always Set Alwav$ Test and set if true, cleared otherwise Not Affected 4 5 6 (Bit V) (Bit V) (Bit V)

true and cleared

12 3

V) (Bit (Bit C) (Bit C)

Test: Result = 1000OOOO7 Test: Result = 000000007 Test: Oecimal value of most significant if previously set.] BCO Character greater than nine? 10000000 prior to execution? 01111111 prior to execution?

( Not cleared

Test: Operand= Test: Operand=

tq

Test: Set equal to result of N@C after shift has occurred

-.

Note Accumulator addresbng mode instructions are included in tho column for IMPLIEO

addressing

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PROGRAM CONTROL OPERATIONSProgram Control operation can be subdivided into two categories: (1) Index Register/ Stack Pointer instructions; (2) Jump and Branch operations. Index Register/ Stack Pointer Operations The instructions for direct operation on the MPUS Index Register and Stack Pointer are summarized in Table 3. Decrement (DEX, DES), increment (INX, INS), load (LDX, LDS), and store (STX, STS) instructions are provided for both. The Compare instruction, CPX, can be used to compare the Index Register to a 16-bit value and update the Condition Code Register accordingly. The TSX instruction causes the Index Register to be loaded with the address of the last data byte put onto the stack. The TXS instruction loads the Stack Pointer with a value equal to one less than the current contents of the Index Register. This causes the next byte to be pulled from the stack to come from the location indicated by the index Register. The utility of these two instructions can be clarified by describing the stack concept relative to the M@W system. The stack can be thought of as a sequential list of data stored in the MPUS read/write memory. The Stack Pointer contains a 16-bit memory address that is used to access the list from one end on a last-in-first-out (LIFO) basis in contrast to the random access mode used by the MPUS other addressing modes. The MC~ instruction set and interrupt structure allow extensive use of the stack concept for efficient handling of data movement, subroutines and interrupts. The instructi~.os can be used to establish one or more stacks anywhg~~~< read/write memory. Stack length is limited only Zero Branch If Higher Branch If < Zero Branch If Lower Or Same Branch If < Zero Branch If Minus Branch If Not Equal Zero Branch If Overflow Branch If Ovefilow Branch If Plus Branch To Subroutine Jump Jump To Subroutine No Operation Return From Interrupt Return From Subroutine Softwre Interrupt Clear Set MNEMONIC BRA BCC B CS BEO BGE BGT BHI BLE B LS B LT BMI BNE BVC BVS BPL BSR JMP JSR NOP RTI RTS

hl

G G 24 25 27 2C 2E 22 2F 23 20 2B 26 28 29 2A 80

Y4 4 4 4 4 4 4 4 4 4 4 4 4 4 8

T # G

T2 2 2 2 2 2 2 2 2 2 2 z 2 2 2

i #

CONO. COOE REG.

L

BRANCH

TEST

T10 Vc

6E AO

3 9

3 3I I I I

SwlWAI and ita Businthet

Wait for Interrupt% IAI puts Address Bus, RN,

~Code

~ nRegister if wait

mfrom Stack. set,

low

I

..?Special Op$@tic

@ ~

(All)

Load

Condition when interrupt to

(See a

(Bit 1) Set

occurs. exit the

previously state.

is required

Non-MaSk,:~e%?errUPt .* ~+. ~

Execution of the Jump Instruction, JMP, and Branch Always, BRA, affects program flow as shown in Figure 17. When the MPU encounters the Jump (Indexed) instruction, it adds the offset to the value in the Index Register and %, the result as the address of the next instruction to~b~;~x~$ ecuted. In the extended addressing mode, the add[e~~~?he next instruction

+~$.. used as the end of a subroutine

~y :

tions immediatelyAlways

to be executed is fetched from ,$~$~*~~cafollowing the JM P instructl~~~}K~WBranch

struction

(BRA) instruction is similar to the J~~?~#~&nded) inexcept that the relative addre&Sin&. fiode applies

and the branch is limited to the rang~Wtkm$125 or + 127 bytes of the branch instruction ~4,i.,..\. i~$~}%%.~~e opcode for the ..., ?,,$< BRA instruction requires one les$by~ than J M P (extended) but takes one more cycle to @? The effect on program fl~~ f$r the Jump (JSR) and Branch to Sw#rQu{*$ to Subroutine

(BSR) is shown in Figures 18 through 20. Note t~%:$@Program Counter is properly incremented to be$:~~~:n~ at the correct return address before it is stac~&i,;~~#~ration of the Branch to Subroutine and Jump to a~w~tine (extended) instruction is similar except for th@~~n~&>The BS R instruction requires less opcode than J $$&R{%Q~#es versus 3 bytes) and also executes one cy -

to return to the main program as indicated in Figure 21, The effect of executing the Software Interrupt, SWI, and the Wait for Interrupt, WAI, and their relationship to the hardware interrupts is shown in Figure 22. SW! causes the M PU contents to be stacked and then fetches the starting address of the interrupt routine from the memory locations that respond to the addresses FFFA and FFFB. Note that as in the case of the subroutine instructions, the Program Counter is incremented to point at the correct return address before being stacked. The Return from Interrupt instruction, RTI, (Figure 22) is used at the end of an interrupt routine to restore control to the main program. The SWI instruction is useful for inserting break points in the control program, that is, it can be used to stop operation and put the MPU registers in memory where they can be examined. The WAI instruction is used to decrease the time required to service a hardware interrupt; it stacks the MPU contents and then waits for the interrupt to occur, effectively removing the stacking time from a hardware interrupt sequence,

FIGURE 17 PROGRAM FLOW FOR JUMP AND BRANCH INSTRUCTIONS

[X+K ~(a) Jump m

[ ,,-,MOTOROLA Semiconductor17

(n+2)*Klxlq = Signed 7-bit value K

(b) Branch

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I

FIGURE 18 PROGRAM FLOW FOR BSR

SP~m2

m1 m

a(n +2)H

m+l

n

+ 1

]

tK

= Offset*

I

n+l

n+ 2 I

Next

Main

lstr.

I

n+2

* K = Signed

7-Bit

value

(a) Before

Execution

-.FIGURE 19 PROGRAM FLOW FOR JSR (~TENDEm,\ \ ,\~.,, %,

,~i)::~

FIGURE 20 PROGRAM FLOW FOR JSR (lNDWED)

r

ml sPm

m1 m 7E 7A B

(n+2)H

(n+2)L 7E 7A

m+l

m+l

PC_n

JSR=AD

JSR

= AD

n+l

K = Of fset Next a Main lstr.

+1 +2

K = Offset Next Main lstr.

1n+ 2 I SL=Sub,.

JS R

I

+2

g

Addr,

I

qK = 8-Bit

Usiged

Value

PC+

X.+K

1st S.br,

Instr.

1

r(a) Before Ex%utton s= (S formed from SH and SL) (a) Before Execution Contents of Index

1Register (b) Afrer Execuxion

1

(b) After

Execution

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FIGURE 21 PROGRAM FLOW FOR RTS

SP-m2

m1 m

HSH SL

m2

(n+3)H

m1

m+l

n n+l

n+l

= Subr.

Addr.

nt2

= Subr.

Addr.

n+2

nt3

I

BLast Subr. R TS

Instr.

FLOW FOR RTI

m7 CCR

m6

m5

ACCB

m4m3

ACCA

x~

m2

XLPCH4

m1

sp~

m 7E

PCL

Pc

+1 I

Next

Main

Istr.

I

sPc

aLast Inter. RTI (a) Before

J

I nstr.

I

Last Sbr.

Instr.

I

s

Execution

(b)

After

Execution

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Semiconductor19

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I

FIGURE ~

PROGRAM

FLOW FOR INTERRUPTS

.Software lnterruDt Main Program Wait For Interrupt Main Program Hardware Interrupt or NonMaskable Interrupt (NMI) Main Program

n:=.

:1=

n-

7Stack MPU Register Contents

Sp

+

m7 m6

m5 m4m3 m2

m1 m

WI

FFF8 FFF9

FFFC FFFD

FFFE FFFF

Interrupt Memorv Assignment FFF8 FFF9 FFFA FFFB I IRQ IRQ I

MsLS MS First Instr. Addr. Formed e BvFetching 2. Eytes From Per, Mere, Assign.

Swl Swl#

dQ

Set Interrupt Mask (CCR 4)

LS

Load Interrupt Vector Into Program Counter

fNOTE: MS= Most Significant Address Bvte; LS = Least S~nificant Address Byte; I

AI nterruot Proaram ,. > 1

1 lstlnterruutlnstr.

1Products Inc.

MOTOROLA@

Semiconductor20

FIGURE 24 CONDITIONALBMI BPL : : N=l N=@ ; ;

BRANCH INSTRUCTIONSBEQ BNE : : Z=l Z=4 ; ;

for testing are regarded

relative

magnitude

when

the values

being

tested

as unsigned

binary

numbers,

that is, the values

BVC BVS

: :

V=$ V=l

; ;

BCC BCS

: :

C=$ C=l

; ;

are in the range 00 (lowest) to FF (highest). BCC following a comparison (CMP) will cause a branch if the (unsigned) value in the accumulator is higher than or the same as the value of the operand. Conversely, BCS will cause a branch if; ;

BHI BLS

: :

c+

z=@

; ;

BLT BGE

: :

N@V=l N@ V=@

C+z=l

BLE BGT

: :

Z+(N@V)=l Z+(N@V)=@ ;

the accumulator value is lower than the operand. The fifth complementary pair, Branch On Higher (Qi&~~~,nd Branch On Lower or Same (BLS) are, in a se~~~/~@~plements to BCC and BCS. BHI tests for both C ~n@~~O; if used following a CMP, it will cause a branc~,?k~~pWalue in the accumulator is higher than the oper&~~%50nversely, BLS will cause a branch if the unsignq~~~a~value in the of accumulator is lower than or the saW:~$J&b operand. The remaining two pairs are u~~l ~ testing results of

The conditional

branch

instructions,

Figure 24, consists

seven pairs of complementary instructions. They are used to test the results of the preceding operation and either continue with the next instruction in sequence (test fails) or cause a branch to another point in the program (test succeeds). Four of the pairs are used for simple Z, V, and C: 1. Branch on Minus tests of status bits N,

operations in which the values at% re&~Yded as signed twos complement numbers. This $%&&}{rom the unsigned binary case in the following sen:~+~~.{~nsigned, the orientation is higher or lower; in si~w~,wos complement, the comparison is between @$~~g~&~ smaller values is between 1~,.,and + 127. where the range of

(B MI) and Branch

On Plus (BPL) tests

Branch On L@$~$anZero (BLT) and Branch On Greater Than Or Eq~#k.~~~~~G E) test the status bits for N @V= 1 and N e V{~$ *N cause. a branch following operations in which two positive values were added or in which the result was zero. The last pair, Branch On Less Than Or Equal Zero (BLE) and Branch On Greater Than Zero (BGT) test the status bits for Z@ (N+V) = 1 and Z@ (N +V) =0, respectively. The action of BLE is identical to that for BLT except that a branch will also occur if the result of the previous result was zero, Conversely, BGT is similar to BGE except that no branch will occur following a zero result.

the sign bit, N, to determine if the previous result was negative or positive, respectively. 2. Branch On Equal (BEQ) and Branch On Not Equal (BNE) are used to test the zero status whether or not the result of the previous to zero. These two instructions pare (CMP) instruction to test bit, Z, to determine operation was equal

are useful following a Comfor equality between an ac-

cumulator and the operand. They are also used following the Bit Test (BIT) to determine whether or not the same bit pos~~ >.t;.: ,Y). ~ ....,.,, tions are set in an accumulator and the operand. 3. Branch On Overflow Clear (BVC) and Branc@$~ns Overflow Set ( BVS) tests the state of the V bit to ~&~*e if the previous operation caused an arithmetic Q@r,@~ Set 4. Branch On Carry Clear (BCC) and Branch @~b$rY ( BCS) tests the state of the C bit to determ~~$$~~~previous operation caused a carry to occur. BCC ~~,~~~b are useful :? .,*.J?, -~>,

,,,1.,. .,.y ~

i$,:,i ;;* . .

. .?s$.~$$: ,, l~~k,J.F $?.,,The within during Condition ~~~~Register (CCR) the MPU~~~kl$*useful in controlling system d;%tlon. The bits are defined

CONDITION CODE REGISTER OPERATIONSis a 6-bit register to precede any SEI instruction with as NOP. These precautions are not processors indicating manufacture later. Systems which require an interrupt under program control should use a rather than CLI-SEI. an odd opcode necessary for in November such MC~ 1977 or

program flow in Figure 25. to the user with

The instr~~lia~% shown in Table 5 are available for dire~#~@@@ulation of the CCR. A C~,$A/ instruction sequence operated earl~:~~$~~ processors, was $~d (Least Significant

properly,

window to be opened CLI-NOP-SEI sequence

only if the preceding instruction Bit= 1), Similarly it was advisable

MOTOROLA@

Semiconductor21

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L

m E= BOOLEAN OPERATION HIq q q q q

CO ND.

COOE

REG.

.

NZVC

1 1 1 1 1 1 1 1

O+c

00m* R****

R

0+1

O+v l+C

.mm

R.

Ore**

s

1+1

l-v

q

S. **Oq

*Q.

s.

A+CCR

CCR+A

q

q \*

w

q

q

The M P&%~&$ates on 8-bit binary numbers via the..~t~~~?{~us. A given number (byte)

presented to it may rePresent

eithe&~{~~@:or an instruction to be executed, depending on w@.@/~,~s encountered in the control program. The Mm ha$~~tinique instructions, however, it recognizes and takes actloh on 197 of the 256 possibilities that can occur using an 8-bit word length. This larger number of instructions results from the fact that many of the executive instructions have more than one addressing mode. These addressing modes refer to the manner in which the program causes the MPU to obtain its instructions and data. The programmer must have a method for addressing the MPUS internal registers and all of the external memory locations. Selection of the desired addressing mode is made by the user as the source statements are written. Translation into

appropriate opcode then depends on the method used. If manual translation is used, the addressing mode is inherent in the opcode. For example, the immediate, Direct, Indexed, and Extended modes may all be used with the ADD instruction. The proper mode is determined by selecting (hexadecimal notation) 8B, 9B, AB, or BB, respectively. The source statement format includes adequate information for the selection if an assembler program is used to generate the opcode. For instance, the Immediate mode is selected by the Assembler whenever it encounters the # symbol in the operand field. Similarly, an X in the operand field causes the Indexed mode to be selected. Only the Relative mode applies to the branch instructions, therefore, the mnemonic instruction itself is enough to determine addressing mode. for the Assembler

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For the instructions that use both Direct and Extended modes, the Assembler selects the Direct mode if the operand vaiue is in the range O-255 and Extended otherwise. There are a number of instructions for which the Extended mode is valid but the Direct is not. For these instructions, the Assembler automatically selects the Extended mode even if the operand summarized Inherent is in the O-255 range. The addressing in Figure 26. Accumulator Addressing modes are

operands but the space between may be omitted. This is commonly

them and the operator done, resulting in apof

parent four character mnemonics for those instructions. The addition instruction, ADD, provides an example dual addressing Operator ADDA or ADDB in the operand field:

Comment Operand MEM12 ADD CONTENTS OF MEM12 TO j&~$:k . t;.., ~ ,,?~ ~,~~1~$~ ..:$ MEM12 ADD CONTENTS OF MEM12 %Q #&C~ i.;~:, ,,,~ ,;i,\.JtJ$+t$ also ad-

(Includes

Mode)

The successive fields in a statement are normally separated by one or more spaces. An exception to this rule occurs for instructions that use dual addressing in the operand field and for instructions that must distinguish retween the two accumulators. In these cases, A and B are

The example

used earlier for the test instru~&~~?ST,

applies to the accumulators and uses th,$~~~~ohulator dressing mode to designate which o$,,xv-accumulators \,*\ ~$.;: is being tested: .~#>, . any place in memory. Direct addressing, since only one address byte is required, provides a faster method of processing data and generates fewer bytes of control code. In most applications, the direct addressing range, memory locations O-255, are reserved for RAM. They are used for data buffering and temporary storage of system variables, the area in which faster addressing is of most value. Cycle-by-cycle Addressing. operation is shown in Table 9 for Extended

define$:$ym O

bols or numerical values. Except for the instru~ti~~WX, LDX, and LDS, the operand may be any valu~,i~:~e,;~nge to 255. Since

Compare Index Register (C&,~Q$.~~&d Index Register (LDX), and Load Stack Pointer (~$~;.$e~uire 16-bit

values, the immediate mode for these~%re~+ ~tistructions require two-byte operands. In th~:T~,Yate addressing

FIGURE ZMPu INDEX MPU

ACCUMULATOR

ADDRESSING

Pc

4INSTR GENERAL

PROGRAM MEMORY

PC = 5000

z@ RAM PROG RAM MEMORY INX

a

RAM F

mM Pu ACCB m RAM pROGRAM MEMORY PC = 5001 FLOW

B Pc INSTR

t

I

w GENERAL

aPROGRAM MEMORY INC B EXAMPLE

-.

FLOW

EXAMPLE

MOrOROLA@

Semiconductor24

Producfs Inc.

the unconditional jump (JMP), jump to subroutine (JSR), and return from subroutine (RTS) are used. In Figure 32, when the MPU encounters the opcode for BEQ (Branch if result of last instruction was zero), it tests the Zero bit in the Condition Code Register. If that bit is O, indicating a non-zero result, the MPU continues execution with the next instruction (in location WIO in Figure 32). If the previous result was zero, the branch condition is satisfied and the MPU adds the offset, 15 in this case, to PC+ 2 and branches to location W25 for the next instruction. The branch instructions allow the programmer to efficientIy direct the MPU to one point or another in the contro$.:~rogram depending on the outcome of test results. ~W~%e control program is normally in read-only memory #ti~$@not be changed, the relative address used in execu@~~@t&ranch instructions is a constant numerical valuq~~~~@-by-cycle operation is shown in Table 10 for relatig& a~Q@ssing. .}:\A ,# ~, .!-, ,, \ -!l!,., s. ,,i, Indexed Addressing Mode ~~~~d~xed addressing, the numerical address is variable qnd d~ends on the current (PC+2) 127SD S(PC+2)+127 contents of the Index Register@~~$ource statement such as )r .+:Y> ,..~\\..!\,. .-,~. ~, *.\:)fJ~ PC125,, , ~j$ ., . 2 3 4 1 2 3 4 1 4 2 3 4 o , 0 1 1 1 Q 0 1 1 0 0 1 1 0 1 1 Op Code Addrass + 1 Stack Pointer Stack Pointer 1

1 1 1 1

., ,{,: .-~ \\, .+ ~ .:! @* ~} \~\ \\t\*. .3..,,, ,. ~:,$.,j$:t $ ,... i:.* . Y ~~.$,, TSX -? -$:. ;*-{., .~ J .~.ikb ,.*T. ,?.. $~ ... J~ 4 :.$ .. . . k~:+.},t~$ *$,f..:% \**,, ,.~.~kq~,,. *Y., ..,, TX$~~~W y;.

PUL

Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1

Data (Note

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Data from Stack

Op Code Address Op Code Address+ Stack Pointer New Index Register Op Code Address OP Code Address+ Index Register New Stack Pointer OP Code Address OP Code Address+ Stack Pointer Stack Pointer Stack Pointer + 1 + 2

Data (Note Data (Note

RTS

1 2 5 3 4 5

1 1

Address of Next Order Byte) Address of Next Order Byte)

Instruction Instruction

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Semiconductor25

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TABLE

6

INHERENT

MOOE

CYCLE-BY-CYCLE

OPERATION R lx Line 1 1

(CONTINUED) Data Bus Op Code Op Code of Next Return Return Instruction

IWA I

Address Mode and Instructions

Cycles

CVcle # 1 2 3 4

VMA Line 1 1 1 1 1 1 1 1 1 1 1

Address Bus Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer 1 2 3 4 5 6 (Note 3)

9

5 6 7 8 9

o 0 0 0 0 01 1 1 1 1 1

Address (Low Order Byte)

Address (High Order Byte) Q,,x, t:f,s.,. * : ;:~;$$ Index Register (Low Order By&G].;;.; ~ ..*.,> !~{$ Index Register (High Ord:[O }$

RTI

1 2 3 4

Op Code Address Op Code Address+ Stack Pointer Stack Pointer + 1 Stack Pointer + 2 Stack Pointer + 3 Stack Pointer + 4 Stack Pointer + 5 ,>;: ,,,.?, , :*. \.*: , ,,,.y;,:,~, ,,. Stack Pointer + 7 ~;? ~...k. ,$ ~!>i, ,;i) .+ \ ..,, ... \ . . Op Code Addresq&+,t~S ,, Op Code Address ~{~ Stack Pointer + 6 Stack Poi$ter ,> ~,*r~+m ., Irrelevant ~ata ~@te 2) lrreleva$$k~~a (Note 1 ) ...*;,*,\, ..,.> ,~< ~.+,>+ CoRW~&~ti Cond. Code Register from S*.@ ,,s. of Accumulator B from Stack A from Stack

Contents

01 1 1 1 1 1

10

.\i?... ~ ..3:,*.,5 6 7 8 9 1,4 :#&q$ %ts .3**:

%ntents

of Accumulator

f$ac ~y~e~ Register from Stack (High Order Index Register from Stack ( Low Order Byte) Next Instruction Address from Stack (High Order Byte) 1 1 1 Next Instruction Address from Stack (Low Order Byte) .Op Code Irrelevant Return Return Data (Note 1)

10 SwI 12 3 4 5

1 11 1 1 1

o 0 o 0 0 0 01

Address (Low Order BVte) Address (High Order Byte) Register (Low Order Byte) (High Order Byte) A B

12

Sta*~hter {!,j$ :;t*,# Pointer J ,.::,, ,:~< /.. , .,:>, ,,{!~$$ ;$tack Pointer 8 ,:,,i:\$\ i?, %~i> $1 Stack Pointer $:TO ;6:r$o Stack Pointer

Index

Index Register Contents Contents Contents Irrelevant

of Accumulator of Accumulator

of Cond. Code Register Data (Note 1) (High Order (Low Order

Note 1. Note 2. Note 3.

Vector Address FFFA (Hex) 1 .>+):$W,$ 1 ,~ $.} :;,* :, ,$, .J$,* .,..> 12 . ? ; 1 Vector Address FFFB (Hex) 1 ....% :.$ , :.+;l+ ,.:y ? t$.~ ~ .QA:.$~ If device wh.?~~ls,@dressed during this cycle uses VMA, then the Data Bus will go to the Dependi,n,~ 4Q b~ capacitance, data from the previous cycle may be retained on the Data Data is,@W~@ bv the MPU, Whil@?~$~,~PU is waiting for the interrupt, Bus Available lo~@~ess BUS, RM, and Data Bus are all in the high will go high indicating

Address of Subroutine Byte) Address of Subroutine Byte) high impedance Bus.

three-state

condition.

the following

states of the control

lines: VMA

is

,.,.!;.,...:,+ ....,y. .:> ~~i>,, ,; ]*;i~.?J> .l,*! ,:,$.

impedanca State.

th$w.~ory location specified by the contents of the Index Re@ter (recall that the label X is reserved to designate the Index Register). Since there are instructions for manipulating X during program execution (LDX, INX, DEC, etc.), the indexed addressing mode provides a dynamic on the fly way to modify program activity. The operand field can also contain a numetical value that will be automatically added to X during execution. (Indexed) This foropcode in mat is illustrated in Figure 33. When the MPU encounters the LDAB

location 5006, it looks in the next memory location for the value to be added to X (5 in the example) and calculates the required address by adding 5 to the present Index Register value of 4~. In the operand format, the offset may be represented by a label or a numerical value in the range O-255 as in the example. In the earlier example, STAA X, the operand is equivalent to O, X, that is, the O may be omitted when the desired address is equal to X. Table 11 shows the cycle-by-cycle operation for the Indexed Mode of Addressing,

MOTOROLA@

Semiconductor26

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FIGURE =MPU

IMMEDIATE

ADDRESSINGMPU ACCA m RAM

MODE

FIGURE 30 MPU

DIRECT ADDRESSING

MODEMPU ACCA

m

%

RAM

m

m

RAM

G

RAM

ADOR

DATA

* PROGRAM MEMORY PROGRAM MEMORY

I

II

PROGRAM MEMORY

Pc

INSTR DATA

GENERAL

FLOW

C=oow C*EXAMPLEEXAMPLE

1ADC ADD AND BIT CMP CPX LDS LDX

Address Mode and 1 nstructions

Cycles

Cycle #

VMA Line

Addrass Bus

,1?,

?!i; .\.!),,

Data Bus

.f*,.., EOR LDA ORA SBC SUB 1 2 2 1 1 Op Code Address Op Code Address+ ~\ .es$% 1 ~+?.,.. ..~~ . .., Op Code Address Op Code Address+ Address of Operand 1 1 1 1 1 1 1 1 1 1 1 o 1 1 1 1 o + 1 0 Data BUS WIII go to ?ne nigh Op Code Address of Operand Operand Op Code Address of Operand Operand Operand Op Code Destination irrelevant Address Data (Note 1} Data (High Order Byte) Data (Low Order Byte) Data

EOR LDA ORA SBC SUB

,, Op Code Address Op Code Address + 1 Address of Operand 4 1 1 1 Operand Address + 1

Op Code Address Op Code Address + 1

3 4 STS STX 5 1 2 3 4 5

0 1 1 1 0 1 1

Destination Destination

Address Address

Data from Accumulator Op Code Address of Operand Irrelevant Data (Note 1)

Op Code Address OP Code Address+ Address of Operand Address of Operand Address of Operand

Register Oata (High Order Byte) Register Data (Low Ordar BVte) ,.,impeaance tnree-s~aIe

Note 1. If device which is address during this cvcle uses VMA, Depending on bus capacitance,

then the

,.. . conolrlon.

data from the previous cycle may be retained

on the Data Bus.

B

MOTOROLA

Semiconductor27

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I

FIGURE 31 EXTENDED ADDRESSINGMPU MPu

MODE

R RAM RAM I

ADOR

DATA

ADDR

= 300

PROGRAM

Pc

w M%MEMORYINSTR ADDR ADDR AODR > 256

PROGRAM MEMORY

I

PC = 5006

LDA 300

B

5009

@EXAMPLE

GENERAL

FLOW

TABLE 9 EXTENDED MODE CYCLE-BY-CYCLEAddress Mode and Instructions STS STX Cycle = VMA Line

Cycles

12 6 3 4 5 6

OP Code Address Address Irrelevant Operand Operand Op Code Address Address of Subroutine of Subroutine of Next Address Address Oata Data (High Order Byte) BVte) of Operand of Operand Data Data Data (Note (High (Low (High (Low 1) Order Order Byte) Byte) Order Order Byte) Byte)

JSR

1 2 3 4 9 5 6 7 8 9

( LOW Order

3

Op Code OP Code OP Code

Address Address Address

+ 1 + 2

L0 0Return Return

1

3P Code

Instruction (Low (High (Note (Note Order Order 1) 1) (Low Order Bvte) Bvte) BVte)

---

1 1 1 11

Irrelevant

Irrelevant

Address Op Code Jump

of Subroutine

II

Address Address

(High

Order

Bvte) Bvte)

Jump

( LOW Order

wOP Code Address Address + 2 of Operand Address OP Code Op Code Op Code Operand Operand ASL ASR CLR COM DEC INC LSR NEG ROL ROR TST Op Op 6 Code Code of Operand Address Address Address Destination Destination Address Address Address of Operand of Operand of Operand + 1 + 2 + 1 + 2 Address Address + 1 Op Code Address Address Address ~te 1. It device Depending Note 2. For TST, which IS addressed during data data this from does cvcle the not uses VMA, previous change, then cycle the mav Data Bus will on bus capacitance, VMA = O and Operand ba retatned on the

1

Op Code Address Address Operand Op Code of Operand of Operand Data (High (Low Order Order BVte) Bvte)

I

11 1 1 1 1 1

Address Address Operand Operand Op Code Destination Destination Irrelevant Data from

of Operand of Operand Data Data (High (LOW

(High (LOW Order Order

Order Order BVte) Bvte)

BVte) BVte)

Address Address Oata (Note

(High ( Low 1)

Order Order

Bvte) Bvte)

o1 II

Accumulator

OP Code Address Address Current Irrelevant New of Operand of Operand Operand Data (High (Low Data (Note Data 1) (Note 2) Order Order Bvte) Bvte)

I

11 1

o

Operand

..go to the Data high Bus. impedance three-state condition,

MOTOROLA@

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FIGURE 32 RELATIVE ADDRESSINGMPU

RAM 1

PrOaram MeGory

i

Pc

Instr. Offset 5008

(PC + 2)

Next

Instr. Pc 5010

Pc

a sMODE MPU~AMProgram Memorv

BEQ 15

Next Instr.

t

MPu

ADDR

= INOX

+ OFFSET

..3 1,

.

... ..,.

-~

OFFSET? Address Mod.@x,.,.j:, and I nstruc,$~~ r*f Cycles : .>,.${,, {t i.>~:+,, ,.

1

\*>: .+

BCC BH#~B~b BCS ,@&~@>>@~ L BE Q $~@\$~.,, ,,+y:>, B:# ,$. \~b:.. , ,>{: Op Code Address~~%?.?#~ ~ ~;,\ ~., Index Register , .: Index ReQ&er Pyus Offset ,...,,,,, Index ~{gf$~~{ Plus Offset I nde~l.%~,~ter PI us Offset .- .~$+t t#d,* R*gister Plus Offset .;$:,>~:,! . ?n. S,pt:+f yt{\, ? &p Code Address Op Code Address+ Index Register Index Register Plus Offset Index Register Plus Offset Index Register Plus Offset Index Resister Plus Offset + 1 Op Code Address Op Code Address+ Index Register Stack Pointer Stack Pointer 1 1 (w/o Carry) 1 (w/o Carry)

?

3 4 5 6 7

Irrelevant Current Irrelevant

Data (Note Data

New Operand

(Note 2)

;TS 3TX

T 2 3$$ q; ;@p 6 7 T 2 3 4 5 6 7 8

1 1 11

Op Code Offset Irrelevant Irrelevant Irrelevant Operand Operand Op Code Offset Irrelevant Return Return Data (Note 1 ) Data (Note Data (Note Data (Note 1) 1) 1)

1 0 0 1 11

Data ( High Order Byte) Data ( Low Order Byte)

Stack Pointer 2 Index Register Index Register Plus Offset (w/o Carry)

0 0 1 1 1

Address ( Low Order Byte) Address (High Order Byte) Data (Note Data (Note Oata (Note 1) 1) 1) condition.

Irrelevant Irrelevant Irrelevant

Note 1. Note 2.

If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance Oepending on bus capacitance, data from the previous cycle may be retained on the Oata Bus. For TST, VMA = O and Operand data does not change.

three-state

@

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PACKAGE

DIMENSIONS

CASE 711-W (PLASTIC)

Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume any Iiabilityarising out of the application or usa of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

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M070ROLA@*,1,,,-,PR,m,, ,. ,.

Semiconductor3501 ED BLUESTEIN BLVD1.,,,,0 LI,,m

Products Inc.AUSTIN, TEXAS 78721q

A SUBSIDIARY OF MOTOROLA lNC,,,,7,12

,-84

.20206

1s,000

-.

.

.

-.

.

-

.. .. ..