2/19/2003 1

MOSFET ScalingDevice scaling: Simplified design goals/guidelines for shrinking device dimensions to achieve density and performance gains, and power reduction in VLSI.Issues: Short-channel effect, Power density, Switching delay, Reliability.

The principle of constant-field scaling lies in scaling the device voltages and the device dimensions (both horizontal and vertical) by the same factor, κ (> 1), such that the electric field remains unchanged.

2/19/2003 2

Rules of Constant Field Scaling

1/κ1/κ2

1/κ3

κ2

1

Circuit delay time (τ ∼ CV/I)Power dissipation per circuit (P ∼ VI)Power-delay product per circuit (P×τ)Circuit density (∝1/A)Power density (P/A)

Derived scalingbehavior of circuitparameters

11

1/κ1/κ1

1/κ1

Electric field (E)Carrier velocity (v)Depletion layer width (Wd)Capacitance (C = εA/t)Inversion layer charge density (Qi)Current, drift (I)Channel resistance (Rch)

Derived scalingbehavior of deviceparameters

1/κκ

1/κ

Device dimensions (tox, L, W, xj)Doping concentration (Na, Nd)Voltage (V)

Scaling

assumptions

Multiplicative Factor (κ > 1)MOSFET Device and Circuit Parameters

2/19/2003 3

Scaling of Depletion WidthW V

qNDsi bi dd

a

=+2ε ψ( )

WqNS

si bi

a

=2ε ψ

Maximum drain depletion width:

For Na → κNa and Vdd → Vdd/κ,WD → WD/κ if Vdd >> ψbi.

However, the source depletion width,

is indep. of Vdd and only scales as WS → WS/ .

Furthermore, the maximum gate depletion width,

scales even less than 1/ .

κ

W kT N nq Ndm

si a i

a

02

4=

ε ln( / )

κ

2/19/2003 4

Generalized ScalingAllows electric field to scale up by α (E → αE) while the device dimensions scale down by κ,i.e., voltage scales by α/κ (V → (α/κ)V).

More flexible than constant-field scaling,but has reliability and power concerns.

To keep Poisson’s equation invariant under the transformation, (x,y) → (x,y)/κ and ψ → ψ/(κ/α) within the depletion region:

Na should be scaled to (ακ)Na.

∂ αψ κ∂ κ

∂ αψ κ∂ κ ε

2

2

2

2( / )( / )

( / )( / )x y

qNa

si+ =

2/19/2003 5

Constant Voltage ScalingSpecial case of α=κ in generalized scaling:

The only mathematically correct scaling as far as 2D Poissoneq. and boundary conditions are concerned.

Na → κ2Na,therefore, the maximum depletion width,scales down by κ.

Both the short-channel Vt roll-off,

and the threshold voltage,

remain unchanged for constant-voltage scaling.

However, it is physically incorrect sinceE → κE (reliability) and P/A → κ2-3P/A (power).

W kT N nq Ndm

si a i

a

02

4=

ε ln( / )

∆Vt

WV et

ox

dmbi bi ds

LW tdm ox= +

−+24 2

3ψ ψπ

( )/

V VqN V

Ct fb Bsi a B bs

ox= + +

+2

2 2ψ

ε ψ( )

2/19/2003 6

Scaling in PracticeCMOS VLSI technology generations

1.4 MV/cm2.0 MV/cm2.8 MV/cm2.8 MV/cm3.3 MV/cm3.6 MV/cm

350 Å250 Å180 Å120 Å100 Å70 Å

5 V5 V5 V

3.3 V3.3 V2.5 V

2 µm1.2 µm0.8 µm0.5 µm

0.35 µm0.25 µm

Oxide FieldGate OxidePower Supply

Feature Size

CMOS technology has gone through mixed steps of constant voltage and constant field scaling. As a result, field and power density have gone up, but performance gains have been maintained and power per circuit has come down.Fortunately, by physics or by learning, we managed to cope with reliability requirements at higher fields.

2/19/2003 7

Non-Scaling Factors

0.1 0.2 0.3 0.5 1 2 330

50

100

200

300

500

1000

(MV/cm)

(cm

/V-s

)

Electron

Hole

0.1 µm CMOS1 µm CMOS

Eeff

2µ ef

fEeff

-0.3

Eeff-0.3

Eeff-2

Eeff-1

t =35 Åt =70 Åoxox

Primary nonscaling factors:

Built-in potential ψbi (Si bandgap)

Subthreshold current (thermal energy kT/q)

Secondary nonscalingfactors (due to higher E):

Velocity saturation

Decreased mobility at higher fields

Oxide reliability (toxscales less, Wdm more)

2/19/2003 8

Other Non-Scaling FactorsSource and drain series resistance

• Doping level limited by solid solubility and is not scalable.• Doping gradient or junction abruptness limited by annealing process.

Polysilicon gate depletion

Inversion layer depth/thickness

Various process tolerances• Gate length. • Gate oxide thickness. • Dopant number fluctuations.

2/19/2003 9

MOSFET Threshold Voltage V V V V Q

Ct fb B ox fb Bd

ox

= + + = + +2 2ψ ψ

( ) I CWL

mkTq

e eds eff oxq V V mkT qV kTg t ds= −

−− −µ ( ) ( )/ /1 1

2

0 0.2 0.4 0.6 0.8 1 1.21E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0

0.2

0.4

0.6

0.8

1

Gate Voltage (V)

Sour

ce-D

rain

Cur

rent

(A/µ

m)

Sour

ce-D

rain

Cur

rent

(mA/

µm)

Slope~q/kT

Vt

Linear scale

Log scale

MOSFET current in linear and log scales:

Subthreshold:

2/19/2003 10

CMOS Circuit Delay

0 0.1 0.2 0.3 0.4 0.5 0.6 0.70

2

4

6

8

Nor

mal

ized

CM

OS

Del

ay

V /Vt dd

~ V /Vt dd0.71

Delay ~ CV/I Desirable to keep Vt/Vdd < 0.3.

100 200 300 400 500

0

1.25

2.5

Time (ps)

Nod

e vo

ltage

(V)

V1 V2 V3 V4

τn τp

2τ

1 2 3 4V1 V2 V3 V4

CL CL CL CL

2/19/2003 11

Choice of Gate Work Function V V V V Q

Ct fb B ox fb Bd

ox

= + + = + +2 2ψ ψ

oxide

p-type siliconn+ poly

q msφ

Vg V fb ms= =φ

n+ poly

oxide

p-type silicon

Vg = 0

Ec

Ev

Ei

Ec

Ev

Ei

ψB

Ef

Ef

Ef Ef

2ψB ~ 1 V, need Vfb ~ -1 V to obtain low Vt;i.e., n+ poly gate on nMOSFET and vice versa.

−−=

−−=

i

a

Bg

ms

nN

qkT

qE

ln56.0

2 ψφ

2/19/2003 12

Threshold Voltage Adjustment

V VqN

CV t

Wt fb Bsi a B

oxfb

ox

dmB= + + = + +2

41 6 2ψ

ε ψψ( )

WqNdm

si B

a

0 4=

ε ψ

In a uniformly doped MOSFET, the maximum gate depletion width (long-channel),

and the threshold voltage,

are coupled through the parameter Na, and therefore cannot be varied independently (for given Vfb, tox).

To adjust threshold voltage, it is necessary to employ nonuniform channel doping.

2/19/2003 13

Nonuniform Channel Doping

si

xdxd

dxd

ερψ )(

2

2

−=−=E

∫= dW

xsi

dxxNqx )()( ε

E

For a nonuniform p-type doping profile N(x), the electric field is obtained by integrating Poisson’s equation once (neglecting mobile carriers):

1-D Poisson’s eq.:

where Wd is the depletion layer width.

ψεs

six

WWq N x dx dxdd= ′ ′∫∫ ( )0

ψεs

si

Wq xN x dxd= ∫ ( )0

Integrating again,

Integration by parts,

Note that the maximum depletion layer width Wdm0 is determined by the

condition ψs = 2ψB when Wd = Wdm0.

The threshold voltage of a nonuniformly doped MOSFET is then determined by both the integral (depletion charge density) and the first moment of N(x) within (0, Wdm

0).

2/19/2003 14

High-Low Doping Profile

xs Wd

Ns

Na

N(x)

Dop

ing

conc

entra

tion

Depth0 x

V VC

qNq N N x q N N x

Ct fb Box

si a Bs a s

si

s a s

ox= + + −

−

+

−2

12 2

2

2

ψ ε ψε

( ) ( )

The maximum depletion width at threshold is:

The body-effect factor takes the same form as before:

m WC

CC

tW

si dm

ox

dm

ox

ox

dm

= + = + = +1 1 1 30

0ε /

WqN

q N N xdm

si

aB

s a s

si

022 2

2= −

−

ε ψε

( )

The threshold voltage is, again, Vfb+2ψΒ+Vox(=Qd/Cox), i.e.,

2/19/2003 15

Implanted Gaussian Profile

V V qN WC

qDCt fb B

a dm

ox

I

ox

= + + +20

ψ

Let (Ns − Na)xs = DI and xs/2 = xc,

Then

and

For shallow surface implants, xc = 0, there is no change in the depletion width. The Vt shift is simply given by qDI/Cox like a sheet of charge at the silicon-oxide interface.

WqN

qD xdm

si

aB

I c

si

0 2 2= −

ε ψε

2/19/2003 16

Low-High Doping ProfileChannelDoping

0 x

Ns

x s Wdm

Na

0

WqN

xdmsi B

as

0 24= +

ε ψ

V VqNC qN

xqN x

Ct fb Ba

ox

si B

as

a s

ox= + + + −2

4 2ψε ψ

Take Ns = 0, then

In contrary to high-low doping, low-high (retrograde) doping results in a lower Vt than uniform doping for a given Wdm.

2/19/2003 17

Extreme Retrograde Profile

i-Layer RegionPoly

p-Substrate

n+ p+

Ef

x Ws dm= ≈ xj

QM

Qi

Qd

V Vx

Ct fb Bsi s

oxB= + +2 2ψ

εψ

/

V V tWt fb

ox

dmB= + +

1 3 2ψ

For xs >> (4εsiψB/qNa′)1/2,

i.e.,

The depletion depth is the sameas the undoped layer thickness.All the depletion charge islocated at the far edge of thedepletion region.Magnitude of the depletion charge is one half of the uniformly doped value.

2/19/2003 18

Channel Profile Evolution> 1 µm CMOS:

HIGH-LOW

0.5 µm CMOS:

UNIFORM

0.2 µm CMOS:

RETROGRADE

0.1 µm CMOS:

HALO

0.05 µm CMOS:

SUPER-HALO

Depth

Dop

ing

Depth

Dop

ing

Depth

Dop

ing

1E16 cm -3

5E16 cm -3

3E17 cm -3

1E18 cm -3

5E18 cm -3

2/19/2003 19

Channel Profile Trends

V VqN

CV t

Wt fb Bsi a B

oxfb

ox

dmB= + + = + +2

41 6 2ψ

ε ψψ( )

For uniform channel doping,

Vt is increasing slightly toward shorter channel lengths and higher Na. 2-D quantum effect further raises Vt as the surface field increases and the electrons experience more confinement.

On the other hand, device design calls for lower Vdd and Vtas the CMOS dimensions are scaled down.

1-D vertically nonuniform doping only addresses Vt of long channel devices. Laterally nonuniform doping helps control Vt of short channel devices.

2/19/2003 20

Laterally Nonuniform Doping (Halo)

Gate

DrainLo

Hi Hi

Depletionboundary

Source

Halo implants are made after gate patterning, therefore self-aligned to the gate like source-drain.Halo doped regions are farther apart for longer gates, andcloser together for shorter gates.As a result, the “effective doping” becomes higher towardshorter devices, thus counteracting short channel effects.

2/19/2003 21

CMOS Inverter

p-substraten+

n+

p+

p+

n-well

In OutOutInI

C+

C−

Vdd VddVdd

Vdd

IN

IP

Since only one of the transistors is on in the steady state, there is no static current or static power dissipation in a CMOS inverter.

2/19/2003 22

CMOS Inverter Transfer Curve

Vout

Vin

Vdd

Vdd

A

B

C

D

00B A

VddVout

IP IN Vin4

Vin3

Vin2

Vin1

Vin0

Vin1

Vin2

Vin3 CD

Qualitatively, the sharpness of the high-to-low transition of the Vout-Vin curve is a measure of how well the circuit performs digital operations.

2/19/2003 23

Switching Waveform for a Step Input

(a)Pull down

Vdd

tVin

Vout

Slope= INsat C/Vdd / 2

τn

(b)Pull up

Vdd

t

Vin

Vout

Slope= IPsat C/Vdd / 2

τ p

For nMOSFET pull down transition,

The pull down delay is

( ) ( )C C dVdt

C dVdt

I V Vout outN in dd− ++ = = − =

τ ndd

Nsat

dd

n nsat

CVI

CVW I

= =2 2

Similarly, the pMOSFET pull up delay is

τ pdd

Psat

dd

p psat

CVI

CVW I

= =2 2

For symmetric transfer curve and best noise margin, the width ratio should be Wp/Wn = Insat/Ipsat ≈ 2.

2/19/2003 24

Active Power DissipationConsider a capacitor C between the output node and the ground. Initially, the output node is at the ground potential and there is no charge on C.

During a pull up transition, current flows from the power supply through the turned-on pMOSFET and raises the output node to Vdd. The capacitor is now charged to Q = CVdd.

The energy flow out of the power supply is QVdd = CVdd2, in which half or

CVdd2/2 is energy stored in C; the other half is dissipated irreversibly as Joule

heat.

Now the node is pulled down and the capacitor discharged by current through the turned-on nMOSFET to ground. The stored CVdd

2/2 energy is now dissipated in the circuit.

⇒ A total energy of CVdd2 is dissipated irreversibly in an up-down switching

cycle. If the clock frequency is f, and on the average a total capacitance Cundergoes an up-down cycle in a clock period T, then the CMOS power dissipation is

P CVT

CV fdddd= =

22

(Note that the cross-over current is neglected.)

2/19/2003 25

CMOS NAND and NOR GatesNOR: Output is low unless all inputs are low.

Vout

Vdd

Vin1

Vin2

Vdd

Vout

Vin2

in1V

Like the inverter, there is no static power dissipation.

NAND: Output is high unless all inputs are high.

2/19/2003 26

MOSFET Layout

W

L

cb a

d

Contact hole

Active region

Polysilicon gate

Silicon substrate

Fieldoxide

Fieldoxide

n p+ +or

d = a + b + c are layoutgroundrules dictated by lithography capability.

L is limited by either lithography or device design.

2/19/2003 27

CMOS Inverter Layout

Folded (orinterdigitated) layout in (b) reduces the junction capacitance contribution by a factor of 2.

Output

Input

Gr. Vdd

N-well/p+ p+n+

N-well/p+

Output

Gr.

Gr.

Input

Vdd

Vdd

n+ p+

(a)

(b)

Active regionPolysilicon gateContact holeMetal

2/19/2003 28

Two-way NAND Layout

P2P1

N1

N2

Vdd

Vout

Vx

Vin1

Vin2

N-well/p+ p+

Vdd

VddGr.

Output

n+

Input-1

Input-2

Vx

Active regionPolysilicon gateContact holeMetal

2/19/2003 29

Source-Drain Series Resistance

Rac is the accumulation-layer resistance which is modulated by gate voltage and should be a part of the channel length.

Rsp is the spreading resistance associated with current injection from the surface channel into the bulk.

Rco is the contact resistance associated with current flowing from Si into metal. WSR shsh / ρ=

2/19/2003 30

Self-Aligned Silicide Technology

Rsh becomes negligible.Rco between silicide and metal is negligible.Long contact regime between silicide and Si.

Sheet resistance:Metal (1 µm) — 0.05 Ω/sqN+, p+ diffusion (0.1 µm) — 50-500 Ω/sqSilicide (0.03 µm) – 5-10 Ω/sq

2/19/2003 31

MOSFET Capacitances

Cg

CJ

Cov

Cd

Cov

CJ

Gate

DrainSource

Intrinsic capacitance:

Parasitic capacitances:• Depletion capacitance• Overlap capacitance• Junction capacitance

C WLCg ox= C WLCg ox=23

dmsd WWLC / ε=

)(2/

jbi

asidjsij V

qNWdWWdC+

==ψεε

2/19/2003 32

Overlap Capacitance

Gate

DrainSourcexj

Cdo

Cof

Cif

tox

tgate

lov

Cif

Cdo

Cof

C Wl C Wltdo ov ox

ox ov

ox

= =ε C W t

tofox gate

ox

= +

2 1επ

ln C W xtif

si j

ox

= +

2 12

επ

ln

Direct overlap Outer fringe Inner fringe

For typical values of tgate/tox ≈ 40 and xj/tox ≈ 20,Cof/W ≈ 2.3εox ≈ 0.08 fF/µm, Cif/W ≈ 1.5εsi ≈ 0.16 fF/µm (off state)

For reliability, lov ≈ (2-3)tox, Cov/W ≈ 10εox ≈ 0.3 fF/µm

C V C C C W ltov g do of if ox

ov

ox

( )= = + + ≈ +

0 7ε

2/19/2003 33

Gate Resistance

Gate L

x=0 x=W

Cdx

I(x)

RdxV(x)

The resistance per unit length iswhere ρg is the silicide sheet resistivity (Ω/ ).

The capacitance per unit length is approximately

Diffusion eq.:

The effective RC delay is RCW2/4 or For ρg = 10 Ω/ , tox = 50 Å; τg < 1 ps if W < 7.6 µm.

Multiple-finger gate layouts with interdigitated source and drain regions should be used.

LR g / ρ=

C C L Ltoxox

ox

= =ε

∂∂

∂∂

2

2Vx

RC Vt

=

τρ

gg oxC W

=2

4

2/19/2003 34

Interconnect Scaling

Ground plane

A

Lw

tins

Lw/κ

tins/κ A/κ2

1

κ2

1

κ

Wire capacitance per unit length (Cw)

Wire resistance per unit length (Rw)

Wire RC-delay (τw)

Wire current density (I/Wwtw)

Derived wirescaling behavior

1/κ

1

1

Interconnect dimensions (tw, Lw, Ww, tins, Wsp)

Resistivity of conductor (ρw)

Insulator permittivity (εins)

Scaling assumptions

Scaling factor (κ > 1)

Interconnect parameters

2/19/2003 35

Interconnect ResistanceInterconnect RC delay is described by the same distributed RC-ckt & diffusion eq. as gate resistance.

where Rw = ρw/Wwtw and Cw ≈ 2πεins (2 pF/cm).

For aluminum and oxide technology,

Local wire RC delay < 1 ps as long as Lw2/Wwtw < 3×105 and

can be scaled down without problem.

For global wires, however, Lw does not scale down, e.g., Lw

2/Wwtw ∼ 108-109, and τw ∼ 1 ns. Therefore, Wwtw cannot scale down ⇒ Use large wires for global wiring.

τ w w w wR C L=12

2

τ πε ρw ins ww

w w

LW t

≈2

sτ ww

w w

LW t

≈ × −( )3 10 182

2/19/2003 36

Global Interconnects

Chip

0.001 0.01 0.1 1 101E-13

1E-12

1E-11

1E-10

1E-9

1E-8

Wire length (cm)

Inte

rcon

nect

del

ay (s

)

Limited by speedof EM-wave

Wire size:0.1 µm0.3 µm1.0 µm

Must also scale up insulator spacing otherwise Cw↑

RC Delay ~ l /A Time of Flight ~ l /c2

Ultimately, signal propagation is limited by the speed of electromagnetic wave, c/(εins/ε0)1/2, (70 ps/cm for oxide), instead of by RC delay.

2/19/2003 37

Propagation Delay

1 2 3 4V1 V2 V3 V4

CL CL CL CL

100 200 300 400 500

0

1.25

2.5

Time (ps)

Nod

e vo

ltage

(V)

V1 V2 V3 V4

τn τp

2τ

For a chain of CMOS inverters or NAND/NOR gates,

CMOS propagation delay equals τ = (τn + τp)/2, where τn is the pull-down delay and τpis the pull-up delay.

2/19/2003 38

Bias Point Trajectories

0 0.5 1 1.5 2 2.5

-4

-2

0

2

4

Output node voltage (V)

Tran

sist

or c

urre

nt (m

A)

Vin = 0

0.5

1.0

1.5

Vin = 1.0

1.5

2.0

2.5

IP

−IN

Pull down Pull up

Equal time interval (10 ps) between dots.

0 0.5 1 1.5 2 2.5

-4

-2

0

2

4

Output node voltage (V)

Tran

sist

or c

urre

nt (m

A)

Vin = 0

0.5

1.0

1.5

Vin = 1.0

1.5

2.0

2.5

IP

−IN

2/19/2003 39

Delay Equation

0 0.05 0.1 0.15 0.2 0.250

50

100

150

200

Load capacitance (pF)

Inve

rter d

elay

(ps)

Fan-out =Wn=10 µmWp=25 µm

Slope=Rsw

τint=Rsw(Cin+Cout)

3

2

1

The delay equation not only allows the delay to be calculated for any fan-out and loading conditions, but also decouples the two important factors that govern CMOS performance: current and capacitance.

Delay equation:

Rsw: Switching Resistance (≡dτ/dCL)Cin: Input Capacitance (to next stage)Cout: Output CapacitanceFO: Number of Fan-Out’s

FOτ = × + × +R C C Csw out in L( )

2/19/2003 40

Input and Output Capacitance

p-substraten+

n+

p+

p+

n-well

In OutOutInI

C+

C−

Vdd VddVdd

Vdd

IN

IP

Cin: For switching n/p gates of the receiving stage.Cout: For switching n/p drains of the sending stage.

Cg

CJ

Cov

Cd

Cov

CJ

Gate

DrainSource

2/19/2003 41

Switching Resistance

Switching resistance Rsw is a direct indicator of the current drive capability of the logic gate.

If we define Rswn ≡ dτn/dCL and Rswp ≡ dτp/dCL, then Rsw = (Rswn + Rswp)/2 and we can write

where In, Ip are maximum on currents at Vds = Vg= Vdd, and kn, kp are numerical fitting parameters.For step inputs with zero rise time, kn = kp = 0.5.For propagation delays, kn, kp ~ 0.75.

R k VW Iswn n

dd

n n

= R k VW Iswp p

dd

p p

=

2/19/2003 42

Delay Sensitivity to n/p Width Ratio

0 0.5 1 1.5 2 2.5 3 3.50

20

40

60

80

100

Device width ratio,

Intri

nsic

del

ay (p

s)

Wp/Wn

τ

τn

τp

Table 5.2 value

Note that for equal pull-up and pull-down delays (τn =τp) and therefore symmetric transfer curve and best noise margin, Wp/Wn = 2.5.

Minimum CMOS delay, (τn+ τp)/2, however, occurs atWp/Wn = 1.5.

2/19/2003 43

Buffer Stage for Heavy LoadsFor a given Wp/Wn ratio, if both widths are increased by a factor of k, then Rsw→Rsw/k, Cin→kCin, Cout→kCout. No change in intrinsic delay,

But driving capability is improved.

Consider a CMOS inverter driving a large capacitive load:

If CL >> Cin, Cout, the delay can be improved by inserting a buffer stage k (> 1) times wider than the original inverter. The two-stage delay is

which has a minimum

when k = (CL/Cin)1/2.

Multiple-stage buffers can be used for very heavy loads (Problem 5.8-10).

τ int ( )= × +R C Csw in out

τ = +R C Csw out L( )

τ b sw out insw

out L sw out inLR C kC R

kkC C R C kC C

k= + + + = + +( ) ( ) ( )2

τ b sw out in LR C C Cmin ( )= +2 2

2/19/2003 44

Delay Sensitivity to Channel Length

0.10.15

0.20.25

0.30.4

0.53,000

4,000

5,0006,0007,0008,0009,000

10,000

15,000

20,000

Channel length (µm)

Switc

hing

resi

stan

ce (

)

WnRswn

WpRswpΩ-µ

m

0.1 0.15 0.2 0.25 0.3 0.4 0.51

1.5

2

3

Channel length (µm)

Inpu

t, ou

tput

cap

acita

nce

(fF/µ

m)

Cin/(Wn+Wp)

Cout/(Wn+Wp)

0.1 0.15 0.2 0.25 0.3 0.4 0.520

30

40

50

60708090

100

Channel length (µm)

Intri

nsic

del

ay (p

s)

2/19/2003 45

Delay Sensitivity to Oxide Thickness

4 5 6 7 8 9 10 113,000

4,000

5,000

6,000

7,000

8,000

9,000

10,000

15,000

0.7

1

2

3

Gate oxide thickness (nm)

Switc

hing

resi

stan

ce (

)

Inpu

t, ou

tput

cap

acita

nce

(fF/

µm)

Cin/(Wn+Wp)

Cout/(Wn+Wp)

WnRswn

WpRswp

Ω- µ

m

4 5 6 7 8 9 10 1130

50

70

100

150

Gate oxide thickness (nm)

Inve

rter d

elay

(ps)

Wn=10 µmWp=25 µm

CL=0

CL=0.1 pF

2/19/2003 46

Delay Sensitivity to Vdd and Vt

0 0.1 0.2 0.3 0.4 0.5 0.6 0.70

2

4

6

8

Nor

mal

ized

CM

OS

Del

ay

V /Vt dd

~ V /Vt dd0.71

Desirable to keep Vt/Vdd < 0.3.

Delay sensitivity to Vddand Vt is mainly in the Rsw factor.

Note that the dependence is stronger thanIon ∝ 1 − Vt /Vdd, due to the finite input rise time.

2/19/2003 47

CMOS Performance and Power

Higheractive power

Higherstandbypower Increasing

performance

Pow

er s

uppl

y vo

ltage

Threshold voltage

V /Vt dd~0.7

~CV fdd2

qV /mkT)t~exp(

2/19/2003 48

CMOS Power vs. Delay Trade-off

Significant power savings by trading off performance and operating at low Vdd (same Vt).

10 30 100 300

0.1

1

10

100

Delay/stage (ps)

Pow

er/s

tage

(uW

)

0.7 V

0.5 V0.4 V

1.0 V

1.5 V

V = 2.0 Vdd 0.1 µm CMOS101-stage inverter

P ~ f

P ~ f3

W = 3 µmW = 4 µm

np

2/19/2003 49

Overlap Capacitance and Miller EffectConsider driving 3 capacitors with respect to different voltages:

i

Vdd

V

V1

V2

V3

C1

C2

C3

i C d V Vdt

C d V Vdt

C d V Vdt

=−

+−

+−

11

22

33( ) ( ) ( )

i C dVdt

C dVdt

C dVdt

C dVdt

= + − +1 2 22

3

If dV2/dt = −dV/dt, then

⇒ C2 appears doubled to the driving source.

i C C C dVdt

= + +( )1 2 32

2/19/2003 50

Components of Cin and Cout

51%---Junction capacitance (non-folded)

35%43%Overlap capacitance

14%57%Intrinsic gate oxide capacitance (n & p)

Output capacitance

Input capacitance

Cg

CJ

Cov

Cd

Cov

CJ

Gate

DrainSource

2/19/2003 51

Two Input (Two-way) NAND

100 200 300 400 500

0

1.25

2.5

Time (ps)

Nod

e vo

ltage

(V)

2-way NAND (Top Switching)

Vin

Vout

Vx

2-way NAND (Bottom Switching)

100 200 300 400 500

0

1.25

2.5

Time (ps)

Nod

e vo

ltage

(V)

Vin

Vout

Vx

P2P1

N1

N2

Vdd

Vout

Vx

Vin1

Vin2

Top (N1) switching: Effective gate drive is Vin1 − Vx,threshold is Vt + (m − 1)Vx due to body effect.

Bottom (N2) switching: Has more capacitance (of N1) to pull down.

2/19/2003 52

Two Input (Two-way) NAND

P2P1

N1

N2

Vdd

Vout

Vx

Vin1

Vin2

0 0.05 0.1 0.15 0.20

50

100

150

200

Load capacitance (pF)Pr

opag

atio

n de

lay

(ps)

Fan-out=1Wn=10 µmWp=20 µm

Inverter

Top switchingBottom switching

2-way NAND

⇒ Delay is about 30% worse than inverter.(Fan-in > 3 rarely used.)

pp

ddp

nn

dsatddnsw IW

VkIW

VVkR22

)1FI( +−+

≈