MOSFET & IC Basics GATE Problems (Part - II) · When a gate voltage is applied, a depletion region...

MOSFET & IC Basics – GATE Problems (Part - II)

1. In MOSFET devices the N-channel type is better than the P – Channel

type in the following respects.

(a) It has better immunity

(b) It is faster

(c) It is TTL compatible

(d) It has better drive

capability

[GATE 1988: 2 Marks]

Soln. In N – Channel MOSFETs the charge carriers are electrons while in

P – channel MOSFETs holes are the charge carriers.

The mobility of electrons is always greater than the mobility of holes.

i.e. 𝝁𝒏 > 𝝁𝒑

Thus, N – Channel MOSFETs are faster

Option (b)

2. In a MOSFET, the polarity of the inversion layer is the same as that of the

(a) Charge on the GATE – EC – electrode

(b) Minority carries in the drain

(c) Majority carriers in the substrate

(d) Majority carries in the source


Soln. In a MOSFET the polarity of inversion layer is the same as that of

majority carriers in the source.

For example, for N – MOSFETs the source is of N – type and

inversion layer formed is of electrons.

Option (d)

3. Which of the following effects can be caused by a rise in the

temperature?

(a) Increase in MOSFET current (IDS)

(b) Increase in BJT current (IC)

(c) Decrease in MOSFET current (IDS)

(d) Decrease in BJT current (IC)


Soln. The current equation for BJT is

𝑰𝑪 = 𝜷 𝑰𝒃 + (𝟏 + 𝜷)𝑰𝑪𝑶

As temperature increases, the leakage current ICO increases, so the

current IC increases in BJT.

Since mobility decreases as temperature increases. So in MOSFETs

current IDS decreases with rise in temperature

Option (b) and (c)

4. When the gate – to – source voltage (VGS) of a MOSFET with threshold

voltage of 400 mV, working in saturation is 900 mV, the drain current is

observed to be 1 mA. Neglecting the channel width modulation effect and

assuming that the MOSFET is operating at saturation, the drain current

for an applied VGS of 1400 mV is

(a) 0.5 mA

(b) 2.0 mA

(c) 3.5 mA

(d) 4.0 mA


Soln. Given,

𝑽𝑻 = 𝟒𝟎𝟎 𝒎𝑽 = 𝟎. 𝟒 𝑽

Voltage applied at gate

𝑽𝑮𝑺 = 𝟗𝟎𝟎 𝒎𝑽 =0.9 V

𝑰𝑫𝑺 = 𝟏 𝒎𝑨

Find the drain current for

𝑽𝑮𝑺 = 𝟏𝟒𝟎𝟎 𝒎𝑽

MOSFET is operating in saturation

𝑰𝑫𝑺 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻)𝟐

𝒐𝒓, 𝟏 × 𝟏𝟎−𝟑 = 𝑲 (𝟎. 𝟗 − 𝟎. 𝟒)𝟐

𝒐𝒓, 𝑲 =𝟏𝟎−𝟑

(𝟎.𝟓)𝟐= 𝟒 × 𝟏𝟎−𝟑 𝑨

𝑽𝟐

For VGS = 1.4 V

𝑰𝑫𝑺 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻)𝟐

= 𝟒 × 𝟏𝟎−𝟑 (𝟏. 𝟒 − 𝟎. 𝟒)𝟐

𝑰𝑫𝑺 = 𝟒 𝒎𝑨

Option (d)

5. The drain of an n – channel MOSFET is shorted to the gate so that

𝑉𝐺𝑆 = 𝑉𝐷𝑆 . The threshold voltage (VT) of MOSFET is 1 V. If the drain

current (ID) is 1 mA for VGS = 2 V, then for 𝑉𝐺𝑆 = 3 𝑉, ID is

(a) 2 mA

(b) 3 mA

(c) 9 mA

(d) 4 mA


Soln. Given,

𝑽𝑮𝑺 = 𝑽𝑫𝑺

Then the device is in saturation.

So, 𝑰𝑫𝑺 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻)𝟐

For 𝑰𝑫𝑺 = 𝟏 𝒎𝑨 , 𝑽𝑮𝑺 = 𝟐𝑽 , 𝑽𝑻 = 𝟏𝑽

𝟏 = 𝑲 (𝟐 − 𝟏)𝟐

𝒐𝒓, 𝑲 = 𝟏 𝒎𝑨 𝑽𝟐⁄

Again,

𝑰𝑫 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻)𝟐

For 𝑽𝑮𝑺 = 𝟑 𝑽

𝑰𝑫 = 𝟏 × (𝟑 − 𝟏)𝟐

𝑰𝑫 = 𝟒 𝒎𝑨

Option (d)

6. An n – channel depletion MOSFET has following two points on its

𝐼𝐷 − 𝑉𝐺𝑆 curve

(i) 𝑉𝐺𝑆 = 0 𝑎𝑡 𝐼𝐷 = 12 𝑚𝐴 𝑎𝑛𝑑

(ii) 𝑉𝐺𝑆 = −6 𝑉 𝑎𝑡 𝐼𝐷 = 0

Which of the following Q point will give the highest transconductance

gain for small signals?

(a) 𝑉𝐺𝑆 = −6 𝑉

(b) 𝑉𝐺𝑆 = −3 𝑉

(c) 𝑉𝐺𝑆 = 0 𝑉

(d) 𝑉𝐺𝑆 = 3 𝑉


Soln. Transconductance (𝒈𝒎) =𝜹 𝑰𝑫

𝜹 𝑽𝑮𝑺 for 𝑽𝑫𝑺 = 𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕

The characteristics is plotted.

VGS

12mA

-6V

𝑰𝑫(𝒎𝑨)

0

As ID increases VGS also increases Larger VGS will have high

transconductance

Thus, Option (d)

7. In the C MOS inverter circuit shown if the transconductance parameters

of N MOS and P MOS transistor are

𝐾𝑛 = 𝐾𝑝 = 𝜇𝑛𝐶𝑂𝑋

𝑊𝑛

𝐿𝑛= 𝜇𝑝𝐶𝑂𝑋

𝑊𝑝

𝐿𝑝= 40 𝜇𝐴 𝑉2⁄

and threshold voltages are 𝑉𝑇 = 1𝑉 the current I is

NMOS

PMOS

5V

2.5V

(a) 0 A

(b) 25 µA

(c) 45 µA

(d) 90 µA


Soln. Given

𝑲𝒏 = 𝑲𝒑 = 𝟒𝟎 𝝁𝑨 𝑽𝟐⁄

𝑽𝑻 = 𝟏 𝑽

The device is in saturation. So the current is given by

𝑰𝑫𝑺 =𝑲𝒏

𝟐 (𝑽𝑮𝑺 − 𝑽𝑻)𝟐

𝟒𝟎

𝟐(𝟐. 𝟓 − 𝟏)𝟐 = 𝟐𝟎 × (𝟏. 𝟓)𝟐 = 𝟒𝟓 𝝁𝑨

Option (c)

8. Two identical N MOS transistors M1 and M2 are connected as shown

below. 𝑉𝑏𝑖𝑎𝑠 Chosen so that both transistor are in saturation. The

equivalents 𝑔𝑚 of the pair is defined to be 𝜕 𝐼𝑜𝑢𝑡

𝜕 𝑉𝑖 at constant𝑉𝑜𝑢𝑡. The

equivalent 𝑔𝑚 of the pair is

M2

M1

𝑽𝒐𝒖𝒕

𝑽𝒃𝒊𝒂𝒔

𝑰𝒐𝒖𝒕

𝑽𝒊

(a) The sum of individual 𝑔𝑚 of two transistors.

(b) The product of individual 𝑔𝑚 of the transistors.

(c) Nearly equal to the 𝑔𝑚 of M1

(d) Nearly equal to 𝑔𝑚 𝑔0⁄ of M2


Soln. As per the principle of transconductance

𝟏

𝒈𝒎=

𝟏

𝒈𝒎𝟏

=𝟏

𝒈𝒎𝟐

𝒐𝒓, 𝒈𝒎 =𝒈𝒎𝟏

𝒈𝒎𝟐

𝒈𝒎𝟏+𝒈𝒎𝟐

≅ 𝒈𝒎𝟏

Option (c)

9. The measured Transconductance 𝑔𝑚 of an NMOS transistor operating in

the linear region is plotted against voltage VG at a Constant drain voltage

VD. Which of the following figures represents the expected dependence

of 𝑔𝑚 on VG .

(a) (b)

(d)(c)

gm gm

gm gm

VG

VG VG

VG V


Soln. Drain current ID in the linear region is given by

𝑰𝑫 = 𝑲𝒏 [(𝑽𝑮𝑺 − 𝑽𝑻)𝑽𝑫𝑺 −𝑽𝑫𝑺

𝟐

𝟐]

𝒂𝒏𝒅 𝒈𝒎 =𝝏 𝑰𝑫

𝝏 𝑽𝑮𝑺= 𝑲𝒏(𝑽𝑮𝑺 − 𝑽𝑻)𝑽𝑫𝑺

𝑺𝒐, 𝒈𝒎 ∝ 𝑽𝑮𝑺

So, linear characteristic

Option (c)

10. Consider the following two situations about the internal conditions in an

n – channel MOSFET operating in the active region.

S1: The inversion charge decreases from source to drain

S2 : The channel potential increases from source to drain

Which of the following is correct?

(a) Only S2 is true

(b) Both S1 and S2 are false

(c) Both S1 and S2 are true but S2 is not a reason for S1

(d) Both S1 and S2 are true and S2 is reason for S1


Soln. MOSFET is also considered as gate – controlled resistor.

When +ve gate voltage in an n – channel MOSFET exceeds VT,

electrons are induced in p – type substrate. This channel is also

connected to n+ source and drain regions. Channel looks like induced

n – type resistor. With increase in gate voltage the channel becomes

more conducting. The drain current increase (linear region). When

more drain current flows, there is more ohmic voltage drop along the

channel. The channel potential varies near zero from source to the

potential at drain end.

The voltage difference between gate and channel reduces from VG

(near source) to (𝑽𝑮 − 𝑽𝑫) near drain. When drain bias is increased

(𝑽𝑮 − 𝑽𝑫) = 𝑽𝑻, the channel is piched off. When VD increase further

the drain current is in saturation.

So, S1 & S2 are true and S2 is reason for S1

Option (d) (Refer: Streetman)

11. The source of a silicon (𝑛𝑖 = 1010 𝑝𝑒𝑟 𝑐𝑚3) n – channel MOS transistor

has an area 1 sq µm and a depth of 1 µm. If the dopant density in the

source is 1019/𝑐𝑚3 the no. of holes in the source region with above

volume is approx.

(a) 107

(b) 100

(c) 10

(d) 0


Soln. Given,

𝒏𝒊 = 𝟏𝟎𝟏𝟎 𝒄𝒎𝟑⁄

𝑨𝒓𝒆𝒂 (𝑨) = 𝟏 × 𝟏𝟎−𝟏𝟐/𝒎𝟐

𝒅𝒆𝒑𝒕𝒉 (𝒅) = 𝟏𝟎−𝟔 𝒎

𝑽𝒐𝒍𝒖𝒎𝒆 = 𝑨 . 𝒅 = 𝟏 × 𝟏𝟎−𝟐 × 𝟏𝟎𝟔 𝒎𝟑

= 𝟏𝟎−𝟏𝟖/𝒎𝟑

= 𝟏𝟎−𝟏𝟐/𝒄𝒎𝟑

𝑵𝑫 = 𝒏 = 𝟏𝟎𝟏𝟗/𝒄𝒎𝟑

𝒑 =𝒏𝒊

𝟐

𝑵𝑫=

𝟏𝟎𝟐𝟎

𝟏𝟎𝟏𝟗 = 𝟏𝟎 𝒄𝒎𝟑⁄

So,

Holes in volume V is

𝑯 = 𝒑 . 𝑽 = 𝟏𝟎−𝟏𝟐 × 𝟏𝟎

= 𝟏𝟎−𝟏𝟏

Since not integer number ≅ 𝟎

Option (d)

12. A depletion type N – channel MOSFET in biased in its linear region for

use as a voltage controlled resistor . Assume threshold voltage 𝑉𝑇𝐻 =

0.5𝑉 , 𝑉𝐺𝑆 = 2.0𝑉 , 𝑉𝐷𝑆 = 5𝑉 , 𝑊 𝐿⁄ = 100, 𝐶𝑂𝑋 = 10−8 𝐹/𝑐𝑚2 and

𝜇𝑛 = 800 𝑐𝑚2 𝑉 − 𝑠⁄ . The value of the resistance of the voltage

controlled resistor (𝑖𝑛 Ω) is __________


Soln. Given,

Depletion type MOSFET (N – Channel)

In linear region

𝑽𝑻𝑯 = 𝟎. 𝟓𝑽

𝑽𝑮𝑺 = 𝟐. 𝟎𝑽

𝑽𝑫𝑺 = 𝟓𝑽

𝑾/𝑳 = 𝟏𝟎𝟎

𝑪𝑶𝑿 = 𝟏𝟎−𝟖 𝑭 𝒄𝒎𝟐⁄

The value of voltage controlled resistor is given by

𝒓𝒅𝒔 =𝟏

𝝁𝒏𝑪𝑶𝑿𝑾𝑳

(𝑽𝑮𝑺 − 𝑽𝑻)

𝒓𝑫𝑺 =𝟏

𝟖𝟎𝟎 × 𝟏𝟎−𝟖 × 𝟏𝟎𝟎[𝟐 − (−𝟎. 𝟓)]

𝒓𝑫𝑺 = 𝟓𝟎𝟎 𝛀

Answer: 𝟓𝟎𝟎 𝛀

13. For the n – channel MOS transistor shown in figure, the threshold

voltage VTH is 0.8V. Neglect channel length modulation effects. When

the drain voltage VD = 1.6, the drain current ID was found to be 0.5 mA. If

VD is adjusted to be 2V by changing the values of R and VDD, the new

value of ID (in m A) is

R

D

S

𝑽𝑫𝑫

G

(a) 0.625

(b) 0.75

(c) 1.125

(d) 1.5


Soln. Given,

𝑽𝑻𝑯 = 𝟎. 𝟖 𝑽

𝑽𝑫 = 𝟏. 𝟔 𝑽

𝑰𝑫 = 𝟎. 𝟓 𝒎𝑨

For the given figure we notice that Gate is connected to drain

So, 𝑽𝑮𝑺 = 𝑽𝑫𝑺 = 𝑽𝑫

In saturation ID is given by

𝑰𝑫𝑺 = 𝑲(𝑽𝑮𝑺 − 𝑽𝑻)𝟐

𝑺𝒐, 𝑰𝑫𝟐

𝑰𝑫𝟏

=[𝑽𝑮𝑺𝟐−𝑽𝑻]

𝟐

[𝑽𝑮𝑺𝟏−𝑽𝑻]𝟐

𝑺𝒐, 𝑰𝑫𝟐

𝑰𝑫𝟏

=(𝟐 − 𝟎. 𝟖)𝟐

(𝟏. 𝟔 − 𝟎. 𝟖)𝟐= 𝟐. 𝟐𝟓

𝒐𝒓, 𝑰𝑫𝟐= 𝟐. 𝟐𝟓 × 𝟎. 𝟓

= 𝟏. 𝟏𝟐𝟓 𝒎𝑨

Option (c)

14. For the MOSFET shown in the figure the threshold voltage |𝑉𝑡| = 2𝑉

and 𝐾 =1

2𝜇𝑐 (

𝑊

𝐿) = 0.1𝑚𝐴/𝑉2. The value of ID (in mA) is ________

𝑽𝑫𝑫 = +𝟏𝟐𝑽

𝑹𝟏

𝑹𝟐

𝟏𝟎 𝑲𝛀

𝟏𝟎 𝑲𝛀

𝑽𝑺𝑺 = −𝟓𝑽

𝑰𝑫


Soln. The two MOSFET are in series so, same current will be flowing. For

the bottom MOSFET it is easier to find VGS

𝑽𝑮𝑺 = 𝑽𝑮 − 𝑽𝑺 = 𝟎— 𝟓

= 𝟓𝑽

VGS is greater than threshold voltage,

So, MOSFET is in saturation

𝑰𝑫 =𝟏

𝟐 𝝁𝒏 𝑪𝑶𝑿

𝑾

𝑳[𝑽𝑮𝑺 − 𝑽𝑻]𝟐

= 𝟎. 𝟏 𝒎𝑨/𝑽𝟐 [𝟓 − 𝟐]𝟐

𝟎. 𝟏 𝒎𝑨/𝑽𝟐 [𝟑]𝟐

𝑰𝑫 = 𝟎. 𝟗 𝒎𝑨

Answer: 0.9 mA

15. The slope of the 𝐼𝐷 𝑣𝑠 . 𝑉𝐺𝑆 curve of an n – channel MOSFET in linear

region is 10−3 Ω−1 at 𝑉𝐷𝑆 = 0.1𝑉 . For the same device, neglecting

channel length modulation, the slope of the √𝐼𝐷 𝑣𝑠 𝑉𝐺𝑆 curve

(𝑖𝑛 √𝐴 𝑉⁄ ) under saturation region is approximately ________


Soln. Given,

Slope of 𝑰𝑫 𝒗𝒔 . 𝑽𝑮𝑺 curve for N – MOSFET in linear region is

𝟏𝟎−𝟑 𝛀−𝟏

𝒊. 𝒆. 𝝏 𝑰𝑫

𝝏 𝑽𝑮𝑺= 𝟏𝟎−𝟑

In linear region the drain current is given by

𝑰𝑫 = 𝑲𝒏 [(𝑽𝑮𝑺 − 𝑽𝑻)𝑽𝑫𝑺 −𝟏

𝟐 𝑽𝑫𝑺

𝟐 ]

𝒘𝒉𝒆𝒓𝒆 𝑲𝒏 = 𝝁𝒏 𝑪𝑶𝑿𝑾

𝑳

𝝏 𝑰𝑫

𝝏 𝑽𝑮𝑺= 𝑲𝒏 𝑽𝑫𝑺

𝒐𝒓, 𝑲𝒏 =

𝝏 𝑰𝑫𝝏 𝑽𝑮𝑺

𝑽𝑫𝑺=

𝟏𝟎−𝟑

𝟎.𝟏= 𝟏𝟎−𝟐

For saturation region

𝑰𝑫 =𝟏

𝟐 𝑲𝒏 [𝑽𝑮𝑺 − 𝑽𝑻]𝟐

𝒐𝒓, √𝑰𝑫 = √𝑲𝒏

𝟐 [𝑽𝑮𝑺 − 𝑽𝑻]

𝝏 √𝑰𝑫

𝝏 𝑽𝑮𝑺= √

𝑲𝒏

𝟐

𝒐𝒓,𝝏 √𝑰𝑫

𝝏 𝑽𝑮𝑺= √

𝟏𝟎−𝟐

𝟐= 𝟎. 𝟎𝟕𝟎𝟕 √𝑨 / 𝑽

Answer: 𝟎. 𝟎𝟕𝟎𝟕 √𝑨 / 𝑽

16. An ideal MOS capacitor has boron doping concentration of 1015 𝑐𝑚−3

in the substrate. When a gate voltage is applied, a depletion region of

width 0.5 𝜇𝑚 is formed with a surface (channel) potential of 0.2 V. Given

that ∈0= 8.854 × 10−14F/cm and the relative permittivity of silicon and

silicon dioxide are 12 and 4 respectively the peak electric filed in 𝑉 𝜇𝑚⁄

in the oxide region is _____________


Soln. Dopant is Boron, so p – type substrate

Thus device is n MOSFET. Peak electric field in Si substrate

𝑬𝒔𝒊 =𝟐𝚿𝒔

𝑾𝒅

Where, 𝚿𝒔 − 𝒔𝒖𝒓𝒇𝒂𝒄𝒆 𝒑𝒐𝒕𝒆𝒏𝒕𝒊𝒂𝒍

𝑾𝒅 − 𝒅𝒆𝒑𝒍𝒆𝒕𝒊𝒐𝒏 𝒓𝒆𝒈𝒊𝒐𝒏 𝒘𝒊𝒅𝒕𝒉

𝑬𝒔𝒊 =𝟐 × 𝟎. 𝟐

𝟎. 𝟓𝝁𝒎= 𝟎. 𝟖 𝝁𝒎⁄

Electric field in oxide

𝑬𝑶𝑿 =∈𝒔

∈𝑶𝑿 . 𝑬𝒔𝒊

=𝟏𝟐

𝟒× 𝟎. 𝟖𝑽 𝝁𝒎⁄

= 𝟐. 𝟒 𝑽 𝝁𝒎⁄

Answer: 𝑬𝑶𝑿 = 𝟐. 𝟒𝑽 𝝁𝒎⁄

17. For the MOSFET M1 shown in figure, assume

𝑊 𝐿⁄ = 2, 𝑉𝐷𝐷 = 2.0𝑉, 𝜇𝑛 𝐶𝑂𝑋 = 100 𝜇𝑚 𝑉2⁄ 𝑎𝑛𝑑 𝑉𝑇𝐻 = 0.5𝑉. The

transistor M1 switches from saturation region to linear region when 𝑉𝑖𝑛

(in volts) is ___________

𝑽𝑫𝑫

R = 𝟏𝟎 𝑲𝛀

𝑽𝒐𝒖𝒕

M1 𝑽𝒊𝒏


Soln. For saturation region drain current is given by

𝑰𝑫 = 𝑲𝒏[𝑽𝑮𝑺 − 𝑽𝑻]𝟐

=𝟏

𝟐𝝁𝒏𝑪𝑶𝑿

𝑾

𝑳[𝑽𝑮𝑺 − 𝑽𝑻]𝟐

=𝟏

𝟐𝝁𝒏𝑪𝑶𝑿

𝑾

𝑳[𝑽𝟎]𝟐

𝒔𝒊𝒏𝒄𝒆, 𝑽𝑮𝑺 − 𝑽𝑻 = 𝑽𝑫𝑺 = 𝑽𝟎

𝑺𝒐, 𝑰𝑫 =𝟏

𝟐× 𝟏𝟎𝟎 × 𝟏𝟎−𝟔 × 𝟐 × 𝑽𝟎

𝟐

𝒐𝒓, 𝑰𝑫 = 𝟏𝟎𝟎 × 𝟏𝟎−𝟔 𝑽𝟎𝟐 − − − − − − − (𝟏)

Applying KVL in outer loop

𝑽𝑫𝑫 = 𝑰𝑫 × 𝟏𝟎𝑲 + 𝑽𝟎 − − − − − −(𝟐)

From equation (1) and (2) we get

𝟐 = 𝟏𝟎𝟎 × 𝟏𝟎−𝟔 𝑽𝟎𝟐 + 𝑽𝟎

𝒐𝒓, 𝟐 = 𝑽𝟎𝟐 + 𝑽𝟎

𝒐𝒓, 𝑽𝟎𝟐 + 𝑽𝟎 − 𝟐 = 𝟎

𝑽𝟎 =−𝟏 ± √𝟏 + 𝟒 × 𝟏 × 𝟐

𝟐 × 𝟏=

−𝟏 ± 𝟑

𝟐

𝑺𝒐, 𝑽𝟎 = 𝟏𝑽 𝒐𝒓 − 𝟐𝑽

Taking 𝑽𝟎 = 𝟏𝑽

𝑽𝑫𝑺 = 𝑽𝑮𝑺 = 𝑽𝑻

𝒐𝒓, 𝑽𝟎 = 𝑽𝒊𝒏 − 𝑽𝑻

𝒐𝒓, 𝑽𝒊𝒏 = 𝟏 + 𝟎. 𝟓 = 𝟏. 𝟓𝑽

Answer: 1.5V

18. In a MOS capacitor with an oxide layer thickness of 10 nm, the

maximum depletion layer thickness is 100 nm. The permittivities of the

semiconductor and the oxide layer are 𝜀𝑠 𝑎𝑛𝑑 𝜀𝑂𝑆 respectively.

Assuming 𝜀𝑠/𝜀𝑂𝑋 = 3, the ratio of the maximum capacitance of the

minimum capacitance of this MOS capacitor is .


Soln. Given,

Oxide layer thickness (𝒕𝑶𝑿) = 𝟏𝟎 𝒏𝒎

Depletion layer thickness (𝒕𝒅𝒆𝒑) = 𝟏𝟎𝟎 𝒏𝒎

𝜺𝒔

𝜺𝑶𝑿= 𝟑

Metal

Si

tOX (10nm)

tdep =100

Both oxide layer capacitance (𝑪𝑶𝑿) and depletion layer capacitances

are coming in series, so the maximum capacitance will be when

depletion layer capacitance (𝑪𝒅𝒆𝒑) will be absent

Maximum capacitance (𝑪𝒎𝒂𝒙) = 𝑪𝑶𝑿

Minimum capacitance (𝑪𝒎𝒊𝒏) is

Given by

𝑪𝒎𝒊𝒏 =𝑪𝑶𝑿 𝑪𝒅𝒆𝒑

𝑪𝑶𝑿 + 𝑪𝒅𝒆𝒑

Where 𝑪𝑶𝑿 𝒂𝒏𝒅 𝑪𝒅𝒆𝒑 are capacitances per unit area

𝑪𝒎𝒂𝒙

𝑪𝒎𝒊𝒏=

𝑪𝑶𝑿

𝑪𝑶𝑿 𝑪𝒅𝒆𝒑

𝑪𝑶𝑿 + 𝑪𝒅𝒆𝒑

=𝑪𝑶𝑿 + 𝑪𝒅𝒆𝒑

𝑪𝒅𝒆𝒑

= 𝟏 +𝑪𝑶𝑿

𝑪𝒅𝒆𝒑= 𝟏 +

𝜺𝑶𝑿

𝒕𝑶𝑿𝜺𝑺

𝒅

= 𝟏 +𝜺𝑶𝑿

𝜺𝒓 .

𝒅

𝒕𝑶𝑿

𝑪𝒎𝒂𝒙

𝑪𝒎𝒊𝒏= 𝟏 +

𝟏

𝟑×

𝟏𝟎𝟎

𝟏𝟎= 𝟒. 𝟑𝟑

Answer: 4.33

19. In the circuit shown both enhancement mode NMOS transistor have the

following characteristics: 𝐾𝑛 = 𝜇𝑛𝐶𝑂𝑋(𝑊 𝐿⁄ ) = 1𝑚𝐴/𝑉2; 𝑉𝑇𝑁 = 1𝑉. Assume that the channel length modulation parameter λ is zero and body

is shorted to source. The minimum supply voltage VDD (in volts) needed

to ensure that transistor M1 operates in saturation mode of operation is __

𝑽𝑫𝑫

M1

M2

2V


Soln. In the given circuit

M1 is to operate in saturation. Both MOSFETs are NMOS

𝑲𝒏 = 𝝁𝒏𝑪𝑶𝑿(𝑾 𝑳⁄ ) = 𝟏 𝒎𝑨/𝑽𝟐

𝑽𝑻𝒏 = 𝟏 𝑽

Both MOSFETs are in series so same current will flow through then

For M1 : 𝑽𝑮𝑺𝟏= 𝟐𝑽 (As per figure)

If M1 is assumed in saturation, then

𝑰𝑫𝟏=

𝟏

𝟐𝑲𝒏[𝑽𝑮𝑺𝟏

− 𝑽𝑻]𝟐

Minimum VDS required for M1 to operate in saturation

𝑽𝑫𝑺𝟏= 𝑽𝑮𝑺𝟏

− 𝑽𝑻 = 𝟐 − 𝟏 = 𝟏𝑽

For M2 : 𝑽𝑮𝑺𝟐− 𝑽𝑫𝑫 − 𝑽𝑫𝑺𝟏

= 𝑽𝑫𝑫 − 𝟏

𝑰𝑫𝟐=

𝟏

𝟐 𝑲𝒏[𝑽𝑮𝑺𝟐

− 𝑽𝑻]𝟐

Since 𝑰𝑫𝟏= 𝑰𝑫𝟐

𝟏

𝟐 𝑲𝒏[𝑽𝑮𝑺𝟏

− 𝑽𝑻]𝟐

=𝟏

𝟐 𝑲𝒏[𝑽𝑮𝑺𝟐

− 𝑽𝑻]𝟐

𝒐𝒓, 𝑽𝑽𝑮𝟏− 𝑽𝑻 = 𝑽𝑮𝑺𝟐

− 𝑽𝑻

𝑽𝑮𝑺𝟏= 𝑽𝑮𝑺𝟐

𝒐𝒓, 𝑽𝑮𝑺𝟏= 𝑽𝑫𝑫 − 𝟏

𝒐𝒓, 𝑽𝑫𝑫 = 𝟐 + 𝟏 = 𝟑𝑽

Answer: 𝑽𝑫𝑫 = 𝟑𝑽

20. The current in an enhancement mode NMOS transistor biased in

saturation mode was measured to be 1 mA at a drain source voltage of

5V. When the drain source voltage was increased to 6V while keeping

gate source voltage same. The drain current increased to 1.02 mA.

Assume that drain to source saturation voltage is much smaller than the

applied drain source voltage. The channel length modulation parameter λ

(𝑖𝑛 𝑉−1) is ______________.


Soln. Given,

N MOS transistor

Biased in saturation 𝑰𝑫 = 𝟏𝒎𝑨 , 𝑽𝑫𝑺 = 𝟓𝑽

Drain current in saturation including the effect of channel length

modulation parameter

𝑰𝑫 =𝟏

𝟐 𝝁𝒏𝑪𝑶𝑿

𝑾

𝑳(𝑽𝑮𝑺 − 𝑽𝑻)𝟐(𝟏 + 𝝀 𝑽𝑫𝑺)

So, we can write the ratio of two current

𝑰𝑫𝟐

𝑰𝑫𝟐

=𝟏 + 𝝀 𝑽𝑫𝑺𝟐

𝟏 + 𝝀 𝑽𝑫𝑺𝟏

𝒐𝒓, 𝟏. 𝟎𝟐

𝟏=

𝟏 + 𝟔𝝀

𝟏 + 𝟓𝝀

𝒐𝒓, 𝟏. 𝟎𝟐 + 𝟓. 𝟏𝝀 = 𝟏 + 𝟔𝝀

𝒐𝒓, 𝟎. 𝟗 𝝀 = 𝟎. 𝟎𝟐

𝒐𝒓, 𝝀 =𝟎. 𝟎𝟐

𝟎. 𝟗= 𝟎. 𝟎𝟐𝟐𝑽−𝟏

21. Consider an n – channel metal oxide semiconductor field effect transistor

(MOSFET) with gate to source voltage of 1.8V. Assume that 𝑊

𝐿= 4, 𝜇𝑛𝐶𝑂𝑋 = 70 × 10−6 𝐴𝑉−2

The threshold voltage is 0.3V, and the channel length modulation

parameter is 0.09𝑉−1. In the saturation region, the drain conduction (in

micro Siemens) is ________


Soln. Given,

N – MOSFET

𝑽𝑮𝑺 = 𝟏. 𝟖𝑽 ,𝑾

𝑳= 𝟒 , 𝝁𝒏𝑪𝑶𝑿 = 𝟕𝟎 × 𝟏𝟎−𝟔 𝑨𝑽−𝟐

𝑽𝑻𝑯 = 𝟎. 𝟑𝑽 , 𝝀 = 𝟎. 𝟎𝟗𝑽−𝟏

Drain current in saturation including the effect of channel length

modulation is

𝑰𝑫 =𝟏

𝟐 𝝁𝒏 𝑪𝑶𝑿 (

𝑾

𝑳) (𝑽𝑮 − 𝑽𝑻)𝟐(𝟏 + 𝝀𝑽𝑫)

Channel conductance (𝒈𝒅)

(𝒈𝒅) =𝝏 𝑰𝑫

𝝏 𝑽𝑫

𝑽𝑮 = 𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕

𝒈𝒅 =𝝏 𝑰𝑫

𝝏 𝑽𝑫=

𝟏

𝟐 𝝁𝒏𝑪𝑶𝑿 (

𝑾

𝑳) (𝑽𝑮 − 𝑽𝑻)𝟐 . 𝝀

So,

𝒈𝒅 =𝟏

𝟐× 𝟕𝟎 × 𝟏𝟎−𝟔 × 𝟒 × (𝟏. 𝟖 − 𝟎. 𝟑)𝟐 × 𝟎. 𝟎𝟗

= 𝟏𝟒𝟎 × 𝟏𝟎−𝟔 × 𝟐. 𝟐𝟓 × 𝟎. 𝟎𝟗

= 𝟐𝟖. 𝟑𝟓 × 𝟏𝟎−𝟔

𝒈𝒅 = 𝟐𝟖. 𝟑𝟓 𝝁 𝑺𝒊𝒆𝒎𝒆𝒏𝒔

Drain conductance 𝒈𝒅 = 𝟐𝟖. 𝟑𝟓 𝝁 𝐒𝐢𝐞𝐦𝐞𝐧𝐬

22. A voltage VG is applied across the MOS capacitor with metal Gate and

p – type silicon substrate at 𝑇 = 300 𝐾. The inversion carrier density (in

number of units per unit area) for

𝑉𝐺 = 0.8𝑉 𝑖𝑠 2 × 1011𝑐𝑚−2 𝑓𝑜𝑟 𝑉𝐺 = 1.3𝑉, the inversion carrier density

is 4 × 1011𝑐𝑚−2. What is value of inversion carrier density of VG = 1.8V

(a) 4.5 × 1011𝑐𝑚−2

(b) 6.0 × 1011𝑐𝑚−2

(c) 7.2 × 1011𝑐𝑚−2

(d) 8.4 × 1011𝑐𝑚−2


Soln. Given,

For VG = 0.8V

Inversion layer carrier density = 𝟐 × 𝟏𝟎𝟏𝟏𝒄𝒎−𝟐

𝑭𝒐𝒓 𝑽𝑮 = 𝟏. 𝟑𝑽 , 𝑰𝒏𝒗𝒆𝒓𝒔𝒊𝒐𝒏 𝒍𝒂𝒚𝒆𝒓 𝒄𝒂𝒓𝒓𝒊𝒆𝒓 𝒅𝒆𝒏𝒔𝒊𝒕𝒚 = 𝟒 ×

𝟏𝟎𝟏𝟏𝒄𝒎𝟐

Find for VG = 1.8 V

For MOS capacitor

Charge (𝑸) ∝ (𝑽𝑮 − 𝑽𝑻)

Charge 𝑸𝟏 = 𝑲. (𝑽𝑮 − 𝑽𝑻)

Or, 𝑸𝟏 = 𝒒𝑨 × 𝒊𝒏𝒗𝒆𝒓𝒔𝒊𝒐𝒏 𝒄𝒂𝒓𝒓𝒊𝒆𝒓 𝒅𝒆𝒏𝒔𝒊𝒕𝒚

So,

𝟐 × 𝟏𝟎𝟏𝟏 . 𝒒𝑨

𝟒 × 𝟏𝟎𝟏𝟏 . 𝒒𝑨=

(𝟎. 𝟖 − 𝑽𝑻)

(𝟏. 𝟑 − 𝑽𝑻)

Or, VT = 0.3V

𝑵𝒐𝒘 𝒇𝒐𝒓 𝑽𝑮 = 𝟏. 𝟖𝑽 , 𝑸𝟏 = 𝒒𝑨 𝝆𝒊

Where 𝝆𝒊 is inversion carrier density

𝝆𝒊 𝒒 . 𝑨

𝟐 × 𝟏𝟎𝟏𝟏 𝒒 . 𝑨=

(𝟏. 𝟖 − 𝟎. 𝟑)

(𝟎. 𝟖 − 𝟎. 𝟑)

𝒐𝒓, 𝝆𝒊 = 𝟔 × 𝟏𝟎𝟏𝟏/𝒄𝒎𝟐

Option (b)

23. Consider long channel N MOS transistor with source and body

connected together.

Assume that the electron mobility is dependent of VGS and VDS. Given,

𝑔𝑚 = 0.5 𝜇 𝐴 𝑉⁄ 𝑓𝑜𝑟 𝑉𝐷𝑆 = 50 𝑚𝑉 𝑎𝑛𝑑 𝑉𝐺𝑆 = 2𝑉

𝑔𝑑 = 8 𝜇 𝐴 𝑉⁄ 𝑓𝑜𝑟 𝑉𝐺𝑆 = 2𝑉 𝑎𝑛𝑑 𝑉𝐷𝑆 = 0𝑉

Where

𝑔𝑚 =𝜕 𝐼𝐷

𝜕 𝑉𝐺𝑆 𝑎𝑛𝑑 𝑔𝑑 =

𝜕 𝐼𝐷

𝜕 𝑉𝐷𝑆

The threshold voltage (in volts) of the transistor is _________


Soln. Given long channel N MOS, it means it does not have the effect of

channel length modulation. Since VDS is 50 mV (small) it is operating

in linear region. The drain current is given by

𝑰𝑫 = 𝝁𝒏 𝑪𝑶𝑿 (𝑾

𝑳) [(𝑽𝑮𝑺 − 𝑽𝑻)𝑽𝑫𝑺 −

𝟏

𝟐𝑽𝑫𝑺

𝟐 ]

𝒈𝒎 =𝝏 𝑰𝑫

𝝏 𝑽𝑮𝑺= 𝝁𝒏 𝑪𝑶𝑿 (

𝑾

𝑳) . 𝑽𝑫𝑺

𝒐𝒓, 𝝁𝒏 𝑪𝑶𝑿

𝑾

𝑳=

𝒈𝒎

𝑽𝑫𝑺=

𝟎. 𝟓 × 𝟏𝟎−𝟔

𝟓𝟎 × 𝟏𝟎−𝟑= 𝟏𝟎 × 𝟏𝟎−𝟔

Now,

𝒈𝒅 =𝝏 𝑰𝑫

𝝏 𝑽𝑫𝑺= 𝝁𝒏 𝑪𝑶𝑿

𝑾

𝑳[𝑽𝑮 − 𝑽𝑻]

𝒐𝒓, 𝟖 × 𝟏𝟎−𝟔 = 𝟏𝟎 × 𝟏𝟎−𝟔[𝑽𝑮𝑺 − 𝑽𝑻]

𝒐𝒓, 𝑽𝑮𝑺 − 𝑽𝑻 =𝟖 × 𝟏𝟎−𝟔

𝟏𝟎 × 𝟏𝟎−𝟔

𝒐𝒓, 𝑽𝑻 = 𝑽𝑮𝑺 − 𝟎. 𝟖

= 𝟐 − 𝟎. 𝟖 = 𝟏. 𝟐𝑽

𝐀𝐧𝐬𝐰𝐞𝐫: 𝑽𝑻 = 𝟏. 𝟐𝑽

24. Figure I and II show two MOS capacitors of unit area. The capacitor in

Figure I has insulator material X of (thickness t1 = 1 nm and dielectric

constant ∈1= 4) and y (of thickness 𝑡2 = 3𝑛𝑚 and dielectric

constant∈1= 20). The capacitor in figure II has only insulator material X

of thickness 𝑡𝑒𝑞 . If the capacitors are of equal capacitance, then the value

of 𝑡𝑒𝑞 (in nm) is________

Metal

Ԑ2 Ԑ1

Metal

Ԑ1

Si Si

t1 t2 teq

Figure IFigure II


Soln. MOS structure is like a parallel plate capacitor

The capacitance per unit area for this geometry is

𝑪′ =∈

𝒅

Where ∈ is permittivity of insulator

d is distance between plates

For area A,

𝑪 =∈𝑨

𝒅

As per figure I the two capacitors formed by the two dielectrics are in

series

𝑪 =𝑪𝟏 𝑪𝟐

𝑪𝟏 + 𝑪𝟐

= [

𝟒𝟏 × 𝟏𝟎−𝟗 ×

𝟐𝟎𝟑 × 𝟏𝟎−𝟗

𝟒𝟏 × 𝟏𝟎−𝟗 +

𝟐𝟎𝟑 × 𝟏𝟎−𝟗

] ∈𝟎

𝑪 = 𝟐. 𝟓 × 𝟏𝟎𝟗 ∈𝟎

For the II case

𝑪 =∈𝒓 ∈𝟎

𝒕𝒆𝒒

𝒐𝒓, 𝒕𝒆𝒒=

∈𝒓 ∈𝟎

𝑪

=∈𝒓 ∈𝟎

𝟐. 𝟓 × 𝟏𝟎𝟗 ∈𝟎=

𝟒

𝟐. 𝟓 × 𝟏𝟎𝟗

= 𝟏. 𝟔 × 𝟏𝟎−𝟗 𝒎

𝒕𝒆𝒒= 𝟏. 𝟔 𝒏𝒎

Ans.1.6 nm

MOSFET & IC Basics GATE Problems (Part - II) · When a gate voltage is applied, a depletion region...

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